ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 Ultra-Small, Low-Power, SPITM-Compatible, 16-Bit Analog-to-Digital Converter and Temperature Sensor with Internal Reference Check for Samples: ADS1118 FEATURES DESCRIPTION * The ADS1118 is a precision analog-to-digital converter (ADC) with 16 bits of resolution offered in an ultra-small, leadless QFN-10 package or an MSOP-10 package. The ADS1118 is designed with precision, power, and ease of implementation in mind. The ADS1118 features an integrated voltage reference and oscillator. Data are transferred via a serial peripheral interface (SPI). The ADS1118 operates from a single power supply ranging from 2.0 V to 5.5 V. 1 23 * * * * * * * * * Ultra-Small QFN Package: 2 mm x 1,5 mm x 0,4 mm Wide Supply Range: 2.0 V to 5.5 V Low Current Consumption: - Continuous Mode: Only 150 A - Single-Shot Mode: Auto Power-Down Programmable Data Rate: 8 SPS to 860 SPS Single-Cycle Settling Internal Low-Drift Voltage Reference Internal Temperature Sensor: 0.5C (max) Error Internal Oscillator Internal PGA Four Single-Ended or Two Differential Inputs APPLICATIONS * * * Temperature Measurement: - Thermocouple Measurement - Cold Junction Compensation - Thermistor Measurement Portable Instrumentation Factory Automation and Process Controls The ADS1118 can perform conversions at rates up to 860 samples per second (SPS). A programmable gain amplifier (PGA) is integrated in the ADS1118 that offers input ranges from as low as 256 mV up to the supply rails, allowing both large and small signals to be measured with high resolution. The ADS1118 also features an input multiplexer (MUX) that provides two differential or four single-ended inputs. The ADS1118 can also function as a high-accuracy temperature sensor. This temperature sensor can be used for system-level temperature monitoring or cold junction compensation for thermocouples. The ADS1118 operates either in continuous conversion mode or single-shot mode that automatically powers down after a conversion. Single-shot mode significantly reduces current consumption during idle periods. The ADS1118 is specified from -40C to +125C. 2V 0.1 mF 2V 1 MW GND 500 W 0.1 mF GND AIN0 VDD 1 mF 1 MW 500 W Device Voltage Reference AIN1 0.1 mF SCLK GND GND 2V 1 MW MUX 500 W GND 16-Bit DS ADC SPI Interface GND 500 W 0.1 mF 1 mF 1 MW PGA 0.1 mF CS DOUT/DRDY DIN AIN2 Oscillator AIN3 High Accuracy Temp Sensor GND GND GND 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010-2013, Texas Instruments Incorporated ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE VDD to GND Analog input current mA 10, continuous mA V -0.3 to +5.5 V Human body model (HBM) JEDEC standard 22, test method A114-C.01, all pins 4000 V Charged device model (CDM) JEDEC standard 22, test method C101, all pins 1000 V -40 to +125 C +150 C -60 to +150 C DIN, DOUT/DRDY, SCLK, CS voltage to GND Operating temperature range Maximum junction temperature Storage temperature range (1) V 100, momentary -0.3 to VDD + 0.3 Analog input voltage to GND Electrostatic discharge (ESD) ratings UNIT -0.3 to +5.5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PRODUCT FAMILY 2 DEVICE RESOLUTION (Bits) MAXIMUM SAMPLE RATE (SPS) INPUT CHANNELS [Differential (Single-Ended)] PGA INTERFACE SPECIAL FEATURES ADS1118 16 860 2 (4) Yes SPI Temperature sensor BBEI, SDQ ADS1018 12 3300 2 (4) Yes SPI Temperature sensor BTNQ, SDZ ADS1115 16 860 2 (4) Yes I2C Comparator BOGI, N4J 2 PACKAGE DESIGNATOR MSOP, QFN ADS1114 16 860 1 (1) Yes IC Comparator BRNI, N5J ADS1113 16 860 1 (1) No I2C None BROI, N6J ADS1015 12 3300 2 (4) Yes I2C Comparator BRPI, N7J 2 ADS1014 12 3300 1 (1) Yes IC Comparator BRQI, N8J ADS1013 12 3300 1 (1) No I2C None BRMI, N9J Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS Maximum and minimum specifications are at TA = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale (FS) = 2.048 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDD V ANALOG INPUT Full-scale input voltage range (1) VIN = (AINP) - (AINN) Analog input voltage AINP or AINN to GND See Table 2 GND Differential input impedance Common-mode input impedance See Table 1 FS = 6.144 V (1) 8 M (1) FS = 4.096 V , 2.048 V 6 M FS = 1.024 V 3 M 100 M FS = 0.512V, 0.256 V SYSTEM PERFORMANCE Resolution No missing codes 16 Data rate (DR) Data rate variation All data rates -10 Output noise Integral nonlinearity Offset error Bits 8, 16, 32, 64, 128, 250, 475, 860 SPS 10 % 1 LSB 2 LSB See Typical Characteristics DR = 8 SPS, FS = 2.048 V (2) FS = 2.048 V, differential inputs 0.1 FS = 2.048 V, single-ended inputs 0.25 LSB Offset drift FS = 2.048 V 0.002 LSB/C Offset power-supply rejection FS = 2.048 V, with dc supply variation 0.2 LSB/V Gain error (3) FS = 2.048 V at TA = +25C 0.01 FS = 0.256 V Gain drift (3) (4) FS = 2.048 V FS = 6.144 V 0.15 7 5 (1) 40 5 Gain power-supply rejection % ppm/C ppm/C ppm/C 10 ppm/V PGA gain match (3) Match between any two PGA gains 0.01 0.1 % Gain match Match between any two inputs 0.01 0.1 % Offset match Match between any two inputs 0.6 LSB At dc and FS = 0.256 V 105 dB At dc and FS = 2.048 V 100 dB Common-mode rejection At dc and FS = 6.144 V (1) 90 dB fCM = 50 Hz, DR = 860 SPS 105 dB fCM = 60 Hz, DR = 860 SPS 105 dB TEMPERATURE SENSOR Temperature sensor range -40 Temperature sensor resolution TA = 0C to +70C Temperature sensor accuracy TA = -40C to +125C vs supply (1) (2) (3) (4) +125 0.03125 0.2 C C/LSB 0.5 0.4 1 0.03125 0.25 C C C/V This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3 V or 5.5 V (whichever is smaller) be applied to this device. Best-fit INL; covers 99% of full-scale. Includes all errors from onboard PGA and reference. Not production tested; ensured by characterization. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 3 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Maximum and minimum specifications are at TA = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C. All specifications are at VDD = 3.3 V, data rate = 8 SPS, and full-scale (FS) = 2.048 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Logic level VIH 0.7 VDD VDD V VIL GND 0.2 VDD V VOH IOH = 1 mA 0.8 VDD VOL IOL = 1 mA GND V 0.2 VDD V Input leakage IH VIH = 5.5 V 10 A IL VIL = GND 10 A 5.5 V 2 A 5 A 200 A 300 A POWER-SUPPLY REQUIREMENTS Power-supply voltage 2 Power-down current at TA = +25C 0.5 Power-down current up to TA = +125C Supply current Operating current at TA = +25C 150 Operating current up to TA = +125C Power dissipation VDD = 5.0 V 0.9 mW VDD = 3.3 V 0.5 mW VDD = 2.0 V 0.3 mW TEMPERATURE Storage temperature -60 +150 C Specified temperature -40 +125 C THERMAL INFORMATION ADS1118 THERMAL METRIC (1) MSOP (DGS) QFN (RUG) 10 PINS 10 PINS 245.2 JA Junction-to-ambient thermal resistance 186.8 JCtop Junction-to-case (top) thermal resistance 51.5 69.3 JB Junction-to-board thermal resistance 108.4 172.0 JT Junction-to-top characterization parameter 2.7 8.2 JB Junction-to-board characterization parameter 106.5 170.8 JCbot Junction-to-case (bottom) thermal resistance n/a n/a (1) 4 UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 PIN CONFIGURATIONS RUG PACKAGE QFN-10 (TOP VIEW) DGS PACKAGE MSOP-10 (TOP VIEW) DIN 10 SCLK 1 9 DOUT/DRDY CS 2 8 VDD GND 3 7 AIN3 AIN0 4 6 AIN2 SCLK 1 10 DIN CS 2 9 DOUT/DRDY GND 3 8 VDD AIN0 4 7 AIN3 AIN1 5 6 AIN2 5 AIN1 PIN DESCRIPTIONS PIN # PIN NAME FUNCTION 1 SCLK Digital input Serial clock input DESCRIPTION 2 CS Digital input Chip select; active low 3 GND Analog 4 AIN0 Analog input Differential channel 1: positive input or single-ended channel 1 input 5 AIN1 Analog input Differential channel 1: negative input or single-ended channel 2 input 6 AIN2 Analog input Differential channel 2: positive input or single-ended channel 3 input 7 AIN3 Analog input Differential channel 2: negative input or single-ended channel 4 input 8 VDD Analog 9 DOUT/DRDY Digital output Serial data out combined with data ready; active low 10 DIN Digital input Serial data input Ground Power supply: 2.0 V to 5.5 V Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 5 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com SPI TIMING CHARACTERISTICS tCSH CS tSCLK tCSSC tSPWH tSCCS SCLK tDIHD tDIST tSPWL tSCSC DIN tCSDOD tDOHD tDOPD Hi-Z tCSDOZ Hi-Z DOUT Figure 1. Serial Interface Timing TIMING REQUIREMENTS: SERIAL INTERFACE TIMING At TA = -40C to +125C and VDD = 2.0 V to 5.5 V, unless otherwise noted. SYMBOL DESCRIPTION MIN MAX UNIT tCSSC CS low to first SCLK: setup time (1) 100 ns tSCLK SCLK period 250 ns tSPWH SCLK pulse width: high 100 ns tSPWL SCLK pulse width: low (2) tDIST Valid DIN to SCLK falling edge: setup time 50 tDIHD Valid DIN to SCLK falling edge: hold time 50 tDOPD SCLK rising edge to valid new DOUT: propagation delay (3) tDOHD SCLK rising edge to DOUT invalid: hold time tCSDOD tCSDOZ 100 ns 28 ms ns ns 50 ns 0 ns CS low to DOUT driven: propagation delay 100 ns CS high to DOUT Hi-Z: propagation delay 100 ns tCSH CS high pulse 200 ns tSCCS Final SCLK falling edge to CS high 100 ns (1) (2) (3) 6 CS can be tied low. Holding SCLK low longer than 28 ms resets the SPI interface. DOUT load = 20 pF || 100 k to GND. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS At TA = +25C and VDD = 3.3 V, unless otherwise noted. TOTAL ERROR vs INPUT SIGNAL 4 DATA RATE vs TEMPERATURE 4 3 2 2 Data Rate Error (%) Total Error (mV) Includes noise, offset, and gain error. 3 1 0 -1 -2 FS = 2.048 V Data Rate = 860 SPS Differential Inputs -3 -4 -2.048 -1.024 0 VDD = 2.0 V VDD = 3.3 V VDD = 5.0 V 1 0 -1 -2 -3 1.024 -4 -60 -40 -20 2.048 0 Input Signal (V) 20 40 60 80 Temperature (C) Figure 2. 100 120 140 G028 Figure 3. NOISE vs INPUT SIGNAL NOISE vs SUPPLY VOLTAGE 10 35 FS = 0.512V FS = 2.048V DR = 860SPS DR = 860SPS 30 RMS Noise (V) RMS Noise (V) 8 6 4 DR = 128SPS 25 20 15 DR = 128SPS 10 DR = 8SPS DR = 8SPS 2 5 0 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 Input Voltage (V) 0.3 0.4 0 2.0 0.5 2.5 3.0 G017 3.5 4.0 4.5 Supply Voltage (V) Figure 4. NOISE vs TEMPERATURE G018 INL vs SUPPLY VOLTAGE 15 Integral Nonlinearity (ppm) FS = 2.048V Data Rate = 8SPS 8 RMS Noise (V) 5.5 Figure 5. 10 9 5.0 7 6 5 4 3 12.5 FS = 0.256V FS = 0.512V FS = 2.048V FS = 6.144V 10 7.5 5 2.5 2 1 -40 -20 0 20 40 60 Temperature (C) 80 100 120 0 2.0 G019 Figure 6. 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 5.0 5.5 G010 Figure 7. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 7 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C and VDD = 3.3 V, unless otherwise noted. INL vs INPUT SIGNAL INL vs INPUT SIGNAL 5 10 FS = 2.048V VDD = 3.3V DR = 8SPS Best Fit 3 2 1 0 -1 -2 -40C +25C +125C -3 -4 -5 -2 -1.5 -40C +25C +125C 8 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) 4 6 4 2 0 -2 -4 FS = 0.512V VDD = 3.3V DR = 8SPS Best Fit -6 -8 -1 -0.5 0 0.5 Input Signal (V) 1 1.5 -10 -0.5 2 -0.4 -0.2 G011 Figure 8. INL vs INPUT SIGNAL 3 2 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) G012 1 0 -1 -2 -40C +25C +125C -3 -2 -1.5 -40C +25C +125C 8 6 4 2 0 -2 -4 FS = 0.512V VDD = 5V DR = 8SPS Best Fit -6 -8 -1 -0.5 0 0.5 Input Signal (V) 1 1.5 -10 -0.5 2 -0.4 -0.2 G013 Figure 10. -0.1 0 0.1 Input Signal (V) 0.2 0.4 0.5 G014 Figure 11. INL vs TEMPERATURE INL vs DATA RATE 12 16 FS = 2.048 V DR = 8 SPS Best Fit VDD = 2.0 V VDD = 3.3 V VDD = 5.0 V 8 6 4 2 0 -60 -40 -20 FS = 2.048V Best Fit 14 Integral Nonlinearity (ppm) Integral Nonlinearity (ppm) 0.5 INL vs INPUT SIGNAL FS = 2.048V VDD = 5V DR = 8SPS Best Fit -4 -40C +25C +125C 12 10 8 6 4 2 0 20 40 60 80 Temperature (C) 100 120 140 0 8 G015 Figure 12. 8 0.4 10 4 10 0.2 Figure 9. 5 -5 -0.1 0 0.1 Input Signal (V) 16 32 64 128 250 Data Rate (SPS) 475 860 G016 Figure 13. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25C and VDD = 3.3 V, unless otherwise noted. SINGLE-ENDED OFFSET VOLTAGE vs TEMPERATURE SINGLE-ENDED OFFSET VOLTAGE vs SUPPLY 60 60 AIN0 to GND AIN1 to GND AIN2 to GND AIN3 to GND AIN0 to GND AIN1 to GND AIN2 to GND AIN3 to GND 40 Offset Voltage (V) Offset Voltage (V) 40 20 0 -20 -40 20 0 -20 -40 FS = 2.048V -60 -40 -20 FS = 2.048V 0 20 40 60 Temperature (C) 80 100 -60 120 2 2.5 3 3.5 4 Supply Voltage (V) G004 Figure 14. G005 DIFFERENTIAL OFFSET VOLTAGE vs SUPPLY 40 40 AIN0 to AIN1 AIN0 to AIN3 AIN1 to AIN3 AIN2 to AIN3 20 AIN0 to AIN1 AIN0 to AIN3 AIN1 to AIN3 AIN2 to AIN3 30 Offset Voltage (V) 30 Offset Voltage (V) 5 Figure 15. DIFFERENTIAL OFFSET VOLTAGE vs TEMPERATURE 10 0 -10 -20 -30 20 10 0 -10 -20 -30 FS = 2.048V -40 -40 -20 FS = 2.048V 0 20 40 60 Temperature (C) 80 100 -40 120 2 2.5 G006 Figure 16. 3 3.5 4 Supply Voltage (V) 4.5 5 G007 Figure 17. OFFSET DRIFT HISTOGRAM OFFSET HISTOGRAM 15 200 TA = -40C to +125C FS = 2.048 V, MUX = AIN0 to AIN3 30 units from one production lot. 540 units from 3 production lots FS = 2.048V Number of Occurrences Number of Occurrences 4.5 10 5 100 50 Offset Drift (LSB/C) -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 0.005 0.004 0.003 0.002 0.001 0 -0.001 -0.002 -0.003 -0.004 0 -0.005 0 150 Offset (V) G046 Figure 18. G000 Figure 19. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 9 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C and VDD = 3.3 V, unless otherwise noted. GAIN ERROR vs TEMPERATURE GAIN ERROR vs SUPPLY 0.15 0.05 0.04 0.1 0.02 Gain Error (%) Gain Error (%) 0.03 0.01 0 FS = 0.256V FS = 0.512V FS = 1.024V FS = 2.048V FS = 4.096V FS = 6.144V -0.01 -0.02 -0.03 -0.04 -0.05 -40 -20 0 20 40 60 80 Temperature (C) 100 120 0.05 FS = 256 mV 0 FS = 2.048 V -0.05 -0.1 -0.15 140 2 2.5 3 G008 3.5 Figure 20. 4.5 5 5.5 Figure 21. GAIN ERROR HISTOGRAM OPERATING CURRENT vs TEMPERATURE 300 200 540 units from 3 production lots FS = 2.048V 250 Operating Current (mA) Number of Occurrences 4 Supply Voltage (V) 150 100 50 VDD = 5 V 200 150 VDD = 3.3 V VDD = 2 V 100 50 0 Gain Error (%) 0.05 0.04 0.045 0.03 0.035 0.02 0.025 0.01 0.015 0 0.005 -0.01 -0.005 -0.02 -0.015 0 -40 -20 0 100 120 140 FREQUENCY RESPONSE 0 VDD = 2.0 V VDD = 3.3 V VDD = 5.0 V Data Rate = 8 SPS -10 -20 3.5 3 Gain (dB) Power-Down Current (dB) 80 Figure 23. POWER-DOWN CURRENT vs TEMPERATURE 2.5 2 -30 -40 -50 1.5 -60 1 -70 0.5 0 -40 -20 0 20 40 60 80 Temperature (C) 100 120 140 -80 1 G003 Figure 24. 10 60 G000 5 4 40 Temperature (C) Figure 22. 4.5 20 10 100 1k 10k Input Frequency (Hz) Figure 25. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25C and VDD = 3.3 V, unless otherwise noted. TEMPERATURE SENSOR ERROR vs AMBIENT TEMPERATURE (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) 1 40 Average Temperature Error Average 3 sigma Average 6 sigma 0.6 TA = -40C 48 units from 3 production lots. 35 Number of Occurrences 0.4 0.2 0 -0.2 -0.4 -0.6 30 25 20 15 10 5 -0.8 G023 0.5 0.4 0.3 0.2 0 120 0.1 100 0 80 -0.1 20 40 60 Temperature (C) -0.2 0 -0.3 -20 -0.5 -1 -40 -0.4 Temperature Error (C) 0.8 Temperature Error (C) Figure 27. TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) 15 Temperature Error (C) 0.5 0.4 0.3 0.2 -0.5 0.5 0.4 0.3 0.2 0.1 0 0 -0.1 0 -0.2 5 -0.3 5 0.1 10 0 10 20 -0.1 15 25 -0.2 20 30 -0.3 Number of Occurrences 25 -0.4 TA = +25C 48 units from 3 production lots 35 30 -0.5 Temperature Error (C) G041 G042 Figure 28. Figure 29. TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) TEMPERATURE SENSOR ERROR HISTOGRAM (MSOP) Temperature Error (C) G043 Figure 30. Temperature Error (C) 0.5 0.4 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 0 -0.2 0 -0.3 5 -0.4 5 0.3 10 0.2 10 15 0.1 15 20 0 20 25 -0.1 25 30 -0.2 30 -0.5 TA = +125C 48 units from 3 production lots 35 Number of Occurrences 35 40 TA = +70C 48 units from 3 production lots -0.3 40 -0.4 Number of Occurrences 35 40 TA = 0C 48 units from 3 production lots -0.4 40 Number of Occurrences G040 Figure 26. G045 Figure 31. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 11 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C and VDD = 3.3 V, unless otherwise noted. TEMPERATURE SENSOR ERROR vs AMBIENT TEMPERATURE (QFN) 1 80 Average Temperature Error Average 3 sigma Average 6 sigma 0.8 0.6 TA iC 94 units from production. 70 Number of Occurrences 0.4 0.2 0 -0.2 -0.4 -0.6 60 50 40 30 20 10 -0.8 -1 C007 0.5 0.4 0.3 0.2 120 0.1 100 0 80 -0.1 20 40 60 Temperature (C) -0.2 0 -0.3 -20 -0.5 0 -40 -0.4 Temperature Error (C) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) Temperature Error (C) Figure 33. TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) 80 80 0.5 0.4 0.3 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 0 -0.2 0 -0.3 10 -0.4 10 0.2 20 0.1 20 30 0 30 40 -0.1 40 50 -0.2 50 60 -0.3 Number of Occurrences 60 Temperature Error (C) Temperature Error (C) C002 C003 Figure 34. Figure 35. TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) TEMPERATURE SENSOR ERROR HISTOGRAM (QFN) 80 80 Temperature Error (C) C004 Figure 36. Temperature Error (C) 0.5 0.4 0.3 -0.5 0.5 0.4 0.3 0.2 0.1 0 -0.1 0 -0.2 0 -0.3 10 -0.4 10 0.2 20 0.1 20 30 0 30 40 -0.1 40 50 -0.2 50 60 -0.3 60 -0.5 TA = +125C 94 units from production. 70 -0.4 TA = +70C 94 units from production. Number of Occurrences 70 Number of Occurrences TA = +25C 94 units from production. 70 -0.4 TA = 0C 94 units from production. -0.5 Number of Occurences 70 12 C001 Figure 32. C006 Figure 37. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 OVERVIEW The ADS1118 is a very small, low-power, 16-bit, delta-sigma () analog-to-digital converter (ADC). The ADS1118 is extremely easy to configure and design into a wide variety of applications, and allows precise measurements to be obtained with very little effort. Both experienced and novice users of data converters find designing with the ADS1118 family to be intuitive and problem-free. The ADS1118 consists of a ADC core with adjustable gain, an internal voltage reference, a clock oscillator, and an SPI. This device is also a highly linear and accurate temperature sensor. All of these features are intended to reduce required external circuitry and improve performance. Figure 38 shows the ADS1118 functional block diagram. VDD Device Voltage Reference MUX AIN0 Gain = 2/3, 1, 2, 4, 8, or 16 CS SCLK AIN1 16-Bit DS ADC PGA SPI Interface DIN DOUT/DRDY AIN2 Oscillator AIN3 Temperature Sensor GND Figure 38. ADS1118 Functional Block Diagram The ADS1118 ADC core measures a differential signal, VIN, that is the difference of AINP and AINN. The converter core consists of a differential, switched-capacitor modulator followed by a digital filter. This architecture results in a very strong attenuation in any common-mode signals. Input signals are compared to the internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the input voltage. The ADS1118 has two available conversion modes: single-shot mode and continuous conversion mode. In single-shot mode, the ADC performs one conversion of the input signal upon request and stores the value to an internal conversion register. The device then enters a power-down state. This mode is intended to provide significant power savings in systems that require only periodic conversions or when there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins a conversion of the input signal as soon as the previous conversion is completed. The rate of continuous conversion is equal to the programmed data rate. Data can be read at any time and always reflect the most recently completed conversion. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 13 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com MULTIPLEXER The ADS1118 contains an input multiplexer, as shown in Figure 39. Either four single-ended or two differential signals can be measured. Additionally, AIN0, AIN1, and AIN2 may be measured differentially to AIN3. The multiplexer is configured by three bits (MUX[2:0], bits 14-12) in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer. VDD Device AIN0 VDD GND AINP AIN1 AINN VDD GND AIN2 VDD GND AIN3 GND GND Figure 39. ADS1118 MUX When measuring single-ended inputs, note that the negative range of the output codes is not used. These codes are intended for measuring negative differential signals, such as (AINP - AINN) < 0. Electrostatic discharge (ESD) diodes to VDD and GND protect the ADS1118 inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range given in Equation 1: GND - 0.3 V < AINx < VDD + 0.3 V (1) If the voltages on the input pins can possibly violate these conditions, external Schottky clamp diodes and series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings table). Although the analog inputs can support signals marginally above supply, under no circumstances should any analog or digital input or output be driven to greater than 5.5 V with respect to the GND pin. Also, overdriving one unused input on the ADS1118 may affect conversions currently taking place on other input pins. If overdriving unused inputs is possible, TI recommends clamping the signal with external Schottky diodes. 14 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 ANALOG INPUTS The ADS1118 uses a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The capacitors used are small, and to external circuitry, the average loading appears resistive. This structure is shown in Figure 40. The resistance is set by the capacitor values and the rate at which they are switched. Figure 41 shows the on/off setting of the switches illustrated in Figure 40. During the sampling phase, switches S1 are closed. This event charges CA1 to AINP, CA2 to AINN, and CB to (AINP - AINN). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the ADS1118 analog inputs. The average value of this current can be used to calculate the effective impedance (Reff), where Reff = VIN / IAVERAGE. 0.7V CA1 AINP S1 ZCM S2 0.7V Equivalent Circuit AINP CB S1 ZDIFF S2 AINN AINN 0.7V ZCM CA2 fCLK = 250kHz 0.7V Figure 40. Simplified Analog Input Circuit tSAMPLE ON S1 OFF ON S2 OFF Figure 41. S1 and S2 Switch Timing for Figure 40 The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the PGA gain setting, but is approximately 6M for the default PGA gain setting. In Figure 40, the common-mode input impedance is ZCM. The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the PGA gain setting. In Figure 40, the differential input impedance is ZDIFF. Table 1 describes the typical differential input impedance. Table 1. Differential Input Impedance FS (V) (1) (1) 6.144 (1) DIFFERENTIAL INPUT IMPEDANCE 22 M 4.096(1) (1) 15 M 2.048 4.9 M 1.024 2.4 M 0.512 710 k 0.256 710 k This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3V be applied to this device. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 15 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com The typical value of the input impedance cannot be neglected. Unless the input source has a low impedance, the ADS1118 input impedance may affect the measurement accuracy. For sources with high output impedance, buffering may be necessary. Note that active buffers introduce noise, and also introduce offset and gain errors. All of these factors should be considered in high-accuracy applications. Because the clock oscillator frequency drifts slightly with temperature, the input impedances also drift. For many applications, this input impedance drift can be ignored, and the values given in Table 1 for typical input impedance are valid. FULL-SCALE INPUT A programmable gain amplifier (PGA) is implemented before the ADS1118 core. The PGA is configured by three bits (PGA[2:0], bits 11-9) in the Config register and can be set to gains of 2/3, 1, 2, 4, 8, and 16. Table 2 shows the corresponding full-scale (FS) ranges. However, analog input voltages may never exceed the analog input voltage limits given in the Electrical Characteristics table. In case a supply voltage of VDD greater than 4 V is used, the 2/3 PGA setting allows input voltages to extend up to the supply. Note though that in this case, or whenever the supply voltage is less than the FS range (for example, VDD = 3.3 V and PGA = 1), a full-scale ADC output code cannot be obtained. This inability means that some dynamic range is lost. Table 2. PGA Gain and Corresponding Full-Scale Range (1) 16 PGA SETTING FS (V) 2/3 6.144 (1) 1 4.096 (1) 2 2.048 4 1.024 8 0.512 16 0.256 This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3 V be applied to this device. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 DATA FORMAT The ADS1118 provides 16 bits of data in binary twos complement format. The positive full-scale input produces an output code of 7FFFh and the negative full-scale input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 3 summarizes the ideal output codes for different input signals. Figure 42 shows code transitions versus input voltage. Table 3. Input Signal versus Ideal Output Code INPUT SIGNAL, VIN (AINP - AINN) 15 FS (2 IDEAL OUTPUT CODE (1) 15 - 1)/2 7FFFh +FS/215 0001h 0 0 15 -FS/2 FFFFh -FS (1) 8000h Excludes the effects of noise, INL, offset, and gain errors. 0x7FFF 0x0001 0x0000 0xFFFF 1/4 Output Code 1/4 0x7FFE 0x8001 0x8000 1/4 -FS 2 15 0 Input Voltage (AINP - AINN) -1 -FS 2 FS 1/4 15 2 15 FS 2 -1 15 Figure 42. ADS1118 Code Transition Diagram Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 17 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com TEMPERATURE SENSOR The temperature measurement mode of the ADS1118 is configured as a 14-bit result when enabled. Two bytes must be read to obtain data. The first byte is the most significant byte (MSB), followed by a second byte, the least significant byte (LSB). The first 14 bits are used to indicate temperature. That is, the 14-bit temperature result is left-justified within the 16-bit result register and the last two bits always read back as '0'. One 14-bit LSB equals 0.03125C. Negative numbers are represented in binary twos complement format. Table 4. 14-bit Temperature Data Format TEMPERATURE (C) DIGITAL OUTPUT (BINARY) HEX 128 01 0000 0000 0000 1000 127.96875 00 1111 1111 1111 0FFF 100 00 1100 1000 0000 0C80 80 00 1010 0000 0000 0A00 75 00 1001 0110 0000 0960 50 00 0110 0100 0000 0640 25 00 0011 0010 0000 0320 0.25 00 0000 0000 1000 0008 0 00 0000 0000 0000 0000 -0.25 11 1111 1111 1000 3FF8 -25 11 1100 1110 0000 3CE0 -55 11 1001 0010 0000 3920 Converting from Temperature to Digital Codes For positive temperatures (for example, +50C): Twos complement is not performed on positive numbers. Therefore, simply convert the number to binary code in a 14-bit left justified format with the MSB = 0 to denote the positive sign. Example: (+50C)/(0.03125C/count) = 1600 = 0640h = 00 0110 0100 0000 For negative temperatures (for example -25C): Generate the twos complement of a negative number by complementing the absolute binary number and adding 1. Then denote the negative sign with the MSB = 1. Example:(|-25C|)/(0.03125C/count) = 800 = 0320h = 00 0011 0010 0000 Twos complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000 Converting from Digital Codes to Temperature To convert from digital codes to temperature, first check whether the MSB is a '0' or a '1'. If the MSB is a '0', simply multiply the decimal code by 0.03125C to obtain the result. If the MSB = 1, subtract '1' from the result and complement all of the bits. Then multiply the result by -0.03125C. Example: ADS1118 reads back 0960h: 0960h has an MSB = 0. (0960h) x (0.03125C) = (2400) x (0.03125C) = +75C Example: ADS1118 reads back 3CE0h: 3CE0h has an MSB = 1. Complement the result: 3CE0h 0320h (0320h) x (-0.03125C) = (800) x (-0.03125C) = -25C 18 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 ALIASING As with any data converter, if the input signal contains frequencies greater than half the data rate, aliasing occurs. To prevent aliasing, the input signal must be bandlimited. However, some signals are inherently bandlimited. For example, the output of a thermocouple (which has a limited rate of change) is inherently bandlimited. Nevertheless, these signals can still contain noise and interference components. These components can fold back into the sampling band in the same way as with any other signal. The ADS1118 digital filter provides some attenuation of high-frequency noise, but the frequency response of this 1st-order sinc filter cannot completely replace an anti-aliasing filter. For a few applications, some external filtering may be required; in such instances, a simple RC filter is adequate. When designing an input filter circuit, be sure to take into account the interaction between the filter network and the ADS1118 input impedance. TI recommends keeping the filter resistance value below 1 k. RESET AND POWER-UP When the ADS1118 powers up, a reset is performed. As part of the reset process, the ADS1118 sets all of its bits in the Config register to the respective default settings. By default, the ADS1118 enters a power-down state at start-up. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS1118 is intended to relieve systems with tight power-supply requirements from encountering a surge during power-up. OPERATING MODES The ADS1118 operates in one of two modes: continuous conversion or single-shot mode. The MODE bit in the Config register selects the respective operating mode. Continuous Conversion Mode In continuous conversion mode (MODE bit set to '0'), the ADS1118 continuously performs conversions. When a conversion completes, the ADS1118 places the result in the Conversion register and immediately begins another conversion. Power-Down (Single-Shot Mode) When the MODE bit in the Config register is set to '1', the ADS1118 enters power-down state and is configured to operate in single-shot mode. This condition is also the default state that the ADS1118 enters when power is first applied. In power-down state, the ADS1118 consumes no more than 2 A of current. During this time, the device responds to commands, but does not perform any data conversions. The ADS1118 is held in power-down state until a '1' is written to the SS bit in the Config register. When the SS bit is asserted, the device powers up, resets the SS bit to '0', and starts a single conversion. When conversion data are ready for retrieval, the device powers down again. Writing a '1' to the SS bit while a conversion is ongoing has no effect. To exit this mode, simply write a '0' to the MODE bit in the Config register to start operating in continuous conversion mode. DUTY CYCLING FOR LOW POWER The noise performance of a ADC generally improves when lowering the output data rate because more samples of the internal modulator can be averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the ADS1118 supports duty cycling that can yield significant power savings by periodically requesting high data rate readings at an effectively lower data rate. For example, an ADS1118 in power-down state with a data rate set to 860 SPS can be operated by a microcontroller that instructs a single-shot conversion every 125 ms (8 SPS). Because a conversion at 860 SPS only requires approximately 1.2 ms, the ADS1118 enters power-down state for the remaining 123.8 ms. In this configuration, the ADS1118 consumes approximately 1/100th the power that it otherwise would consume in continuous conversion mode. The duty cycling rate is completely arbitrary and is defined by the master controller. The ADS1118 offers lower data rates that do not implement duty cycling and also offers improved noise performance if required. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 19 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com SERIAL INTERFACE The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three signals (in which case CS may be tied low). The interface is used to read conversion data, read and write registers, and control device operation. CHIP SELECT (CS) The chip select (CS) selects the ADS1118 for SPI communication. This feature is useful when multiple devices share the same serial bus. CS must remain low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state, DOUT/DRDY cannot provide data ready indication. In situations where multiple devices are present and DOUT/DRDY must be monitored, CS must be periodically lowered. At this point, the DOUT/DRDY pin either immediately goes high to indicate that no new data are available, or DOUT/DRDY immediately goes low to indicate that new data are present in the Conversion register and are available for transfer. New data can be transferred at any time without concern of data corruption. When a transmission starts, the current result is locked into the output shift register and does not change until the communication completes. This system avoids any possibility of data corruption. If the ADS1118 does not share the serial bus with another device, CS may be tied low. SERIAL CLOCK (SCLK) The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and DOUT/DRDY pins into and out of the ADS1118. Even though the input has hysteresis, TI recommends keeping SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 28 ms, the serial interface resets and the next SCLK pulse starts a new communication cycle. This timeout feature can be used to recover communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK low. DATA INPUT (DIN) The data input pin (DIN) is used along with SCLK to send data to the ADS1118. The device latches data on DIN on the SCLK falling edge. The ADS1118 never drives the DIN pin. DATA OUTPUT AND DATA READY (DOUT/DRDY) The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from the ADS1118. DOUT/DRDY is also used to indicate that a conversion is completed and new data are available. This pin transitions low when new data are ready for retrieval. The data ready signal can be used to trigger a microcontroller to start reading data from the ADS1118. Data on DOUT/DRDY are shifted out on the SCLK rising edge. In continuous conversion mode, DOUT/DRDY transitions high again 8 s before the next data ready signal (when DOUT/DRDY asserts low) if no data are retrieved from the device. This transition is shown in Figure 43. Data transmission must complete before DOUT/DRDY automatically returns high. By default, DOUT/DRDY is configured with a weak pull-up resistor if CS is high. This feature is intended to reduce the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master device. Alternatively, the ADS1118 DOUT/DRDY pin can be configured in the Config register to go to a high-impedance state when CS is high. If the ADS1118 does not share the serial bus with another device, CS may be tied low. CS(1) SCLK DOUT/DRDY 8 s Hi-Z DIN (1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 43. DOUT/DRDY Behavior Without Data Retrieval in Continuous Conversion Mode 20 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 REGISTERS The ADS1118 has two registers that are accessible via the SPI port. The Conversion register contains the result of the last conversion. The Config register allows the user to change the ADS1118 operating modes and query the status of the devices. Conversion Register The 16-bit Conversion register contains the result of the last conversion in binary twos complement format. Following power-up, the Conversion register is cleared to '0', and remains '0' until the first conversion is completed. The register format is shown in Table 5. Table 5. Conversion Register (Read-Only) BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Config Register The 16-bit Config register can be used to control the ADS1118 operating mode, input selection, data rate, PGA settings, and temperature sensor mode. The register format is shown in Table 6. Table 6. Config Register (Read/Write) 15 14 13 12 11 10 9 8 SS MUX2 MUX1 MUX0 PGA2 PGA1 PGA0 MODE 7 6 5 4 3 2 1 0 DR2 DR1 DR0 TS_MODE PULL_UP_EN NOP1 NOP0 NOT USED Default = 058Bh. Bit 15 SS: Single-shot conversion start This bit is used to start a single conversion. SS can only be written when in power-down state and has no effect when a conversion is ongoing. When writing: 0 = No effect 1 = Start a single conversion (when in power-down state) Always reads back as '0' (default). Bits[14:12] MUX[2:0]: Input multiplexer configuration These bits configure the input multiplexer. 000 = AINP 001 = AINP 010 = AINP 011 = AINP Bits[11:9] is is is is AIN0 AIN0 AIN1 AIN2 and AINN is and AINN is and AINN is and AINN is AIN1 (default) AIN3 AIN3 AIN3 100 = AINP 101 = AINP 110 = AINP 111 = AINP is is is is AIN0 AIN1 AIN2 AIN3 and AINN is and AINN is and AINN is and AINN is GND GND GND GND PGA[2:0]: Programmable gain amplifier configuration These bits configure the programmable gain amplifier. 000 = FS 001 = FS 010 = FS 011 = FS (1) is is is is 6.144 4.096 2.048 1.024 V (1) V (1) V (default) V 100 = FS 101 = FS 110 = FS 111 = FS is is is is 0.512 0.256 0.256 0.256 V V V V This parameter expresses the full-scale range of the ADC scaling. In no event should more than VDD + 0.3 V be applied to this device. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 21 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 Bit 8 www.ti.com MODE: Device operating mode This bit controls the ADS1118 operating mode. 0 = Continuous conversion mode 1 = Power-down and single-shot mode (default) Bits[7:5] DR[2:0]: Data rate These bits control the data rate setting. 000 = 8 SPS 001 = 16 SPS 010 = 32 SPS 011 = 64 SPS Bit 4 100 = 128 SPS (default) 101 = 250 SPS 110 = 475 SPS 111 = 860 SPS TS_MODE: Temperature sensor mode This bit configures the ADC to convert temperature or input signals. 0 = ADC mode (default) 1 = Temperature sensor mode Bit 3 PULL_UP_EN: Pull-up enable This bit enables a weak pull-up resistor on the DOUT/DRDY pin. When enabled, a 400-k resistor connects the bus line to supply. When disabled, the DOUT/DRDY pin floats. 0 = Pull-up resistor disabled on DOUT/DRDY pin 1 = Pull-up resistor enabled on DOUT/DRDY pin (default) Bits[2:1] NOP[1:0]: No operation The NOP[1:0] bits control whether data are written to the Config register or not. In order for data to be written to the Config register, the NOP[1:0] bits must be '01'. Any other value results in a NOP command. DIN can be held high or low during SCLK pulses without data being written to the Config register. 00 01 10 11 Bit 0 = Invalid data, do not update the contents of the Config register = Valid data, update the Config register (default) = Invalid data, do not update the contents of the Config register = Invalid data, do not update the contents of the Config register Not used Always reads '1' 22 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 DATA RETRIEVAL Data can be written to and read from the ADS1118 in the same manner in single-shot mode as in continuous conversion mode, without having to issue any commands. The mode in which ADS1118 operates in can be selected by the MODE bit in the Config register. Setting the MODE bit to '0' puts the device in continuous conversion mode. In this mode, the device is constantly starting new conversions even when CS is high. When configured for single-shot mode by setting the MODE bit to '1,' a new conversion only starts by writing a '1' to the SS bit. The conversion data are always buffered, and retain the current data until replaced by new conversion data. Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low, indicating that new conversion data are ready, the conversion data are read by shifting the data out on DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN on the SCLK falling edge. The ADS1118 also offers the possibility of direct readback of the Config register settings in the same data transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register data readback is used) or 16 bits. The short 16-bit cycle can only be used when the CS line can be controlled and is not permanently tied low. 32-Bit Data Transmission Cycle As shown in Figure 44, the data in a 32-bit data transmission cycle consists of four bytes: two bytes for the conversion result and an additional two bytes for the Config register readback. The MSB is always read first. Direct Config register data readback is only functional for the first two bytes that are written to the device in a data transmission cycle. Therefore, TI recommends writing the same Config register setting twice during one cycle. CS(1) 1 9 17 25 SCLK DOUT/DRDY Hi-Z DIN DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready (1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 44. 32-Bit Data Transmission Cycle with Config Register Readback Alternatively, DIN can be held either low or high for the second half of the data transmission cycle, as shown in Figure 45. When the ADS1118 is configured for continuous conversion mode by setting the MODE bit to '0', DIN can even be held either low or high for the entire transmission cycle as well if no changes to the device setup must be made. CS(1) 1 9 17 25 SCLK DOUT/DRDY DIN Hi-Z DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Next Data Ready (1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available. Figure 45. 32-Bit Data Transmission Cycle: DIN Held Low Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 23 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com 16-Bit Data Transmission Cycle If Config register data are not required to be readback, the ADS1118 conversion data can also be clocked out in a short 16-bit data transmission cycle, as shown in Figure 46. Therefore, CS must be taken high after the 16th SCLK cycle. Taking CS high resets the SPI interface. The next time CS is taken low, data transmission starts with the currently buffered conversion result on the first SCLK rising edge. If DOUT/DRDY is low when data retrieval starts, the conversion buffer is already updated with a new result. Otherwise, if DOUT/DRDY is high, the same result from the previous data transmission cycle is read. CS 1 9 1 9 SCLK DOUT/DRDY DIN Hi-Z DATA MSB DATA LSB DATA MSB DATA LSB CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB Figure 46. 16-Bit Data Transmission Cycle 24 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 APPLICATION INFORMATION The following sections give example circuits and suggestions for using the ADS1118 in various situations. BASIC CONNECTIONS AND LAYOUT CONSIDERATIONS For many applications, connecting the ADS1118 is simple. A basic connection diagram for the ADS1118 is shown in Figure 47. Most microcontroller SPI peripherals can operate with the ADS1118. The interface operates in SPI mode 1 where CPOL = 0 and CPHA = 1. In SPI mode 1, SCLK idles low and data are launched or changed only on SCLK rising edges; data are latched or read by the master and slave on SCLK falling edges. Details of the SPI communication protocol employed by the ADS1118 can be found in the SPI Timing Characteristics section. Although not required, placing 49.9- resistors in series with all of the digital pins is good practice. This resistance smooths sharp transitions, suppresses overshoot, and offers some overvoltage protection. Care must be taken to still meet all SPI timing requirements because the additional resistors interact with the bus capacitances present on the digital signal lines. Device 10 VDD DIN Microcontroller or Microprocessor with SPI Port 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 5 DOUT DIN Inputs Selected from Configuration Register CS SCLK Figure 47. Typical Connections of the ADS1118 The fully-differential input of the ADS1118 is ideal for connecting to differential sources (such as thermocouples and thermistors) with a moderately low source impedance. Although the ADS1118 can read bipolar differential signals, the device cannot accept negative voltages on either input because every pin on the ADS1118 employs the use of ESD protection diodes. In the event that an input exceeds supply or drops below ground, these diodes begin to turn on. Therefore, thinking of the ADS1118 positive input as noninverting, and of the negative input as inverting may be helpful. The 0.1-F bypass capacitor supplies the momentary bursts of extra current required from the supply when the ADS1118 is converting. This bypass capacitor should be placed as close to the device as possible. For very sensitive systems, or systems in harsh noise environments, avoiding the use of vias for connecting the bypass capacitor may offer superior bypass and noise immunity. Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 25 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com TI recommends employing best design practices when laying out a printed circuit board (PCB) for both analog and digital components. This recommendation generally means that the layout should separate analog components [such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching regulators]. An example of good component placement is shown in Figure 48. While Figure 48 provides a good example of component placement, the best placement for each application is unique to the geometries, components, and PCB fabrication capabilities being employed. That is, there is no single layout that is perfect for every design and careful consideration must always be used when designing with any analog components. Ground fill or Ground plane Supply Generation Interface Tranceiver Microprocessor ADS1118 Optional: Split Ground Cut Signal Conditioning (RC filters and amplifiers) Ground fill or Ground plane Optional: Split Ground Cut Ground fill or Ground plane Connector or Antenna Ground fill or Ground plane Figure 48. System Component Placement The use of split analog and digital ground planes is not necessary for improved noise performance (although for thermal isolation this option is a worthwhile consideration). However, the use of a solid ground plane or ground fill in PCB areas with no components is essential for optimum performance. If the system being used employs a split digital and analog ground plane, TI generally recommends that the ground planes be connected together as close to the ADS1118 as possible. TI also strongly recommends that digital components, especially RF portions, be kept as far as practically possible from analog circuitry in a given system. Additionally, minimize the distance that digital control traces run through analog areas and avoid allowing these traces to be near sensitive analog components. Digital return currents usually flow through a ground path that is as close to the digital path as possible. If a solid ground connection to a plane is not available, these currents may find paths back to the source that interfere with analog performance. The implications that layout has on the temperature sensing functions are much more significant than they are for the ADC functions. Details on layout considerations for the temperature sensor can be found in the Thermocouple Measurement with Cold Junction Compensation section. For a detailed layout example, refer to the ADS1118EVM User's Guide (SBAU184). 26 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 CONNECTING MULTIPLE DEVICES Connecting multiple ADS1118s to a single bus is simple. SCLK, DIN, and DOUT/DRDY can be safely shared by using a dedicated chip-select (CS) for each SPI-enabled device. By default, when CS goes high for the ADS1118, DOUT/DRDY is pulled up to the supply of the ADS1118 by a weak 400 k resistor. This feature is intended to prevent DOUT/DRDY from floating near mid-rail and causing excess current leakage on a microcontroller input. If the PULL_UP_EN bit in the Config register is set to '0', the DOUT/DRDY pin enters a 3state mode when CS transitions high. The ADS1118 cannot issue a data ready pulse on DOUT/DRDY when CS is high. In order to evaluate when a new conversion is ready from the ADS1118 when using multiple devices, the master can periodically drop CS to the ADS1118. When CS goes low, the DOUT/DRDY pin immediately drives either high or low. If the DOUT/DRDY line drives low on a low CS, new data are currently available for clocking out at any time. If the DOUT/DRDY line drives high, no new data are available and the ADS1118 returns the last read conversion result. Valid data can be retrieved from the ADS1118 at anytime without concern of data corruption. If a new conversion becomes available during data transmission, it is not available for readback until a new SPI transmission is initiated. Microcontroller or Microprocessor Device SCLK DIN 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 DOUT 3 GND AIN3 7 CS1 4 AIN0 AIN2 6 AIN1 5 CS2 Device 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 AIN2 6 4 AIN0 AIN1 5 NOTE: Power and input connections omitted for clarity. Figure 49. Connecting Multiple ADS1118s Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 27 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com USING GPIO PORTS FOR COMMUNICATION Most microcontrollers have programmable input/output (I/O) pins that can be set in software to act as inputs or outputs. If an SPI controller is not available, the ADS1118 can be connected to GPIO pins and the SPI bus protocol can be simulated. Using GPIO pins to generate the SPI interface only requires that the pins be configured as push or pull inputs or outputs. Furthermore, if the SCLK line is held low for more than 28 ms, the communication times out. This condition means that the GPIO ports must be capable of providing SCLK pulses with no more than 28 ms between pulses. SINGLE-ENDED INPUTS Although the ADS1118 has two differential inputs, the device can easily measure four single-ended signals. Figure 50 shows a single-ended connection scheme. The ADS1118 is configured for single-ended measurement by configuring the MUX to measure each channel with respect to ground. Data are then read out of one input based on the selection in the Config register. The single-ended signal can range from 0 V up to positive supply or +FS, whichever is lower. Negative voltages cannot be applied to this circuit because the ADS1118 can only accept positive voltages with respect to ground. The ADS1118 does not loose linearity within the input range. The ADS1118 offers a differential input voltage range of FS. The single-ended circuit shown in Figure 50 however only uses the positive half of the ADS1118 FS input voltage range because it does not produce differentially negative inputs. Because only half of the FS range is used, one bit of resolution is lost. For optimal noise performance, TI recommends using differential configurations whenever possible. Differential configurations maximize the dynamic range of the ADC and provide strong attenuation of common-mode noise. VDD Device 10 DIN 1 SCLK DOUT/DRDY 9 2 CS VDD 8 3 GND AIN3 7 4 AIN0 AIN2 6 0.1mF (typ) AIN1 5 Inputs Selected from Configuration Register NOTE: Digital pin connections omitted for clarity. Figure 50. Measuring Single-Ended Inputs The ADS1118 is also designed to allow AIN3 to serve as a common point for measurements by adjusting the MUX configuration. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration the ADS1118 can operate with inputs where AIN3 serves as the common point. This ability improves the usable range over the single-ended configuration because it allows negative differential voltages when GND < AIN3 < VDD; however, it does not offer attenuation of common-mode noise. 28 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 THERMOCOUPLE MEASUREMENT WITH COLD JUNCTION COMPENSATION For an independent, two-channel thermocouple system, Figure 51 shows the basic connections. This circuit contains a simple low-pass, anti-aliasing filter, mid-point bias, and open detection. While the digital filter of the ADS1118 strongly attenuates high-frequency components of noise, TI generally recommends providing a firstorder passive RC filter to further improve this performance. The differential RC filter formed by the 500 resistors (RDIFFA and RDIFFB) and the 1 F (CDIFF) capacitor offers a cutoff frequency of approximately 320 Hz. Additional filtering can be achieved by increasing the differential capacitor or the resistance values. However, avoid increasing the filter resistance beyond 1 k because the effects of the interaction with ADCs input impedance begin to affect the linearity and gain error of the ADS1118. Because of the high sampling rates supported by the ADS1118, simple post digital filtering in a microcontroller can alleviate the requirements of the analog filter and can also offer the flexibility to implement filter notches at 50 Hz or 60 Hz. Two 0.1 F (CCMA and CCMB) capacitors are also added to offer attenuation of high-frequency common-mode noise components. Because mismatches in the common-mode capacitors cause differential noise, TI recommends that the differential capacitor be at least an order of magnitude (10x) larger than the common-mode capacitors. 3.3 V 0.1 PF GND 3.3 V GND RDIFFA 500 RPU = 1 M CCMA = 0.1 PF AIN0 VDD CDIFF = 1 PF AIN1 RDIFFB 500 RPD = 1 M Voltage Reference (PGA Gain = 16) 256mV FS CCMB = 0.1 PF SCLK GND GND MUX GND 3.3 V DOUT/DRDY Temperature Sensor Oscillator GND RDIFFB 500 GND CS CCMA = 0.1 PF AIN2 CDIFF = 1 PF AIN3 RPD = 1 M Digital Filter and Interface 16-Bit uADC DIN RDIFFA 500 RPU = 1 M PGA CCMB = 0.1 PF GND GND Figure 51. Two-Channel Thermocouple System Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 29 ADS1118 SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 www.ti.com The two 1-M resistors (RPU and RPD) serve two purposes. The first purpose is to offer a common-mode bias near midsupply. Although the ADS1118 does offer the ability to float the common-mode of a signal or connect any of the inputs to a common point such as ground or supply, TI generally recommends avoiding such situations. Connecting one of the inputs to a common point decreases performance by converting common-mode noise into differential signal noise that is not strongly attenuated. The second purpose of the 1-M resistors is to offer a weak pull-up and pull-down for sensor open detection. In the event that a sensor is disconnected, the inputs to the ADC extend to supply and ground and yield a full-scale readout, indicating a sensor disconnection. The procedure to actually achieve cold-junction compensation is simple and can be done in several ways. One way is to interleave readings between the thermocouple inputs and the temperature sensor. That is, acquire one on-chip temperature result for every thermocouple ADC voltage measured. If the cold junction is in a very stable environment, more periodic cold junction measurements may be sufficient. These operations yield two results for every thermocouple measurement and cold junction measurement cycle: the thermocouple voltage VTC and the on-chip temperature TCJC. In order to account for the cold junction, the temperature sensor within the ADS1118 must first be converted to a voltage proportional to the thermocouple currently being used yielding VCJC. This conversion is generally accomplished by performing a reverse lookup on the table being used for the thermocouple voltage to temperature conversion. Then, adding the two voltages yields the thermocouple compensated voltage (VActual), where VCJC + VTC = VActual. VActual is then converted to temperature using the same lookup table as before, yielding TActual. Thermocouple manufacturers usually supply a lookup table with their thermocouples that offer excellent accuracy for linearization of a specific type of thermocouple. The granularity on these lookup tables is generally very precise (at around 1C for each lookup value). To save microcontroller memory and development time, an interpolation technique applied to these values can be used. By choosing 16 to 32 equally-spaced values from the manufacturer's lookup tables over a desired temperature range, using a simple linear approximation of intervals between is generally very precise. 30 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 ADS1118 www.ti.com SBAS457D - OCTOBER 2010 - REVISED OCTOBER 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (February 2013) to Revision D Page * Deleted device graphic ......................................................................................................................................................... 1 * Changed bit 1 to NOP0 in Table 6 ..................................................................................................................................... 21 * Changed NOP bit description in Table 6: changes bits[2:0] to bits [2:1] and changed NOP to NOP[1:0] ......................... 22 Changes from Revision B (August 2012) to Revision C Page * Updated document to current standards .............................................................................................................................. 1 * Changed Single-Shot Mode sub-bullet in Low Current Consumption Features bullet ......................................................... 1 * Changed Internal Temperature Sensor Features bullet ....................................................................................................... 1 * Changed Description section ................................................................................................................................................ 1 * Changed Product Family table ............................................................................................................................................. 2 * Changed conditions for Electrical Characteristics table ....................................................................................................... 3 * Changed Analog Input, Full-scale input voltage range parameter row in Electrical Characteristics table ........................... 3 * Changed footnotes 1 and 2 in Electrical Characteristics table ............................................................................................. 3 * Changed System Performance, Integral nonlinearity and Gain Error test conditions in Electrical Characteristics table ..... 3 * Changed first two Temperature Sensor, Temperature sensor accuracy parameter test conditions in Electrical Characteristics table ............................................................................................................................................................. 3 * Changed Power-Supply Requirements, Supply current parameter test conditions in Electrical Characteristics table ........ 4 * Added QFN (RUG) data to Thermal Information table ......................................................................................................... 4 * Changed Function column name in Pin Descriptions table .................................................................................................. 5 * Changed footnote 3 of Timing Requirements: Serial Interface Timing table ........................................................................ 6 * Updated Figure 3 .................................................................................................................................................................. 7 * Updated Figure 12 ................................................................................................................................................................ 8 * Changed title of Figure 14 to Figure 17 ................................................................................................................................ 8 * Updated Figure 18 and Figure 24 ......................................................................................................................................... 9 * Changed conditions in Figure 27 to Figure 31 ................................................................................................................... 10 * Updated Figure 26 .............................................................................................................................................................. 11 * Changed comments in Figure 33 to Figure 37 ................................................................................................................... 11 * Changed Overview section ................................................................................................................................................. 13 * Changed Multiplexer section .............................................................................................................................................. 14 * Changed Full-Scale Input section ....................................................................................................................................... 16 * Added multiplication points to example equations in Converting from Digital Codes to Temperature section .................. 18 * Changed Aliasing, Reset and Power-Up, Operating Modes, and Duty Cycling for Low Power sections .......................... 19 * Changed Serial Interface, Chip Select, Serial Clock, Data Input, and Data Output and Data Ready sections ................. 20 * Changed Registers section ................................................................................................................................................. 21 * Changed Data Retrieval section ......................................................................................................................................... 23 * Changed Application Information section ........................................................................................................................... 25 * Updated Figure 51 .............................................................................................................................................................. 29 Changes from Revision A (July 2011) to Revision B Page * Added (MSOP) to titles of Figure 26 to Figure 31 .............................................................................................................. 11 * Added Figure 32 to Figure 37 ............................................................................................................................................. 12 Submit Documentation Feedback Copyright (c) 2010-2013, Texas Instruments Incorporated Product Folder Links: ADS1118 31 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) ADS1118IDGSR ACTIVE VSSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BBEI ADS1118IDGST ACTIVE VSSOP DGS 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BBEI ADS1118IRUGR ACTIVE X2QFN RUG 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDQ ADS1118IRUGT ACTIVE X2QFN RUG 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 SDQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS1118IDGSR VSSOP DGS 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 5.3 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.3 1.3 8.0 12.0 Q1 ADS1118IDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 ADS1118IRUGR X2QFN RUG 10 3000 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 ADS1118IRUGT X2QFN RUG 10 250 179.0 8.4 1.75 2.25 0.65 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1118IDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 ADS1118IDGST VSSOP DGS 10 250 195.0 200.0 45.0 ADS1118IRUGR X2QFN RUG 10 3000 203.0 203.0 35.0 ADS1118IRUGT X2QFN RUG 10 250 203.0 203.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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