PRODUCT 128 x 16 bit Electrically Erasable Programmable Rom PART NUMBER BR9020/FFV~RFVRFVMW DESCRIPTION The BR9020-W series are serial EEPROMs that can be connected directly to a serial port and can be erased and written electrically, Writing and reading is perfomed in word units, using four types of operation commands. Communication occurs through CS, SK, DI, and DO pins, WG pin control is used to initiate a write disabled state, enabling these EEPROMs to be used as one-time ROMs. During writing, operation is checked via the internal status check. . APPLICATION General Purpose FEATURES : 128words x 16 bit organization 2kbit serial EEPROM * Single power supply Serial data I/O Self-timed programming cycle with auto-e *Low supply current Active (5V); 2mA (max.) rase Standby (5V); 3uA (max) (CMOS INPUT) Noise filter on the SK pin Write protection when the supply is low Space Saving DIP8/SOP8/SSOP8/MSOP8pin Packages "High reliability CMOS process *100,000 erase/write cycles endurance Provide 10 years of data retention "Easy connection to serial port -"FFFFh stored in all address on shipped ABSOLUTE MAXIMUM _RATINGS(Ta=25C) Parameter Symbol Rating Unit Supply Voltage VCC 0. 3~7.0 V DIP8 800(3K1) Loa, SOP8 450(3K2) Power dissipation Pd SSOPBS8 300(3%3) mV MSOP8 3100K%4) Storage Temperature Tstg 65~125 c Operating Temperature Topr 40~85 C Terminal Voltage _- 0. 3~VectO. 3 V 1 Degradation is done at 8.0mW/C for operation above Ta=25C <2 Degradation is done at 4.5mW/C for operation above Ta=25C %3 Degradation is done at 3.0mW/C for operation above Ta=25C 4 Degradation is done at 3.1mW/C for operation above Ta=25C RECOMMENDED OPERATING CONDITION Parameter Symbol Rating Unit 2. 7~5. 5(WRITE) Supply Voltage vcc 2. 7-~5. B(READ) Vv Input Voltage Vin oO ~ VCCr ELECTRICAL CHARACTERISTICS Unless otherwise specified(Ta=~40~85C, VCC=2. 7~5. 5V) Limit , _ Test Parameter Symbol Min. Typ. Max Unit Condition Circuit 0.3x . Input Low Voltage 1 VIL1 voc V DI Pin Input High Voltage 1 vier | 22% - - Vv | DIPin nput High Voltage voc Input Low Voltage 2 vig | _ 02x | vy 16s,sk,WoP nput Low Voltage VeC ' in Input High Voltage 2 vino | 28 - _ V__ | GS, SK, WC Pin a ome vec mm Output Low Voltage VOL 0 _ 0.4 V 1OL=2.1mA, Fig.-4 . Vcc- . Output High Voltage VOH 04 _ vcc V IOH=-0.4mA Fig.-5 Input Leakage Current Iu -1 - 1 LA | VIN=-0V~VCC Fig.-6 Output Leakage Current | ILO -1 - 1 uA | VOUT=0V~VCC.CS =VCC Fig-7 Icc1 - - 2 . mA | fSK=2MHz,tE/W=10ms (WRITE) | Fig.-8 Operating Current Ic2 - _ 1 mA | fSK=2MHz (READ) Fig.-8 CS,SK,DIWC=VCC Standby Current ISB _ 3 uA DO.R/B=OPEN Fig.-9 Clock Frequency fSK _ _ 2 MHzUnless otherwise specified (Ta=40~85C, VCC=2. 7~3. 3V) Limit . a Test Parameter Symbol Min, Typ. Max. Unit Condition Circuit Input Low Voltage 1 VIL - vie Vv | DIPin Input High Voltage 1 vini | 7% V | DIPin P 6 VGG Input Low Voltage 2 VIL2 _ 0.2x Vv cs SK WC Pin p 6 vec J ; 0.8x =z FT Input High Voltage 2 VIH2 - - V CS, SK, WC Pin vcc Output Low Voltage VOL 0 _ 0.4 V IOL=100uA Fig.-4 ; Vvcc- . Output High Voltage VOH 04 _- VCC Vv JOH=-100uA Fig. -5 Input Leakage Current ILI -1 _ 1 HA | VIN=-O~VCC Fig.-6 Output Leakage Current ILO -1 _ 1 HA VOUT=0~VCC,CS=VCC Fig.-7 ICG - - 1.5 mA | fSK =2MHz,tE/W=10ms (WRITE) | Fig.-8 Operating Current Icc2 - - 0.5 mA | fSK =2MHz (READ) Fig. -8 CS,SK,DLWG=VCC Standby Current ISB - 2 uA DO.R/B=OPEN Fig.-9 Clock Frequency #SK _ _ 2 MHz OThis product is not designed for protection against radioactive rays.DIMENSION 65+03 7.62 3.2+0.2 3.4403 | 0.51Min. Fig.1-1 Outline Dimensions DIP&(BR9020-W)|_| c OTV'Y I | 0.15 0.4+0.1 Lo! \ 2/ ; TEE O $'0+c'9 OFS" | SOP8(BR9020F-W) Fig.1-2 Outline Dimensions(6440.3 Go I+ NO Fh Pe |.0.3Min. > oO > On I+ wo, S | a TL C7 0.1 = 0.22 +0.1 (0.52)/| |0.65 Fig.1-3 Outline Dimensions SSOPB8(BR9020RFV-W)6.4+0.3 8 3 Ny c Nr +H = _ Pie = _ | 4 10.15+0.1 s +] / (0.52),| 0.65 Fig.1-4 Outline Dimensions SSOPB8(BR9020FV-W)+I 0.29 +0.15 0.145 +8-88 ~< M+ + Big ct Ni, 0.22 *8:83| 5] 0.088 2 Fp] 0654S] 0.08 |S LO) Ne OO | | | | | | Fig.1-5 Outline Dimensions MSOP8(BR9020RFVM-W)cs Di DO y " > RB DETECT INSTRUCTION DECODE SUPPLY CONTROL AND CLOCK VOLTAGE GENERATION L HIGH WRITE VOLTAGE wo DISABLE ?| GENERATOR +>| ADDRESS ADDRESS INSTRUCTION BUFFER | 7bit ) pecoRDER [## REGISTER 2 048bit 3 DATA R/W EEPROM REGISTER (am) AMPS Fig.-2 Block DiagramPIN CONFIGURATIONS VCC R/B WC GND WG GND DO DI re a | C1 rr 1 O LILITIT 4 LIC oat BR9020W:DIP8 TERMINAL FUNCTION R/B VCC CS SK BR9OZ0FVW:SSOP8 BR9OZOFW:SOP8 Fig.-3 Pin Configurations vCC R/B WG GND Pit if if O a cS) SK ODI DO BRSO020RFVM-W:MSOP8 BR9O2Z0RFVW:SSOP8 Terminal IN/ our Function vec _ Power Supply GND _ Ground (OV) cs INPUT Chip Select Input sk INPUT Serial Data Ciock Input DI INPUT Serial Data Input (Op code, address) DOG OUTPUT Serial Data Output WC INPUT Write Contral Input RB OUTPUT READY/BUSY Status OutputOTEST CIRCUIT VCC | [OL vec <_ DO GND VOL Set Output Pin to Low Fig.-4 Output Low voltage test circuit vcc | IOH voc _> R/B,DO GND VOH Set Output Pin to High Fig-5 Output High voltage test circuit Voc ; ILI vec GS,SK,DIWC GND Fig.-6 Input leakage current test circuitOTEST CIRCUIT Vcc vcc VGC 1L0 cs DO GND | voov-vee Fig? Output leakage current test circuit Vcc Icc SK Clock jsk VCC READ/WRITE COMMAND Input DI R/BDO t+~"~ OPEN vIL 1s GND -Fig.-8 Operating Current test circuit voc VCC CC ISB vec 5K vec = WG | Di R/B,DO [ OPEN cs GND Fig.-9 Standby current test circuitINSTRUCTION CODE Instruction Start Bit Op Code Address Data DO Di - B14 B15 101 READ 010 1000 AO Ai A2 A3 A4 A5 AB 0 (READ DATA) BDO D1 -~ B14 B15 WRITE 1010 0100 AO Al A2 A3 Ad A5 AB 0 (WRITE DATA) Write Enable(WEN) 1010 0011 * * ok Ok Ok OR * Write Disable(WDS) 1010 0000 * oe Ok ke kk ** Means either VIH or VIL Address and data must be transferred from LSB. SYNCHRONOUS DATA INPUT OUTPUT TIMING cs DIS <-> 0 MMMM ___ > CL Pp Ke tPD > tOH DO Pe : > WG / \ Fig.-10 Synchronous data input output timing Olnput Data is clocked into the DI pin on the rising edge of the clock SK. QOutput data is clocked out on the falling edge of the SK clock. OThe WC pin does not have any affect on the READ, WEN and WDS operations. OBetween instructions, CS must be brought High for greater than the minimum of tCS. If CS is maintained Low, the next instruction isn't detected.AC OPERATION CHARACTERISTICS(Ta=40~85C, VCC=2. 7~5. 5V) Parameter Symbol Min. Typ. Max. Unit Chip Select Setup Time ; tCSS 100 - - ns Chip Select Hold Time tCSH 100 _ _ ns Data In Setup Time tDIS 100 | | ns Data In Hold Time tDIH 100 - - ns Delay to Output High tPD1 _ _- 150 ns Delay to Output Low tPDO _ _ 150 ns Self-Timed Program Cycle tE/W _ _ -10 ms Minimum Chip Select High Time tcs 250 - - | ns Data Output Disable Time (From cs) tOH 0 =- 150 ns Glock High Time . . tWH 230 _ ns Clock Low Time | tWL 230 - - ns Write Control Setup Time twcs 0 _ _ ns Write Control Hold Time tWCH 0 _ _ ns Glock High to Output READY/BUSY Status tsV | 150 | nsTIMING CHART 1. WRITE Enable/Disable 4H L {| ENABLE =11 cs H \ DISABLE = 00 / Fig.-11 WRITE Enable and Disable Cycle Timing OWhen power is first applied, the device has been held in a reset status, with respect to the write enable, in the same way the write disable (WDS) instruction is executed. Before the write instruction is executed, the device must be received the write enable (WEN) instruction. Once the device is done, the device remains programmable until the write disable (WDS) instruction is executed or the supply is removed from the device. Olt is unnecessary to add the clock after 16th clock. If the device is recieved the clock, the device ignores the clock. OAs both of the enable and disable instructions dont depend on the status of the WG pin, the state of WG isn't cared during the instruction. OThe instruction is recognized after the rising edge of 8th clock for the address following 8clocks for the opcode, but the specified address isnt cared during the instructions.2. READ INSTRUCTION "TALL LAL ) " - SK 1 4 8 16 | 2 | | | L tos 28 H \ aan i i pie? STANDBY H DI His \ofs\of1\ 0 0 o /aok Kas \ a6} & L hy t) Hi-Z oe \ 5 Gis - % Do D15, DO po forskook Xt ?tOH RB oH Read Data(n) Read Data(n+1) wc HorL Fig-12 READ Cycle Timing On the falling edge of 16th clock, the data stored in the specified address (n) is clocked out of the BO pin. __ The output DO is toggled after the internal propagation tPDO or tPD1 on the falling edge of SK. During PDO or tPD1, the data is the previous data or unstable, and to take in the data, tPD is needed(Refer to Fig -10 Synchronous data input output timing.) , OThe data stored in the next address is clocked out of the device on the falling edge of 32nd clock. The data stored in the upper address every 16 clocks is output sequentially by the continual SK input. Also the read operation is reset by CS High.3. WRITE INSTRUCTION _ oH SK 1 4 L H cs | L H DI ih o/1\o0 of 1 Hi72Z ita ut i Hi-Z DO iy y tSV i tE/W R68 H fy be \, fo 7 A WS mn we , tWCH Till we Dh : s te Sy Fig.-13 WRITE Cycle Timing ODuring the write instruction, CS must be brought Low. However once the write operation started, cs may be either High or Low. But in the case of connecting the WC pin to the CS pin, CS and WC must be brought Low during programming cycle. (If the WC pin is brought High during the write cycle, the write operation is halted. In that case, the data of the specified address is not guaranteed. It is necessary to rewrite it.) OAfter the R/B pin changed Busy to Ready, once CS is brought High, then cs keep Low, which means the status of being able to accept an instruction. The device can take in the input from SK and DI, but in the case of keeping CS Low without being brought High once, the input is canceled until being cs High once. OAt the rising edge of 32nd clock, the R/B pin will be driven Low after the specified time delay(tSV). ODuring programming, R/B is tied to Low by the device (On the rising edge of SK taken in the last data (D15), internal timer starts and automatically finished after the data of memory cell is written spending tE/W. SK could be either High or Low at the time. OAfter r input write instruction, also the DO Opin will be abie to show the status of s of R/B, B, in the case that CS is falling from High to Low while SK is tied to Low. (Refer to READY/BUSY STATUS in the next page.)READY/BUSY STATUS (on the R/B pin, the DO pin} *The DO pin outputs the READY / BUSY status of the internal part, which shows whether the device is ready to receive the next instruction or not. (High or Low) _ After the write instruction is completed, if CS is brought from high to low while SK is Low, the DO pin outputs the internal status.(The R/B pin may be no connection.) When written to the memory cell, R/B status is output after tSV spent from the rising edge of 32th clock on SK. RB =Low : under writing After spending tE/W operating the internal timer, the device automatically finishes writing. During tE/W, the memory array is accessed and any instruction is not received. RB =High_ : ready Auto programming has been completed. The device is ready to receive the next Instruction. cs Joy sk \ CLOCK | \ fo " \ wee mesrevonen HHL READY BUSY READY Fig-14 READY/BUSY Status Output timing About the direct connection between the DI and DO pins The device can be used with the DI pin connected to the DO pin directly. But when the READY/BUSY status is output, be careful about the bus conflict on the port of the controller.@ATTENTION TO USE 1. Power ON/OFF *The C$ is brought High during power-up and power-down. *This device is in active state while CS is Low. "The extraordinary function or data collapse may occur in that condition because of noise etc., if power-up and power-down is done with CS brought Low. __ In order to prevent above errors from happening, keep GS High during power-up and powerdown. (Good example) CS is brought High during power-up and powerdown. Please take more than 10ms between power-up and power-off, or the internal circuit is not always reset. (Bad example )CS is brought Low during power-up and power-down. The CS pin is always Low in this case, the noise may force the device to make malfunction or inadvertent write. % It sometimes securs in the case that the CS pin is Hi-Z. voc Veco GND vec cs GND 2. NOISE REJECTION 21 SK NOISE If SK line has a lot of noise for rising time of SK, the device may recognize the noise as a clock and then clock will be shifted. 2-2 WC NOISE if WC line has noise during write cycle(tE/W), there may be a chance to deny the programming. 2-3 VGC NOISE It recommended that capacitor is put between VCC and GND to prevent these case, since it is possible to occur malfunction by the effect of noise or surge on power line.<3. INSTRUCTION MODE GANCEL 31. READ instruction SK | 32clocks | DI | startar | opcone | appress | 4bit 4bit Bbit 16bit on 1 i Bo DI5 Se i DATA ! It is possible to be canceled for any timing. i we HorL How to cancel : CS is brought High. 3-2. Write instruction cs 7 ( f ( ' { ' ' _. { ' SK \ [ 32clocks | \ ! ! DI | start ert | oPcopEe appress | po | DATA ois | ' t \ Abit Abit abit 16bit | ' 1 _ ' ! t | . | | wee ee A +------- ee bo aa-n------- big --- og ----le- dy WG ae nny, r | How to cancel __ a: CS is brought High to cancel the instruction, and WC may be either High or Low. b : Incase that WC is brought High for a moment, or CS is brought High, the write instruction is canceled, the data o of the specified address is not changed. c : When WC i is brought High, or the device is powered down (But the latter way is not recommended), the instruction is canceled but the specifi ed data is not guaranteed. Send the instruction again", ae d : WhenCSis brought High during R/ B High, the device is reset and ready to receive a next instru NOTE : The document may be strategic technical data subject to COCOM regulations.