
RT9728B
11
DS9728B-01 March 2018 www.richtek.com
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Copyright 2018 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Fault Flag
The RT9728B provides a FAULT signal pin which is an
open-drain N-MOSFET output. This open-drain output is
pulled low when current exceeds current limit threshold.
The FAULT output is capable of sinking a 1mA load to
180mV (typ.) above ground. The FAULT pin requires a
pull-up resistor; this resistor should be large in value to
reduce energy drain. A 100kΩ pull-up resistor works well
for most applications. In case of an over-current condition,
FAULT will be asserted only after the flag response delay
time, tD, has elapsed. This ensures that FAULT is asserted
upon valid over-current conditions and that erroneous error
reporting is eliminated. For example, false over-current
conditions may occur during hot-plug events when
extremely large capacitive loads are connected, which
induces a high transient inrush current that exceeds the
current limit threshold. The FAULT response delay time,
tD, is typically 7.5ms.
Supply Filter/Bypa ss Ca pa citor
A 10μF low ESR ceramic capacitor connected from VIN to
GND and located close to the device is strongly
recommended to prevent input voltage drooping during hot-
plug events. However, higher capacitor values may be used
to further reduce the voltage droop on the input. Without
this bypass capacitor, an output short may cause sufficient
ringing on the input (from source lead inductance) to
destroy the internal control circuitry. Note that the input
transient voltage must never exceed 6V as stated in the
Absolute Maximum Ratings.
Output Filter Capacitor
A low ESR 150μF aluminum electrolytic capacitor
connected between VOUT and GND is strongly
recommended to meet the USB standard maximum droop
requirement for the hub, VBUS. Standard bypass methods
should be used to minimize inductance and resistance
between the bypass capacitor and the downstream
connector to reduce EMI and decouple voltage droop
caused by hot-insertion transients in downstream cables.
Ferrite beads in series with VBUS, the ground line and
the 0.1μF bypass capacitors at the power connector pins
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOT-23-6 packages, the thermal resistance, θJA, is 250°C/
W on a standard JEDEC 51-3 single-layer thermal test
board. For WDFN-6L 2x2 packages, the thermal
resistance, θJA, is 165°C/W on a standard JEDEC 51-3
single-layer thermal test board. The maximum power
are recommended for EMI and ESD protection. The bypass
capacitor itself should have a low dissipation factor to allow
decoupling at higher frequencies.
Chip Enable Input
The RT9728BH/L is disabled when the EN/EN pin is in a
logic-low/high condition. During this condition, the internal
circuitry and MOSFET are turned off, reducing the supply
current to 1μA typically. The maximum guaranteed voltage
for a logic-low at the EN/EN pin is 0.66V. A minimum
guaranteed voltage of 1.1V at the EN/EN pin will turn off
the RT9728B. Floating the input may cause unpredictable
operation. EN/EN should not be allowed to go negative
with respect to GND.
Under-Voltage Lockout
Under-Voltage Lockout (UVLO) prevents the MOSFET
switch from turning on until input voltage exceeds
approximately 2.3V. If input voltage drops below
approximately 2.1V, UVLO turns off the MOSFET switch.