CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
HCPL-316J
2.5 Amp Gate Drive Optocoupler with Integrated (VCE)
Desaturation Detection and Fault Status Feedback
Data Sheet
Description
Avago’s 2.5 Amp Gate Drive Optocoupler with Integrated
Desaturation (VCE) Detection and Fault Status Feedback
makes IGBT VCE fault protection compact, aordable, and
easy-to-implement while satisfying worldwide safety and
regulatory requirements.
Features
x2.5 A maximum peak output current
xDrive IGBTs up to IC = 150A, VCE = 1200V
xOptically isolated, FAULT status feedback
xSO-16 package
xCMOS/TTL compatible
x500 ns max. switching speeds
Fault Protected IGBT Gate Drive
MICRO-CONTROLLER
M
HCPL - 316J
–HV
+HV
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
HCPL - 316J
ISOLATION
BOUNDARY
3-PHASE
INPUT
FAULT
Features (continued)
x“Soft” IGBT turn-o
xIntegrated fail-safe IGBT protection
– Desat (VCE) detection
– Under Voltage Lock-Out protection (UVLO)
with hysteresis
xUser congurable: inverting, noninverting, auto-reset,
auto-shutdown
xWide operating VCC range: 15 to 30 Volts
x-40°C to +100°C operating temperature range
x15 kV/µs min. Common Mode Rejection (CMR) at
VCM = 1500 V
xRegulatory approvals: UL, CSA, IEC/EN/DIN EN 60747-
5-2 (1230Vpeak Working Voltage)
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
2
Desat Condition Pin 6
UVLO Detected on (FAULT)
VIN+ V
IN- (VCC2 - VE) Pin 14 Output VOUT
X X Active X X Low
X X X Yes Low Low
Low X X X X Low
X High X X X Low
High Low Not Active No High High
Typical Fault Protected IGBT Gate Drive Circuit
The HCPL-316J is an easy-to-use, intelligent gate driver
which makes IGBT VCE fault protection compact, aord-
able, and easy-to-implement. Features such as user con-
gurable inputs, integrated VCE detection, under volt-
Figure 1. Typical desaturation protected gate drive circuit, noninverting.
Output Control
The outputs (VOUT and FAULT) of the HCPL-316J are con-
trolled by the combination of VIN, UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
HCPL-316J can be congured as inverting or non-invert-
ing using the VIN+ or VIN- inputs respectively. When an in-
verting conguration is desired, VIN+ must be held high
and VIN- toggled. When a non-inverting conguration is
desired, VIN- must be held low and VIN+ toggled. Once
UVLO is not active (VCC2 - VE > VUVLO), VOUT is allowed to
go high, and the DESAT (pin 14) detection feature of the
HCPL-316J will be the primary source of IGBT protection.
UVLO is needed to ensure DESAT is functional. Once VU-
VLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of
the HCPL-316J work in conjunction to ensure constant
IGBT protection.
* THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED.
Description of Operation during Fault Condition
1. DESAT terminal monitors the IGBT VCE voltage through
DDESAT.
2. When the voltage on the DESAT terminal exceeds
7 volts, the IGBT gate voltage (VOUT) is slowly
lowered.
3. FAULT output goes low, notifying the microcontroller
of the fault condition.
4. Microcontroller takes appropriate action.
+
–
+
–
*
*
*
CBLANK
DDESAT
RPULL-DOWN
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
+
–
μC
RF
VF
+–
RG
VCE
VCE
+
–
+
–
100 Ω
age lockout (UVLO), “soft” IGBT turn-o and isolated fault
feed back provide maximum design exibility and circuit
protection.
3
Product Overview Description
The HCPL-316J is a highly integrated power control de-
vice that incorporates all the necessary components for a
complete, isolated IGBT gate drive circuit with fault pro-
tection and feedback into one SO-16 package. TTL input
logic levels allow direct interface with a microcontroller,
and an optically isolated power output stage drives
IGBTs with power ratings of up to 150 A and 1200 V. A
high speed internal optical link minimizes the propaga-
tion delays between the microcontroller and the IGBT
while allowing the two systems to operate at very large
common mode voltage dierences that are common in
industrial motor drives and other power switching ap-
plications. An output IC provides local protection for
the IGBT to prevent damage during overcurrents, and a
second optical link provides a fully isolated fault status
feedback signal for the microcontroller. A built in “watch-
dog” circuit monitors the power stage supply voltage to
prevent IGBT caused by insucient gate drive voltages.
This integrated IGBT gate driver is designed to increase
the performance and reliability of a motor drive without
the cost, size, and complexity of a discrete design.
Two light emitting diodes and two integrated circuits
housed in the same SO-16 package provide the input
control circuitry, the output power stage, and two op-
tical channels. The input Buer IC is designed on a bi-
polar process, while the output Detector IC is designed
manufactured on a high voltage BiCMOS/Power DMOS
process. The forward optical signal path, as indicated by
LED1, transmits the gate control signal. The return opti-
cal signal path, as indicated by LED2, transmits the fault
status feedback signal. Both optical channels are com-
pletely controlled by the input and output ICs respec-
tive-ly, making the internal isolation boundary transpar-
ent to the microcontroller.
Under normal operation, the input gate control signal di-
rectly controls the IGBT gate through the isolated output
detector IC. LED2 remains o and a fault latch in the in-
put buer IC is disabled. When an IGBT fault is detected,
the output detector IC immediately begins a “soft” shut-
down sequence, reducing the IGBT current to zero in a
controlled manner to avoid potential IGBT damage from
inductive overvoltages. Simultaneously, this fault status
is transmitted back to the input buer IC via LED2, where
the fault latch disables the gate control input and the ac-
tive low fault output alerts the microcontroller.
During power-up, the Under Voltage Lockout (UVLO) fea-
ture prevents the application of insucient gate voltage
to the IGBT, by forcing the HCPL-316J’s output low. Once
the output is in the high state, the DESAT (VCE) detec-
tion feature of the HCPL-316J provides IGBT protection.
Thus, UVLO and DESAT work in conjunction to provide
constant IGBT protection.
SHIELD
DESAT
FAULT
UVLO
OUTPUT IC
SHIELD
INPUT IC
RESET 5
FAULT 6
V
IN+
1
V
IN-
2
V
CC1
3
V
CC2
13
12
V
OUT
11
V
EE
9,10
V
E
16
DESAT
14
V
C
V
LED2+
GND1
154
V
LED1-
7 8
V
LED1+
LED2
LED1 D
R
I
V
E
R
4
Package Pin Out
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
E
V
LED2+
DESAT
V
CC2
V
C
V
OUT
V
EE
V
EE
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
Pin Descriptions
Symbol Description Symbol Description
VIN+ Noninverting gate drive voltage output (VOUT) VE Common (IGBT emitter) output supply voltage.
control input.
VIN- Inverting gate drive voltage output VLED2+ LED 2 anode. This pin must be left unconnected
(VOUT) control input. for guaranteed data sheet performance. (For
optical coupling testing only.)
VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference
voltage of 7 V while the IGBT is on, FAULT
output is changed from a high impedance
state to a logic low state within 5 µs. See
Note 25.
GND1 Input Ground. VCC2 Positive output supply voltage.
RESET FAULT reset input. A logic low input for at least VC Collector of output pull-up triple-darlington
0.1 µs, asynchronously resets FAULT output high transistor. It is connected to VCC2 directly or
and enables VIN. Synchronous control of RESET through a resistor to limit output turn-on
relative to VIN is required. RESET is not aected current.
by UVLO. Asserting RESET while VOUT is high does
not aect VOUT.
FAULT Fault output. FAULT changes from a high VOUT Gate drive voltage output.
impedance state to a logic low output within
5 µs of the voltage on the DESAT pin exceeding
an internal reference voltage of 7 V. FAULT
output remains low until RESET is brought low.
FAULT output is an open collector which allows
the FAULT outputs from all HCPL-316Js in a
circuit to be connected together in a “wired OR”
forming a single fault bus for interfacing directly
to the micro-controller.
VLED1+ LED 1 anode. This pin must be left unconnected VEE Output supply voltage.
for guaranteed data sheet performance. (For
optical coupling testing only.)
VLED1- LED 1 cathode. This pin must be connected to
ground.
5
Package Outline Drawings
16-Lead Surface Mount
Dimensions in inches (millimeters)
Notes:
Initial and continued variation in the color of the HCPL-316J’s white mold compound is normal and does note aect
device performance or reliability.
Floating Lead Protrusion is 0.25 mm (10 mils) max.
Ordering Information
HCPL-316J is UL Recognized with 5000 Vrms for 1 minute per UL1577.
Part number
Option
Package
Surface
Mount
Tape
& Reel
IEC/EN/DIN EN
60747-5-2 Quantity
RoHS
Compliant
Non RoHS
Compliant
HCPL-316J -000E No option SO-16 X X 45 per tube
-500E #500 X X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-316J-500E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN
EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-316J to order product of SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2
Safety Approval and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
9
0.295 ± 0.010
(7.493 ± 0.254)
10111213141516
87654321
0.018
(0.457)
0.138 ± 0.005
(3.505 ± 0.127)
9°
0.406 ± 0.10
(10.312 ± 0.254)
0.408 ± 0.010
(10.363 ± 0.254)
0.025 MIN.
0.008 ± 0.003
(0.203 ± 0.076)
STANDOFF
0.345 ± 0.010
(8.763 ± 0.254)
0–8°
0.018
(0.457)
0.050
(1.270)
ALL LEADS
TO BE
COPLANAR
± 0.002
A 316J
YYWW
TYPE NUMBER
DATE CODE
0.458 (11.63)
0.085 (2.16)
0.025 (0.64)
LAND PATTERN RECOMMENDATION
6
Recommended Pb-Free IR Prole
Recommended reow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Package Characteristics
All specications and gures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V,
VE - VEE = 0 V, and TA = +25°C.
Parameter Symbol Min. Typ. Max. Units Test Conditions Note
Input-Output Momentary VISO 5000 Vrms RH < 50%, t = 1 min., 1, 2,
Withstand Voltage TA = 25°C 3
Resistance (Input-Output) RI-O >109 VI-O = 500 Vdc 3
Capacitance (Input-Output) CI-O 1.3 pF f = 1 MHz
Output IC-to-Pins 9 &10 TO9-10 30 °C/W TA = 100°C
Thermal Resistance
Input IC-to-Pin 4 Thermal Resistance TI4 60
7
Regulatory Information
The HCPL-316J has been approved by the following organizations:
Figure 2. Dependence of safety limiting values on temperature.
PS – POWER – mW
0
0
TS – CASE TEMPERATURE – °C
200
1200
800
25
1400
50 75 100
400
150 175
PS, OUTPUT
PS, INPUT
125
200
600
1000
UL
Recognized under UL 1577, component recognition
program, File E55361.
CSA
Approved under CSA Component Acceptance Notice
#5, File CA 88324.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description Symbol Characteristic Unit
Installation classication per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I - IV
for rated mains voltage ≤ 300 Vrms I - IV
for rated mains voltage ≤ 600 Vrms I - IV
for rated mains voltage ≤ 1000Vrms I - III
Climatic Classication 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1230 VPEAK
Input to Output Test Voltage, Method b**
V
IORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 2306 VPEAK
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a**
V
IORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, VPR 1968 VPEAK
Partial Discharge < 5 pC
Highest Allowable Overvoltage** (Transient Overvoltage tini = 60 sec) VIOTM 8000 VPEAK
Safety-limiting values – maximum values allowed in the event of a failure,
also see Figure 2.
Case Temperature TS 175 °C
Input Power PS, INPUT 400 mW
Output Power PS, OUTPUT 1200 mW
Insulation Resistance at TS, VIO = 500 V RS >109
*Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classication is class A in accordance with CECCOO802.
**Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/
EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test proles.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-5:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01.
8
Insulation and Safety Related Specications
Parameter Symbol Value Units Conditions
Minimum External Air Gap L(101) 8.3 mm Measured from input terminals to output terminals,
(Clearance) shortest distance through air.
Minimum External Tracking L(102) 8.3 mm Measured from input terminals to output terminals,
(Creepage) shortest distance path along body.
Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to
(Internal Clearance) conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance CTI >175 Volts DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature Ts -55 125 °C
Operating Temperature TA -40 100
Output IC Junction Temperature TJ 125 4
Peak Output Current |Io(peak)| 2.5 A 5
Fault Output Current IFAULT 8.0 mA
Positive Input Supply Voltage VCC1 -0.5 5.5 Volts
Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1
Total Output Supply Voltage (VCC2 - VEE) -0.5 35
Negative Output Supply Voltage (VE - VEE) -0.5 15 6
Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE)
Gate Drive Output Voltage Vo(peak) -0.5 VCC2
Collector Voltage VC V
EE + 5 V VCC2
DESAT Voltage VDESAT V
E V
E + 10
Output IC Power Dissipation PO 600 mW 4
Input IC Power Dissipation PI 150
Solder Reow Temperature Prole See Package Outline Drawings section
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Operating Temperature TA -40 +100 °C
Input Supply Voltage VCC1 4.5 5.5 Volts 28
Total Output Supply Voltage (VCC2 - VEE) 15 30 9
Negative Output Supply Voltage (VE - VEE) 0 15 6
Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE)
Collector Voltage VC V
EE + 6 VCC2
9
Electrical Specications (DC)
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
Logic Low Input Voltages VIN+L, VIN-L, 0.8 V
V
RESETL
Logic High Input Voltages VIN+H, VIN-H, 2.0
V
RESETH
Logic Low Input Currents IIN+L, IIN-L, -0.5 -0.4 mA VIN = 0.4 V
I
RESETL
FAULT Logic Low Output IFAULTL 5.0 12 VFAULT = 0.4 V 30
Current
FAULT Logic High Output IFAULTH -40 µA VFAULT = VCC1 31
Current
High Level Output Current IOH -0.5 -1.5 A VOUT = VCC2 - 4 V 3, 8, 7
-2.0 VOUT = VCC2 - 15 V 32 5
Low Level Output Current IOL 0.5 2.3 VOUT = VEE + 2.5 V 4, 9, 7
2.0 VOUT = VEE + 15 V 33 5
Low Level Output Current IOLF 90 160 230 mA VOUT - VEE = 14 V 5, 34 8
During Fault Condition
High Level Output Voltage VOH V
C - 3.5 VC - 2.5 VC - 1.5 V IOUT = -100 mA 6, 8, 9, 10, 11
V
C -2.9 VC - 2.0 VC - 1.2 IOUT = -650 µA 35
V
C I
OUT = 0
Low Level Output Voltage VOL 0.17 0.5 IOUT = 100 mA 7, 9, 26
36
High Level Input Supply ICC1H 17 22 mA VIN+ = VCC1 = 5.5 V, 10, 37
Current VIN- = 0 V 38
Low Level Input Supply ICCIL 6 11 VIN+ = VIN- = 0 V,
Current VCC1 = 5.5 V
Output Supply Current ICC2 2.5 5 VOUT open 11, 12, 11
39, 40
Low Level Collector Current ICL 0.3 1.0 IOUT = 0 15, 59 27
High Level Collector Current ICH 0.3 1.3 IOUT = 0 15, 58 27
1.8 3.0 IOUT = -650 µA 15, 57
VE Low Level Supply IEL -0.7 -0.4 0 14, 61
Current
VE High Level Supply IEH -0.5 -0.14 0 14, 40 25
Current
Blanking Capacitor ICHG -0.13 -0.25 -0.33 VDESAT = 0 - 6 V 13, 41 11, 12
Charging Current -0.18 -0.25 -0.33 VDESAT = 0 - 6 V,
T
A = 25°C - 100°C
Blanking Capacitor IDSCHG 10 50 VDESAT = 7 V 42
Discharge Current
UVLO Threshold VUVLO+ 11.6 12.3 13.5 V VOUT > 5 V 43 9, 11, 13
V
UVLO- 11.1 12.4 VOUT < 5 V 9, 11, 14
UVLO Hysteresis (VUVLO+ - 0.4 1.2
V
UVLO-)
DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 - VE > VUVLO- 16, 44 11
10
Switching Specications (AC)
Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V;
all Minimum/Maximum specications are at Recommended Operating Conditions.
Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note
VIN to High Level Output tPLH 0.10 0.30 0.50 µs Rg = 10  17,18,19, 15
Propagation Delay Time Cg = 10 nF, 20,21,22,
VIN to Low Level Output tPHL 0.10 0.32 0.50
f = 10 kHz, 45,54,55
Propagation Delay Time Duty Cycle = 50%
Pulse Width Distortion PWD -0.30 0.02 0.30 16,17
Propagation Delay Dierence (tPHL - tPLH) -0.35 0.35 17,18
Between Any Two Parts PDD
10% to 90% Rise Time tr 0.1 45
90% to 10% Fall Time tf 0.1
DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.3 0.5 Rg = 10 , 23,56 19
Cg = 10 nF
DESAT Sense to 10% VOUT Delay tDESAT(10%) 2.0 3.0 VCC2 - VEE = 30 V 24,28,
46,56
DESAT Sense to Low Level FAULT tDESAT(FAULT) 1.8 5 25,47, 20
Signal Delay 56
DESAT Sense to DESAT Low tDESAT(LOW) 0.25 56 21
Propagation Delay
RESET to High Level FAULT Signal tRESET(FAULT) 3 7 20 26,27, 22
Delay 56
RESET Signal Pulse Width PWRESET 0.1
UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms 49 13
UVLO to VOUT Low Delay tUVLO OFF 6.0 ramp 14
Output High Level Common Mode |CMH| 15 30 kV/µs TA = 25°C, 50,51, 23
Transient Immunity VCM = 1500 V, 52,53
V
CC2 = 30 V
Output Low Level Common Mode |CML| 15 30 TA = 25°C, 24
Transient Immunity VCM = 1500 V,
V
CC2 = 30 V
11
Notes:
1. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second. This test is per-
formed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table,
if applicable.
2. The Input-Output Momentary With stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specication or IEC/EN/DIN EN 60747-5-2 Insulation
Characteristics Table.
3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
4. In order to achieve the absolute maximum power dissipation specied, pins 4, 9, and 10 require ground plane connections and may require
airow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction tem-
perature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power
dissipation achievable will depend on the application environment (PCB Layout, air ow, part placement, etc.). See the Recommended PCB
Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C.
Input IC power dissipation does not require derating.
5. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for compo nent tolerances for designs with IO
peak minimum = 2.0 A. See Applications section for additional details on IOH peak. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This
compensates for increased IOPEAK due to changes in VOL over temperature.
6. This supply is optional. Required only when negative gate drive is implemented.
7. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.
9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VU-
VLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH
will approach VCC as IOH approaches zero units.
10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
11. Once VOUT of the HCPL-316J is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the HCPL-316J will be the primary
source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- <
12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J work in conjunction to ensure constant IGBT protection.
12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details.
13. This is the “increasing” (i.e. turn-on or “positive going” direction) of VCC2 - VE.
14. This is the “decreasing” (i.e. turn-o or “negative going” direction) of VCC2 - VE.
15. This load condition approximates the gate load of a 1200 V/75A IGBT.
16. Pulse Width Distortion (PWD) is dened as |tPHL - tPLH| for any given unit.
17. As measured from VIN+, VIN- to VOUT.
18. The dierence between tPHL and tPLH between any two HCPL-316J parts under the same test conditions.
19. Supply Voltage Dependent.
20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low.
21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low.
22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specication of 3 µs is the guaran-
teed minimum FAULT signal pulse width when the HCPL-316J is congured for Auto-Reset. See the Auto-Reset section in the applications
notes at the end of this data sheet for further details.
23. Common mode transient immunity in the high state is the maximum tolerable
dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and
a 3K  pull-up resistor is needed in fault detection mode.
24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the
output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V).
25. Does not include LED2 current during fault or blanking capacitor discharge current.
26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650
µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-
down resistor is not used.
27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE.
28. In most applications VCC1 will be powered up rst (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control
of the IGBT gate. In applications where VCC2 is powered up rst, it is important to ensure that Vin+ remains low until VCC1 reaches the proper
operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down.
12
Performance Plots
Figure 3. IOH vs. temperature. Figure 5. IOLF vs. VOUT.
Figure 6. VOH vs. temperature. Figure 7. VOL vs. temperature. Figure 8. VOH vs. IOH.
Figure 9: VOL vs. IOL. Figure 10. ICC1 vs. temperature. Figure 11: ICC2 vs. t emperature.
Figure 4. IOL vs. temperature.
I
OH
– OUTPUT HIGH CURRENT – A
-40
1.0
T
A
– TEMPERATURE – °C
100
1.8
1.6
-20
2.0
02040
1.2
60 80
1.4
I
OL
– OUTPUT LOW CURRENT
-40
0
T
A
– TEMPERATURE – °C
100
6
4
-20
7
02040
2
80
V
OUT
= V
EE
+ 15 V
V
OUT
= V
EE
+ 2.5 V
60
1
3
5
(V
OH
-V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-40
-4
T
A
– TEMPERATURE – °C
100-20
0
02040 80
I
OUT
= -650 μA
I
OUT
= -100 mA
60
-3
-2
-1
ICC2 – OUTPUT SUPPLY CURRENT – mA
-40
2.2
TA – TEMPERATURE – °C
100-20
2.6
02040 80
ICC2H
ICC2L
60
2.3
2.4
2.5
VOL – OUTPUT LOW VOLTAGE – V
-40
0
TA – TEMPERATURE – °C
100
0.20
0.15
-20
0.25
02040
0.05
60 80
0.10
IOUT = 100 mA
I
CC1
– SUPPLY CURRENT – mA
-40
0
T
A
– TEMPERATURE – °C
100-20
20
02040 80
I
CC1H
I
CC1L
60
5
10
15
VOH – OUTPUT HIGH VOLTAGE – V
0
27.4
IOH – OUTPUT HIGH CURRENT – A
1.0
28.6
28.4
29.0
0.4
27.8
0.6
28.0
0.2 0.8
27.6
28.2
28.8 +100°C
+25°C
-40°C
IOLF – LOW LEVEL OUTPUT CURRENT
DURING FAULT CONDITION – mA
0
25
VOUT – OUTPUT VOLTAGE – V
30
175
125
5
200
10 2515
50
100
150
75
20
-40°C
25°C
100°C
VOL – OUTPUT LOW VOLTAGE – V
0.1
0
IOL – OUTPUT LOW CURRENT – A
0.5
6
1.0 1.5 2.0 2.5
3
4
5
2
1
+100°C
+25°C
-40°C
13
Figure 12. ICC2 vs. VCC2. Figure 13. ICHG vs. temperature. Figure 14. IE vs. temperature.
Figure 15. IC vs. IOUT. Figure 16. DESAT threshold vs. temperature. Figure 17. Propagation delay vs. temperature.
Figure 18. Propagation delay vs. supply voltage. Figure 19. VIN to high propagation delay vs.
temperature.
Figure 20. VIN to low propagation delay vs.
temperature.
I
CC2
– OUTPUT SUPPLY CURRENT – mA
15
2.35
V
CC2
– OUTPUT SUPPLY VOLTAGE – V
30
2.55
2.50
2.60
20
2.40
25
2.45
I
CC2H
I
CC2L
I
CHG
– BLANKING CAPACITOR
CHARGING CURRENT – mA
-40
-0.30
T
A
– TEMPERATURE – °C
100-20
-0.15
02040 8060
-0.25
-0.20
VDESAT – DESAT THRESHOLD – V
-40
6.0
TA – TEMPERATURE – °C
100-20
7.5
02040 8060
7.0
6.5
TP – PROPAGATION DELAY – μs
-40
0.2
TA – TEMPERATURE – °C
100-20
0.5
02040 8060
0.4
0.3
tPHL
tPLH
TP – PROPAGATION DELAY – μs
15
0.20
VCC – SUPPLY VOLTAGE – V
30
0.40
20 25
0.25
0.30
0.35
tPHL
tPLH
PROPAGATION DELAY – μs
0.25
TEMPERATURE – °C
0.45
0 50 100
0.30
0.35
0.40
V
CC1
= 5.5 V
V
CC1
= 5.0 V
V
CC1
= 4.5 V
-50
PROPAGATION DELAY – μs
0.25
TEMPERATURE – °C
0.50
0 50 100
0.40
0.45
V
CC1
= 5.5 V
V
CC1
= 5.0 V
V
CC1
= 4.5 V
0.30
0.35
-50
IC (mA)
0
0
IOUT (mA)
2.0
4
0.5 1.0 1.5
2
3
1
-40°C
+25°C
+100°C
IE -VE SUPPLY CURRENT – mA
-40
0.30
TA – TEMPERATURE – °C
100-20
0.50
02040 80
IEH
IEL
60
0.40
0.45
0.35
14
Figure 21. Propagation delay vs. load capaci-
tance.
Figure 22. Propagation delay vs. load resistance. Figure 23. DESAT sense to 90% Vout delay vs.
temperature.
Figure 24. DESAT sense to 10% Vout delay vs.
temperature.
Figure 25. DESAT sense to low level fault signal
delay vs. temperature.
Figure 26. DESAT sense to 10% Vout delay vs. load
capacitance.
Figure 27. DESAT sense to 10% Vout delay vs. load
resistance.
Figure 28. RESET to high level fault signal delay vs.
temperature.
DELAY – μs
0.25
TEMPERATURE – °C
0.45
0 100
0.30
0.35
0.40
50
-50
DELAY – μs
1.0
TEMPERATURE – °C
3.0
0 100
1.5
2.0
2.5
50
V
CC2
= 15 V
V
CC2
= 30 V
-50
DELAY – μs
1.6
TEMPERATURE – °C
2.6
0 50 100
2.2
2.4
1.8
2.0
-50
V
EE
= 0 V
V
EE
= -5 V
V
EE
= -10 V
V
EE
= -15 V
DELAY – μs
0.0010
LOAD RESISTANCE – Ω
50
0.0030
10 20 40
0.0015
0.0020
0.0025
30
VCC2 = 15 V
VCC2 = 30 V
DELAY – μs
4
TEMPERATURE – °C
150
12
0 50 100
6
8
10
V
CC1
= 5.5 V
V
CC1
= 5.0 V
V
CC1
= 4.5 V
-50
DELAY – μs
0.20
LOAD CAPACITANCE – nF
100
0.40
20 40 80
0.25
0.30
0.35
tPLH
tPHL
060
DELAY – μs
0.20
LOAD RESISTANCE – Ω
50
0.40
10 20 40
0.25
0.30
0.35
tPLH
tPHL
030
DELAY – ms
0
LOAD CAPACITANCE – nF
50
0.008
10 20 40
0.002
0.004
0.006
030
VCC2 = 15 V
VCC2 = 30 V
15
Test Circuit Diagrams
Figure 32. IOH pulsed test circuit. Figure 33. IOL pulsed test circuit.
Figure 34. IOLF test circuit. Figure 35. VOH pulsed test circuit.
Figure 31. IFAULTH test circuit.Figure 30. IFAULTL test circuit.
0.1 μF
+
–
10 mA
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
4.5 V
IFAULT
–
+
0.4 V
+
–
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
5 V
+
–
I
FAULT
0.1 μF
+
–
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
+
–
30 V
30 V
15 V
PULSED
0.1 μF
IOUT
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
+
–
30 V
30 V
15 V
PULSED
0.1 μF
IOUT
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
+
–
30 V
30 V
14 V
0.1
μF
IOUT
+
–
0.1
μF
5 V
0.1 μF
+
–
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
0.1
μF
VOUT
2A
PULSED
16
Figure 36. VOL test circuit. Figure 37. ICC1H test circuit.
Figure 38. ICC1L test circuit. Figure 39. ICC2H test circuit.
Figure 40. ICC2L test circuit. Figure 41. ICHG pulsed test circuit.
0.1 μF
+
–
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
0.1
μF
VOUT
100
mA
+
–
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5.5 V
ICC1
+
–
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5.5 V
ICC1
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICC2
0.1 μF
+
–
5 V
0.1
μF
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICC2
0.1 μF
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
ICHG
0.1 μF
+
–
5 V
0.1
μF
17
Figure 42. IDSCHG test circuit. Figure 43. UVLO threshold test circuit.
Figure 44. DESAT threshold test circuit. Figure 45. tPLH, tPHL, tr, tf test circuit.
Figure 46. tDESAT(10%) test circuit. Figure 47. tDESAT(FAULT) test circuit.
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
IDSCHG
+
–
7 V
0.1 μF
+
–
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
SWEEP
0.1 μF
VOUT
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
+
–
+
–
15 V
15 V
SWEEP
0.1 μF
+
–
10 mA
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
VOUT 0.1
μF
10
nF
10 Ω
+
–
VIN
3 k
0.1
μF
0.1
μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
VOUT
0.1
μF
10
nF
10 Ω
3 k
VIN
+
–
0.1
μF
0.1
μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
0.1
μF
10
nF
10 Ω
3 k
VIN
+
–
VFAULT
18
Figure 49. UVLO delay test circuit.
Figure 50. CMR test circuit, LED2 o. Figure 51. CMR test circuit, LED2 on.
Figure 52. CMR test circuit, LED1 o. Figure 53. CMR test circuit, LED1 on.
Figure 48. tRESET(FAULT) test circuit.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
μF
10 Ω
0.1 μF
10 nF
VCm
5 V
25 V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
μF
10 Ω
10 nF
VCm
+
–
750 Ω
9 V
25 V
5 V
0.1 μF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
3 kΩ
100
pF
0.1
μF
10 Ω
10 nF
VCm
0.1 μF
SCOPE
25 V
5 V
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1
SCOPE
3 kΩ
100 pF
0.1
μF
10 Ω
10 nF
VCm
0.1 μF
25 V
5 V
0.1
μF
0.1
μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
+
–
+
–
30 V
30 V
0.1
μF
10
nF
10 Ω
3 k
STROBE
8 V
+
–
VFAULT
VIN HIGH
TO LOW
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
0.1
μF
5 V
VOUT 0.1
μF
10
nF
10 Ω
3 k
+
–
RAMP
19
Figure 54. VOUT propagation delay waveforms, noninverting conguration. Figure 55. VOUT propagation delay waveforms, inverting conguration.
Figure 56. Desat, VOUT, fault, reset delay waveforms.
V
IN+
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
V
IN-
2.5 V 2.5 V
0 V
V
IN+
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
V
IN-
2.5 V 2.5 V
5.0 V
V
OUT
t
RESET (FAULT)
50% (2.5 V)
50%
10%
7 V
50%
t
DESAT (FAULT)
V
DESAT
FAULT
RESET
t
DESAT (90%)
t
DESAT (LOW)
t
DESAT (10%)
90%
20
Figure 57. ICH test circuit. Figure 58. ICH test circuit.
Figure 59. ICL test circuit. Figure 60. IEH test circuit.
Figure 61. IEL test circuit.
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
650 μA
0.1 μF
IC
+
–
0.1
μF
5 V 0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 μF
IC
+
–
0.1
μF
5 V
0.1 μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 μF
IC
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 μF
IE
+
–
0.1
μF
5 V
0.1
μF
0.1 μF
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
+
–
+
–
30 V
30 V
0.1 μF
IE
+
–
0.1
μF
5 V
21
Typical Application/Operation
Introduction to Fault Detection and Protection
The power stage of a typical three phase inverter is sus-
ceptible to several types of failures, most of which are
potentially destructive to the power IGBTs. These failure
modes can be grouped into four basic categories: phase
and/or rail supply short circuits due to user misconnect
or bad wiring, control signal failures due to noise or com-
putational errors, overload conditions induced by the
load, and component failures in the gate drive circuitry.
Under any of these fault conditions, the current through
the IGBTs can increase rapidly, causing excessive power
dissipation and heating. The IGBTs become damaged
when the current load approaches the saturation cur-
rent of the device, and the collector to emitter voltage
rises above the saturation voltage level. The drastically
increased power dissipation very quickly overheats the
power device and destroys it. To prevent damage to the
drive, fault protection must be implemented to reduce
or turn-o the overcurrents during a fault condition.
A circuit providing fast local fault detection and shut-
down is an ideal solution, but the number of required
components, board space consumed, cost, and complex-
ity have until now limited its use to high performance
drives. The features which this circuit must have are high
speed, low cost, low resolution, low power dissipation,
and small size.
Applications InformationThe HCPL-316J satises these cri-
teria by combining a high speed, high output current
driver, high voltage optical isolation between the input
and output, local IGBT desaturation detection and shut
down, and an optically isolated fault status feedback sig-
nal into a single 16-pin surface mount package.
The fault detection method, which is adopted in the
HCPL-316J, is to monitor the saturation (collector) volt-
age of the IGBT and to trigger a local fault shutdown se-
quence if the collector voltage exceeds a predetermined
threshold. A small gate discharge device slowly reduces
the high short circuit IGBT current to prevent damaging
voltage spikes. Before the dissipated energy can reach
destructive levels, the IGBT is shut o. During the o
state of the IGBT, the fault detect circuitry is simply dis-
abled to prevent false ‘fault’ signals.
The alternative protection scheme of measuring IGBT
current to prevent desaturation is eective if the short
circuit capability of the power device is known, but
this method will fail if the gate drive voltage decreases
enough to only partially turn on the IGBT. By directly
measuring the collector voltage, the HCPL-316J limits
the power dissipation in the IGBT even with insucient
gate drive voltage. Another more subtle advantage of
the desaturation detection method is that power dissi-
pation in the IGBT is monitored, while the current sense
method relies on a preset current threshold to predict
the safe limit of operation. Therefore, an overly- conser-
vative overcurrent threshold is not needed to protect
the IGBT.
Recommended Application Circuit
The HCPL-316J has both inverting and non-inverting
gate control inputs, an active low reset input, and an
open collector fault output suitable for wired ‘OR’ appli-
cations. The recommended application circuit shown in
Figure 62 illustrates a typical gate drive implementation
using the HCPL-316J.
The four supply bypass capacitors (0.1 µF) provide the
large transient currents necessary during a switching
transition. Because of the transient nature of the charg-
ing currents, a low current (5 mA) power supply suces.
The desat diode and 100 pF capacitor are the necessary
external components for the fault detection circuitry.
The gate resistor (10 Ω) serves to limit gate charge cur-
rent and indirectly control the IGBT collector voltage
rise and fall times. The open collector fault output has
a passive 3.3 kΩ pull-up resistor and a 330 pF ltering
capacitor. A 47 kΩ pulldown resistor on VOUT provides a
more predictable high level output voltage (VOH). In this
application, the IGBT gate driver will shut down when a
fault is detected and will not resume switching until the
microcontroller applies a reset signal.
22
Figure 62. Recommended application circuit.
Description of Operation/Timing
Figure 63 below illustrates input and output waveforms
under the conditions of normal operation, a desat fault
condition, and normal reset behavior.
Normal Operation
During normal operation, VOUT of the HCPL-316J is con-
trolled by either VIN+ or VIN-, with the IGBT collector-to-
emitter voltage being monitored through DDESAT. The
FAULT output is high and the RESET input should be held
high. See Figure 63.
Figure 63. Timing diagram.
Fault Condition
When the voltage on the DESAT pin exceeds 7 V while
the IGBT is on, VOUT is slowly brought low in order to
“softly” turn-o the IGBT and prevent large di/dt induced
voltages. Also activated is an internal feedback channel
which brings the FAULT output low for the purpose of
notifying the micro-controller of the fault condition. See
Figure 63.
Reset
The FAULT output remains low until RESET is brought
low. See Figure 63. While asserting the RESET pin (LOW),
the input pins must be asserted for an output low state
(VIN+ is LOW or VIN- is HIGH). This may be accomplished
either by software control (i.e. of the microcontroller) or
hardware control (see Figures 73 and 74).
VOUT
VDESAT
VIN+
FAULT
RESET
NORMAL
OPERATION
FAULT
CONDITION
RESET
VIN+
VIN-
VIN-
5 V
0 V
5 V
5 V
7 V
NON-INVERTING
CONFIGURED
INPUTS
INVERTING
CONFIGURED
INPUTS
+
–
+
–
100 pF
DDESAT
0.1
μF
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
+
–
μC
3.3
kΩ
0.1
μF
5 V
330 pF
Rg
VCC2 = 18 V
VEE = -5 V
47
kΩ
3-PHASE
OUTPUT
0.1
μF
0.1
μF
VF
+–
Q1
Q2
VCE
+
–
VCE
+
–
100 Ω
23
Slow IGBT Gate Discharge During Fault Condition
When a desaturation fault is detected, a weak pull-down
device in the HCPL-316J output drive stage will turn on
to ‘softly’ turn o the IGBT. This device slowly discharges
the IGBT gate to prevent fast changes in drain current
that could cause damaging voltage spikes due to lead
and wire inductance. During the slow turn o, the large
output pull-down device remains o until the output
voltage falls below VEE + 2 Volts, at which time the large
pull down device clamps the IGBT gate to VEE.
DESAT Fault Detection Blanking Time
The DESAT fault detection circuitry must remain disabled
for a short time period following the turn-on of the IGBT
to allow the collector voltage to fall below the DESAT
theshold. This time period, called the DESAT blanking
time, is controlled by the internal DESAT charge current,
the DESAT voltage threshold, and the external DESAT ca-
pacitor. The nominal blanking time is calculated in terms
of external capacitance (CBLANK), FAULT threshold volt-
age (VDESAT), and DESAT charge current (ICHG) as tBLANK
= CBLANK x VDESAT / ICHG. The nominal blanking time
with the recommended 100 pF capacitor is 100 pF * 7 V
/ 250 µA = 2.8 µsec. The capacitance value can be scaled
slightly to adjust the blanking time, though a value small-
er than 100 pF is not recommended. This nominal blank-
ing time also represents the longest time it will take for
the HCPL-316J to respond to a DESAT fault condition. If
the IGBT is turned on while the collector and emitter are
shorted to the supply rails (switching into a short), the
soft shut-down sequence will begin after approximately
3 µsec. If the IGBT collector and emitter are shorted to
the supply rails after the IGBT is already on, the response
time will be much quicker due to the parasitic parallel
capacitance of the DESAT diode. The recommended 100
pF capacitor should provide adequate blanking as well
as fault response times for most applications.
Under Voltage Lockout
The HCPL-316J Under Voltage Lockout (UVLO) feature is
designed to prevent the application of insucient gate
voltage to the IGBT by forcing the HCPL-316J output low
during power-up. IGBTs typically require gate voltages
of 15 V to achieve their rated VCE(ON) voltage. At gate
voltages below 13 V typically, their on-voltage increases
dramatically, especially at higher currents. At very low
gate voltages (below 10 V), the IGBT may operate in the
linear region and quickly overheat. The UVLO function
causes the output to be clamped whenever insucient
operating supply (VCC2) is applied. Once VCC2 exceeds
VUVLO+ (the positive-going UVLO threshold), the UVLO
clamp is released to allow the device output to turn on
in response to input signals. As VCC2 is increased from 0 V
(at some level below VUVLO+), rst the DESAT protection
circuitry becomes active. As VCC2 is further increased
(above VUVLO+), the UVLO clamp is released. Before the
time the UVLO clamp is released, the DESAT protection
is already active. Therefore, the UVLO and DESAT FAULT
DETECTION features work together to provide seamless
protection regardless of supply voltage (VCC2).
24
Behavioral Circuit Schematic
The functional behavior of the HCPL-316J is rep-
resented by the logic diagram in Figure 64
which fully describes the interaction and se-
quence of internal and external signals in the
HCPL-316J.
Input IC
In the normal switching mode, no output fault has been
detected, and the low state of the fault latch allows the
input signals to control the signal LED. The fault output
is in the open-collector state, and the state of the Reset
pin does not aect the control of the IGBT gate. When a
fault is detected, the FAULT output and signal input are
both latched. The fault output changes to an active low
state, and the signal LED is forced o (output LOW). The
latched condition will persist until the Reset pin is pulled
low.
Figure 64. Behavioral circuit schematic.
Output IC
Three internal signals control the state of the driver out-
put: the state of the signal LED, as well as the UVLO and
Fault signals. If no fault on the IGBT collector is detected,
and the supply voltage is above the UVLO threshold,
the LED signal will control the driver output state. The
driver stage logic includes an interlock to ensure that the
pull-up and pull-down devices in the output stage are
never on at the same time. If an undervoltage condition
is detected, the output will be actively pulled low by the
50x DMOS device, regardless of the LED state. If an IGBT
desaturation fault is detected while the signal LED is on,
the Fault signal will latch in the high state. The triple dar-
lington AND the 50x DMOS device are disabled, and a
smaller 1x DMOS pull-down device is activated to slowly
discharge the IGBT gate. When the output drops below
two volts, the 50x DMOS device again turns on, clamp-
ing the IGBT gate rmly to Vee. The Fault signal remains
latched in the high state until the signal LED turns o.
VIN+ (1)
VIN– (2)
VCC1 (3)
GND (4)
FAULT (6)
RESET (5)
DELAY
RS
Q
FAULT
LED
12 V
+
–VCC2 (13)
7 V
–
+DESAT (14)
VE (16)
250 μA
VC (12)
VOUT (11)
VEE (9,10)
50 x
1 x
FAULT
UVLO
25
Other Recommended Components
The application circuit in Figure 62 includes an output
pull-down resistor, a DESAT pin protection resistor, a
FAULT pin capacitor (330 pF), and a FAULT pin pull-up
resistor.
Output Pull-Down Resistor
During the output high transition, the output voltage
rapidly rises to within 3 diode drops of VCC2. If the output
current then drops to zero due to a capacitive load, the
output voltage will slowly rise from roughly VCC2-3(VBE)
to VCC2 within a period of several microseconds. To limit
the output voltage to VCC2-3(VBE), a pull-down resistor
between the output and VEE is recommended to sink a
static current of several 650 µA while the output is high.
Pull-down resistor values are dependent on the amount
of positive supply and can be adjusted according to the
formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA.
DESAT Pin Protection
The freewheeling of yback diodes connected across
the IGBTs can have large instantaneous forward voltage
transients which greatly exceed the nominal forward
voltage of the diode. This may result in a large negative
voltage spike on the DESAT pin which will draw substan-
tial current out of the IC if protection is not used. To limit
this current to levels that will not damage the IC, a 100
ohm resistor should be inserted in series with the DE-
SAT diode. The added resistance will not alter the DESAT
threshold or the DESAT blanking time.
Capacitor on FAULT Pin for High CMR
Rapid common mode transients can aect the fault
pin voltage while the fault output is in the high state. A
330 pF capacitor (Fig. 66) should be connected between
the fault pin and ground to achieve adequate CMOS
noise margins at the specied CMR value of 15 kV/µs.
The added capacitance does not increase the fault out-
put delay when a desaturation condition is detected.
Pull-up Resistor on FAULT Pin
The FAULT pin is an open-collector output and therefore
requires a pull-up resistor to provide a high-level signal.
Driving with Standard CMOS/TTL for High CMR
Capacitive coupling from the isolated high voltage
circuitry to the input referred circuitry is the primary
CMR limitation. This coupling must be accounted for to
achieve high CMR perform ance. The input pins VIN+ and
VIN- must have active drive signals to prevent unwanted
switching of the output under extreme common mode
transient conditions. Input drive circuits that use pull-up
or pull-down resistors, such as open collector congu-
rations, should be avoided. Standard CMOS or TTL drive
circuits are recommended.
Figure 65. Output pull-down resistor. Figure 66. DESAT pin protection. Figure 67. FAULT pin CMR protection.
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
100 Ω
HCPL-316J
100 pF
DDESAT
Rg
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
+
–
μC
330 pF
3.3
kΩ
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
HCPL-316J
Rg
RPULL-DOWN
26
User-Conguration of the HCPL-316J Input Side
The VIN+, VIN-, FAULT and RESET input pins make a wide
variety of gate control and fault congurations pos-
sible, depending on the motor drive requirements. The
HCPL-316J has both inverting and non inverting gate
control inputs, an open collector fault output suitable
for wired ‘OR’ applications and an active low reset input.
Driving Input pf HCPL-316J in Non-Inverting/Inverting
Mode
The Gate Drive Voltage Output of the HCPL-316J can
be congured as inverting or non-inverting using the
VIN– and VIN+ inputs. As shown in Figure 68, when a
non-inverting conguration is desired, VIN– is held low
by connecting it to GND1 and VIN+ is toggled. As shown
in Figure 69, when an inverting conguration is desired,
VIN+ is held high by connecting it to VCC1 and VIN– is tog-
gled.
Local Shutdown, Local Reset
As shown in Figure 70, the fault output of each HCPL-
316J gate driver is polled separately, and the individual
reset lines are asserted low independently to reset the
motor controller after a fault condition.
Global-Shutdown, Global Reset
As shown in Figure 71, when congured for inverting op-
eration, the HCPL-316J can be congured to shutdown
automatically in the event of a fault condition by tying
the FAULT output to VIN+. For high reliability drives, the
open collector FAULT outputs of each HCPL-316J can be
wire ‘OR’ed together on a common fault bus, forming a
single fault bus for interfacing directly to the micro-con-
troller. When any of the six gate drivers detects a fault,
the fault output signal will disable all six HCPL-316J gate
drivers simultaneously and thereby provide protection
against further catastrophic failures.
Figure 68. Typical input conguration, noninverting.
Figure 69. Typical Input Conguration, Inverting.
Figure 70. Local shutdown, local reset conguration.
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
+
–
μC
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
+
–
μC
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
HCPL-316J
+
–
μC
27
Figure 71. Global-shutdown, global reset conguration.
Figure 72. Auto-reset conguration.
Auto-Reset
As shown in Figure 72, when the inverting VIN- input is
connected to ground (non-inverting conguration), the
HCPL-316J can be congured to reset automatically by
connecting RESET to VIN+. In this case, the gate control
signal is applied to the non-inverting input as well as the
reset input to reset the fault latch every switching cycle.
During normal operation of the IGBT, asserting the reset
input low has no eect. Following a fault condition, the
gate driver remains in the latched fault state until the
gate control signal changes to the ‘gate low’ state and
resets the fault latch. If the gate control signal is a con-
tinuous PWM signal, the fault latch will always be reset
by the next time the input signal goes high. This cong-
uration protects the IGBT on a cycle-by-cycle basis and
automatically resets before the next ‘on’ cycle. The fault
outputs can be wire ‘OR’ed together to alert the micro-
controller, but this signal would not be used for control
purposes in this (Auto-Reset) conguration. When the
HCPL- 316J is congured for Auto-Reset, the guaranteed
minimum FAULT signal pulse width is 3 µs.
Figure 73a. Safe hardware reset for noninverting input
conguration (automatically resets for every VIN+ input). Figure 73b. Safe hardware reset for noninverting input
conguration.
Resetting Following a Fault Condition
To resume normal switching operation following a fault
condition (FAULT output low), the RESET pin must rst
be asserted low in order to release the internal fault
latch and reset the FAULT output (high). Prior to assert-
ing the RESET pin low, the input (VIN) switching signals
must be congured for an output (VOL) low state. This
can be handled directly by the microcontroller or by
hardwiring to synchronize the RESET signal with the ap-
propriate input signal. Figure 73a shows how to connect
the RESET to the VIN+ signal for safe automatic reset in
the noninverting input conguration. Figure 73b shows
how to congure the VIN+/RESET signals so that a RESET
signal from the microcontroller causes the input to be
in the “output-o” state. Similarly, Figures 73c and 73d
show automatic RESET and microcontroller RESET safe
congurations for the inverting input conguration.
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
HCPL-316J
+
–
μC
CONNECT
TO OTHER
FAULTS
CONNECT
TO OTHER
RESETS
HCPL-316J fig 72
1
2
3
4
5
6
7
8
V
IN+
V
IN-
V
CC1
GND1
RESET
FAULT
V
LED1+
V
LED1-
HCPL-316J
+
–
μC
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
μC
VCC
VIN+/
RESET
FAULT
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
μC
VCC
RESET
FAULT
VIN+
28
0.5 A, the value of RC can be estimated in the following
way:
RC + RG = [VCC2 – VOH – (VEE)]
IOH,PEAK
= [4 V – (-5 V)]
0.5 A
= 18 Ω
RC = 8 Ω
See “Power and Layout Considerations” section for more
information on calculating value of RG.
User-Conguration of the HCPL-316J Output Side RG
and Optional Resistor RC:
The value of the gate resistor RG (along with VCC2 and VEE)
determines the maximum amount of gate-charging/dis-
charging current (ION,PEAK and IOFF,PEAK) and thus should
be carefully chosen to match the size of the IGBT being
driven. Often it is desirable to have the peak gate charge
current be somewhat less than the peak discharge cur-
rent (ION,PEAK < IOFF,PEAK). For this condition, an optional
resistor (RC) can be used along with RG to independently
determine ION,PEAK and IOFF,PEAK without using a steering
diode. As an example, refer to Figure 74. Assuming that
RG is already determined and that the design IOH,PEAK =
Figure 73d. Safe hardware reset for inverting input conguration
(automatically resets for every VIN- input).
Figure 73c. Safe hardware reset for inverting input conguration.
Figure 74. Use of RC to further limit ION,PEAK.
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
10 Ω
HCPL-316J
100 pF
RC 8 Ω
10 nF
-5 V15 V
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
μC
VCC
RESET
FAULT
VIN-
VCC
1
2
3
4
5
6
7
8
VIN+
VIN-
VCC1
GND1
RESET
FAULT
VLED1+
VLED1-
HCPL-316J
μC
VCC
RESET
FAULT
VIN-
VCC
29
Figure 75. Current buer for increased drive current.
Power/Layout Considerations
Operating Within the Maximum Allowable Power Ratings
(Adjusting Value of RG):
When choosing the value of RG, it is important to con-
rm that the power dissipation of the HCPL-316J is
within the maximum allowable power rating.
The steps for doing this are:
1. Calculate the minimum desired RG;
Higher Output Current Using an External Current Buf-
fer:
To increase the IGBT gate drive current, a non-inverting
current buer (such as the npn/pnp buer shown in
Figure 75) may be used. Inverting types are not com-
patible with the desatura-tion fault protection circuitry
and should be avoided. To preserve the slow IGBT turn-
o feature during a fault condition, a 10 nF capacitor
should be connected from the buer input to VEE and
a 10 : resistor inserted between the output and the
common npn/pnp base. The MJD44H11/MJD45H11
pair is appropriate for currents up to 8A maximum. The
D44VH10/ D45VH10 pair is appropriate for currents up
to 15 A maximum.
DESAT Diode and DESAT Threshold
The DESAT diode’s function is to conduct forward cur-
rent, allowing sensing of the IGBT’s saturated collector-
to-emitter voltage, VCESAT, (when the IGBT is “on”) and to
block high voltages (when the IGBT is “o”). During the
short period of time when the IGBT is switching, there is
commonly a very high dVCE/dt voltage ramp rate across
the IGBT’s collector-to-emitter. This results in ICHARGE (=
CD-DESAT x dVCE/dt) charging current which will charge
the blanking capacitor, CBLANK. In order to minimize
this charging current and avoid false DESAT triggering,
it is best to use fast response diodes. Listed in the be-
low table are fast-recovery diodes that are suitable for
use as a DESAT diode (DDESAT). In the recommended ap-
plication circuit shown in Figure 62, the voltage on pin
14 (DESAT) is VDESAT = VF + VCE, (where VF is the forward
ON voltage of DDESAT and VCE is the IGBT collector-to-
emitter voltage). The value of VCE which triggers DESAT
to signal a FAULT condition, is nominally 7V – VF. If de-
sired, this DESAT threshold voltage can be decreased by
using multiple DESAT diodes in series. If n is the number
of DESAT diodes then the nominal threshold value be-
comes VCE,FAULT(TH) = 7 V – n x VF. In the case of using two
diodes instead of one, diodes with half of the total re-
quired maximum reverse-voltage rating may be chosen.
Max. Reverse Voltage
Part Number Manufacturer trr (ns) Rating, VRRM (Volts) Package Type
MUR1100E Motorola 75 1000 59-04 (axial leaded)
MURS160T3 Motorola 75 600 Case 403A (surface mount)
UF4007 General Semi. 75 1000 DO-204AL (axial leaded)
BYM26E Philips 75 1000 SOD64 (axial leaded)
BYV26E Philips 75 1000 SOD57 (axial leaded)
BYV99 Philips 75 600 SOD87 (surface mount)
16
15
14
13
12
11
10
9
VE
VLED2+
DESAT
VCC2
VC
VOUT
VEE
VEE
10 Ω
HCPL-316J
100 pF
10 nF
MJD44H11 or
D44VH10
4.5 Ω
2.5 Ω
MJD45H11 or
D45VH10
15 V -5 V
2. Calculate total power dissipation in the part referring
to Figure 77. (Average switching energy supplied to
HCPL-316J per cycle vs. RG plot);
3. Compare the input and output power dissipation
calculated in step #2 to the maximum recommended
dissipation for the HCPL-316J. (If the maximum rec-
ommended level has been exceeded, it may be nec-
essary to raise the value of RG to lower the switching
power and repeat step #2.)
30
PO(BIAS) = steady-state power dissipation in the HC-
PL-316J due to biasing the device.
PO(SWITCH) = transient power dissipation in the HC-
PL-316J due to charging and discharging power device
gate.
ESWITCH = Average Energy dissipated in HCPL-316J due
to switching of the power device over one switching
cycle (µJ/cycle).
fSWITCH = average carrier signal frequency.
For RG = 10.5, the value read from Figure 77 is ESWITCH
= 6.05 µJ. Assume a worst-case average ICC1 = 16.5 mA
(which is given by the average of ICC1H and ICC1L ). Simi-
larly the average ICC2 = 5.5 mA.
PI = 16.5 mA * 5.5 V = 90.8 mW
PO = PO(BIAS) + PO,SWITCH
= 5.5 mA * (18 V – (–5 V)) + 6.051 µJ * 15 kHz
= 126.5 mW + 90.8 mW
= 217.3 mW
Step 3: Compare the calculated power dissipation with the abso-
lute maximum values for the HCPL-316J:
For the example,
P
I = 90.8 mW < 150 mW (abs. max.) OK
P
O = 217.3 mW < 600 mW (abs. max.) OK
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
Please refer to the following Thermal Model section for
an explanation on how to calculate the maximum junc-
tion temperature of the HCPL-316J for a given PC board
layout conguration.
As an example, the total input and output power dis-
sipation can be calculated given the following condi-
tions:
• ION, MAX ~ 2.0 A
• VCC2 = 18 V
• VEE = -5 V
• fCARRIER = 15 kHz
Step 1: Calculate RG minimum from IOL peak specication:
To nd the peak charging lOL assume that the gate is
initially charged the steady-state value of VEE. Therefore
apply the following relationship:
[VOH@650 μA – (VOL+VEE)]
RG = ——————————
IOL,PEAK
[VCC2 – 1 – (VOL + VEE )]
= —————————
IOL,PEAK
18 V – 1 V – (1.5 V + (-5 V))
= ——————————
2.0 A
= 10.25 :
≈ 10.5 : (for a 1% resistor)
(Note from Figure 76 that the real value of IOL may vary from the value
calculated from the simple model shown.)
Step 2: Calculate total power dissipation in the HCPL-316J:
The HCPL-316J total power dissipation (PT) is equal to
the sum of the input-side power (PI) and output-side
power (PO):
PT = PI + PO
PI = ICC1 * VCC1
PO = PO(BIAS) + PO,SWTICH
= ICC2 * (VCC2–VEE ) + ESWITCH * fSWITCH
where,
Figure 76. Typical peak ION and IOFF currents vs. Rg (for
HCPL-316J output driving an IGBT rated at 600 V/100 A.
Figure 77. Switching energy plot for calculating average Pswitch
(for HCPL-316J output driving an IGBT rated at 600 V/100 A).
ION, IOFF (A)
0
-3
Rg (Ω)
200
3
1
4
20 100
-1
140
-2
0
2
IOFF (MAX.)
MAX. ION, IOFF vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
40 60 80 120 160 180
ION (MAX.)
Ess (μJ)
0
0
Rg (Ω)
200
8
5
9
50 100
3
150
1
4
7
Ess (Qg = 650 nC)
6
2
SWITCHING ENERGY vs. GATE RESISTANCE
(VCC2 / VEE2 = 25 V / 5 V
31
Figure 78. HCPL-316J thermal model.
Tji = junction temperature of input side IC
Tjo = junction temperature of output side IC
TP4 = pin 4 temperature at package edge
TP9,10 = pin 9 and 10 temperature at package edge
TI4 = input side IC to pin 4 thermal resistance
TI9,10 = output side IC to pin 9 and 10 thermal resistance
T4A = pin 4 to ambient thermal resistance
T9,10A = pin 9 and 10 to ambient thermal resistance
*The T4A and T9,10A values shown here are for PCB layouts shown
in Figure 78 with reasonable air ow. This value may increase or
decrease by a factor of 2 depending on PCB layout and/or airow.
Thermal Model
The HCPL-316J is designed to dissipate the majority of
the heat through pins 4 for the input IC and pins 9 and 10
for the output IC. (There are two VEE pins on the output
side, pins 9 and 10, for this purpose.) Heat ow through
other pins or through the package directly into ambient
are considered negligible and not modeled here.
In order to achieve the power dissipation specied in
the absolute maximum specication, it is imperative
that pins 4, 9, and 10 have ground planes connected to
them. As long as the maximum power specication is
not exceeded, the only other limita tion to the amount
of power one can dissipate is the absolute maximum
junction temperature specication of 125°C. The junc-
tion temperatures can be calculated with the following
equations:
Tji = Pi (Ti4 + T4A) + TA
Tjo = Po (To9,10 + T9,10A) + TA
where Pi = power into input IC and Po = power into out-
put IC. Since T4A and T9,10A are dependent on PCB layout
and airow, their exact number may not be available.
Therefore, a more accurate method of calcu lat ing the
junction temperature is with the following equations:
Tji = PiTi4 + TP4
Tjo = PoTo9,10 + TP9,10
These equations, however, require that the pin 4 and pins
9, 10 temperatures be measured with a thermal couple
on the pin at the HCPL-316J package edge.
From the earlier power dissipation calculation example:
Pi = 90.8 mW, Po = 217.3 mW, TA = 100°C, and assuming
the thermal model shown in Figure 77 below.
Tji = (90.8 mW)(60°C/W + 50°C/W) + 100°C
= 110°C
Tjo = (217.3 mW)(30°C/W + 50°C/W) + 100°C
= 117°C
both of which are within the absolute maximum speci-
cation of 125°C.
If we, however, assume a worst case PCB layout and no
air ow where the estimated q4A and q9,10A are 100°C/W.
Then the junction temperatures become
Tji = (90.8 mW)(60°C/W + 100°C/W) + 100°C
= 115°C
Tjo = (217.3 mW)(30°C/W + 100°C/W) + 100°C
= 128°C
The output IC junction temperature exceeds the abso-
lute maximum specication of 125°C. In this case, PCB
layout and airow will need to be designed so that the
junction temperature of the output IC does not exceed
125°C.
If the calculated junction temperatures for the thermal
model in Figure 78 is higher than 125°C, the pin temper-
ature for pins 9 and 10 should be measured (at the pack-
age edge) under worst case operating environment for a
more accurate estimate of the junction temperatures.
TP4 TP9,10
θ4A = 50°C/W* θ9,10A = 50°C/W*
TA
θi4 = 60°C/W θO9,10 = 30°C/W
Tji Tjo
32
Printed Circuit Board Layout Considerations
Adequate spacing should always be maintained be-
tween the high voltage isolated circuitry and any input
referenced circuitry. Care must be taken to provide the
same minimum spacing between two adjacent high-side
isolated regions of the printed circuit board. Insucient
spacing will reduce the eective isolation and increase
parasitic coupling that will degrade CMR performance.
The placement and routing of supply bypass capacitors
requires special attention. During switch ing transients,
the majority of the gate charge is supplied by the bypass
capacitors. Maintaining short bypass capacitor trace
lengths will ensure low supply ripple and clean switch-
ing waveforms.
Ground Plane connections are necessary for pin 4 (GND1)
and pins 9 and 10 (VEE) in order to achieve maximum
power dissipation as the HCPL-316J is designed to dissi-
pate the majority of heat generated through these pins.
Actual power dissipation will depend on the application
environment (PCB layout, air ow, part placement, etc.)
See the Thermal Model section for details on how to es-
timate junction temperature.
The layout examples below have good supply bypassing
and thermal properties, exhibit small PCB footprints, and
have easily connected signal and supply lines. The four
examples cover single sided and double sided compo-
nent placement, as well as minimal and improved per-
formance circuits.
Figure 79. Recommended layout(s).
For product information and a complete list of distributors, please go to our website: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes AV01-0579EN
AV02-0717EN - March 28, 2011
Figure 80. Minimum LED Skew for Zero Dead Time. Figure 81. Waveforms for Dead Time Calculation.
System Considerations
Propagation Delay Dierence (PDD)
The HCPL-316J includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 62) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between
the high and low voltage motor rails, a potentially cata-
strophic condi tion that must be prevented.
To minimize dead time in a given design, the turn-on of
the HCPL-316J driving Q2 should be delayed (relative to
the turn-o of the HCPL-316J driving Q1) so that under
worst-case conditions, transistor Q1 has just turned o
when transistor Q2 turns on, as shown in Figure 80. The
amount of delay necessary to achieve this condition is
equal to the maxi mum value of the propagation delay
dierence specication, PDDMAX, which is specied to
be 400 ns over the operating temperature range of -40°C
to 100°C.
Delaying the HCPL-316J turn-on signals by the maximum
propaga tion delay dierence ensures that the minimum
dead time is zero, but it does not tell a designer what the
maximum dead time will be. The maximum dead time is
equivalent to the dierence between the maximum and
minimum propagation delay dierence specications
as shown in Figure 81. The maximum dead time for the
HCPL-316J is 800 ns (= 400 ns - (-400 ns)) over an operat-
ing temperature range of -40°C to 100°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal tempera tures and test
conditions since the optocouplers under consider a tion
are typically mounted in close proximity to each other
and are switching identical IGBTs.
tPHLMAX
tPLHMIN
PDD* MAX = (tPHL- tPLH)MAX = tPHLMAX - tPLHMIN
*PDD = PROPAGATION DELAY
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
VIN+2
VOUT2
VIN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPLHMIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (tPHLMAX - tPHLMIN) + (tPLHMAX - tPLHMIN)
= (tPHLMAX - tPLHMIN) – (tPHLMIN - tPLHMAX)
= PDD*MAX – PDD*MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
VIN+2
VOUT2
VIN+1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
tPHLMIN
tPHLMAX
tPLHMAX
= PDD*MAX
(tPHL-tPLH)MAX