_______________General Description
The MAX1114 is a monolithic, flash analog-to-digital
converter (ADC) that can digitize a 2V analog input
signal into 8-bit digital words at a typical 150Msps
update rate.
For most applications, no external sample-and-hold is
required for accurate conversion due to the device's
narrow aperture time, wide bandwidth, and low input
capacitance. A single standard -5.2V power supply is
required to operate the MAX1114, with nominal 2.2W
power dissipation. A special decoding scheme reduces
metastable errors to 1LSB.
The part is packaged in a 42-pin ceramic sidebraze
that is pin-compatible with the CX20116 and
CXA1396D. The surface-mount 44-pin CERQUAD
allows access to additional reference ladder taps, an
overrange bit, and a data-ready output. For higher con-
version rates, the pin-compatible 300Msps MAX1125 is
available.
________________________Applications
Digital Oscilloscopes
Transient Capture
Radar, EW, ECM
Direct RF Down-Conversion
Medical Electronics
Ultrasound, CAT Instrumentation
____________________________Features
♦Metastable Errors Reduced to 1LSB
♦10pF Input Capacitance
♦210MHz Input Bandwidth
♦150Msps Conversion Rate
♦2.2W Typical Power Dissipation
♦Single -5.2V Supply
MAX1114
8-Bit, 150Msps Flash ADC
________________________________________________________________
Maxim Integrated Products
1
19-1101; Rev 0; 6/96
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
PART
MAX1114AIDO
MAX1114BIDO
MAX1114AIBH -20°C to +85°C
-20°C to +85°C
-20°C to +85°C
TEMP. RANGE PIN-PACKAGE
42 Ceramic SB
42 Ceramic SB
44 CERQUAD
MAX1114BIBH -20°C to +85°C 44 CERQUAD
______________Ordering Information
MAX1114
CERQUAD
23
24
25
26
27
28
29
30
31
32 VEE
LINV
N.C.
DRINV
N.C.
VEE
AGND
AGND
VRTS
VRTF
33 AGND
2
3
4
5
6
7
8
9
10
11
VRBF
VRBS
AGND
AGND
VEE
CLK
CLK
MINV
VEE
AGND 1
DGND
38
39
40
41
42
34
35
36
37
43
44
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
DREADY
DGND
D8 (MSB)
15
18
20
19
21
22
16
17
13
14
AGND
VR1
AGND
VIN
AGND
VR2
AGND
VIN
VEE
VR3
VEE 12
TOP VIEW
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VEE
N.C.
LINV
VEE
AGND
DGND
DO (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DGND
AGND
VEE
MINV
N.C.
CLK
CLK
N.C.
VRTF
N.C.
VEE
VEE
N.C.
N.C.
AGND
VIN
AGND
VR2
AGND
VIN
AGND
N.C.
N.C.
VEE
VEE
N.C.
VRBF
N.C.
TOP VIEW
Ceramic SB
MAX1114
_________________Pin Configurations
____Pin Configurations (continued)
±1
±0.75
±1
±0.75
INL (LSBs)
EVALUATION KIT
AVAILABLE
Functional Diagram appears at end of data sheet.
MAX1114
8-Bit, 150Msps Flash ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA= TMIN to TMAX,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Negative Supply Voltage (VEE TO GND) ..............-7.0V to +0.5V
Ground Voltage Differential...................................-0.5V to +0.5V
Analog Input Voltage ...............................................VEE to +0.5V
Reference Input Voltage..........................................VEE to +0.5V
Digital Input Voltage.................................................VEE to +0.5V
Reference Current VRTF to VRBF.........................................25mA
Digital Output Current ...........................................0mA to -30mA
Operating Temperature Range ...........................-25°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec).............................+300°C
V
V
V
VI
V
V
VI
VI
V
VI
VI
V
V
V
VI
IV
V
IV
V
TEST
LEVEL
ns1.5Acquisition Time ps5Aperture Jitter ns2.0
CLK-to-Data Ready Delay
(tD)ps/°C2Output Delay Tempco ns2.4Clock to Data Delay Msps125 150Maximum Sample Rate
MHz10Reference Bandwidth Ω100 200 300Ladder Resistance
MHz335IN = 500mVp-pSmall-Signal Bandwidth MHz210VIN = full scaleLarge-Signal Bandwidth V/µs1,000Input Slew Rate
LSB-0.75 +0.75fCLK = 100 kHzDifferential Linearity LSB-0.75 ±0.60 +0.75fCLK = 100 kHzIntegral Linearity
µA250 500Input Current kΩ15Input Resistance pF10Over full input rangeInput Capacitance V-2.0 0.0Input Voltage Range
GuaranteedNo missing codes
mV-30 +30Offset Error VRT mV-30 +30Offset Error VRB
UNITS
MAX1114A
MIN TYP MAX
CONDITIONSPARAMETER
1.5
5
2.0
2
2.4
125 150
10
100 200 300
335
210
1,000
-0.95 +0.95
-0.95 ±0.80 +0.95
250 500
15
10
-2.0 0.0
Guaranteed
-30 +30
-30 +30
MAX1114B
MIN TYP MAX
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT
TIMING CHARACTERISTICS
dB
MAX1114
8-Bit, 150Msps Flash ADC
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
VEE = -5.2V, RSOURCE = 50Ω, VRBF = -2.00V, VR2 = -1.00V, VRTF = 0.00V, fCLK = 150MHz, 50% Duty Cycle, TA= TMIN to TMAX,
unless otherwise noted.)
I
VI
I
V
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
V
VI
TEST
LEVEL
W2.2 2.9TA= +25°CPower Dissipation mA425 550TA= +25°CSupply Current ns2.4 V-1.550Ωto -2VDigital Output Low Voltage V-1.150Ωto -2VDigital Output High Voltage
ns43Clock High Width, TPWH
ns43Clock Low Width, TPWL
µA40
Clock Synchronous
Input Currents
42 46 dB
46 48fIN = 3.58MHz
Signal-to-Noise Ratio
V-2.0 -1.5
Digital Input High Voltage
(MINV, LINV) V-1.1 -0.7
dB
-48 -52fIN = 3.58MHz
Total Harmonic Distortion -40 -44fIN = 50MHz
dB
45 48fIN = 3.58MHz
Signal-to-Noise and
Distortion (SINAD) 39 42fIN = 50MHz
UNITS
MAX1114A
MIN TYP MAX
CONDITIONSPARAMETER
2.2 2.9
425 550
2.4 -1.5
-1.1
43
43
40
40 44
45 47
-2.0 -1.5
-1.1 -0.7
-46 -50
-39 -43
43 46
37 40
MAX1114B
MIN TYP MAX
Digital Input Low Voltage
(MINV, LINV)
fIN = 50MHz
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications are
guaranteed. The Test Level column indicates the
specific device testing actually performed during
production and Quality Assurance inspection.
Any blank section in the data column indicates
that the specification is not tested at the specified
condition.
Unless otherwise noted, all tests are pulsed;
therefore, Tj= TC= TA.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25°C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and
characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25°C. Parameter is guaranteed
over specified temperature range.
POWER SUPPLY REQUIREMENTS
DIGITAL OUTPUTS
DIGITAL INPUTS
DYNAMIC PERFORMANCE
MAX1114
8-Bit, 150Msps Flash ADC
4 _______________________________________________________________________________________
52
1 10 100
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
36
34
INPUT FREQUENCY (MHz)
SNR (dB)
40
38
44
42
46
48
50
fs = 125Msps
MAX1114 -01
__________________________________________Typical Operating Characteristics
(Circuit of Figure 1, TA= +25°C, unless otherwise noted.)
52
1 10 100
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
36
34
INPUT FREQUENCY (MHz)
THD (dB)
40
38
44
42
46
48
50
fs = 125Msps
MAX1114 -02
52
1 10 100
SIGNAL-TO-NOISE AND DISTORTION
vs. INPUT FREQUENCY
36
34
INPUT FREQUENCY (MHz)
SINAD (dB)
40
38
44
42
46
48
50
fs = 125Msps
MAX1114 -03
50
80
SNR, THD, SINAD
vs. TEMPERATURE
45
TEMPERATURE (°C)
SNR, THD, SINAD (dB)
0
35
30 -40 -20 60
40
20 40
SNR
SINAD
THD
fs = 125Msps
fIN = 50MHz
MAX1114 -04
MAX1114
_______________________________________________________________________________________ 5
21
1, 4, 17, 25, 26, 38, 39 Negative Analog Supply (nominally -5.2V)
ECL Clock Input Pin
2, 19, 22, 24, 27, 28, 36,
37, 40, 42 No Connect. Not internally connected.
20
6, 15 Digital Ground
Inverse ECL Clock Input Pin
7 Digital Data Output (LSB)
—
— Overrange Output
Reference Voltage Bottom, Sense
30, 34
14 Digital Data Output (MSB)
Analog Input. Can be connected to the input
signal or used as a sense.
8–13 Digital Data Outputs
32 Reference Voltage Tap 2 (typically -1V)
— Reference Voltage Top, Sense
41 Reference Voltage Top, Force
—
— Data-Ready Output
Data-Ready Inverse
CLK
VEE
N.C.
CLK
DGND
D0
VRBS
D8
VIN
D7
D1–D6
VR2
VRTS
VRTF
DRINV
DREADY
6
3, 7, 12, 22, 27, 32
28, 30
5
PIN
1, 34
36
10
44
15, 19
43
37–42
17
24
23
29
35
3D0–D6 Output Conversion Control LINV31
5, 16, 29, 31, 33, 35 Analog GroundAGND
2, 8, 9, 14, 16, 18, 20,
25, 26, 33
23 Reference Voltage Bottom, ForceVRBF11
— Reference Voltage Tap 1 (typically -1.5V)VR113
— Reference Voltage Tap 3 (typically -0.5V)VR321
______________________________________________________________Pin Description
8-Bit, 150Msps Flash ADC
FUNCTION
Ceramic SB NAME
CERQUAD
_______________Detailed Description
The MAX1114 is a 150Msps, monolithic, 8-bit parallel
flash analog-to-digital converter (ADC) with an analog
bandwidth of over 200MHz. A major advance over pre-
vious flash converters is the inclusion of 256 input pre-
amplifiers between the reference ladder and input
comparators. (See
Functional Diagram.
) This feature
not only reduces clock-transient kickback to the input
and reference ladder due to a low AC beta, but also
reduces the effect of the dynamic state of the input sig-
nal on the latching characteristics of the input compara-
tors. The preamplifiers act as buffers and stabilize the
input capacitance so it remains constant for varying
input voltages and frequencies, making the part easier
to drive than previous flash converters. The MAX1114
incorporates a special decoding scheme that reduces
metastable errors (sparkle codes or flyers) to a maxi-
mum of 1LSB.
18 D7 Output Conversion ControlMINV4
The MAX1114 has true differential analog and digital
data paths from the preamplifiers to the output buffers
(Current-Mode Logic) for reducing potential missing
codes while rejecting common-mode noise.
Careful layout of the analog circuitry reduces signature
errors. Every comparator has a clock buffer to reduce
differential delays and to improve signal-to-noise ratio.
The output drive capability of the device can provide
full ECL swings into 50Ωloads.
___________Typical Interface Circuit
Figure 1 shows the typical interface circuit. The
MAX1114 is relatively easy to apply, depending on the
accuracy needed. Wire-wrap may be employed with
careful point-to-point ground connections if desired, but
a double-sided PC board with a ground plane on the
component side, separated into digital and analog sec-
tions gives the best performance. The converter is
bonded-out to place the digital pins on the left side of
the package and the analog pins on the right side.
Additionally, an RF bead connection through a single
point from the analog to digital ground planes reduces
ground noise pickup.
Figure 2 (CERQUAD package only) shows the most
elaborate method of achieving the least error by cor-
recting for integral nonlinearity, input-induced distor-
tion, and power-supply/ground noise. It uses external
reference ladder tap connections, an input buffer, and
supply decoupling. The function of each pin and exter-
nal connections to other components is as follows:
V
EE
, AGND, DGND
VEE is the supply pin with AGND as ground for the
device. The power-supply pins should be bypassed as
close to the device as possible with at least a 0.01µF
ceramic capacitor. A 1µF tantalum should also be used
for low-frequency suppression. DGND is the ground for
the ECL outputs and should be referenced to the output
pulldown voltage and bypassed as shown in Figure 1.
Analog Input VIN
There are two analog input pins that are tied to the
same point internally. Either one may be used as an
analog input sense and the other for input force. This is
convenient for testing the source signal to see if there is
sufficient drive capability. The pins can also be tied
together and driven by the same source. The MAX1114
is superior to similar devices due to a preamplifier
stage before the comparators (Figure 4). This makes
the device easier to drive because it has constant
capacitance and induces less slew-rate distortion. An
optional input buffer may be used.
Clock Inputs CLK,
CLK
The clock inputs are designed to be driven differentially
with ECL levels. The clock may be driven single-ended
since CLK is internally biased to -1.3V (Figure 5). CLK
may be left open but a 0.01µF bypass capacitor from
CLK to AGND is recommended. NOTE: System perfor-
mance may be degraded due to increased clock noise
or jitter.
Output Logic Control MINV, LINV
These are ECL-compatible digital controls for changing
the output code from straight binary to two's comple-
ment, etc. (Table 1 and Figure 4). Both MINV and LINV
are in the logic low (0) state when they are left open.
The high state can be obtained by tying to AGND
through a diode or 3.9kΩresistor.
Digital Outputs D0 to D7
The digital outputs can drive ECL levels into 50Ωwhen
pulled down to -2V. When pulled down to -5.2V, the out-
puts can drive 150Ωto 1kΩloads.
Reference Inputs VRBF, VR2, VRTF
There are two reference inputs and one external refer-
ence voltage tap. These are -2V (VRBF), mid-tap (VR2)
and AGND (VRTF). The reference pins can be driven as
shown in Figure 1. VR2 should be bypassed to AGND
for further noise suppression.
MAX1114
8-Bit, 150Msps Flash ADC
6 _______________________________________________________________________________________
Table 1. Output Coding
MINV
LINV 0
00
11
01
1
0V 111...11 100...00 011...11 000...00
111...10 100...01 011...10 000...01.
.....
.....
.....
. 011...11 000...00 111...11 100...00
.....
.....
.....
-2V 000...00 011...11 100...00 111...11
000...01 011...10 100...01 111...10.
. 100...00 111...11 000...00 011...11
1: V
IH,
V
OH
0: V
IL,
V
OL
V
IN
Reference Inputs VRBF, VRBS, VR1, VR2,
VR3, VRTF, VRTS (CERQUAD package only)
These are five external reference voltage taps from -2V
(VRBF) to AGND (VRTF) which can be used to control
integral linearity over temperature. The taps can be driv-
en by op amps (Figure 2). These voltage level inputs
can be bypassed to AGND for further noise suppres-
sion, if so desired. VRB and VRT have force and sense
pins for monitoring the top and bottom voltage refer-
ences.
Not Connected (N.C.)
All N.C. pins should be tied to DGND on the left side of
the package and to AGND on the right side of the
package.
Data Ready and Data-Ready Inverse
DREADY, DRINV (CERQUAD package only)
The data-ready pin is a flag that goes high or low at the
output when data is valid or ready to be received. It is
essentially a delay line that accounts for the time nec-
essary for information to be clocked through the
MAX1114’s decoders and latches. This function is use-
ful for interfacing with high-speed memory. Using the
data-ready output to latch the output data ensures mini-
mum setup and hold times. DRINV is a data-ready
inverse control pin (Figure 3).
Overrange Input D8
(CERQUAD package only)
When the MAX1114 is in an overrange condition, D8
goes high and all data outputs go high as well. This
makes it possible to include the MAX1114 in higher res-
olution systems.
Operation
The MAX1114 has 256 preamp/comparator pairs that
are each supplied with the voltage from VRTF to VRBF
divided equally by the resistive ladder as shown in the
Functional Diagram
. This voltage is applied to the posi-
tive input of each preamplifier/comparator pair. An ana-
log input voltage applied at VIN is connected to the
negative inputs of each preamplifier/comparator pair.
The comparator states are then clocked through each
comparator's individual clock buffer. When CLK is low,
the master, or input stage, of the comparators com-
pares the analog input voltage to the respective refer-
ence voltage. When CLK changes from low to high, the
comparators are latched to the state prior to the clock
transition and output logic codes in sequence from the
top comparators, closest to VRTF (0V), down to the
point where the magnitude of the input signal changes
sign (thermometer code). The output of each compara-
tor is then registered into four 64-to-6 bit decoders
when CLK is changed from high to low. At the
decoders' output is a set of four 7-bit latches that are
enabled (track) when CLK changes from high to low.
From here, the outputs of the latches are coded into 6
LSBs from 4 columns and 4 columns are coded into 2
MSBs. Next are the MINV and LINV controls for output
inversions that consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to
drive the external loads. The conversion takes one
clock cycle from the input to the data outputs.
_________________Evaluation Boards
The MAX1114/MAX1125 evaluation kit (EV kit) demon-
strates the full performance of the MAX1114. This
board includes a voltage reference circuit, clock driver
circuit, output data latches and an on-board recon-
struction of the digital data. A separate EV kit manual
describing the operation of this board is also available.
Contact the factory for price and delivery.
MAX1114
8-Bit, 150Msps Flash ADC
_______________________________________________________________________________________ 7
MAX1114
8-Bit, 150Msps Flash ADC
8 _______________________________________________________________________________________
MAX1114
CLOCK
BUFFER
VEE
-5.2V
VRTF
VIN
VRBF
VREF
CLK
CONVERT
100116
CLK
256-BIT
TO 8-BIT
ENCODER
ECL
LATCHES
AND
BUFFERS
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
1
2
2
63
64
127
128
151
152
255
256
VEE
-5.2V
VIN MINV
LINV
L
PREAMP COMPARATOR
0.01µF
0.01µF
-2V
(DIGITAL)
0.01µF
0.01µF
0.01µF
10Ω TO
25Ω
50Ω50Ω
50Ω x 8
-2V
(ANALOG)
-2V OP07
BUFFER
OPTIONAL ANALOG INPUT
CAN BE EITHER
FORCE OR SENSE
= AGND
= DGND
VR2
0.01µF
ANALOG INPUT
CAN BE EITHER
FORCE OR SENSE
Figure 1. Typical Interface Circuit 1
MAX1114
8-Bit, 150Msps Flash ADC
_______________________________________________________________________________________ 9
MAX1114
CLOCK
BUFFER
VEE
-5.2V
VEE
VRTS
VRTF VIN
VIN
VRBF
VRBS
VREF
-2V
CLK
CONVERT CLK
256-BIT
TO 8-BIT
ENCODER
ECL
LATCHES
AND
BUFFERS
D7
(MSB)
OVERRANGE
D8
D6
D5
D4
D3
D2
D1
D0
(LSB)
1
2
2
63
64
127
128
151
152
255
256
VEE
-5.2V
AGNDDGND
MINV
LINV
PREAMP COMPARATOR
0.01µF
0.01µF
0.01µF
-2V
(DIGITAL)
-2V 0.01µF
0.01µF
0.01µF
10Ω TO
25Ω
50Ω50Ω
50Ω
x 10
DREADY
DRINV
-2V
(ANALOG)
VR1
0.01µF
10Ω TO
25Ω
VR2
0.01µF
10Ω TO
25Ω
VR3
0.01µF
10Ω TO
25Ω
0.01µF
10Ω TO
25Ω
BUFFER
OPTIONAL
U5
U4
U3
U2
U1
1k,
0.1%
1k,
0.1%
1k,
0.1%
1k,
0.1%
NOTE: U1–U5
ARE OP07 OR
EQUIVALENT,
LOW-NOISE,
LOW-OFFSET
AMPLIFIERS.
*
**
L
*ANALOG INPUT (FORCE)
**ANALOG INPUT (SENSE)
100116
Figure 2. Typical Interface Circuit 2 (CERQUAD package only)
MAX1114
8-Bit, 150Msps Flash ADC
10 ______________________________________________________________________________________
I
NPUT CIRCUIT OUTPUT CIRCUIT MINV, LINV INPUT CIRCUIT
AGND DGND
DATA OUT
AGND
VR
VIN
V
EE
AGND
-1.3V
10k
16k
V
EE
MINV
LINV
Figure 3. Timing Diagram
Figure 4. Subcircuit Schematics
CLK
CLK
ANALOG INPUT
VIN
NN + 1 N + 2
CLOCK
MASTER
SLAVE
COMPARATOR OUTPUT
6-BIT LATCH OUTPUT
8-BIT LATCH OUTPUT
DATA OUTPUT D0–D7 N - 1 NN + 1
INTERNAL TIMING
Tpw1 Tpw0
OVERRANGE D8
DREADY
tD
TIMING FOR CERQUAD PACKAGE ONLY
MAX1114
8-Bit, 150Msps Flash ADC
______________________________________________________________________________________ 11
Figure 5. Clock Input
Figure 6. Burn-In Circuit (Ceramic SB package only)
AGND
V
EE
-1.3V
CLK
CLK
13k
13k
R1 R1 R1 R1 R1 R1 R1 R1
-2V
R2
R2
R2
R4
R3
1N4736
D0
D1
D2
D3
D4
D5
D6
D7
MINV
LINV
MAX1114
R2
-2V
CLK CLK
CLK
CLK
DGND
AGND
VIN VIN
VREF
VRBF
VRTF
VEE
VEE
R1 = 50Ω 1/4 Watt CC 5%
R2 = 1kΩ 1/4 Watt CC 5%
R3 = 6.5Ω 1/4 Watt CC 5%
R4 = 6.5Ω 1/2 Watt CC 5%
VREF = -2.00V
VEE = -6.6V
R4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
MAX1114
8-Bit, 150Msps Flash ADC
MAX1114
CLOCK
BUFFER
THESE FUNCTIONS ARE
AVAILABLE IN THE
CERQUAD PACKAGE ONLY.
ANALOG INPUT
(FORCE OR SENSE)
ANALOG INPUT
(FORCE OR SENSE) VEE
VRTS
VRTF
VR3
VR2
VR1
VRBS
VRBE
CLK
CONVERT CLK
256-BIT
TO 8-BIT
ENCODER
ECL
LATCHES
AND
BUFFERS
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
OVERRANGE
DREADY
DRINV
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
AGND
1
2
2
63
64
127
128
151
152
255
256
VEE
DGNDAGND MINVLINV
PREAMP COMPARATOR
_________________________________________________________Functional Diagram
