1
Features
•Low-powerOperationIncludingSpecialSTOPMode
•Frequency:16.78MHzat5V±10%Supplyand20.97MHzat5V±5%,Software
Programmable
•Technology:1µHigh-densityComplementaryMetal-OxideSemiconductor(HCMOS),
StaticDesign
•Package:132-pinCeramicLeadedChipCarrier(CERQUAD)and132-pinCeramicPin
GridArray(PGA)
•ModularArchitectureinaSingleChip
•CPU:32-bit6800Family(UpwardObject-codeCompatibleWithThe68010)
•NewInstructionsForControllerApplications
•Intelligent16-bitTimer
– 16Independent,ProgrammableChannels
– AnyChannelCanPerformAnyTimeFunction(forExampleInputCapture,Output
Compare,PulseWidthModulation,etc.)
– TwotimerCountRegisterswith2-bitProgrammablePrescalers
– SelectableChannelPriorityLevels
– ReducedCPUIntervention
– RISClikeCPUWithintheTPU
•TwoSerialI/OSubsystems
– Enhanced68HC11-typeSerialCommunicationsInterface(SCI)Universal
AsynchronousReceiverTransmitter(UART)withParity
– Enhanced68HC11-typeSerialPeripheralInterfaceWithI/ORAMQueue(QSPI)
•On-chipMemory:2-KbytesStandbyRAM
•On-chip,Programmable,Chip-selectLogic
– Upto12SignalsforMemoryandPeripheralInterfacewithI/OSelect
•SystemFailureProtection
– 68HC11-typeComputerOperatingProperly(COP)WatchdogTimer
– 68HC11-typePeriodicInterruptTimer
– 68000FamilySpuriousInterrupt,Halt,andBusTime-outMonitors
•Upto48DiscreteI/OPins
Description
TheTS68332isa32-bitmicrocontroller,combininghigh-performancedatamanipula-
tioncapabilitieswithpowerfulperipheralsubsystems.TheTS68332isthefirst
memberofthe68300familyofmodularembeddedcontrollersfeaturingfullystatic,
high-speedcomplementarymetal-oxidesemiconductortechnology.Basedonthe
powerfulTS68020,theCPU32instructionprocessingmoduleprovidesenhancedsys-
temperformanceandutilizestheextensivesoftwarebaseofthe68000family.
High-
performance
32-bitIntegrated
Microcontroller
TS68332
Rev.2118A–HIREL–03/02
2TS68332 2118A–HIREL–03/02
Screening/Quality
Thisproductismanufacturedinfullcompliancewith:
• MIL-STD-883(classB)
• DSCC5962-91501
• OraccordingtoAtmel-Grenoblestandard
Introduction Figure1isablockdiagramoftheTS68332showingthemajorcomponents.Thepin
descriptionsareprovidedinTable1.TheTS68332containsintelligentperipheralmod-
ulessuchastheTimeProcessorUnit(TPU),whichprovides16microcodedchannels
forperformingtime-relatedactivitiesfromsimpleinputcaptureoroutputcompareto
complicatedmotorcontrolorpulsewidthmodulation.High-speedserialcommunications
areprovidedbytheQueuedSerialModule(QSM)withsynchronousandasynchronous
protocolsavailable.2-KbytesoffullystaticstandbyRAMallowfasttwo-cycleaccessfor
systemanddatastacksandvariablestoragewithprovisionforbatteryback-up.Thereis
aSystemIntegrationModule(SIM)whichincludestwelvechipselectstoenhancesys-
temintegrationforfastexternalmemoryorperipheralaccess.Thepowerful32-bitCPU
(CPU32)isbasedontheindustry-standardTS68020.Thesemodulesareconnectedon
chipviatheIntermoduleBus(IMB)andprovidereducedsystempartcount,size,costof
implementationandincreasedreliability.
R suffix
PGA 132
Ceramic Pin Grid Array
A suffix
CERQUAD 132
Ceramic Leaded Chip Carrier
3
TS68332
2118A–HIREL–03/02
Figure1.BlockDiagramofTS68332
QS5/PCS2
PQS7/TXD
PQS4/PCS1
PQS6/PCS3
CPU 32
QSM
IMB
TPU
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PORT QS
TXD
PCS2
SCK
MISO
MOSI
CONTROL
PCS1
PQS3/PCS0/SS PCS0/SS
RXD
PCS3
BKPT/DSCLK
IFETCH/DSI
IPIPE/DSO
DSI
DSO
IPIPE
IFETCH
BKPT
IRQ[7:1]
ADDR[23:0]
CONTROL
PORT F PORT C
FC2
FC1
FC0
BG
BR
BGACK
MODCLK
ADDR[23:19]
CLOCK
EBI
CS[10:0]
BR/CS0
BG/CS1
BGACK/CS2
R/W
RESET
HALT
BERR
CLKOUT
XTAL
EXTAL
CHIP
SELECTS CSBOOT
ADDR[18:0]
DATA[15:0]DATA[15:0]
QUOT
TEST
FREEZE/QUOT
TSC
CONTROL
TSC
PC0/FC0/CS3
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CONTROL
PORT E
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
DSACK0 PE0/DSACK0
DSACK1 PE1/DSACK1
AVEC PE2/AVEC
PE3/RMC
DS PE5/DS
RMC
PE4/AS
T2CLK T2CLK
TPUCH[15:0] TPUCH[15:0]
XFC
VDDSYN
2 KBYTES
RAM
VSTBY
CONTROL
AS
CONTROL
DSCLK
FREEZE
4TS68332 2118A–HIREL–03/02
SignalDescription Figure1illustratesthefunctionalsignalgroupsandTable1liststhesignalsandtheir
function.
Table1.SignalIndex
SignalName Mnemonic Function
AddressBus A23-A0 24-bitaddressbus
DataBus D15-D0 16-bitdatabususedtotransferbyteorworddataperbuscycle
DataBusFunctionCodes FC2-FC0 Identifytheprocessorstateandtheaddressspaceofthecurrentbuscycle
BootChipSelect CSBOOT Chip-selectbootstatupROMcontaininguser’sresetvectorandinitialization
program
ChipSelects CS10-CSO Enablesperipheralsatprogrammedaddresses
BusRequest BR Indicatesthatanexternaldevicerequiresbusmastership
BusGrant BG IndicatesthatcurrentbuscycleiscompleteandtheTS68332hasrelinquishedthe
bus
BusGrantAcknowledge BGACK Indicatesthatanexternaldevicehasassumedbusmastership
DataandSize
Acknowledgement DSACK1,
DSACK0 Providesasynchronousdatatransfersanddynamicbussizing
Autovector AVEC Requestsanautomaticvectorduringaninterruptacknowledgecycle
Read-Modify-WriteCycle RMC Identifiesthebuscycleaspartofanindivisibleread-modify-writecycle
AddressStrobe AS Indicatesthatavalidaddressisontheaddressbus
DataStrobe DS Duringareadcycle,DSindicatesthatanexternaldeviceshouldplacevaliddataon
thedatabus.Duringawritecycle,DSindicatesthatvaliddataisonthedatabus.
Size SIZ1-SIZ0 Indicatesthenumberofbytesremainingtobetransferredforthiscycle
Read/Write R/W Indicatesthedirectionofdatatransferonthebus
InterruptRequestLevel IRQ7-IRQ0 ProvidesaninterruptpriorityleveltotheCPU
Reset RESET Systemreset
Halt HALT Suspendexternalbusactivity
BusError BERR Indicatesthatanerroneousbusoperationisbeingattempted
SystemClockout CLKOUT Internalsystemclock
CrystalOscillator EXTAL,
XTAL Connectionforanexternalcrystaltotheinternaloscillatorcircuit
ExternalFilterCapacitor XFC Connectionpinforanexternalcapacitortofilterthecircuitofthephase-lockedloop
ClockModeSelect MODCK Selectsthesourceoftheinternalsystemclock
InstructionFetch IFETCH IndicateswhentheCPUisperforminganinstructionwordpre-fetchandwhenthe
instructionpipelinehasbeenflushed
InstructionPipe IPIPE Usedtotrackmovementofwordsthroughtheinstructionpipeline
Breakpoint BKPT SignalsahardwarebreakpointtotheCPU
Freeze FREEZE IndicatesthattheCPUhasacknowledgedabreakpoint
QuotientOut QUOT SerialI/Oandclockforbackgrounddebugmode
TestModeEnable TSTME Hardwareenablefortestmode
Three-StateControl TSC Placesalloutputdriversinahigh-impedancestate
5
TS68332
2118A–HIREL–03/02
DevelopmentSerialIn,Out,
Clock DSI,DSO,
DSCLK SerialI/Oandclockforbackgrounddebugmode
TPUChannels TP15-TP0 TPUchannelinput/outputSerialI/Oandclockforbackgrounddebugmode
TPUClockIn T2CLK ExternalclocksourcetotheTPU
SCIReceiveData RXD SerialinputtotheSCI
SCITransmitData TXD SerialoutputfromtheSCI
PeripheralChipSelect PCS3-PCS0 QSPIperipheralchipselects
SlaveSelect SS PlacestheQSPIinslavemode
QSPISerialClock SCK FurnishestheclockfromtheQSPIinmastermodeortotheQSPIinslavemode
Master-inSlave-out MISO FurnishesserialinputtotheQSPIinmastermode,andserialoutputfromtheQSPIin
slavemode
Master-outSlave-in MOSI FurnishesserialoutputfromtheQSPIinmastermode,andserialinputtotheQSPIin
slavemode
StandbyRAM VSTBY PowersupplyforRAM
SynchronizerPower VDDSYN PowersupplytoVCO
SystemPowerSupplyand
Return VDD,VSS PowersupplyandreturntotheMCU
Table1.SignalIndex(Continued)
SignalName Mnemonic Function
6TS68332 2118A–HIREL–03/02
Figure2.PGATerminalDesignation
7
TS68332
2118A–HIREL–03/02
Figure3.CERQUADTerminalDesignation
TOP VIEW
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
VDD
VSS
VDD
PE1/DSACK1
PE0/DSACK0
PE2/AVEC
PE3/RMC
PE5/DS
CSBOOT
BGACK/CS2
BG/CS1
BR/CS0
VSTBY
51 17
117
16
15
14
13
12
11
10
9
8
7
6
5
4
3
131
130
129
128
127
126
125
124
123
122
121
120
119
118
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
PQS7/TXD
RXD
IPIPE/DSO
FREEZE/QUOT
XTAL
EXTAL
XFC
CLKOUT
PF0/MODCLK
PE7/SIZ1
PE6/SIZ0
TPUCH0
TPUCH1
TPUCH2
TPUCH3
TPUCH4
TPUCH5
TPUCH6
TPUCH7
TPUCH8
TPUCH9
TPUCH10
TPUCH11
TPUCH13
TPUCH14
TPUCH15
T2CLK
TPUCH12
VSS
VDD
VSS
PC0/FC0/CS3
PC1/FC1/CS4
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
ADDR23/CS10
AS
R/W
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
TSC
BKPT/DSCLK
IFETCH/DSI
2
1
132
VDDSYN
VSS
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
VDD
VDD
VSS
VDD
VDD
VSS
VSS
VDD
VSS
VSS
VSS
VDD
VDD
8TS68332 2118A–HIREL–03/02
Scope Thisdrawingdescribesthespecificrequirementsforthemicrocontroller68332at16.78
MHzand20.97MHz,incomplianceeitherwithMIL-STD-883classBorAtmel-Grenoble
standard.
Applicable
Documents
MIL-STD-883 1. MIL-STD-883:testmethodsandproceduresforelectronics.
2. MIL-I-38535:generalspecificationsformicrocircuits.
3. DSCCDrawing:5962-91501.
Requirements
General Themicrocircuitsareinaccordancewiththeapplicabledocumentandasspecified
herein.
DesignAndConstruction
TerminalConnections Dependingonthepackage,theterminalconnectionsshallbeasshowninFigure2and
Figure3.
LeadMaterialandFinish LeadmaterialandfinishshallbeanyoptionofMIL-STD-853.
Package Themacrocircuitsarepackagedinhermeticallysealedceramicpackageswhichcon-
formtocaseoutlinesofMIL-M-38510appendixC(whendefined):
• 132-PINSQ.PGAUPPAEoutline
• 132-PINCeramicCERQUAD
ElectricalCharacteristics Thefollowingratingsdefinetheconditionsunderwhichthedeviceoperateswithout
damage.Sectionsofthedevicemaynotoperatenormallywhilebeingexposedtothe
electricalextremesandcontainscircuitrytoprotectagainstdamagefromhighstatic
voltagesorelectricalfields.Itisadvised,however,thatnormalprecautionsbetakento
avoidapplicationofanyvoltageshigherthanmaximum-ratedvoltagestothishigh-
impedancecircuit.Reliabilityofoperationisenhancedifunusedinputsaretiedtoan
appropriatelogicvoltage(i.e.,eitherVSSorVDD).
9
TS68332
2118A–HIREL–03/02
PowerConsiderations Theaveragechip-junctiontemperature,TJ,in°Ccanbeobtainedfrom:
TJ=TA+(PD⋅θJA) (1)
TA=AmbientTemperature,°C
θJA=PackageThermalResistance,Junction-to-Ambient,°C/W
PD=PINT+PI/O
PINT=ICC⋅VCC,Watts-ChipInternalPower
PI/O=PowerDissipationonInputandOutputPins-UserDetermined
FormostapplicationsPI/O<PINTandcanbeneglected.
AnapproximaterelationshipbetweenPDandTJ(ifPI/Oisneglected)is:
PD=K÷(TJ+273) (2)
Solvingequations(1)and(2)forKgives:
K=PD ⋅ (TA+273)+θJA⋅PD2(3)
whereKisaconstantpertainingtotheparticularpartKcanbedeterminedfromequa-
tion(3)bymeasuringPD(atequilibrium)foraknownTA.UsingthisvalueofK,the
valuesofPDandTJcanbeobtainedbysolvingequations(1)and(2)iterativelyforany
valueofTA.
Table2.AbsoluteMaximumRatings
Symbol Parameter TestConditions Min Max Unit
VDD SupplyVoltage -0.3 +7.0 V
VIInputVoltage -0.3 +7.0 V
PDMAX MaxPowerDissipation LowPowerOperation 600 mW
StandByMode 500 mW
Tcase OperatingTemperature MSuffix -55 +125 °C
VSuffix -40 +85 °C
Tstg StorageTemperature -55 +150 °C
Tleads LeadTemperature Max5Sec.Soldering +270 °C
Table3.ThermalCharacteristics(at25°C)
Package Symbol Parameter Value Unit
PGA132 θJ-A ThermalResistanceCeramicJunction-to-ambient TBD °C/W
θJ-C ThermalResistanceCeramicJunction-to-case 10 °C/W
CERQUAD132 θJ-A ThermalResistanceCeramicJunction-to-ambient TBD °C/W
θJ-C ThermalResistanceCeramicJunction-to-case 10 °C/W
10 TS68332 2118A–HIREL–03/02
Thetotalthermalresistanceofapackage(θJA)canbeseparatedintotwocomponents,
θJCandθCA,representingthebarriertoheatflowfromthesemiconductorjunctiontothe
package(case),surface(θJC)andfromthecasetotheoutsideambient(θCA).These
termsarerelatedbytheequation:
θJA=θJC+θCA (4)
θJCisdevicerelatedandcannotbeinfluencedbytheuser.However,θCAisuserdepen-
dentandcanbeminimizedbysuchthermalmanagementtechniquesasheatsinks,
ambientaircoolingandthermalconvection.Thus,goodthermalmanagementonthe
partoftheusercansignificantlyreduceθCAsothat θJAapproximatelyequals θJC.Substi-
tutionof θJCforθJAinequation(1)willresultinalowersemiconductorjunction
temperature.
Mechanicaland
Environment ThemicrocircuitsshallmeetallmechanicalenvironmentalrequirementsofeitherMIL-
STD-883forclassBdevicesorscreenedaccordingtoAtmel-Grenoblestandards
devices.
Marking Thedocumentwherearedefinedthemarkingareidentifiedintherelatedreferencedoc-
uments.Eachmicrocircuitarelegibleandpermanentlymarkedwiththefollowing
informationasminimum:
• Atmellogo
• Manufacturer’spartnumber
• ClassBidentification
• Date-codeofinspectionlot
• ESDidentifierifavailable
• Countryofmanufacturing
QualityConformanceInspection
DESC/MIL-STD-883 IsinaccordancewithMIL-M-38535andmethod5005ofMIL-STD-883.GroupAandB
inspectionsareperformedoneachproductionlot.GroupCandDinspectionareper-
formedonaperiodicalbasis.
Electrical
Characteristics
GeneralRequirements Allstaticanddynamicelectricalcharacteristicsspecifiedandtherelevantmeasurement
conditionsaregivenbelow.Forinspectionpurpose,refertorelevantspecification:
•DSCC
(lastissueonrequesttoourmarketingservices)
Table4:Staticelectricalcharacteristicsforallelectricalvariants.
Table6:Dynamicelectricalcharacteristicsfor6832-16(16.78MHz).
Forstaticcharacteristics,testmethodsrefertoIEC748-2methodnumber,where
existing.
Fordynamiccharacteristics,testmethodsrefertoclause5.4hereafterofthis
specification.
11
TS68332
2118A–HIREL–03/02
StaticCharacteristics
Table4.DCCharacteristics.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;VSS=0VDC;
TC=-55°Cto+125°Cor-40°Cto+85°C
Number Symbol Parameter
16.78MHz 20.97MHz
UnitMin Max Min Max
1V
IH InputHighVoltage 0.7(VDD)V
DD+0.3 0.7(VDD)V
DD+0.3 V
2V
IL InputLowVoltage VSS-0.3 0.2(VDD)V
SS-0.3 0.2(VDD)V
3V
HYS InputHysteresis(1) 0.5 - 0.5 - V
4I
IN InputLeakageCurrent(2)
VIN=VDDorVSS Input-onlypins -2.5 2.5 -2.5 2.5 µA
5I
OZ HighImpedance(off-state)
LeakageCurrent(2)
VIN=VDDorVSSL Allinput/output
andoutputpins -2.5 2.5 -2.5 2.5 µA
6V
OH CMOSOutputHighVoltage(2)(3)
IOH=-10.0µA Group1,2,4
input/outputand
alloutputpinsand
alloutputpins
VDD-0.2 - VDD-0.2 - V
7V
OL CMOSOutputHighVoltage(2)
IOH=-10.0µA Group1,2,4
input/outputand
alloutputpins
-0.2-0.2V
8V
OH OutputHighVoltage(2)(3)
IOH=-0.8mA Group1,2,4
input/outputand
alloutputpins
VDD-0.8 - VDD-0.8 - V
9V
OL OutputLowVoltage(2)
IOL=1.6mA
IOL=5.3mA
IOL=12mA
Group1I/Opins
CLKOUT,
FREEZE/QUOT,
IPIPE
Group2,4I/O
pins,CSBOOT,
BG/CS
Group3
-
-
-
0.4
0.4
0.4
-
-
-
0.4
0.4
0.4
V
V
V
10 VIHTSC ThreeStateControlInputHighVoltage 1.6(VDD)9.11.6(V
DD)9.1 V
11 IMSP DataBusModeSelectPull-up
Current(5)
VIN=VIL
VIN=VIH
DATA[15:0]
DATA[15:0] -
-15 -120
--
-15 -120
-µA
µA
12 IDD
IDD
SIDD
SIDD
VDDsupplycurrent(5)
RUN(6)
RUN,TPUemulationmode
LPSTOP,32.768kHzcrystal,VCOoff(STSIM=0)
LPSTOP(externalclockinputfrequency=maximum
fsys)
-
-
-
-
124
134
350
5
-
-
-
-
140
150
350
5
mA
mA
µA
mA
12 TS68332 2118A–HIREL–03/02
Notes: 1. Appliesto:
PortE[7:4]-SIZ[1:0],AS,DS.
PortF[7:0]-IRQ[7:1],MODCLK.
PortQS[7:0]-TXD,PCS[3:1],PCS0/SS,SCK,MOSI,MISO.
TRUCH[15:0],T2CLK.
BKPT/DSCLK,IFETCH,RESET,RXD,TSSTME/TSC.
EXTAL(whenPLLenabled).
2. Input-onlypins:EXTAL,TSTME/TSC,BKPTT2CLK,RXD.
Output-onlypins:CSBOOT,BG/CS,CLKOUT,FREEZE/QUOT,IPIPE.
Input/outputpins:
Group1:DATA[15:0],IFETCH,TPUCH[15:01].
Group2:PortC[6:0]-ADDR[22:19]/CS[9:6],FC[2:0]/CS[5:3].
PortE:[7:0]-SIZ[1:0],AS,DS,AVEC,RMC,DSACK[1:0]
PortF[&:0]-IRQ[7:1],MODCLK.
PortQS[7:3]-TXD,PCS[3:1],PCS0/SS.
ADDR23/CS10/ECLK,ADDR[18:0],R/W,BERR,BR/CSO,BGACK/CS2.
Group3:HALT,RESET.
Group4:MISO,MOSI,SCK.
3. DoesnotapplytoHALTandRESETbecausetheyareopendrainpins.DoesnotapplytoPortQS[7:0],(TXD,PCS[3:1],
PCS0/SS,SCK,MOSI,MISO)inwired-ORmode.
4. Useofanactivepull-downdeviceisrecommended.
5. TotaloperatingcurrentisthesumoftheappropriateIDD,IDDSYN,andISBvalues.IDDvalues.IDDvaluesincludesupplycur-
rentsfordevicemodulespoweredbyVDDEandVDDIpins
6. Currentmeasuredwithsystemclockfrequencyof16.78MHz,allmodulesactive.
13 VDDSYN Clocksynthesizeroperatingvoltage 4.5 5.5 4.75 5.25 V
14 IDDSYN
IDDSYN
SIDDSYN
IDDSYN
VDDSYNsupplycurrent(5)
32.768kHzcrystal,VCOon,maximumfsys
Externalclock,maximumfsys
LPSTOP,32.768kHzcrystal,VCOoff(STSIM=0)
32.768kHzcrystal,VDDpowereddown
-
-
-
-
1
5
150
100
-
-
-
-
2
6
150
100
mA
mA
µA
µA
15 VSB RAMstandbyvoltage(7)
SpecifiedVDDapplied
VDD=VSS
0.0
3.0 5.5
5.5 0.0
3.0 5.25
5.25 V
V
16 ISB RAMstandbycurrent(5)(7)(8)
NormalRAMoperation
Transientcondition
Standbyoperation
VDD>VSB-0.5V
VSB-0.5≥VDD≥
VSS+0.5V
VDD<VSS+0.5V
-
-
-
10
3
60
-
-
-
10
3
50
µA
mA
µA
17 PDPowerdissipation(9) - 690 - 766 mW
18 Cin Inputcapacitance(2)(10)
Allinput-onlypins
Allinput/outputpins -
-10
20 -
-10
20 pF
pF
19 CLLoadcapacitance(2)
Group1I/OpinsCLKOUT,FREEZE/QUOT,IPIPE
Group2I/OpinsandCSBOOT,BG/CS
Group3I/Opins
Group4I/Opins
-
-
-
-
90
100
130
200
-
-
-
-
90
100
130
200
pF
pF
pF
pF
Table4.DCCharacteristics.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;VSS=0VDC;
TC=-55°Cto+125°Cor-40°Cto+85°C(Continued)
Number Symbol Parameter
16.78MHz 20.97MHz
UnitMin Max Min Max
13
TS68332
2118A–HIREL–03/02
7. TheRAMmodulewillnotswitchintostandbymodeaslongasVSBdoesnotexceedVDDbymorethan0.5-volt.
TheRAMarraycannotbeaccessedwhilethemoduleisinstandbymode.
8. WhenVDDistransitioningduringpower-uporpower-downsequence,andVSBisapplied,currentflowsbetweentheVSTBY
andVDDpins,whichcausesstandbycurrenttoincreasetowardthemaximumtransientconditionspecification.Systemnoise
ontheVDDandVSTBYpinscancontributetothiscondition.
9. Powerdissipationmeasuredatspecifiedsystemclockfrequency,allmodulesactive.Powerdissipationcanbecalculated
usingtheexpression:
PD=MaximumVDD(IDD+IDDSYN+ISB)
IDDincludessupplycurrentsforalldevicemodulespoweredbyVDDEandVDDIpins.
10.Thisparameterisperiodicallysampledratherthan100%tested.
Dynamic(Switching)
Characteristics TheINTERVALnumbersrefertothetimingdiagram.
Sp
Notes: 1. Allinternalregistersretaindataat0Hz.
2. Thisparameterisperiodicallysampledratherthan100%tested.
3. Assumesthatalow-leakageexternalfilternetworkisusedtoconditionclocksynthesizerinputvoltage.Totalexternalresis-
tancefromXFCpinduetoexternalleakagemustbegreaterthan15MΩtoguaranteethisspecification.Filternetwork
geometrycanvarydependinguponoperatingenvironment.
4. Properlayoutproceduresmustbefollowedtoachievespecifications.
5. AssumesthatstableVDDSYNisapplied,andthatthecrystaloscillatorisstable.LocktimeismeasuredfromthetimeVDDand
VDDSYNarevaliduntilRESETisreleased.ThisspecificationalsoappliestotheperiodrequiredforPLLlockafterchanging
theWandYfrequencycontrolbitsinthesynthesizercontrolregister(SYNCR)whilethePLLisrunning,andtotheperiod
requiredfortheclocktolockafterLPSTOP.
6. InternalVCOfrequency(fVCO)isdeterminedbySYNCRWandYbitvalues.TheSYNCRXbitcontrolsadivide-by-twocir-
cuitthatisnotinthesynthesizerfeedbackloop.WhenX=0,thedividerisenabled,andfsys=fVCO:4.WhenX=1,the
dividerisdisabled,andfsys=fVCO:2.Xmustequalonewhenoperatingatmaximumspecifiedfsys.
7. Stabilityistheaveragedeviationfromtheprogrammedfrequencymeasuredoverthespecifiedintervalatmaximumfsys.
Measurementsaremadewiththedevicepoweredbyfilteredsuppliesandclockedbyastableexternalclocksignal.Noise
injectedintothePLLcircuitryviaVDDSYNandVSSandvariationincrystaloscillatorfrequencyincreasetheCstabpercentage
foragiveninterval.Whenclockstabilityisacriticalconstraintoncontrolsystemoperation,thisparametershouldbemea-
suredduringfunctionaltestingofthefinalsystem.
Table5.ClockControlTiming.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;
VSS=0VDC;TC=-55°Cto+125°Cor-40°Cto+85°C
Number Symbol Parameter
16.78 20.97
UnitMin Max Min Max
1f
ref PLLreferencefrequencyrange 25 50 25 50 kHz
2f
sys Systemfrequency(1)
On-chipPLLsystemfrequency
Externalclockoperation
dc
0.131
dc
16.78
16.78
16.78
dc
0.131
dc
20.97
20.97
20.97
MHz
MHz
MHz
3f
lpll PLLlocktime(2)(3)(4)(5) -20- 20ms
4f
vco VCOfrequency(6) -2(f
sysmax) - 2(fsysmax) MHz
5f
LIMP Limpmodeclockfrequency
SYNCRXbit=0
SYNCRXbit=1 -
-fsysmax/2
fsysmax -
-fsysmax/2
fsysmax MHz
MHz
6C
stab CLKOUTstability(2)(3)(4)(7)
Shortterm(5µsinterval)
Longterm(500µsinterval) -05
-0.05 05
0.05 -05
-0.05 05
0.05 %
%
14 TS68332 2118A–HIREL–03/02
.
Table6.ACTiming.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;VSS=0VDC;
TC=-55°Cto+125°Cor-40°Cto+85°C (1)
Number Symbol Parameter
16.78MHz 20.97MHz
UnitMin Max Min Max
F1 f Frequencyofoperation(32.768kHzcrystal)(2) 0.13 16.78 0.13 20.97 MHz
1t
CYC Clockperiod 59.6 - 47.7 - ns
1A tEcyc ECLKperiod 476 - 381 - ns
1B tXcyc Externalclockinputperiod(3) 59.6 - 47.7 - ns
2,3 tCW Clockpulsewidth 24 - 18.8 - ns
2A,3A tECW ECLKpulsewidth 236 - 183 - ns
2B,3B tXCHL Externalclockinputhigh/lowtime(3) 29.8 - 23.8 - ns
4,5 tCrf Clockriseandfalltime - 5 - 5 ns
4A,5A trt Riseandfalltime-AlloutputsexceptCLKOUT - 8 - 8 ns
4B,5B TXCrf Externalclockriseandfalltime(4) -5-5ns
6t
CHAV Clockhightoaddress,FC,SIZE,RMCvalid 0 29 0 23 ns
7t
CHAZx Clockhightoaddress,Data,FC,SIZE,RMChigh
impedance 0 59 0 47 ns
8t
CHAZn Clockhightoaddress,FC,SIZE,RMCinvalid 0 - 0 - ns
9t
CLSA ClocklowtoAS,DS,CS,asserted 2 25 0 23 ns
9A tSTSA AStoDSorCS,asserted(read)(5) -15 15 -10 10 ns
9C tCLIA ClocklowtoIFETCH,IPIPEasserted 2 22 2 22 ns
11 tAVSA Address,FC,SIZE,RMCvalidtoAS,CS(andDS
read)asserted 15 - 10 - ns
12 tCLSN ClocklowtoAS,DS,CSnegated 2 29 2 23 ns
12A tCLIN ClocklowtoIFETCH,IPIPEnegated 2 22 2 22 ns
13 tSNAI AS,DS,CSnegatedtoaddress,FC,SIZEinvalid
(addresshold) 15 - 10 - ns
14 tSWA AS,CS(andDSread)widthasserted 100 - 80 - ns
14A tSWAW DS,CS,widthasserted(write) 45 - 36 - ns
14B tSWDW AS,CS(andDSread)widthasserted(fastwrite
cycle) 40 - 32 - ns
15 tSN AS,DS,CSwidthnegated(6) 40 - 32 - ns
16 tCHSZ ClockhightoAS,DS,R/Whighimpedance - 59 - 47 ns
17 tSNRN AS,DS,CSnegatedtoR/Wnegated 15 - 10 - ns
18 tCHRH ClockhightoR/Whigh 0 29 0 23 ns
20 tCHRL ClockhightoR/Wlow 0 29 0 23 ns
21 tRAAA R/WassertedtoAS,CSasserted 15 - 10 - ns
22 tRASA R/WlowtoDS,CSasserted(write) 70 - 54 - ns
23 tCHDO Clockhightodataoutvalid - 29 - 23 ns
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24 tDVASN DataoutvalidtonegatingedgeofAS,CS(fast
writecycle) 15 - 10 - ns
25 tSNDOI DS,CSnegatedtodataoutinvalid(dataouthold) 15 - 10 - ns
26 tDVSA DataoutvalidtoDS,CSasserted(write) 15 - 10 - ns
27 tDICL Datainvalidtoclocklow(datasetup) 5 - 5 - ns
27A tBELCL LateBERR,HALT
assertedtoclocklow(setuptime) 20 - 15 - ns
28 tSNDN AS,DSnegatedtoDSACK[1:0],BERR,HALT,
AVECnegated 0 80 0 60 ns
29 tSNDI DS,CSnegatedtodataininvalid(datainhold)(7) 0-0 ns
29A tSHDI DS,CSnegatedtodateinhighimpedance(7)(8) - 55 - 48 ns
30 tCLDI CLKOUTlowtodataininvalid(fastcyclehold)(7) 15 - 10 - ns
30A tCLDH CLKOUTlowtodatainhighimpedance(7) - 90 - 72 ns
31 tDADI DSACK[1:0]assertedtodatainvalid(9) - 50 - 46 ns
33 tCLBAN ClocklowtoBGasserted/negated - 29 - 23 ns
35 tBRAGA BRassertedtoBGasserted(RMCnotasserted)(10) 1-1-t
CYC
37 tGAGN BGACKassertedtoBGnegated 1212t
CYC
39 tGH BGwidthnegated 2 - 2 - tCYC
39A tGA BGwidthasserted 1 - 1 - tCYC
46 tRWA R/Wwidthasserted(writeorread) 150 - 115 - ns
46A tRWAS R/Wwidthasserted(fastwriteorreadcycle) 90 - 70 - ns
47A tAIST AsynchronousinputsetuptimeBR,BGACK,
DSACK[1:0],BERR,AVEC,HALT 5-5-ns
47B tAIHT Asynchronousinputholdtime 15 - 12 - ns
48 tDABA DSACK[1:0],assertedtoBERR,HALTasserted(11) - 30 - 30 ns
53 tDOCH Dataoutholdfromclockhigh 0 - 0 - ns
54 tCHDH Clockhightodataouthighimpedance - 28 - 23 ns
55 tRADC R/Wassertedtodatabusimpedancechange 40 - 32 - ns
56 tHRPW RESETpulsewidth(resetinstruction) 512 - 512 - tCYC
57 tBNHN BERRnegatedtoHALTnegated(rerun) 0 - 0 - ns
70 tSCLDD Clocklowtodatabusdriven(show) 0 29 0 23 ns
71 tSCLDS Datasetuptimetoclocklow(show) 15 - 10 - ns
72 tSCLDH Dataholdfromclocklow(show) 10 - 10 - ns
73 tBKST BKPTinputsetuptime 15 - 10 - ns
74 tBKHT BKPTinputholdtime 10 - 10 - ns
75 tMSS Modeselectsetuptime 20 - 20 - tCYC
Table6.ACTiming.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;VSS=0VDC;
TC=-55°Cto+125°Cor-40°Cto+85°C(Continued)(1)
Number Symbol Parameter
16.78MHz 20.97MHz
UnitMin Max Min Max
16 TS68332 2118A–HIREL–03/02
Notes: 1. AllACtimingisshownwithrespectto20%VDDand70%VDDlevelsunlessotherwisenoted.
2. Minimumsystemclockfrequencyisfourtimesthecrystalfrequency,subjecttospecifiedlimits.
3. Whenanexternalclockisused,minimumhighandlowtimesarebasedona50%dutycycle.TheminimumallowabletXcyc
periodisreducedwhenthedutycycleoftheexternalclocksignalvaries.Therelationshipbetweenexternalclockinputduty
cycleandminimumtXcycisexpressed:
MinimumtXcycperiod=minimumtXCHL/(50%-externalinputdutycycletolerance)
4. ParametersforanexternalclocksignalappliedwhiletheinternalPLLisdisabled(MODCLKpinheldlowduringreset).Does
notpertaintoanexternalVCOreferenceappliedwhilethePLLisenabled(MODCLKpinheldhighduringreset).Whenthe
PLLisenabled,theclocksynthesizerdetectssuccessivetransitionsofthereferencesignal.Iftransitionsoccurwithinthe
correctclockperiod,rise/falltimesanddutycycleareatcritical.
5. Specification9Aistheworst-caseskewbetweenASandDSorCS.Theamountofskewdependsontherelativeloadingof
thesesignals.Whenloadsarekeptwithinspecifiedlimits,skewwillnotcauseASandDStofalloutsidethelimitsshownin
specification9.
6. Ifmultiplechipselectsareused,CSwidthnegated(specification15)appliestothetimefromthenegationofaheavily
loadedchipselecttotheassertionofalightlyloadedchipselect.TheCSwidthnegatedspecificationbetweenmultiplechip
selectsdoesnotapplytochipselectsbeingusedforsynchronousECLKcycles.
7. HoldtimesarespecifiedwithrespecttoDSorCSonasynchronousreadsandwithrespecttoCLKOUTonfastcyclereads.
Theuserisfreetouseeitherholdtime.
8. Maximumvalueisequalto(tcyc/2)+25ns.
9. Iftheasynchronoussetuptime(specification47A)requirementsaresatisfied,theDSACK[1:0]lowtodatasetuptime(spec-
ification31)andDSACK[1:0]lowtoBERRlowsetuptime(specification48)canbeignored.Thedatamustonlysatisfythe
data-intoclocklowsetuptime(specification27)forthefollowingclockcycle.BERRmustsatisfyonlythelateBERRlowto
clocklowsetuptime(specification27A)forthefollowingclockcycle.
10.Toensurecoherencyduringeveryoperandtransfer,BGwillnotbeassertedinresponsetoBRuntilafterallcyclesofthe
currentoperandtransferarecompleteandRMCisnegated.
11.IntheabsenceofDSACK[1:0],BERRisanasynchronousinputusingtheasynchronoussetuptime(specification47A).
12.AfterexternalRESETnegationisdetected,ashorttransitionperiod(approximately2tcyc)elapses,thentheSIMdrives
RESETlowfor512tcyc.
13.ExternalassertionoftheRESETinputcanoverlapinternally-generatedresets.Toinsurethatanexternalresetisrecog-
nizedinallcases,RESETmustbeassertedforatleast590CLKOUTcycles.
14.ExternallogicmustpullRESEThighduringthisperiodinorderfornormalMCUoperationtobegin.
15.Addressaccesstime=(2.5+WS)tcyc-tCHAV-tDICL.Chipselectaccesstime=(2+WS)tcyc-tCLSA-tDICL.
Where:WS=numberofwaitstates.Whenfastterminationisused(2clockbus)WS=-1.
76 tMSH Modeselectholdtime 0 - 0 - ns
77 tRSTA RESETassertiontime(12) 4-4-t
CYC
78 tRSTR RESETrisetime(13)(14) -10-10t
CYC
Table6.ACTiming.VDDandVDDSYN=5.0VDC±10%for16.78MHzand5.0VDC±5%for20.97MHz;VSS=0VDC;
TC=-55°Cto+125°Cor-40°Cto+85°C(Continued)(1)
Number Symbol Parameter
16.78MHz 20.97MHz
UnitMin Max Min Max
17
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TestConditionsSpecific
totheDevice
TimeDefinitions ThetimesspecifiedinTable6asdynamiccharacteristicsaredefinedinFigure4toFig-
ure15below,byareferencenumbergiventhecolumn“NUM”ofthetablestogetherwith
therelevantfigurenumber.
Figure4.ClkoutOutputTimingDiagram
Note: Timingshownwithrespectto20%and70%VDD.
Figure5.ExternalInputTimingDiagram
Note: Timingshownwithrespectto20%and70%VDD.Pulsewidthshownwithrespectto50%
VDD.
Figure6.ECLKOutputTimingDiagram
Note: TimingShownWithRespectTo20%And7%VDD.
18 TS68332 2118A–HIREL–03/02
Figure7.ReadCycleTimingDiagram
19
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Figure8.WriteCycleTimingDiagram
20 TS68332 2118A–HIREL–03/02
Figure9.FastTerminationReadCycleTimingDiagram
21
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Figure10.FastTerminationWriteCycleTimingDiagram
22 TS68332 2118A–HIREL–03/02
Figure11.BusArbitrationTimingDiagram–ActiveBusCase
23
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Figure12.BusArbitrationTimingDiagram–IdleBusCase
Figure13.ShowCycleTimingDiagram
Note: ShowcyclescanstretchduringS42whenbusaccessestakelongerthantwocyclesduetoIMBmodulewait-stateinsertion.
24 TS68332 2118A–HIREL–03/02
Figure14.ChipSelectTimingDiagram
Note: ASandDStimingshownforreferenceonly.
Figure15.ResetandModeSelectTimingDiagram
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Functional
Description
ModuleMemoryMap TheRAMarrayispositionedbythebaseaddressregisterintheRAMCTRLblock.
ResetforcestheRAMarraytobedisabled.Unimplementedblocksaremapped
externally.
Figure16.ModuleMemoryMap
Note: Y-M111,whereMisthemodmapsignalstateontheIMBwhichreflectsthestateofthe
modmapbitinthemoduleconfigurationregisterofthesystemintegrationmodule(Y=$7
or$F).
CPU32Overview TheCPU32,theinstructionprocessingmoduleofthe68300family,isbasedonthe
industry-standardTS68000coreprocessorwithmanyfeaturesofthe68010and
TS68020aswellasuniquefeaturessuitedforhigh-performancecontrollerapplications.
TheCPU32isdesignedtoprovideasignificantincreaseinperformanceoverexisting
microcontrollerCPUstomeetthedemandforhigherperformancerequirementsforthe
1990s,whilemaintainingsourcecodeandbinarycodecompatibilitywiththe68000
family.
Easeofprogrammingisanimportantconsiderationinusingamicrocontroller.An
instructionformatimplementingaregister-memoryinteractionphilosophypredominates
inthedesign,andalldataresourcesareavailabletoalloperationsrequiringthose
resources.
AllcapabilitiesandfunctionsofthismodulearedetailedfullyintheCPU32reference
manual.
26 TS68332 2118A–HIREL–03/02
BlockDiagram Themajorclocksdepictedoperateinahighlyindependentfashionthatmaximizescon-
currencyofoperationwhilemanagingtheessentialsynchronizationofinstruction
executionandbusoperation.Thebuscontrollerloadsinstructionsfromthedatabusinto
thedecodeunit.
Thesequencerandcontrolunitprovideoverallchipcontrol,managingtheinternal
buses,registers,andfunctionsoftheexecutionunit.
ArchitectureSummary TheCPU32architectureincludesseveralimportantfeaturesthatprovidebothpower
andversatilitytotheuser.TheCPU32issourceandobjectcodecompatiblewiththe
TS68000and68010.Alluser-stateprogramscanbeexecutedunchanged.Themajor
CPU32featuresareasfollows:
• 32-bitinternaldatapathandarithmetichardware
• 32-bitinternaladdressbus,24-bitexternaladdressbus
• eight32-bitgeneral-purposedataregisters
• seven32-bitgeneral-purposeaddressregisters
• separateuserandsupervisorstackpointersandaddressspaces
• separateprogramanddataaddressspaces
• fullinterruptprocessing
• fullyupwardobjectcodecompatiblewith68000family
• virtualmemoryimplementation,loopmodeofinstructionexecution,
• fastmultiply,divide,andshiftinstructions
• fastbusinterfacewithdynamicbusportsizing
• improvedexecutionhandlingforcontrollerapplications
• enhancedaddressingmodes:
-scaledindex
-addressregisterindirectwithbasedisplacementandindex
-expandedPCrelativemodes32-bitbranchdisplacementsbreakpointinstruction.
• instructionsetenhancements:
-highprecisionmultiplyanddivide
-traponconditioncodes
-upperandlowerboundschecking
-enhancedbreakpointinstruction
• traceonchangeofflow
• tablelookupandinterpolateinstruction
• lowpowerstopinstruction
• hardwarebreakpointsignal,backgroundmode
• 16.78MHzand20.97MHzoperatingfrequencyat-55°Cto+125°C
• fullystaticimplementation
27
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Figure17.CPU32BlockDiagram
Programmer’sModel TheprogrammingmodeloftheCPU32consistsoftwogroupsofregisters:usermodel
andsupervisormodel,whichcorrespondtotheuserandsupervisorprivilegelevels.
Executingattheuserprivilegelevel,userprogramscanonlyusetheregistersofthe
usermodel.Executingatthesupervisorlevel,systemsoftwareusesthecontrolregis-
tersofthesupervisorleveltoperformsupervisorfunctions.
Thesupervisorlevelhashigherprivilegesthantheuserlevel.Notallinstructionsare
permittedtoexecuteinthelowerprivilegeduserlevel,butallinstructionsareavailable
atthesupervisorlevel.Thisschemeallowsaseparationofsupervisoranduserlevels,
andsothesupervisorcanprotectsystemresourcesfromuncontrolledaccess.Thepro-
cessorusestheprivilegelevelindicatedbytheSbitinthestatusregistertoselecteither
theuserorsupervisorprivilegelevelandeithertheUSPorSSPforstackoperations.
Theuserprogrammingmodelremainsunchangedfromprevious68000familymicropro-
cessors.Thesupervisorprogrammingmodel,whichsupplementstheuserprogramming
modelisusedexclusivelybytheCPU32systemprogrammerswhoutilizethesupervisor
privilegeleveltoimplementsensitiveoperatingsystemfunctions.Thesupervisorpro-
grammingmodelcontainsallthecontrolstoaccessandenablethespecialfeaturesof
theCPU32.Allapplicationsoftware,writtentorunatthenonprivilegeduserlevel,
migratestotheCPU32fromany68000platformwithoutmodification.Theprogramming
modelsareshowninFigure18andFigure19.
Registers RegistersD7-D0areusedasdataregistersandreadilysupport8-bit(byte),16-bit
(word)and32-bit(longword)operandlengthsforalloperations.RegistersA6-A0and
theuserandsupervisorstackpointersareaddressregistersthatmaybeusedassoft-
warestackpointersofbaseaddressregisters.RegisterA7isaregisterthatappliesto
theuserstackpointerintheuserprivilegelevelandtothesupervisorstackpointerinthe
userprivilegelevel.Inaddition,theaddressregistersmaybeusedforwordandlong-
wordoperations.Allofthe16general-purposeregisters(D7-D0,A7-A0)maybeused
asindexregisters.
ThePCcontainstheaddressofthenextinstructiontobeexecutedbytheCPU32.
28 TS68332 2118A–HIREL–03/02
Thestatusregister(SR)storestheprocessorstatus.Itcontainstheconditioncodesthat
reflecttheresultsofapreviousoperationandcanbeusedforconditionalinstruction
executioninaprogram.
Thevectorbaseregister(VBR)containsthebaseaddressoftheexceptionvectortable
inmemory.Thedisplacementofanexceptionvectorisaddedtothevalueinthisregis-
tertoaccessthevectortable.
Alternatefunctioncoderegisters(SFCandDFC)contain3-bitfunctioncodes.Function
codescanbeconsideredextensionsofthe24-bitlinearaddressthatoptionallyprovide
asmanyaseight16-Mbyteaddressspaces.Theseaddressspacesaredesignatedas
eitheruserorsupervisorspaceandaseitherprogramordataspace.ThereisaCPU
spacetoallowtheCPUtoacquirespecificcontrolinformationnotusuallyassociated
withreadorwritebuscycles.ThefunctioncodesignalsFC2-FC0selecttheappropriate
addressspace.
Figure18.UserProgrammingModel
29
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Figure19.SupervisorProgrammingModelSupplement
DataTypes Sixbasicdatatypesaresupported:
•bits
• packagedbinary-codeddecimaldigits
• byteintegers(8bits)
• wordintegers(16bits)
• long-wordintegers(32bits)
• quad-wordintegers(64bits)
OrganizationInRegisters Theeightdataregisterscanstoredataoperandsof1,8,16,32and64bitsand
addressesof16or32bits.Thesevenaddressregistersandthetwostackpointersare
usedforaddressoperandsof16or32bits.ThePCis32bitswide.
SystemFeatures TheCPU32includesanumberoffeaturestoaidsystemimplementation.Theseinclude
aprivilegemechanism,separationofaddressspaces,multilevelpriorityinterrupts,trap
instructions,andatracefacility.
Theprivilegemechanismprovidesuserandsupervisorprivilegestates,privileged
instructions,andexternaldistinctionofuserandsupervisorstatereferences.Thepro-
cessorseparatesreferencesbetweenprogramanddataspace.Thispermitssharingof
codesegmentsthataccessseparatedatasegments.
TheCPU32supportssevenprioritylevelsfor199memoryvectoredinterrupts.Foreach
interrupt,thevectorlocationcanbeprovidedexternallyorgeneratedinternally.Thesev-
enthlevelprovidesanon-maskableinterruptcapability.
Tosimplifysystemdevelopment,instructionsareprovidedtocheckinternalprocessor
conditionsandallowsoftwaretraps.Thetracefacilityallowsinstruction-by-instruction
tracingofprogramexecutionwithoutalterationoftheprogramorspecialhardware.
VirtualMemory ThefulladdressingrangeoftheCPU32ontheTS68332is16-Mbyteineachofeight
addressspaces.Eventhoughmostsystemsimplementasmallerphysicalmemory,the
systemcanbemadetoappeartohaveafull16-Mbyteofmemoryavailabletoeachuser
programbyusingvirtualmemorytechniques.
30 TS68332 2118A–HIREL–03/02
LoopModeInstruction
Execution TheCPU32hasseveralfeaturesthatprovideefficientexecutionofprogramloops.One
ofthesefeaturesistheDBccloopingprimitiveinstruction.Toincreasetheperformance
oftheCPU32,aloopmodehasbeenaddedtotheprocessor.Theloopmodeisusedby
asinglewordinstructionthatdoesnotchangeprogramflow.Loopmodeisimplemented
inconjunctionwiththeDBccinstruction.Onceinloopmode,theprocessorperforms
onlythedatacyclesassociatedwiththeinstructionandsuppressesallinstruction
fetches.
VectorBaseRegister TheVBRcontainsthebaseaddressofthe1024-byteexceptionvectortable,consisting
of256exceptionvectors.Exceptionvectorscontainmemoryaddressesofroutinesthat
beginexecutionatthecompletionofexceptionprocessing,i.e.aninterruptroutine.
ProcessingStates Theprocessorisalwaysinoneoffourprocessingstates:normal,exception,haltedor
background.Thenormalprocessingstateisthatassociatedwithinstructionexecution;
thebusisusedtofetchinstructionsandoperandsandtostoreresults.Theexception
processingstateisassociatedwithinterrupts,trapinstructions,tracing,andother
exceptionconditions.Theexceptionmaybeinternallygeneratedexplicitlybyaninstruc-
tionorbyanunusualconditionarisingduringtheexecutionofaninstruction.Externally,
exceptionprocessingcanbeforcedbyaninterrupt,abuserror,orareset.Thehalted
processingstateisanindicationofcatastrophichardwarefailure.Forexample,ifduring
theexceptionprocessingofabuserroranotherbuserroroccurs,theprocessor
assumesthatthesystemisunusableandhalts.Thebackgroundprocessingstateisini-
tiatedbybreakpoints,executionofspecialinstructions,oradoublebusfault.
Backgroundprocessingallowsinteractivedebuggingofthesystemviaasimpleserial
interface.
AddressingModes AddressingintheCPU32isregister-oriented.Mostinstructionsallowtheresultsofthe
specifiedoperationtobeplacedeitherinaregisterordirectlyinmemory;thisflexibility
eliminatestheneedforextrainstructionstostoreregistercontentsinmemory.
Thesevenbasicaddressingmodesareasfollows:
• registerdirect
• registerindirect
• registerindirectwithindex
• programcounterindirectwithdisplacement
• programcounterindirectwithindex
• absolute
• immediate
Includedintheregisterindirectaddressingmodesarethecapabilitiestopost-increment,
pre-decrement,andoffset.Theprogramcounterrelativemodealsohasindexandoffset
capabilities.Inadditiontotheseaddressingmodes,manyinstructionsimplicitlyspecify
theuseofthestatusregister,stackpointer,and/orprogramcounter.
31
TS68332
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Instructions
68000FamilyCompatibility Itisthephilosophyofthe68000familythatalluser-codeprogramscanexecute
unchangedonamoreadvancedprocessor,andsupervisor-modeprogramsandexcep-
tionhandlersshouldrequireonlyminimalalteration.
TheCPU32canbethoughtofasanintermediatememberofthe68000family.Object
codefromanTS68000or68010maybeexecutedontheCPU32,andmanyofthe
instructionandaddressingmodeextensionsoftheTS68020arealsosupported.Refer
totheCPU32referencemanualforadetailedcomparisonoftheCPU32andTS68020
instructionset(seealsoTable7).
NewInstructions TwonewinstructionshavebeenaddedtotheTS68000instructionsetforuseincontrol-
lerapplications.Theyarelowpowerstop(LPSTOP)andtablelookupandinterpolate
(TBL).
LowPowerStop(LPSTOP):Inapplicationswherepowerconsumptionisaconsider-
ation,theCPU32forcesthedeviceintoalow-powerstandbymodewhenimmediate
processingisnotrequired.Thelow-powerstopmodeisenteredbyexecutingthe
LPSTOPinstruction.
Theprocessorwillremaininthismodeuntilauser-specification(orhigher)interrupt
levelorresetoccurs.
TableLookupandInterpolate(TBL):Tomaximizethroughputforreal-timeapplications,
referencedataisoften“pre-calculated”andstoredinmemoryforquickaccess.The
storageofeachdatapointwouldrequireaninordinateamountofmemory.Thetable
instructionrequiresonlyasampleofdatapointsstoredinthearray,reducingmemory
requirements.Thissingleinstructionallowsintermediatevaluestoberecoveredbylin-
earinterpolation,thussignificantlyincreasingCPUthroughputcomparedwithearlier
interpolationmethodswhichusedseveralinstructions.Theresultsareoptionally
roundedwiththeround-to-nearestalgorithm.
DevelopmentSupport ThefollowingfeatureshavebeenimplementedontheCPU32toenhancetheinstru-
mentationanddevelopmentenvironment:
• 68000familydevelopmentsupport,
• backgrounddebugmode,
• deterministicopcodetracking,
• hardwarebreakpoints.
68000FamilyDevelopment
Support All68000familymembersincludefeaturestofacilitateapplicationsdevelopment.These
featuresincludethefollowing:
TraceOnInstruction:68000familyprocessorsincludeaninstruction-by-instructiontrac-
ingfacilityasanaidtoprogramdevelopment.TheCPU32alsoallowstheusertotrace
onlythoseinstructionscausingachangeinprogramflow.
BreakpointInstruction:Anemulatormayinsertsoftwarebreakpointsintothetargetcode
toindicatewhenabreakpointhasoccurred.OntheCPU32,thisfunctionisprovidedvia
illegalinstructions,$4848-$484F,toserveasbreakpointinstructions.
UnimplementedInstructionEmulation:Duringinstructionexecution,whenanattemptis
madetoexecuteanillegalinstruction,anillegalinstructionexceptionoccurs.Unimple-
mentedinstructions(F-line,A-line,...)utilizeseparateexceptionvectorstopermit
efficientemulationofunimplementedinstructionsinsoftware.
32 TS68332 2118A–HIREL–03/02
BackgroundDebugMode Microcomputersystemsgenerallyprovideadebugger,implementedinsoftware,for
systemanalysisatthelowestlevel.ThebackgrounddebugmodeintheCPU32is
uniqueinthatthedebuggerhasbeenimplementedinCPUmicrocode.Registerscanbe
viewedand/oraltered,memorycanbereadorwrittento,andtestfeaturescanbe
invoked.Incorporatingthesecapabilitieson-chipsimplifiestheenvironmentinwhichthe
in-circuitemulatoroperates.
DeterministicOpcodeTracking CPU32functioncodeoutputsareaugmentedbytwosupplementarysignalstomonitor
theinstructionpipeline.Theinstructionpipe(PIPE)outputindicatesthestartofeach
newinstructionandeachmid-instructionpipelineadvance.Theinstructionfetch
(FETCH)outputidentifiesthebuscyclesinwhichtheoperandisloadedintotheinstruc-
tionpipeline.PipelineflushesarealsosignaledwithIFETCH.Monitoringthesetwo
signalsallowsabusanalyzertosynchronizeitselftotheinstructionstreamandmonitor
itsactivity.
On-chipBreakpointHardware Anexternalbreakpointtraponanymemoryaccess.
.
Table7.InstructionSetSummary
Mnemonic Description
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL,ASR
AddDecimalwithExtend
Add
AddAddress
AddImmediate
AddQuick
AddwithExtend
LogicalAND
LogicalANDImmediate
ArithmeticShiftLeftandRight
Bcc
BCHG
BCLR
BGND
BKPT
BRA
BSET
BSR
BTST
BranchConditionally
TestBitandChange
TestBitandClear
Background
Breakpoint
Branch
TestBitandSet
BranchtoSubroutine
TestBit
CHK,CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
CheckRegisterAgainstUpperandLowerBounds
Clear
Compare
CompareAddress
CompareImmediate
CompareMemorytoMemory
CompareRegisterAgainstUpperandLowerBounds
DBcc
DIVS,DIVSL
DIVU,DIVUL
TestCondition,DecrementandBranch
SignedDivide
UnsignedDivide
33
TS68332
2118A–HIREL–03/02
EOR
EORI
EXG
EXT,EXTB
LogicalExclusiveOR
LogicalExclusiveORImmediate
ExchangeRegisters
SignExtend
ILLEGAL TakeIllegalInstructionTrap
JMP
JSR Jump
JumptoSubroutine
LEA
LINK
LPSTOP
LSL,LSR
LoadEffectiveAddress
LinkandAllocate
LowPowerStop
LogicalShiftLeftandRight
MOVE
MOVECCR
MOVESR
MOVEUSP
MOVEA
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS,MULS.L
MULU,MULU.L
Move
MoveConditionCodeRegister
MoveStatusRegister
MoveUserStackPointer
MoveAddress
MoveControlRegister
MoveMultipleRegisters
MovePeripheral
MoveQuick
MoveAlternateAddreeSpace
SignedMultiply
UnsignedMultiply
NBCD
NEG
NEGX
NOP
NegateDecimalwithExtend
Negate
NegatewithExtend
NoOperation
OR
ORI LogicalInclusiveOR
LogicalInclusiveORImmediate
PEA PushEffectiveAddress
RESET
ROL,ROR
ROXL,ROXR
RTD
RTE
RTR
RTS
ResetExternalDevices
RotateLeftandRight
RotatewithExtendLeftandRight
ReturnandDe-allocate
ReturnfromException
ReturnandRestoreCodes
ReturnfromSubroutine
Table7.InstructionSetSummary(Continued)
Mnemonic Description
34 TS68332 2118A–HIREL–03/02
BusOperation Thissectionprovidesafunctionaldescriptionofthebusandthesignalsthatcontrolit.
OperationofthebusisthesamewhethertheMCUoranexternaldeviceisthebusmas-
ter;thenamesanddescriptionofbuscyclesarefromthepointofviewofthebus
master.TheMCUarchitecturesupportsbyte,word,andlong-wordoperands,allowing
accessto8-bitand16-bitdataportsthroughuseofasynchronouscyclescontrolledby
thedatatransfer(SIZ1andSIZ0)anddatasizeacknowledgepins(DSACK1and
DSACK0).
FunctionCodes Thefunctioncodesignals(FC2-FC0)selectoneofeight16-Mbyteaddressspaceto
whichtheaddressapplies.
AddressBus Theaddressbussignals(A23-A0)definetheaddressofthebyte(orthemostsignifi-
cantbyte)tobetransferredduringabuscycle.TheaddressisvalidwhileASasserted.
AddressStrobe TheAddressStrobe(AS)isatimingsignalthatindicatesthevalidityofanaddresson
theaddressbusandofmanycontrolsignals.
DataBus Thedatasignals(D15-D0)compriseabi-directional,non-multiplexedparallelbusthat
containsthedatabeingtransferredtoorfromtheMCU.Areadorwriteoperationmay
transfer8or16bitsofdata(1or2bytes)inonebuscycle.
DataStrobe TheDataStrobe(DS)isatimingsignalthatappliestothedatabus.Forareadcycle,
theMCUassertsDStosignaltheexternaldevicetoplacedataonthebus.Forawrite
cycle,DSsignalstotheexternaldevicesthatthedatatobewrittenisvalidonthebus.
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
SubtractDecimalwithExtend
SetConditionally
Stop
Subtract
SubtractAddress
SubtractImmediate
SubtractQuick
SubtractwithExtend
SwapRegisterWords
TBLS,TBLSN
TBLU,TBLUN
TAS
TRAP
TRAPcc
TRAPV
TST
Signed/UnsignedTableLookup
andInterpolate
TestOperandandSet
Trap
TrapConditionally
TraponOverflow
TestOperand
UNLK Unlink
Table7.InstructionSetSummary(Continued)
Mnemonic Description
35
TS68332
2118A–HIREL–03/02
BusControlSignals TheMCUinitiatesabuscyclebydrivingtheaddress,size,function,code,and
read/writeoutputs.Atthebeginningofabuscycle,thesizesignals(SIZ1,SIZ0)are
drivenalongwiththefunctioncodesignals.SIZ1andSIZ0indicatethenumberofbytes
remainingtobetransferredduringanoperandcycle(consistingofoneormorebus
cycles).Table8showstheencodingofSIZ1andSIZ0.Theread/write(R/W)signal
determinesthedirectionofthetransferduringabuscycle.Theread-modify-writecycle
signal(RMC)isassertedatthebeginningofthefirstbuscycleofaread-modify-write
operation,andremainsasserteduntilcompletionofthefinalbuscycleoftheoperation.
BusCycleTermination
Signals Duringbuscycles,externaldevicesassertthedatatransferandsizeacknowledgesig-
nalsDSACK1and/orDSACK0aspartofthebusprotocol.Duringareadcycle,this
signalstheMCUtoterminatethebuscycleandtolatchthedata.Duringawritecycle,
thisindicatesthattheexternaldevicehassuccessfullystoredthedataandthatthecycle
mayterminate.ThesesignalsalsoindicatetotheMCUthesizeoftheportforthebus
cyclejustcompleted.
Thebuserror(BERR)signalisalsoabuscycleterminationindicatorandcanbeusedin
theabsenceofDSACKxtoindicateabuserrorcondition.Itcanalsobeassertedincon-
junctionwithDSACKxtoindicateabuserrorcondition,provideditmeetsthe
appropriatetiming.Additionally,theBERRandHALTsignalscanbeassertedsimulta-
neously,inlieuof,orinconjunctionwith,theDSACKxsignals.
TheinternalbusmonitorcanbeusedtogeneratetheBERRsignalforinternalandinter-
nal-to-externaltransfers.AnexternalbusmastermustprovideitsownBERRgeneration
anddrivetheBERRpin,sincetheinternalBERRmonitorhasnoinformationabout
transfersinitiatedbyanexternalbusmaster.
Finally,theautovector(AVEC)signalcanbeusedtoterminateinterruptacknowledge
cycles,indicatingthattheMCUshouldinternallygenerateavectornumbertolocatean
interrupthandlerroutine.AVECisignoredduringallotherbuscycles.
DynamicBusSizing TheMCUdynamicallyinterruptstheportsizeoftheaddresseddeviceduringeachbus
signal,allowingoperandtransferstoorfrom8-and16-bitports.Duringanoperand
transfercycle,theslavedevicesignalsitsportsize(byteorword)andindicatescomple-
tionofthebuscycletotheMCUthroughtheuseoftheDSACKxencodingsand
assertionresults.RefertoTable9forDSACKxencodingsandassertionresults.For
example,iftheMCUisexecutinganinstructionthatreadsalong-wordoperandfroma
16-bitport,theMCUlatchesthe16bitsofvaliddataandrunsanotherbuscycleto
obtaintheother16bits.
Dynamicbussizingrequiresthattheportionofthedatabusforatransfertoorfroma
particularportsizebefixed.Forexamplean8-bitportmustresideondatabusbits15-
8.
TheSIZxsignalsalsoformpartofthebussizingprotocol.Theseoutputsindicatethe
remainingnumberorbytestobetransferredduringthecurrentbuscycle.
Table8.SizeSignalEncoding
SIZ1 SIZ2 TransferSize
01 Byte
10 Word
11 3Byte
0 0 LongWord
36 TS68332 2118A–HIREL–03/02
BusOperation TheMCUbusisusedinanasynchronousmanner.Theexternaldevicesconnectedto
thebuscanoperateatclockfrequenciesdifferentfromtheclockfortheMCU.Busoper-
ationusesthehandshakelines(AS,DS,DSACK1,DSACK0,BERRandHALT)to
controldatatransfers.DecodingthesizeoutputsandloweraddresslineA0provides
strobesthatselecttheactiveportionofthedatabus.Theslavedevice(memoryor
peripheral)thenrespondsbyplacingtherequesteddataonthecorrectportionofthe
databusforareadcycleorlatchingthedataonawritecycle,andassertingthe
DSACK1/DSACK0combinationthatcorrespondstotheportsizetoendthecycle.Ifno
slaverespondsortheaccessisinvalid,externalcontrollogicassertstheBERR,or
BERRandHALT)signal(s)toabortorretrythebuscycle,respectively.
FastTerminationCycles Withanexternaldevicethathasafastaccesstime,thechip-selectcircuitfast-termina-
tionoptioncanprovideatwo-cycleexternalbustransfer.Sincethechipselectcircuits
aredrivenfromthesystemclock,thebuscycleterminationisinherentlysynchronized
withthesystemclock.
BusExceptionControlCycles
ThebusarchitecturerequiresassertionofDSACKxfromanexternaldevicetosignal
thatabuscycleiscomplete.DSACKxorAVECisnotassertedinthesecases:
• Theexternaldevicedoesnotrespond
• Nointerruptvectorisprovided
• Variousotherapplication-dependenterrorsoccur
ThisMCUhasabuserrorinput(BERR)whennodevicerespondsbyasserting
DSACKxorwithinanappropriateperiodoftimeaftertheMCUassertstheAVEC.This
allowsthecycletoterminateandtheMCUtoenterexceptionprocessingfortheerror
condition.Anothersignalthatisusedforbusexceptioncontrolisthehaltsignal
(HALT).Thissignalcanbeassertedbyanexternaldevicefordebuggingpurposesto
causesinglebusoperationor(incombinationwithBERR)aretryofabuscycleinerror.
Table9.DSACKCodesandResults
DSACK1 DSACK0 Result
1
(Negated) 1
(Negated) Insertwaitstatesincurrentbuscycle
1
(Negated) 0
(Asserted) Completecycle–Databusportsizeis8-bits
0
(Asserted) 1
(Negated) Completecycle–Databusportsizeis16-bits
0
(Asserted) 0
(Asserted) Reserved
37
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BusArbitration ThebusdesignoftheMCUprovidesforasinglebusmasteratanyonetime:eitherthe
MCUoranexternaldevice.Oneormoreoftheexternaldevicesonthebuscanhave
thecapabilityofbecomingbusmaster.Busarbitrationistheprotocolbywhichanexter-
naldevicebecomesbusmaster;thebuscontrollerintheMCUmanagesthebus
arbitrationsignalssothattheMCUhasthelowestpriority.Externaldevicesthatneedto
obtainthebusmustassertthebusarbitrationsignalsinacertainsequence.Systems
thatincludeseveraldevicesthatcanbecomebusmasterrequireexternalcircuitryto
assignprioritiestothedevices,sothatwhentwoormoreexternaldevicesattemptto
becomebusmasteratthesametime,theonehavingthehighestprioritybecomesthe
busmasterfirst.TheprotocolisexplainedfullyintheSIMmanual,howeverhereisthe
basicsequenceofevents:
• Anexternaldeviceassertsthebusrequestsignal(BR),
• TheMCUassertsthebusgrantsignaltoindicatethatthebusisavailable(BG),
• Theexternaldeviceassertsthebusgrantacknowledgesignal(BGACK)toindicate
thatithasassumedbusmastership.
Busarbitrationrequestsarerecognizedduringnormalprocessing,HALTassertion,
whentheCPUhashaltedduetoadoublebusfault.
ResetOperation TheMCUhasresetcontrollogictodeterminethecauseofresetandsynchronizeitif
necessary.IfanexternaldevicedrivestheRESETpinlow,theresetcontrollogicholds
RESETassertedinternallyuntiltheexternalRESETisreleased.Whentheresetcontrol
logicdetectsthattheexternalRESETisnolongerbeingdriven,itdrivesRESETlowfor
anadditional512cyclestoguaranteethislengthofresettotheentiresystem.IfRESET
isassertedfromanyothersource,theresetcontrollogicassertsRESETforaminimum
of512cyclesanduntilthesourceofresetisnegated.Figure20isatimingdiagramof
thepower-upresetoperation,showingtherelationshipbetweenRESET,VDD,andbus
signals.Duringtheresetperiod,theentirebus(exceptfornon-tri-statablesignals,which
aredriventotheirinactivestatethree-states.OnceRESETnegates,allcontrolsignals
aredriventotheirinactivestate,thedatabusisinreadmode,andtheaddressbusis
driven.Afterthis,thefirstbuscycleforRESETexceptionprocessingbegins.
RESETshouldbeassertedforatleast590clockperiodstoensurethattheMCUresets.
ResettingtheMCUcausesanybuscycleinprogresstoterminateasifDSACKxor
BERRhasbeenasserted.Inaddition,theMCUinitializesregistersappropriatelyfora
resetexception.
ForfurtherinformationrefertotheSystemIntegrationModuleManual.
38 TS68332 2118A–HIREL–03/02
Figure20.InitialResetOperationTiming
Notes: 1. Internalstartuptime
2. SSPreadhere
3. PCreadhere
4. Firstinstructionfetchedhere
SystemIntegration
Module TheTS68332systemintegrationmodule(SIM)consistsoffivesudmodulesthatcontrol
themicrocontrollerunit(MCU)systemstart-up,initialization,configuration,andexternal
buswithaminimumofexternaldevices.ThefivessubmodulesthatmakeuptheSIM,
showninFigure21,areasfollows:
• SystemConfigurationandProtection
• ClockSynthesizer
•ChipSelects
• ExternalBusInterface
•SystemTest
SystemConfigurationand
ProtectionSubmodule TheSIMmoduleallowstheusertocontrolsomefeaturesofsystemconfigurationby
writingbitsintheModuleConfigurationRegister.Thisregisteralsocontainsread-only
statusbitsthatshowthestateofsomeoftheSIMfeatures.
ThisMCUisdesignedwiththeconceptofprovidingmaximumsystemsafe-guards.
Manyofthefunctionsthatnormallymustbeprovidedinexternalcircuitsareincorpo-
ratedinthisMCU.Thefeaturesprovidedinthesystemconfigurationandprotection
submoduleareasfollows:
SystemConfiguration Themoduleconfigurationregisterallowstheusertoconfigurethesystemaccordingto
theparticularsystemrequirements.
39
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InternalBusMonitor TheMCUprovidesaninternalbusmonitortomonitortheDSACKxresponsetimeforall
internalbusaccesses.Anoptionallowsthemonitoringofinternaltoexternalbus
accesses.Therearefourselectableresponsetimesthatallowfortheresponsespeedof
peripheralsusedinthesystem.Abuserror(BERR)signalisassertedinternallyifthe
DSACKxresponsetimeisexceeded.Whenoperatingasabusmaster,theBERRsignal
isnotassertedexternally.
Figure21.SystemIntegrationModuleBlockDiagram
HaltMonitor Ahaltmonitorcausesaresettooccuriftheinternalhalt(HALT)isassertedbytheCPU.
SpuriousInterruptMonitor Ifnointerruptarbitrationoccursduringaninterruptacknowledge(IACK)cycle,the
BERRsignalisassertedinternally.
SoftwareWatchdog ThewatchdogassertsRESETifthesoftwarefailstoservicethesoftwarewatchdogfora
designatedperiodoftime(presumablybecauseitistrappedinalooporlost).Thereare
fourselectabletime-outperiods,andaprescalermaybeusedforlongtime-outperiods.
PeriodicInterruptTimer TheMCUprovidesatimertogenerateperiodicinterrupts.Theperiodicinterrupttime
periodcanvaryfrom122µs-15.94µs(witha32.768kHzcrystalusedtogeneratethe
systemclock).
40 TS68332 2118A–HIREL–03/02
Figure22.ClockSubmoduleBlockDiagram
Note: Mustbelowleakagecapacitor.
ClockSynthesizer Theclocksynthesizer(Figure22)canoperatefromanon-chipphaselockedloop(PLL)
usinganexternalcrystalconnectedbetweentheEXTALandXTALpinsasareference
frequencysource.A32.768kHzwatchcrystalprovidesaninexpensivereference,but
thereferencecrystalfrequencycanbeanyfrequencyfrom25-50kHz.Outsidethe25-
50kHzrange,anexternaloscillatorcanbeusedwiththeon-chipsynthesizerandVCO,
orthefrequencycanbedrivendirectlyintotheEXTALpin(theXTALpinshouldbeleft
floatingforthiscase).
Thesystemclockfrequencyisprogrammablefrom131kHztothemaximumclockfre-
quencywitharesolutionof131kHz.Aseparatepowerpin(VDDSYN)isusedtoallowthe
clockcircuitstorunwiththerestoftheMCUpowereddownandtoprovideincreased
noiseimmunityfortheclockcircuits.Ifforsomereasontheexternalsignalisremoved
fromthedevicethentheclocksynthesizerwillgenerateitsowninternalclocksignalto
allowthedevicetoentersomekindoferrorrecoveryroutine.ThisisknownasLIMP
mode.Theclockfrequencygeneratedwillnothaveanassociatedtimingspecbut
shouldbearound9MHz.
Chip-selectSubmodule Typicalmicrocomputersystemsrequireexternalhardwaretoprovideselectsignalsto
externalperipherals.ThisMCUintegratesthesefunctionson-chipinordertoprovidethe
cost,speed,andreliabilitybenefitsofahigherlevelofintegration.Thechip-selectsig-
nalscanalsobeprogrammedasoutputenable,readorwritestrobe,orIACKsignals.
Sinceinitializationsoftwarewouldprobablyresideinaperipheralmemorydevicecon-
trolledbythechip-selectcircuits,aCSBOOTregisterprovidesdefaultresetvaluesto
supportbootstrapoperation.
Thechip-selectsubmodulesupportsthefollowingprogrammablefeatures:
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TwelveProgrammableChip-
selectCircuits Twelvechipselectsignalsareavailable(CSBOOT)andCS10troCSO).Thesesignals
usetheCSBOOTpin,busarbitrationpinsBR,BG,andBGACK,functioncodepins
FC2-FC0,andaddresspinsA23-A19.The(CSBOOT)pinisdedicatedtoasinglefunc-
tionbecauseitmustfunctionafteraresetwithnoinitialization,theotherchipselect
circuitssharefunctionsontheiroutputpins.All12chipselectcircuitsareindependently
programmablefromthesamelistofselectablefeatures.Eachchipselectcircuithasan
individualbaseregisterandoptionregisterwhichcontaintheprogrammablecharacter-
isticsofthatchipselect.Usingtheseaddresslinesaschipselectsignalsdoesnot
restrictthelargelinearaddressspaceoftheMCUsincethechipselectlogicalways
usestheinternaladdresslines.
VariableBlockSizes Theblocksizestartingfromthespecifiedbaseaddresscanbeprogrammedas2K,8K,
16K,64K,128K,256K,512Kbytesor1-Mbyte.
Both8-bitand16-bitPorts
Supported Eight-bitportsareaccessibleonbothoddandevenaddresseswhenconnectedtodata
busbits15-8.Sixteen-bitportscanbeaccessedasoddbytes,evenbytes,orwords.
ReadOnly,WriteOnly,or
Read/writeCapability Chipselectscanbeassertedsynchronizedwithread,write,orbothreadandwrite.
AddressStrobeandDataStrobe
TimingOption Chip-selectsignalscanbesynchronizedwitheitheraddressstrobeordatastrobe,so
thatcontrolsignalssuchasoutputenableorwriteenablecanbeeasilygenerated.
InternalDSACKGeneration
withWaitStates Theportprogrammedinthepinassignmentregistercanbereferencedforgenerating
DSACKandthepropernumberofwaitstatesforaparticulardeviceprogrammedbythe
user.
AddressSpaceChecking Supervisor,user,andCPUspaceaccessescanbeoptionallychecked.
InterruptPriorityLevel
Checking IntheIACKcycle,theacknowledgedinterruptlevelcanbecomparedwiththeuser-
specifiedlevelprogrammedintheoptionfield.Ifautovectoroptionisselected,AVECis
internallyasserted.
DiscreteOutput PortCpinsA22-A19andFC2-FC0canbeprogrammedfordiscreteoutput,withdata
storedinthepindataregister(CSPDR).
68000-typePeripheralSupport 68000-typeperipheralsthatrequireanEclockforsynchronizationcanbesupported.
Chipselectisasserted,synchronizedwiththeEclockonpinA23,providingcorrectdata
bustimingfortheMCU.
42 TS68332 2118A–HIREL–03/02
TestSubmodule Thetestsubmoduleisaprimarytooltosupportalltypesoftesting,suchasproduction
testanduserself-test,thatisintegratedintotheMCU.Thesubmodulesupportsscan-
basedtestingofvariousmodulesintheMCU.Thescantestemployedhereconsistsof
thetestsubmoduleperformingthefollowingsteps:
• seriallyshiftingstimulusdatatoanidlemoduleundertest(MUT)
• activatingthemoduleundertest
• seriallyshiftingresponsedatabackfromthemoduleundertest
• latchingtheresponsedataforinterrogationbythebusmaster
ThefurtherinformationtotheSystemIntegrationModuleManual.
QSMQueuedSerial
Module Thequeuedserialmodule(QSM)providesthemicrocontrollerunit(MCU)withtwoserial
communicationinterfacesdividedintotwosubmodules:thequeuedserialperipheral
interface(QSP)andtheserialcommunicationsinterface(SCI).TheQSPIisafull-
duplex,synchronousserialinterfaceforcommunicatingwithperipheralsandother
MCUs.ItisenhancedbytheadditionofaRAMqueueforreceiveandtransmitdata.The
SCIisafull-duplexuniversalasynchronousreceivertransmitter(UART)serialinterface.
Thesesubmodulesoperateindependently(seeFigure23).
QSMPins TheQSMhasnineexternalpins.Eightofthesepinscanbeusedasgeneral-purpose
I/Opins.Ifthepinisnotbeinguserforitssubmodulefunction.Theninthpin,RXD,isan
input-onlypinusedexclusivelybytheSCIsubmodule.Thepinsareidentifiedasfollows:
MISO–MasterInSlaveOut
MOSI–MasterOutSlaveIn
SCK–SerialClock
PCS0/SS–PeripheralChip-Select0/SlaveSelect
PCS3-PCS1–PeripheralChipSelects3-1
TXD–TransmitData
RXD–ReceiveData
QSPISubmodule TheQSPIsubmodulecommunicateswithexternalperipheralsandotherMCUsviaa
synchronousserialbus.TheQSPIisfullycompatiblewiththeSerialPeripheralInterface
(SPI)systemsfoundonotherAtmel-Grenobledevicessuchasthe68HC11and
68HC05families.IthasallofthecapabilitiesofthestandardSPIsystemaswellassev-
eralnewfeatures.ThefollowingparagraphsdescribethemainfeatureoftheQSPI.
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Figure23.QSMBlockDiagram
QSPIFeatures StandardSPIfeaturesarelistedbelow,followedbyalistoftheadditionalfeatures
offeredontheQSPI:
• fullduplex,three-wiresynchronoustransfers,
• half-duplex,two-wiresynchronoustransfers,
• masterorslaveoperation,
• programmablemasterbitrates,
• programmableclockpolarityandphase,
• end-of-transmissioninterruptflag,
• master-mastermodefaultflag,
• easilyinterfacestosimpleexpansionparts(A/Dconverters,EEPROMs,display
drivers,etc.).
QSPIEnhancedFeatures AprogrammablequeueallowstheQSPItoperformupto16serialtransferswithout
CPUintervention.Eachtransfercorrespondstoaqueueentrycontainingalltheinfor-
mationneededbytheQSPItoindependentlycompleteoneserialtransfer.Thisunique
featuregreatlyreducesCPU/QSPIinteraction,resultinginincreasedCPUandsystem
throughput.
OncetheCPUhassetupthequeueofQSPIcommandsandenablestheQSPI,the
QSPIoperatesindependentlyoftheCPU.TheQSPIexecutesallofthecommandsinits
queue,setsaflagindicatingthatithasfinished,andtheneitherinterruptstheCPUor
waitsforCPUintervention.
ProgrammablePeripheralChipSelects:Fourperipheralchip-selectpinsallowtheQSPI
toaccessupto16independentperipheralsbydecodingthefourperipheralchip-select
signals.Uptofourindependentperipheralscanbeselectedbydirectconnectiontoa
chip-selectpin.Theperipheralchipselectssimplifyinterfacingtotwoormoreserial
peripheralsbyprovidingdedicatedperipheralchip-selectsignalsandthusalleviatingthe
needforCPUintervention.
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WraparoundTransferMode:Wraparoundtransfermodeallowsforautomatic,continu-
ousre-executionofthepreprogrammedqueueentries.Newlytransferreddatareplaces
previouslytransferreddata.WraparoundsimplifiesinterfacingwithA/Dconvertersby
automaticallyprovidingtheCPUwiththelatestconversionsintheQSPIRAM.Conse-
quently,serialperipheralsappearasmemory-mappedparalleldevicestotheCPU.
ProgrammableTransferLength:Thenumberofbitsinaserialtransferisprogrammable
from8to16bits,inclusive.Forexample,10-bitscouldbeusedforcommunicatingwith
anexternal10-bitsA/Dconvertor.Likewise,avacuumfluorescentdisplaydrivermight
requirea12-bitsserialtransfer.Theprogrammablelengthsimplifiesinterfacingtoserial
peripheralsthatrequiredifferentdatalengths.
ProgrammableTransferDelay:Aninter-transferdelaymaybeprogrammedfrom
approximately1to500µs(usinga16.78MHzsystemclock).Forexample,anA/Dcon-
vertormayrequiretimebetweentransferstocompleteanewconversion.Thedefault
delayis1µs.Theprogrammablelengthofdelaysimplifiesinterfacingtoserialperipher-
alsthatrequiredelaytimebetweendatatransfers.
ProgrammableQueuePointer:TheQSPIhasapointerthatpointstothequeuelocation
containingthedataforthenextserialtransfer.TheCPUcanswitchfromonetaskto
anotherintheQSPIbywritingtothequeuepointer,changingthelocationinthequeue
thatistobetransferrednext.Otherwise,thepointerincrementsaftereachserialtrans-
fer.Bysegmentingthequeue,multiple-tasksupportcanbeprovidedbytheQSPI.
ContinuousTransferMode:Thecontinuoustransfermodeallowstheusertoexchange
anuninterruptedbitstreamwithaperipheral.Aminimumof8-bitsandamaximumof
256-bitsmaybetransferredinasingleburstwithoutCPUintervention.Longertransfers
arepossible;however,minimalCPUinterventionisrequiredtopreventlossofdata.A
1microsecondpause(usinga16.78MHzsystemclock)isinsertedbetweeneachentry
transfer.
QSPIRAM:TheQSPIusesan80-byteblockofdual-accessstaticRAMthatcanbe
accessedbyboththeQSPIandtheCPU.Becauseofsharing,thelengthoftimetaken
bytheCPUtoaccesstheQSPIRAM,whentheQSPIisenabled,maybelongerthan
whentheQSPIisdisabled.FromonetofourCPUwaitstatesmaybeinsertedbythe
QSPIintheprocessofreadingorwriting.
TheRAMisdividedintothreesegments:receivedata,transmitdata,andcommand
control.ReceivedataisinformationreceivedfromaserialdeviceexternaltotheMCU.
TransmitdataisinformationstoredbytheCPUfortransmissiontoanexternalperiph-
eralchip.CommandcontrolcontainsalltheinformationneededbytheQSPItoperform
thetransfer.Figure24illustratestheorganizationoftheRAM.
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Figure24.OrganizationoftheQSPIRAM
SCISubmodule TheSCIsubmoduleisusedtocommunicatewithexternaldevicesandotherMCUsvia
anasynchronousserialbus.TheSCIisfullycompatiblewiththeSCIsystemsfoundon
otherAtmelMCUssuchasthe68HC11and68HC05families.Ithasallofthecapabili-
tiesofpreviousSCIsystemsaswellasseveralsignificantnewfeatures.
•Features
StandardSCIfeaturesarelistedbelow,followedbyalistofadditionalfeaturesoffered:
StandardSCITwo-wireSystemsFeature:
• StandardNonReturntoZero(NRZ)Mark/spaceFormat
• AdvancedErrorDetectionMechanism(DetectsNoiseDurationUpTo1/16ofABit-
time)
• Full-duplexOperation
• SoftwareSelectableWordLength(8-or9-bitsWords)
• SeparateTransmitterAndReceiverEnableBits
• MayBeInterruptDriven
• FourSeparateInterruptEnableBits
StandardSCIReceiverFeatures:
• ReceiverWakeUpFunction(IdleorAddressMarkBit)
• Idle-lineDetect
• FramingErrorDetect
• NoiseDetect
• OverrunDetect
• ReceiveDataRegisterFullFlag
StandardSCITransmitterFeatures:
• TransmitDataRegisterEmptyFlag
• TransmitCompleteFlag
• SendBreak
QSM-enhancedSCITwo-wireSystemsFeatures:
46 TS68332 2118A–HIREL–03/02
• 13-bitsProgrammableBaudRateModulusCounter
• Even/oddParityGenerationAndDetection
QSM-enhancedSCIReceiverFeatures
• TwoIdle-lineDetectModes
• ReceiverActiveFlag
13-bitProgrammableBaudRateModulusCounter:Abaudratemoduluscounterhas
beenaddedtoprovidetheuserwithmoreflexibilityinchoosingthecrystalfrequencyfor
thesystemclock.ThemoduluscounterallowstheSCIbaudrategeneratortoproduce
standardtransmissionfrequenciesforawiderangeofsystemclocks.Theuserisno
longerconstrainedtoselectcrystalfrequenciesbasedonthedesiredserialbaudrate.
Thiscounterbaudratesfrom64baudto524baudwitha16.78MHzsystemclock.
Even/oddParityGenerationandDetection:Theusernowhasthechoiceeitherofseven
oreightdatabitsplusoneparitybit,orofeightorninedatabitswithnoparitybit.Even
oroddparityisavailable.Thetransmitterautomaticallygeneratestheparitybitfora
transmittedbyte.Thereceiverdetectswhenaparityerrorhasoccurredonareceived
byteandsetsaparityerrorflag.
TwoIdle-lineDetectModes:StandardAtmel-GrenobleSCIsystemsdetectanidleline
when10or11consecutivebit-timesareallones.Usedwiththereceiverwakeupmode,
thereceivercanbeawakenedprematurelyifthemessageprecedingthestartoftheidle
linecontainedonesinadvanceofitsstopbit.Thenew(second)idle-linedetectmode
onlystartscountingidletimeafteravalidstopbitisreceived,whichensurescorrectidle-
linedetection.
ReceiverActiveFlag(RAF):ReceiverActiveFlag(RAF)indicatesthestatusofthe
receiver.Itissetwhenapossiblestartbitisdetectedandisclearedwhenanidlelineis
detected.RAFisalsoclearedifthestartbitisdeterminedtobelinenoise.Thisflagcan
beusedtopreventcollisionsinsystemswithmultiplemasters.
ForfurtherinformationrefertotheSystemIntegrationModuleManual.
StandbyRAM(withTPU
emulation) TheTS68332contains2-KbytesofstandbyRAM.Thissectiondescribestheoperation
andcontroloftheRAMmodule.
Overview TheRammodulecontains2048bytesoffullystaticRAM,poweredbyVDDinnormal
operation.TheentirearraymaybeusedasstandbyRAMifpowerissuppliedtothe
VSTBYpin.SwitchingbetweenVDDandVSTBYoccursautomatically.
TheRAMmaybeusedasgeneral-purposememoryfortheMCU,providingfast,two-
clockaccessestotheCPU.Typically,theRAMisusedforprogramcontrolstacksand
frequentlymodifieddatavariables.TheCPUmayreadorwritebyte,word,orlong-word
data.
TheRAMmayalsobeusedasmicrocodecontrolmemoryfortheTimeProcessorUnit
(TPU).TheTPUmustbeplacedinemulationmodetousetheRAMinthismanner
whichallowsuserstodeveloptheirownmicrocodeprimitives.
RAMArrayAddressing TheRAMarraycanbeplacedanywhereintheaddressmapofthearraybaseaddress
(RAMBAR),providedthatitisona2-Kbytesboundaryanddoesnotoverlapthethree
RAMmodulecontrolregistersusedforcontrolandtesting.RAMBARcanbewrittenonly
onceafterreset.ThispreventstheRAMarraybeingaccidentallyremappedbysoftware.
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TPUEmulationMode
Operation TheRAMarraymaybeusedasthemicrocodecontrolstorefortheTPUmodule.This
modeofoperationisselectedfromwithintheTPU.SeeDevelopmentsupportinthe
TPUmanualforacompletedescription.
TheTPUisconnectedtotheRAMviaadedicatedbus.Whileinemulationmode,the
accesstimingoftheRAMmodulematchesthetimingoftheTPUmicroinstructionROM
toensureaccurateemulation.NormalaccessesviatheIMBareinhibitedandthecontrol
registerhavetoeffect,allowingexternalRAMtoemulatethe2KRAMarrayatthesame
addresses.
ThefurtherinformationrefertotheSystemIntegrationModuleManual.
TPUOverview TheTPUperformssimpleaswellascomplextimingtasks,independentlyfromtheCPU,
makingitthelatestadvanceintimersystems.Viewedasaspecialpurposemicrocom-
puter,thisprocessorperformstwooperations,matchandcapture,ononeoperand:
TIME.Everyoccurrenceofeitheractioniscalledanevent.Theservicingofthese
eventsbytheTPUreplacestheservicingofinterruptsbythehostCentralProcessing
Unit(CPU).Thetimingfunctionscurrentlysynthesizedarethefollowing:
• DiscreteInput/output
• InputCapture/inputTransitionCounter
• OutputCompare
• PulseWidthModulation
• SynchronizedPulseWidthModulation
• PeriodMeasurementWithAdditionalTransitionDefect
• PeriodMeasurementWithMissingTransitionDetect
• Position-synchronizedPulseGenerator
• StepperMotor
• Period/pulse-widthAccumulator
Thepreviouspre-programmedfunctionsarerelatedtotheTPURommasksetA,cur-
rentlyinusefortheTS68332MCU,asthe“standard”TPUmaskset.
TheadvancedTPUaffordsforthefirsttimehigh-resolutiontimingandmultipletime
functioncapability(flexibility)inthetimersystempins.
High-resolutionTiming High-resolutiontimingislimitedbyCPUoverheadrequiredforservicingtimingtasks
suchasperiodmeasurement,pulsemeasurement,pulse-widthmodulatedwaveform
generation,etc.OntheTPU,high-resolutiontimingisachievedbytwomaincapabilities:
• reducedlatency,
• reducedservicetime,whichfreetheCPUtofocusonotherresponsibilities.
TheTPUprovidesahigherresolutionthantheCPUcouldachieve,andcreatesnoCPU
overheadforservicingtimingtasks.
Latency Latencyistheintervaloftimefromaneventothestartofeventservicing.Theabilityof
theTPUtoserviceitsowninterruptsoreventsreduceslatencyandtheCPUisnot
requiredtoserviceeachinputtransitioncapturethatoccursonapin,ortodetermine
eachmatchtimerequiredforwaveformsynthesis.OnceconfiguredbythehostCPU,
theself-containedTPUperformscomplextimefunctionsrequiringhighresolutionwith
littleornoCPUintervention.
48 TS68332 2118A–HIREL–03/02
ServiceTime Serviceisthetimeexpendedservicinganevent.Inoldermicrocontrollerunit(MCU)
timerfunctions,theservicetimeisconstrainedbecausetheMCUinstructionsetisnot
optimizedfortimefunctionsynthesis.TheTPUinstructionsetisoptimized,andtime
functionsaresynthesizedwithfewerinstructionsthantheCPU.Instructionsexecute
fasterandservicetimeisreduced.InstructionsexecutedbytheTPUarenotusersoft-
ware,butfirmware,special-purposemicrocodewrittenbyAtmel-Grenobletoperformas
settimefunctions.MicrocodeisplacedintotheTPUcontrolstore(ROM)whenthe
deviceismanufactured.
Features • 16channels;eachchannelassociatedwithapin
• Eachchannelcanperformanytimefunction
• Eachtimefunctionmaybeassignedtomorethanonechannelatagiventime
• Eachchannelhasaneventregistercomprisedofthefollowing:
– 16-bitscaptureregister
– 16-bitscompare/matchregister
– 16-bitsgreater-thanorequal-tocomparator
• Eachchannelcanbesynchronizedtooneorbothofthetwo16-bitsfree-running
timercountregisters(TCR1andTCR2)
• TCR1isclockedfromtheoutputofaprescaler.Theprescaler’sinputistheinternal
TPUsystemclockdividedbyeither4or32.Thefoursettingsoftheprescalerare
divideby1,2,4and8.ChannelsusingTRC1havethecapabilitytoresolvedownto
theTPUsystemclockdividedbyfour.
• TCR2isclockedfromtheoutputofaprescaler.Theprescaler’sinputistheexternal
TCR2pin.Thefoursettingsoftheprescaleraredivideby1,2,4and8.Channels
usingtheTCR1havethecapabilitytoresolvedowntothePRUsystemclock
dividedby8.
• TCR2maybeusedasahardwarepulseaccumulatorclockedfromtheexternal
TCR2pin,orasagatedpulseaccumulatorortheclockthatincrementsTCR1.
• Allchannelshaveatleastsix16-bitsparameterregisters.Channels14and15each
haveeight16-bitsparameterregisters.Allparameterregistersarecontainedina
dual-portRAM,accessiblefromboththeTPUandCPU.
• Aschedulerwiththreeprioritylevelssegregateshigh,middle,andlow-prioritytime
functions.Anychannelmaybeassignedtooneofthesethreeprioritylevels.
• Alltimefunctionsaremicrocoded.
• Emulationanddevelopmentsupportisprovidedforalltimefunctionfeaturessuch
asbreakpoint,freezeandsinglestep,givinginternalregisteraccessibility.
• Coherenttransfercapabilityfortwoparameterisprovidedinhardware.
• CoherenttransfercapabilityforNparametersmaybeperformedasaTPU
microcodefunction.(RefertoDevelopmentsupportintheTPUreferencemanualfor
furtherdetailsonthisfeature).
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GeneralConcept TheTPUisanintelligent,semi-autonomousperipheraldedicatedtotimingcontrol.Its
intelligenceenablestheservicingoftimingeventswithoutCPUintervention.Thisdevice
usesaprivatemicroengineforaprocessor,ascheduler,input/outputchannels,ROM
instructions,andshared-accessdataRAMtooperateindependentlyandsimultaneously
withtheCPU(seeFigure25).Consequently,thesetupandservicetimeforeachtimer
eventisminimized.
A“time-of-delay”approachisusedwherealltimefunctionsarerelatedtooneoftwo16-
bitsfree-runningTCRs.Timefunctionsaresynthesizedbycombiningthetwotimeprim-
itives,matchandcaptureevents.Byperformingthesetimeprimitivesinhardware,the
TPUcanpreciselydeterminethetimewhenamatcheventistooccurandthenspecify
thestateoftheoutputpinaccordingly.TheTPUcanalsoaccuratelyrecordthetimeat
whichaninputtransitionoccursandcanperformcalculationsbasedonthetimeofthe
occurrence.Aneventregisterforeachchannelprovidesforsimultaneityofmatch/cap-
ture-eventoccurrencesonallchannels.
Whenamatchorinputcaptureeventrequiringserviceoccursonachannel,thechannel
generatesaservicerequesttothescheduler.Theschedulerprioritizestherequestwith
otherpendingservicerequests.Whenthemicroengineisidle,theschedulercausesthe
microenginetoexecuteamicrocodesequence.Whenthemicroengineisbusy,thenew
sequencebeginswhenthecodebeingexecutedends.Themicroengineperformsthe
function,whichisdefinedbythecontentofthecontrolstore,usingparametersfromthe
parameterRAMandfromtheeventregisters,etc.,asneeded.Thefollowingisan
example.
ChannelXisgeneratingaperiodicwaveformandpresentlytheoutputishigh.Whenthe
valueoftheTCRusedbythatchannelincrementstomatchthevalueoftheeventregis-
terofchannelX,amatcheventoccurs.Theeventswitchestheoutputtolowand
generatesanewservicerequesttothescheduler.Theschedulerthanschedulesand
initiatesserviceofchannelXbythemicroengine.
Whenexecutionofthesequencebegins,themicroengineusestheexecutionunit:
• Toobtain(fromtheparameterRAM)thevaluerepresentingthedurationofcounts
forwhichchannelXshouldremainlow,and
• ToaddtothisvaluethevaluefromthecontentoftheeventregisterofchannelX.
Thecontentoftheeventregisteristhenreplacedbythissum;thechannelcontrolis
setforamatcheventonthesameTCR;andthepincontrolissettocausethe
outputpinforchannelXtoswitchhighwhentheeventoccurs.Achannelinterrupt,
whichsignalstheendofservicetotheCPU,maybeasserted(ifthetimefunction
providesforitandtheinterruptisenabled).Themicroengineisthenfreetoservice
thenexteventdeterminedbythescheduler.
50 TS68332 2118A–HIREL–03/02
Figure25.TPUSimplifiedBlockDiagram
Flexibility TheTPUhastheflexibilitytobeconfiguredtodirectlysolvetheuser’stimerrequire-
ments.Thisflexibilityisattainedthroughfivecapabilities:
• channelorthogonality
• inter-channelcommunication
• programmablechannelservicepriority
• selectionoftimingfunctions
• emulationcapability
ChannelOrthogonality Traditionally,timersystemshavebeenlimitedbythespecificfunctionsofchannelpins
dedicatedtoperformtimefunctionssuchasinputcapture,outputcompare,orpulse
accumulation.AllchannelsoftheTPUcontainidenticalhardwareandarefunctionally
equivalentinoperation,suchthatanychannelcanbeconfiguredtoperformanytime
function.Theusercontrolsthecombinationoftimefunctions;theonlyconstraintisthe
numberofpinsavailablefortimingfunctions.
Inter-channelCommunication TheTPU’sabilitytoserviceitselfrequiresacontinuousflowofdirectandindirectcom-
munication.Directcommunicationisaccomplishedthrougha“changechannel”feature
inwhichanychanneloftheTPUcanoperateanotherchanneltoaffectitsstate.Indirect
communicationisprovidedbyalinkfeatureinwhichanychannelcanlonktoonemore
channels,includingitself,tosignalaneedforfutureservice.Asaresult,theusercan
referencetheoperationofonechanneltotheoccurrenceofaspecificactiononanother
channel.
ProgrammableChannelService
Priority Applicationsmayrequiredifferentprioritiesofeventservice.Thechannelservicepriority
maybeprogrammedtooneofthreelevels:high,middle,andlow.Theschedulerallows
calculationofworst-caselatencyforeventservicingandensuresservicingofallchan-
nelsbypreventingpermanentblockage.
T2CLK
PINS
SERVICE REQUESTS
DATA
TCR1
TCR2
MICROENGINE
CONTROL
STORE
EXECUTION
UNIT
I M B
PARAMETER
RAM
CHANNEL
CONTROL
DEVELOPMENT
SUPPORT AND TEST
SYSTEM
CONFIGURATION
SCHEDULER
CONTROL AND DATA
CONTROL
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
CHANNEL 15
CHANNEL
DATA
HOST
INTERFACE
51
TS68332
2118A–HIREL–03/02
SelectionofTimingFunctions Theavailabletimingfunctionscanbeprogrammedtooperateonanychannel.Parame-
terregistersassociatedwitheachchannelareusedasgeneral-purposetimeoperands.
EmulationCapability TheTPUcannotresolvealltimerproblemsusingpredefinedtimefunctionsalone;there-
fore,developmentofuser-definedtimefunctionsisallowedinemulationmode.Using
theRAMmoduleoftheMCUasa“writablecontrolstore”providesTPUemulation.In
TPUemulationmode,anauxiliarybusconnectionismadebetweentheRAMmodule
andtheTPUmodule,andaccesstotheRAMmoduleviatheintermodulebusisdis-
abled.A9-bitsaddressbus,a32-bitsdatabus,andcontrollinestransferinformation
betweenthemodules.Toensureexactemulation,theaccesstimingoftheRAMmodule
remainsconsistentwiththeTPUROMcontrolstore.
Applications TheTPU’shighspeed,versatilearchitecture,andtimefunctionsfacilitateitsusein
manycontrolapplications,suchassteppermotorsandangle-basedenginecontrol.
Controlofasteppermotororanangle-basedautomotiveengineusuallyrequireshigh
CPUoverhead.TheseapplicationsshowhowtheSM,PMA/PPM,andtimefunctions
minimizetheoverheadassociatedwiththeseapplications,andprovidesophistication
andflexibilityforawidevarietyofapplications.
FurtherdetailedinformationontheTPUisfoundintheTPUreferencemanual.
PreparationFor
Delivery
Packaging MicrocircuitarepreparedfordeliveryinaccordancewithMIL-M-38510.
CertificateofCompliance Atmel-Grenobleoffersacertificateofcompliancewitheachshipmentofparts,affirming
theproductsareincomplianceeitherwithMIL-STD-883orAtmel-Grenoblestandard
andguaranteeingtheparametersaretestedatextremetemperaturesfortheentiretem-
peraturerange.
Handling
MOSdevicesmustbehandledwithcertainprecautionstoavoiddamageduetoaccu-
mulationofstaticcharge.Inputprotectiondeviceshavebeendesignedinthechipto
minimizetheeffectofthisstaticbuildup.However,thefollowinghandlingpracticesare
recommended:
a)Deviceshouldbehandledonbencheswithconductiveandgroundedsurface
b)Groundtestequipment,toolsandoperator
c)Donothandledevicesbytheleads
d)Storeinconductivefoamorcarriers
e)Avoiduseofplastic,rubber,orsilkinMOSareas
f)Maintainrelativehumidityabove50%,ifpractical
52 TS68332 2118A–HIREL–03/02
PackagingInformation
Figure26.132–ball–CeramicPin–GridArray(PGA)
53
TS68332
2118A–HIREL–03/02
Figure27.132–leadCERQUAD
Notes: 1. DimensioningandtolerancingperansiY14.5M,1982.
2. Controllingdimensions:inch.
3. DimAandBdefinemaximumceramicbodydimensionsincludingglassprotrusionandmismatchofceramicbodytopand
bottom.
4. Datumplane-W-islocatedattheundersideofleadswhereleadsexitpackagebody.
5. DatumsX-YandZtobedeterminedwherecenterleadsexitpackagebodyatdatum-W-.
6. DimSandVtobedeterminedatseatingplane,datum-T-.
7. DimAandBtobedeterminedatdatumplane-T-.
54 TS68332 2118A–HIREL–03/02
OrderingInformation
Hi-RelProduct
CommercialAtmel
Part-Number Norms Package Temperature
RangeTc(°C) Frequency
(MHz) DrawingNumber
TS68332MRB/C16 MIL-STD-883 PGA132 -55/+125 16.78 Atmel-Grenobledatasheet
TS68332MR1B/C16 MIL-STD-883 PGA132tin -55/+125 16.78 Atmel-Grenobledatasheet
TS68332MAB/C16 MIL-STD-883 CERQUAD132 -55/+125 16.78 Atmel-Grenobledatasheet
TS68332MRB/C20 MIL-STD-883 PGA132 -55/+125 20.97 Atmel-Grenobledatasheet
TS68332MR1B/C20 MIL-STD-883 PGA132tin -55/+125 20.97 Atmel-Grenobledatasheet
TS68332MAB/C20 MIL-STD-883 CERQUAD132 -55/+125 20.97 Atmel-Grenobledatasheet
TS68332DESC01ZA MIL-STD-883 PGA132tin -55/+125 16.78 5962-9150101MZA
TS68332DESC01ZC MIL-STD-883 PGA132 -55/+125 16.78 5962-9150101MZC
TS68332DESC02ZC MIL-STD-883 PGA132 -55/+125 20.97 5962-9150102MZC
TS68332DESC01XA MIL-STD-883 CERQUAD132 -55/+125 16.78 5962-9150101MXA
TS68332DESC02XA MIL-STD-883 CERQIAD132 -55/+125 20.97 5962-9150102MXA
StandardProduct
CommercialAtmel
Part-Number Norms Package Temperature
RangeTc(°C) Frequency
(MHz) DrawingNumber
TS68332VR16 Atmel-GrenobleStandard PGS132 -40/+85 16.78 Atmel-Grenobledatasheet
TS68332MR16 Atmel-GrenobleStandard PGS132 -55/+125 16.78 Atmel-Grenobledatasheet
TS68332VA16 Atmel-GrenobleStandard CERQUAD132 -40/+85 16.78 Atmel-Grenobledatasheet
TS68332MA16 Atmel-GrenobleStandard CERQUAD132 -55/+125 16.78 Atmel-Grenobledatasheet
TS68332VR20 Atmel-GrenobleStandard PGS132 -40/+85 20.97 Atmel-Grenobledatasheet
TS68332MR20 Atmel-GrenobleStandard PGS132 -55/+125 20.97 Atmel-Grenobledatasheet
TS68332VA20 Atmel-GrenobleStandard CERQUAD132 -40/+85 20.97 Atmel-Grenobledatasheet
TS68332MA20 Atmel-GrenobleStandard CERQUAD132 -55/+125 20.97 Atmel-Grenobledatasheet
55
TS68332
2118A–HIREL–03/02
Note: Foravailabilityofdifferentversions,contactyourAtmelsalesoffice.
TS 68332 M R B/C 16 A
Tem perature range : Tc
M : -55, +125°C
V : -40, +85 °C
C : 0, +70°C
S c reen ing le v el :
__ : Standar d
B/ C : MIL-STD-883, class B
DS CC : DESCOx Mxx *
Lead finish :
1 : Tinned for PGA
Package :
R : Pin grid Array 132
A : CERQUAD 132
(Gullwing leads)
S tand ard lead fini sh
Gold
Hot solder dip
Speed (MHz)
Re visio n lev e l
16 : 16 MHz
20 : 20 MHz
Manufacturer's
Prefix
Type
Printedonrecycledpaper.
©AtmelCorporation2002.
AtmelCorporationmakesnowarrantyfortheuseofitsproducts,otherthanthoseexpresslycontainedintheCompany’sstandardwarranty
whichisdetailedinAtmel’sTermsandConditionslocatedontheCompany’swebsite.TheCompanyassumesnoresponsibilityforanyerrors
whichmayappearinthisdocument,reservestherighttochangedevicesorspecificationsdetailedhereinatanytimewithoutnotice,anddoes
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2118A–HIREL–03/02 0M
ATMEL®istheregisteredtrademarksofAtmel.
Othertermsandproductnamesmaybethetrademarksofothers.