General Description
The MAX5060/MAX5061 pulse-width modulation (PWM)
DC-DC controllers provide high-output-current capability
in a compact package with a minimum number of exter-
nal components. These devices utilize an average-cur-
rent-mode control that enables optimal use of low
RDS(ON) MOSFETs, eliminating the need for external
heatsinks even when delivering high output currents.
Differential sensing (MAX5060) enables accurate control
of the output voltage, while adaptive voltage positioning
provides optimum transient response. An internal regula-
tor enables operation with 4.75V to 5.5V or 7V to 28V
input voltage ranges. The high switching frequency, up
to 1.5MHz, allows the use of low-output inductor values
and input capacitor values. This accommodates the use
of PC-board-embedded planar magnetics.
The MAX5060 features a clock output with 180° phase
delay to control a second out-of-phase converter for
lower capacitor ripple currents. The MAX5060 also limits
the reverse current if the bus voltage becomes higher
than the regulated output voltage. The MAX5060 is
specifically designed to limit current sinking when multi-
ple power-supply modules are paralleled. The
MAX5060/MAX5061 offer an adjustable 0.6V to 5.5V out-
put voltage. The MAX5060 offers an overvoltage protec-
tion, power-good signal, and an output enable function.
The MAX5060/MAX5061 operate over the automotive
temperature range (-40°C to +125°C). The MAX5060 is
available in a 28-pin thin QFN package while the
MAX5061 is available in a 16-pin TSSOP package.
Applications
Servers and Workstations
Point-of-Load Telecom DC-DC Regulators
Networking Systems
RAID Systems
High-End Desktop Computers
Features
♦4.75V to 5.5V or 7V to 28V Input Voltage Range
♦Adjustable Output Voltage from 0.6V to 5.5V
♦Up to 30A Output Current
♦Can Parallel Outputs For Higher Output Current
♦Programmable Adaptive Output Voltage
Positioning
♦True-Differential Remote Output Sensing
(MAX5060)
♦Average-Current-Mode Control
•Superior Current Sharing Between Paralleled
Modules
•Accurate Current Limit Eliminates MOSFET
and Inductor Derating
♦Limits Reverse Current Sinking in Paralleled
Modules (MAX5060)
♦Programmable Switching Frequency from 125kHz
to 1.5MHz
♦Integrated 4A Gate Drivers
♦Clock Output for 180° Out-of-Phase Operation
(MAX5060)
♦Voltage Signal Proportional to Output Current for
Load Monitoring (MAX5060)
♦Output Overvoltage Crowbar Protection
(MAX5060)
♦Programmable Hiccup Current-Limit Threshold
and Response Time
♦Overtemperature Thermal Shutdown
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
Selector Guide
PART TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX5060ATI
-40°C to +125°C
28 TQFN-EP*
T2855-3
MAX5060ETI
-40°C to +85°C
28 TQFN-EP*
T2855-3
MAX5061AUE
-40°C to +125°C 16 TSSOP-EP*
U16E-3
MAX5061EUE
-40°C to +85°C 16 TSSOP-EP*
U16E-3
PART OUTPUT
MAX5060
Average-Current-Mode DC-DC Controller
for 5V/12V/24V Input Bus with CLKOUT,
Load Monitoring, Overvoltage, EN Input,
SYNC Input, and PGOOD Output
MAX5061
Average-Current-Mode DC-DC Controller
for 5V/12V/24V Input with SYNC/ENABLE
Input
19-3583; Rev 2; 7/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Pin Configurations appear at end of data sheet.
*EP = Exposed pad.
EVALUATION KIT
AVAILABLE
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
2_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IN to SGND.............................................................-0.3V to +30V
BST to SGND..........................................................-0.3V to +35V
DH to LX .......................................-0.3V to [(VBST - VLX_) + 0.3V]
DL to PGND (MAX5060).............................-0.3V to (VDD + 0.3V)
DL to PGND (MAX5061).............................-0.3V to (VCC + 0.3V)
BST to LX..................................................................-0.3V to +6V
VCC to SGND............................................................-0.3V to +6V
VCC, VDD to PGND ...................................................-0.3V to +6V
SGND to PGND .....................................................-0.3V to +0.3V
Current Sink in PGOOD ........................................................6mA
All Other Pins to SGND...............................-0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 21.3mW/°C above +70°C)* ......1702mW
28-Pin TQFN (derate 34.5mW/°C above +70°C)*......2758mW
Operating Temperature Range
MAX5060A_ _ and MAX5061A_ _ .................-40°C to +125°C
MAX5060E_ _ and MAX5061E_ _....................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
*Per JEDEC 51 standard.
ELECTRICAL CHARACTERISTICS
(VCC = 5V, VDD = VCC (MAX5060 only), TA= TJ= TMIN to TMAX, unless otherwise noted. Typical specifications are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
728
Input Voltage Range VIN Short IN and VCC together for 5V input
operation
4.75 5.50
V
Quiescent Supply Current IQEN = VCC or SGND, not switching 2.7 5.5 mA
Efficiency ηILOAD = 20A, VIN = 12V, VOUT = 3.3V 90 %
OUTPUT VOLTAGE
No load, VCC = 4.75V to 5.5V,
fSW = 500kHz
0.594
0.6
0.606
SENSE+ to SENSE- Accuracy
(MAX5060) (Note 2)
No load, VIN = 7V to 28V, fSW = 500kHz 0.594
0.6
0.606
V
Soft-Start Time tSS
1024
Clock
Cycles
No load, VCC = 4.75V to 5.5V,
no switching
0.591
0.6
0.606
EAN Reference Voltage
(MAX5061) VREF
No load, VIN = 7V to 28V, no switching 0.591
0.6
0.606
V
STARTUP/INTERNAL REGULATOR
VCC Undervoltage Lockout UVLO VCC rising 4.1 4.3 4.5 V
VCC Undervoltage Lockout
Hysteresis
200
mV
VCC Output Voltage
VIN = 7V to 28V, ISOURCE = 0 to 60mA 4.85
5.1
5.30
V
MOSFET DRIVERS
Output-Driver Impedance RON Low or high output,
ISOURCE/SINK = 20mA 1.1 3 Ω
Output-Driver Source/Sink Current
IDH_, IDL_ 4A
Nonoverlap Time tNO CDH/DL = 5nF 35 ns
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VDD = VCC (MAX5060 only), TA= TJ= TMIN to TMAX, unless otherwise noted. Typical specifications are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Switching Frequency Range 125
1500
kHz
RT = 500kΩ121
125 129
RT = 120kΩ495
521 547
Switching Frequency fSW
RT = 39.9kΩ
1515 1620 1725
kHz
120kΩ ≤ RT ≤ 500kΩ-5 +5
Switching Frequency Accuracy 40kΩ ≤ RT ≤ 120kΩ-8 +8 %
CLKOUT Phase Shift (MAX5060)
φCLKOUT fSW = 125kHz
180
degrees
CLKOUT Output Low Level
(MAX5060) VCLKOUTL ISINK = 2mA 0.4 V
CLKOUT Output High Level
(MAX5060) VCLKOUTH ISOURCE = 2mA 4.5 V
SYNC Input-High Pulse Width tSYNC RT/SYNC (MAX5060), RT/SYNC/EN
(MAX5061) 200 ns
SYNC Input Clock High Threshold
VSYNCH RT/SYNC (MAX5060), RT/SYNC/EN
(MAX5061) 2.0 V
SYNC Input Clock Low Threshold
VSYNCL RT/SYNC (MAX5060), RT/SYNC/EN
(MAX5061) 0.4 V
SYNC Pullup Current ISYNC_OUT VRT/SYNC = 0V (MAX5060),
VRT/SYNC/EN = 0V (MAX5061)
250 750
µA
SYNC Power-Off Level VSYNC_OFF 0.4 V
CURRENT LIMIT
Average Current-Limit Threshold
VCL CSP to CSN
24.0 26.9 28.2
mV
Reverse Current-Limit Threshold VCLR CSP to CSN (MAX5060)
-3.2 -2.3 -0.1
mV
Cycle-by-Cycle Current Limit CSP to CSN 60 mV
Cycle-by-Cycle Overload
Response Time VCSP to VCSN = 75mV
260
ns
Hiccup Divider Ratio LIM to VCM, no switching
0.547 0.558 0.565
V/V
Hiccup Reset Delay
200
ms
LIM Input Impedance LIM to SGND
55.9
kΩ
CURRENT-SENSE AMPLIFIER
CSP to CSN Input Resistance RCS 4kΩ
Common-Mode Range VCMR(CS) VIN = 7V to 28V 0 5.5 V
Input Offset Voltage VOS(CS) 0.1 mV
Amplifier Gain AV(CS)
34.5
V/V
3dB Bandwidth f3dB 4
MHz
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
4_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VDD = VCC (MAX5060 only), TA= TJ= TMIN to TMAX, unless otherwise noted. Typical specifications are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT-ERROR AMPLIFIER (Transconductance Amplifier)
Transconductance gC
550
µS
Open-Loop Gain AVOL(CE) No load 50 dB
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF, MAX5060 only)
Common-Mode Voltage Range VCMR(DIFF) 0
+1.0
V
DIFF Output Voltage VCM VSENSE+ = VSENSE- = 0V 0.6 V
Input Offset Voltage VOS(DIFF) -1 +1 mV
Amplifier Gain AV(DIFF)
0.994
1
1.006
V/V
3dB Bandwidth f3dB CDIFF = 20pF 3
MHz
Minimum Output-Current Drive IOUT(DIFF) 4mA
SENSE+ to SENSE- Input
Resistance RVS VSENSE- = 0V 50
100
kΩ
V_IOUT AMPLIFIER (V_IOUT, MAX5060 only)
Gain-Bandwidth Product VV_IOUT = 2.0V 4
MHz
3dB Bandwidth VV_IOUT = 2.0V 1.0
MHz
Output Sink Current 30 µA
Output Source Current 90 µA
Maximum Load Capacitance 50 pF
V_IOUT Output to IOUT Transfer
Function
RSENSE = 1mΩ,
100mV ≤ V_IOUT ≤ 5.5V
132.3 135 137.7
mV/A
Offset Voltage 1mV
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain AVOLEA 70 dB
Unity-Gain Bandwidth fGBW 3
MHz
VEAN = 2.0V (MAX5060)
EAN Input Bias Current IB(EA) VEAN = 0.4V, VEAOUT = GND
(MAX5061)
-0.2 0.03 +0.2
µA
Error-Amplifier Output-Clamping
Voltage VCLAMP(EA) With respect to VCM (MAX5060),
with respect to SGND (MAX5061) 883
930 976
mV
POWER-GOOD AND OVERVOLTAGE PROTECTION (MAX5060 only)
PGOOD Trip Level VUV PGOOD goes low when VOUT is below
this threshold
87.5
90
92.5
%VOUT
PGOOD Output Low Level VPGLO ISINK = 4mA 0.4 V
PGOOD Output Leakage Current
IPG PGOOD = VCC 1µA
OVI Trip Threshold OVPTH With respect to SGND
1.244 1.276 1.308
V
OVI Input Bias Current IOVI 0.2 µA
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 5V, VDD = VCC (MAX5060 only), TA= TJ= TMIN to TMAX, unless otherwise noted. Typical specifications are at TA= +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE INPUTS
EN Input High Voltage (MAX5060)
VEN EN rising
2.437
2.5
2.562
V
EN Input Hysteresis (MAX5060)
0.28
V
EN Pullup Current (MAX5060) IEN
13.5
15
16.5
µA
RT/SYNC/EN Input High Voltage
Enable (MAX5061)
VRT/SYNC/EN_H
1.6 V
RT/SYNC/EN Input Low Voltage
Disable (MAX5061)
VRT/SYNC/EN_L
0.4 V
THERMAL SHUTDOWN
Thermal Shutdown Temperature rising
+150
°C
Thermal-Shutdown Hysteresis 30 °C
Note 1: Specifications at TA= +25°C are 100% tested. Specifications over the temperature range are guaranteed by design.
Note 2: Does not include an error due to finite error amplifier gain (see the Voltage-Error Amplifier section).
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5060 toc01
OUTPUT CURRENT (A)
η (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
020
VOUT = 3.3V
fSW = 250kHz
VIN = 5V VIN = 12V
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
MAX5060 toc02
OUTPUT CURRENT (A)
η (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
020
VOUT = 0.6V
fSW = 250kHz
VIN = 5V
VIN = 12V
EFFICIENCY vs. OUTPUT CURRENT
MAX5060 toc03
OUTPUT CURRENT (A)
η (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
020
VIN = 24V
VOUT = 3.3V
fSW = 125kHz
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5060 toc04
OUTPUT CURRENT (A)
η (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
020
VIN = 12V
fSW = 250kHz
VOUT = 5V
VOUT = 3.3V
VOUT = 0.6V
VOUT = 1V
VOUT = 1.8V
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
MAX5060 toc05
OUTPUT CURRENT (A)
η (%)
181612 144 6 8 102
10
20
30
40
50
60
70
80
90
100
0
020
VIN = 5V
fSW = 500kHz
VOUT = 3.3V
VOUT = 1.8V
VOUT = 1V
VOUT = 0.6V
SUPPLY CURRENT (IQ) vs. FREQUENCY
MAX5060 toc06
FREQUENCY (kHz)
SUPPLY CURRENT (mA)
13001100900700500300
10
20
30
40
50
60
0
100 1500
EXTERNAL CLOCK
NO DRIVER LOAD
VIN = 12V
VIN = 24V
VIN = 5V
SUPPLY CURRENT vs. TEMPERATURE
MAX5060 toc07
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
603510-15
62
64
66
68
70
60
-40 85
VIN = 12V
fSW = 250kHz
CDL/CDH = 22nF
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
MAX5060 toc08
VOUT (V)
(VCSP - VCSN) (mV)
4321
26.5
27.0
27.5
28.0
28.5
29.0
26.0
05
VIN = 12V
fSW = 250kHz
HICCUP CURRENT LIMIT vs. REXT
MAX5060 toc09
REXT (MΩ)
CURRENT LIMIT (A)
161284
23.5
24.0
24.5
25.0
25.5
26.0
23.0
020
VIN = 12V
fSW = 250kHz
R1 = 1mΩ
VOUT = 1.5V
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
6_______________________________________________________________________________________
Typical Operating Characteristics
(TA = +25°C, Figures 1 and 2, unless otherwise noted.)
LOW-SIDE DRIVER (DL) SINK
AND SOURCE CURRENT
MAX5060 toc16
3A/div
100ns/div
CLOAD = 22nF
VIN = 12V
Typical Operating Characteristics (continued)
(TA = +25°C, Figures 1 and 2, unless otherwise noted.)
OUTPUT VOLTAGE vs. OUTPUT CURRENT
AND ERROR AMPLIFIER GAIN (RF/RIN)
MAX5060 toc10
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
181612 144 6 8 102
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.300
020
VIN = 12V
fSW = 250kHz
VOUT = 1.5V
RF/RIN = 40
RF/RIN = 10
RF/RIN = 20
V_IOUT VOLTAGE vs. LOAD CURRENT
MAX5060 toc11
LOAD CURRENT (A)
VV_IOUT (V)
15105
0.5
1.0
1.5
2.0
2.5
3.0
0
020
VOUT = 3.3V
R1 = 1mΩ
MAX5060
VIN = 12V
VIN = 7V
VIN = 24V
VCC LOAD REGULATION
vs. INPUT VOLTAGE
MAX5060 toc12
VCC LOAD CURRENT (mA)
VCC (V)
125100755025
4.85
4.95
5.05
5.15
5.25
4.75
0150
VIN = 12V
VIN = 5V
VIN = 24V
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
MAX5060 toc13
CAPACITANCE (nF)
tR (ns)
2116116
20
40
60
80
100
0
1
VIN = 12V
fSW = 250kHz
DH
DL
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
MAX5060 toc14
CAPACITANCE (nF)
tF (ns)
2116116
20
40
60
80
100
0
1
VIN = 12V
fSW = 250kHz
DH
DL
HIGH-SIDE DRIVER (DH) SINK
AND SOURCE CURRENT
MAX5060 toc15
2A/div
100ns/div
CLOAD = 22nF
VIN = 12V
HIGH-SIDE DRIVER (DH) RISE TIME
MAX5060 toc17
2V/div
40ns/div
CLOAD = 22nF
VIN = 12V
HIGH-SIDE DRIVER (DH) FALL TIME
MAX5060 toc18
2V/div
40ns/div
CLOAD = 22nF
VIN = 12V
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
_______________________________________________________________________________________ 7
REVERSE CURRENT SINK
vs. TEMPERATURE
MAX5060 toc25
TEMPERATURE (°C)
SINK CURRENT (A)
603510-15
1.6
1.8
2.0
2.2
2.4
1.4
-40
VIN = 12V
V0UT = 1.5V
R1 = 1mΩ
VEXTERNAL = 3.3V
VEXTERNAL = 2V
85
LOW-SIDE DRIVER (DL) RISE TIME
MAX5060 toc19
2V/div
40ns/div
CLOAD = 22nF
VIN = 12V
LOW-SIDE DRIVER (DL) FALL TIME
MAX5060 toc20
2V/div
40ns/div
CLOAD = 22nF
VIN = 12V
OUTPUT RIPPLE
MAX5060 toc21
50mV/div
1µs/div
VIN = 12V
VOUT = 1.5V
IOUT = 20A
INPUT STARTUP RESPONSE
MAX5060 toc22
VOUT
2V/div
2ms/div
VIN = 12V
VOUT = 1.5V
IOUT = 20A VPGOOD
5V/div
VIN
5V/div
ENABLE STARTUP RESPONSE
MAX5060 toc23
VOUT
2V/div
2ms/div
VIN = 12V
VOUT = 1.5V
IOUT = 20A
VPGOOD
5V/div
VEN
2V/div
LOAD-TRANSIENT RESPONSE
MAX5060 toc24
100µs/div
VIN = 12V
VOUT = 3.3V
ISTEP = 5A TO 20A
SLEW = 2A/µs
VOUT
200mV/div
IOUT
10A/div
0
REVERSE CURRENT SINK AT INPUT TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.0V)
MAX5060 toc26
200µs/div
2A/div
REVERSE CURRENT SINK AT INPUT TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5060 toc27
200µs/div
5A/div
Typical Operating Characteristics (continued)
(TA = +25°C, Figures 1 and 2, unless otherwise noted.)
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
8_______________________________________________________________________________________
Typical Operating Characteristics (continued)
(TA = +25°C, Figures 1 and 2, unless otherwise noted.)
REVERSE CURRENT SINK AT ENABLE TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 2.0V)
MAX5060 toc28
200µs/div
2A/div
REVERSE CURRENT SINK AT ENABLE TURN-ON
(VIN = 12V, VOUT = 1.5V, VEXTERNAL = 3.3V)
MAX5060 toc29
200µs/div
5A/div
FREQUENCY vs. RT
MAX5060 toc30
RT (kΩ)
fSW (kHz)
470
430
390
350
310
270
230
190
150
110
70
1000
10,000
100
30 510
VIN = 12V
FREQUENCY vs. TEMPERATURE
MAX5060 toc31
TEMPERATURE (°C)
fSW (kHz)
603510-15
242
244
246
248
250
252
254
256
258
260
240
-40 85
VIN = 12V
OUTPUT SHORT-CIRCUIT WAVEFORM
MAX5060 toc32
40ms/div
VOUT
2V/div
VIN = 12V CEN = 0.47µF
VOUT = 3.3V RLIM = OPEN
EN
2V/div
IOUT
10A/div
SYNC, CLKOUT, AND LX WAVEFORM
MAX5060 toc33
1µs/div
CLKOUT
5V/div
VIN = 12V
fSW = 250kHz
LX
10V/div
SYNC
5V/div
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
_______________________________________________________________________________________ 9
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
10 ______________________________________________________________________________________
Pin Description
PIN
MAX5060 MAX5061 NAME FUNCTION
13PGND Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and
VDD (MAX5060)/VCC (MAX5061) bypass capacitor returns together.
2, 7 8 N.C. No Connection. Not internally connected.
34 DL Low-Side Gate-Driver Output. Synchronous MOSFET gate driver.
45BST
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-
side MOSFET driver supply. Connect a 0.47µF ceramic capacitor between BST
and LX.
56 LX
Inductor Connection. Source connection for the high-side MOSFETs. Also serves
as the return terminal for the high-side driver.
67 DH High-Side Gate-Driver Output. Drives the gate of the high-side MOSFET.
8, 22, 25 16 SGND Signal Ground. Ground connection for the internal control circuitry. Connect
SGND and PGND together at one point near the input bypass capacitor return.
9—CLKOUT Oscillator Output. Rising edge of CLKOUT is phase-shifted from rising edge of
DH by 180°.
10 — PGOOD
Power-Good Output. PGOOD is an open-drain output that goes low when the
programmed output voltage falls out of regulation. The power-good comparator
threshold is 90% of the programmed output voltage.
11 — EN
Output Enable. Drive EN high or leave unconnected for normal operation. Drive
EN low to shut down the power drivers. EN has an internal 15µA pullup current.
Connect a capacitor from EN to SGND to program the hiccup mode duty cycle.
12 — RT/SYNC
Switching Frequency Programming and Chip-Enable Input. Connect a resistor
from RT/SYNC to SGND to set the internal oscillator frequency. Drive RT/SYNC
externally to synchronize the switching frequency with system clock.
13 — V_IOUT Voltage-Source Output Proportional to the Output Load Current. The voltage at
V_IOUT is 135 x ILOAD x RS.
14 10 LIM
Current-Limit Setting Input. Connect a resistor from LIM to SGND to set the
hiccup current-limit threshold. Connect a capacitor from LIM to SGND to ignore
short output overcurrent pulses.
15 — OVI
Overvoltage Protection Circuit Input. Connect OVI to DIFF. When OVI exceeds
+12.7% above the programmed output voltage, DH is latched low and DL is
latched high. Toggle EN low to high or recycle the power to reset the latch.
16 11 CLP Current-Error-Amplifier Output. Compensate the current loop by connecting an
RC network to ground.
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 11
Pin Description (continued)
PIN
MAX5060 MAX5061 NAME FUNCTION
17 12 EAOUT
Voltage-Error-Amplifier Output. Connect to the external gain-setting feedback
resistor. The error-amplifier gain-setting resistors determine the amount of
adaptive voltage positioning.
18 13 EAN
Voltage-Error-Amplifier Inverting Input. Receives a signal from the output of the
differential remote-sense amplifier (MAX5060). Connect the center tap of the
resistor-divider from the output to SGND (MAX5061).
19 — DIFF Differential Remote-Sense Amplifier Output. DIFF is the output of a precision
unity-gain amplifier whose inputs are SENSE+ and SENSE-.
20 14 CSN
Current-Sense Differential Amplifier Negative Input. The differential voltage
between CSN and CSP is amplified internally by the current-sense amplifier
(gain = 34.5) to measure the inductor current.
21 15 CSP
Current-Sense Differential Amplifier Positive Input. The differential voltage
between CSP and CSN is amplified internally by the current-sense amplifier
(gain = 34.5) to measure the inductor current.
23 — SENSE- Differential Output-Voltage-Sensing Negative Input. SENSE- is used to sense a
remote load. Connect SENSE- to VOUT- or PGND at the load.
24 — SENSE+
Differential Output-Voltage-Sensing Positive Input. SENSE+ is used to sense a
remote load. Connect SENSE+ to VOUT+ at the load. The device regulates the
difference between SENSE+ and SENSE- according to the preset reference
voltage of 0.6V.
26 1 IN Supply Voltage Connection. Connect IN to VCC for a +5V system.
27 2 VCC
Internal +5V Regulator Output. VCC is derived from the IN voltage. Bypass VCC
to SGND with 4.7µF and 0.1µF ceramic capacitors. For MAX5061, connect an
additional 0.1µF bypass capacitor from VCC to PGND.
28 — VDD
Supply Voltage for Low-Side and High-Side Drivers. Connect a parallel
combination of 0.1µF and 1µF ceramic capacitors to PGND and a 1Ω resistor to
VCC to filter out the high peak currents of the driver from the internal circuitry.
—9RT/SYNC/EN
Switching Frequency Programming and Chip-Enable Input. Connect a resistor
from RT/SYNC/EN to SGND to set the internal oscillator frequency. Drive
RT/SYNC/EN externally to synchronize the switching frequency with system
clock. If RT/SYNC/EN is held low for 50µs, the device turns off the output drivers.
—— EP
Exposed Paddle. Connect the exposed paddle to a copper pad (SGND) to
improve power dissipation.
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
12 ______________________________________________________________________________________
Typical Application Circuit
VIN
CSP
L1 R1
DH Q1
Q2
D1
C12
C10
C12 C13
RH
RL
VOUT = 0.6V TO
5.5V AT 20A
C8
C3–C7
LX
DL
BST
PGNDCLP SGND
CSN
VCC
VDD
LOAD
LIM
C3
C1, C2
IN SENSE- SENSE+
IN
R13
R3
MAX5060
PGOOD
PGOOD
RT/
SYNC
SYNC
R11
C11
EAOUT
DIFF
EAN
OVI
V_IOUT
V_IOUT
(VOLTAGE α IOUT)
ON
OFF
EN
C5
RIN
RF
C6
R5
C7
C4
REXT
VIN = 12V
D3
Figure 1. Typical Application Circuit, VIN = 12V (MAX5060)
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 13
Typical Application Circuit (continued)
VIN
CSP
L1 R1
DH Q1
Q2
D1
C12 C10 C11
VOUT = 0.6V TO
5.5V AT 20A
C9
C13–C16
LX
DL
BST
PGND SGND
CSN
VCC
LOAD
RT/SYNC/EN
C3
C1, C2
IN
IN
R13
MAX5061
EAN EAOUT
SYNC
RH
RL
RF
VCC
C7* C8
CLP
ON
C5
C6
R5
LIM
RT
C4
REXT
VIN = 12V
D3
* USE C13 = 47pf AND C7 = 4.7µF/6.3V (CERAMIC).
OFF
RC2
C13*
RC1
VCC
Figure 2. Typical Application Circuit, VIN = +12V (MAX5061)
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
14 ______________________________________________________________________________________
Block Diagram
2 x fS (V/s)
RAMP
RT/SYNC
CSP
CSN
SGND
SENSE-
SENSE+
CLP
LIM
IN
EN
VDD
BST
DH
LX
DL
PGND
PGOOD
AV = 34.5
AV = 4
100kΩ
126.7kΩ
PWM
COMPARATOR
0.5V x VCC
TO INTERNAL
CIRCUITS HICCUP MODE
CURRENT LIMIT
S
R
Q
Q
V_IOUT
gm = 500µS
DIFF
CLKOUT
CLK
CPWM
CEA
VCLAMP
HIGH
VCLAMP
LOW
CA
VCC
0.1 x VREF
N
+0.6V
VREF = 0.6V
VCM (0.6V)
OVP COMP
0.12 x VREF
LATCH
RAMP
GENERATOR
SOFT-
START
OSCILLATOR
CLEAR ON UVLO RESET OR
ENABLE LOW
OVP LATCH
DIFF
AMP
EAN
EAOUT
OVI
VEA
ERROR AMP
0.5 x VCLAMP
VCM
VCM
IS
VCC
Ct
RT
S
R
Q
Q
UVLO
POR
TEMP SENSOR
5V
LDO
REGULATOR
MAX5060
Figure 3. Functional Diagram (MAX5060)
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 15
Block Diagram (continued)
2 x fS (V/s)
RAMP
RT/SYNC/EN
CSP
CSN
CLK
SGND
CLP
LIM
IN
VCC BST
DH
LX
DL
PGND
AV = 34.5
100kΩ
126.7kΩ
PWM
COMPARATOR
0.5V x VCC
TO INTERNAL
CIRCUITS HICCUP MODE
CURRENT LIMIT
S
R
Q
Q
gm = 500µS
CPWM
CEA
VCLAMP
HIGH
CA
VCC
VREF = 0.6V
RAMP
GENERATOR
SOFT-
START
OSCILLATOR
EAN
EAOUT
VEA
ERROR AMP
0.5 x VCLAMP
VCM
VCM
IS
VCC
Ct
RT
S
R
Q
Q
UVLO
POR
TEMP SENSOR
5V
LDO
REGULATOR
MAX5061
Figure 4. Functional Diagram (MAX5061)
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
16 ______________________________________________________________________________________
Detailed Description
The MAX5060/MAX5061 are high-performance average-
current-mode PWM controllers. The average-current-
mode control technique offers inherently stable
operation, reduces component derating and size by
accurately controlling the inductor current. This also
improves the current-sharing accuracy when paralleling
multiple converters. The devices achieve high efficiency,
at high current (up to 30A) with a minimum number of
external components. The high- and low-side drivers
source and sink up to 4A for lower switching frequencies
while driving high-gate-charge MOSFETs.
The MAX5060’s CLKOUT output is 180° out-of-phase
with respect to the high-side driver. The CLKOUT drives
a second MAX5060 or a MAX5061 regulator out-of-
phase, reducing the input capacitor ripple current and
increasing the load current capacity. The paralleling
capability of the MAX5060/MAX5061 improves design
flexibility in applications requiring upgrades (higher load).
The MAX5060/MAX5061 consist of an inner average-
current-loop controlled by an outer-voltage-loop voltage-
error amplifier (VEA). The combined action of the inner
current loop and outer voltage loop corrects the output
voltage errors by adjusting the inductor current. The
inductor current is sensed across a current-sense resis-
tor. The differential amplifier (MAX5060) senses the out-
put right at the load for true-differential output voltage
sensing. The sensed voltage is compared against inter-
nal 0.6V reference at the error-amplifier input. The output
voltage can be set from 0.6V to 5.5V (IN ≥7V) using a
resistor-divider at SENSE+ and SENSE-.
IN, VCC, and VDD
The MAX5060/MAX5061 accept a 4.75V to 5.5V or 7V
to 28V input voltage range. All internal control circuitry
operates from an internally regulated nominal voltage
of 5V (VCC). For input voltages of 7V or greater, the
internal VCC regulator steps the voltage down to 5V.
The VCC output voltage is a regulated 5V output capa-
ble of sourcing up to 60mA. Bypass the VCC to SGND
with 4.7µF and 0.1µF low-ESR ceramic capacitors for
high-frequency noise rejection and stable operation.
The MAX5060 uses VDD to power the low-side and
high-side drivers, while the MAX5061 uses the VCC to
power internal circuitry as well as the low- and high-
side driver supply. In the case of the MAX5061, use
one or more 0.1µF low-ESR ceramic capacitors
between VCC and PGND to reject the noise spikes due
to high-current driver switching.
The TQFN-28 and TSSOP-16 are thermally enhanced
packages and can dissipate up to 2.7W and 1.7W,
respectively. The high-power packages allow the
high-frequency, high-current buck converter to oper-
ate from a 12V or 24V bus. Calculate power dissipa-
tion in the MAX5060/MAX5061 as a product of the
input voltage and the total VCC regulator output cur-
rent (ICC). ICC includes quiescent current (IQ) and
gate-drive current (IDD):
PD= VIN x ICC
ICC = IQ+ [fSW x (QG1 + QG2)]
where QG1 and QG2 are the total gate charge of the
low-side and high-side external MOSFETs at VGATE =
5V, IQis 3.5mA (typ), and fSW is the switching frequen-
cy of the converter.
Undervoltage Lockout (UVLO)
The MAX5060/MAX5061 include an undervoltage lock-
out with hysteresis and a power-on-reset circuit for con-
verter turn-on and monotonic rise of the output voltage.
The UVLO rising threshold is internally set at 4.35V with
a 200mV hysteresis. Hysteresis at UVLO eliminates
chattering during startup.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches 4V. The
MAX5060/MAX5061 draw up to 3.5mA of current
before the input voltage reaches the UVLO threshold.
Soft-Start
The MAX5060/MAX5061 has an internal digital soft-start
for a monotonic, glitch-free rise of output voltage. Soft-
start is achieved by the controlled rise of error amplifier
dominant input in steps using a 5-bit counter and a 5-bit
DAC. The soft-start DAC generates a linear ramp from 0
to 0.7V. This voltage is applied to the error amplifier at a
third (noninverting) input. As long as the soft-start volt-
age is lower than the reference voltage, the system will
converge to that lower reference value. Once the soft-
start DAC output reaches 0.6V, the reference takes over
and the DAC output continues to climb to 0.7V assuring
that it is out of the way of the reference voltage.
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 17
Internal Oscillator
The internal oscillator generates a clock with the fre-
quency proportional to the inverse of RT. The oscillator
frequency is adjustable from 125kHz to 1.5MHz with
better than 8% accuracy using a single resistor con-
nected from RT/SYNC to SGND (MAX5060) and from
RT/SYNC/EN to SGND (MAX5061). The frequency accu-
racy avoids the over-design, size, and cost of passive
filter components like inductors and capacitors. Use the
following equation to calculate the oscillator frequency:
for 120kΩ≤RT≤500kΩ:
for 40kΩ≤RT≤120kΩ:
The oscillator also generates a 2VP-P voltage-ramp sig-
nal for the PWM comparator and a 180° out-of-phase
clock signal for CLKOUT (MAX5060) to drive a second
DC-DC converter out-of-phase.
Synchronization
The MAX5060/MAX5061 can be easily synchronized by
connecting an external clock to RT/SYNC (MAX5060) or
RT/SYNC/EN (MAX5061). If an external clock is pre-
sent, then the internal oscillator is disabled and the
external clock is used to run the MAX5060/MAX5061. If
the external clock is removed, the absence of clock for
32µs is detected and the circuit starts switching from
the internal oscillator. Pulling RT/SYNC on the MAX5060
or RT/SYNC/EN on the MAX5061 to ground for at least
50µs disables the converter.
Use an open-collector transistor to synchronize the
MAX5060/MAX5061 with the external system clock (see
Figures 1 and 2).
Rf
TSW
.
=×640 10
10
Rf
TSW
.
=×625 10
10
DRIVE
VIN
VOUT
COUT
VREF + VCM
RF*
*RF AND RIN ARE EXTERNAL.
CCFF
CCF
IL
RCF
CSN CSP CLP
RS
LOAD
CPWM
CEA
VEA
DIFF
AMP
SENSE+
SENSE-
CA
RIN*
MAX5060
Figure 5. MAX5060 Control Loop
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
18 ______________________________________________________________________________________
Control Loop
The MAX5060/MAX5061 use an average-current-mode
control scheme to regulate the output voltage (Figure 5).
The main control loop consists of an inner current loop
and an outer voltage loop. The inner loop controls the
output current (IPHASE), while the outer loop controls the
output voltage. The inner current loop absorbs the
inductor pole reducing the order of the outer voltage
loop to that of a single-pole system.
The current loop consists of a current-sense resistor
(RSENSE), a current-sense amplifier (CA), a current-
error amplifier (CEA), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM) (Figure 6). The
precision CA amplifies the sense voltage across RS by
a factor of 34.5. The inverting input to the CEA senses
the CA output. The CEA output is the difference
between the voltage-error-amplifier output (EAOUT)
and the amplified voltage from the CA. The RC com-
pensation networks connected to CLP provide external
frequency compensation for the CEA. The start of every
clock cycle enables the high-side drivers and initiates a
PWM ON cycle. Comparator CPWM compares the out-
put voltage from the CEA with a 0 to 2V ramp from the
oscillator. The PWM ON cycle terminates when the
ramp voltage exceeds the error voltage.
The MAX5060 outer voltage control loop consists of the
differential amplifier (DIFF AMP), reference voltage, and
VEA. The unity-gain differential amplifier provides true-
differential remote sensing of the output voltage. The dif-
ferential amplifier output connects to the inverting input
(EAN) of the VEA. For MAX5061, the DIFF AMP is
bypassed and the inverting input is available to the pin
for direct feedback. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5060/MAX5061 reference voltage is set
to 0.6V. The VEA controls the inner current loop (Figure
4). Use a resistive feedback network to set the VEA gain
as required by the adaptive voltage-positioning circuit
(see the Adaptive Voltage Positioning section).
2 x fS (V/s)
RAMP
CLK
CSP
CSN
GMIN
SHDN
CLP
VDD
BST
DH
LX
DL
PGND
AV = 34.5
PWM
COMPARATOR
PEAK-CURRENT
COMPARATOR
60mV
S
R
Q
Q
gm = 550µS
CPWM
CEA
CA
MAX5060
Figure 6. Phase Circuit
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 19
Current-Sense Amplifier
The differential current-sense amplifier (CA) provides a
DC gain of 34.5. The maximum input offset voltage of
the current-sense amplifier is 1mV and the common-
mode voltage range is 0 to 5.5V (IN = 7V to 28V). The
current-sense amplifier senses the voltage across a
current-sense resistor. The maximum common-mode
voltage is 3.6V when VIN = 5V. The common-mode volt-
age range determines the maximum output voltage of
the buck converter.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 5).
Note the average current-limit threshold of 26.9mV still
limits the output current during short-circuit conditions.
To prevent inductor saturation, select an output inductor
with a saturation current specification greater than the
average current limit. Proper inductor selection ensures
that only the extreme conditions trip peak-current com-
parator, such as a broken output inductor. The 60mV
threshold for triggering the peak-current limit is twice the
full-scale average current-limit voltage threshold. The
peak-current comparator has only a 260ns delay.
Current-Error Amplifier
The MAX5060/MAX5061 has a transconductance cur-
rent-error amplifier (CEA) with a typical gmof 550µS
and 320µA output sink- and source-current capability.
The current-error amplifier output CLP, serves as the
inverting input to the PWM comparator. CLP is external-
ly accessible to provide frequency compensation for
the inner current loops (Figure 5). Compensate (CEA)
so the inductor current down slope, which becomes the
up slope to the inverting input of the PWM comparator,
is less than the slope of the internally generated voltage
ramp (see the Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2VP-P ramp. At the start of each clock
cycle, an R-S flip-flop resets and the high-side driver
(DH) turns on. The comparator sets the flip-flop as soon
as the ramp voltage exceeds the CLP voltage, thus ter-
minating the ON cycle (Figure 5).
Differential Amplifier (MAX5060)
The differential amplifier (DIFF AMP) facilitates output-
voltage remote sensing at the load (Figure 5). It pro-
vides true-differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA pro-
vides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The dif-
ferential amplifier has a bandwidth of 3MHz. The differ-
ence between SENSE+ and SENSE- is regulated to
0.6V for the MAX5060. Connect SENSE+ to the center
of the resistive divider from the output to SENSE-.
Connect SENSE- to PGND near the load.
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop. The
VEA determines the error between the differential
amplifier output and the internal reference voltage.
The VEA output clamps to 930mV relative to the inter-
nally generated common-mode voltage (VCM, 0.6V),
thus limiting the maximum output current. The maxi-
mum average current-limit threshold is equal to the
maximum clamp voltage of the VEA divided by the gain
(34.5) of the current-sense amplifier. This results in
accurate settings for the average maximum current for
each phase. Set the VEA gain using RFand RIN (see
Figures 1 and 2) for the amount of output voltage posi-
tioning required within the rated current range as dis-
cussed in the Adaptive Voltage Positioning section. The
finite gain of the VEA introduces an error in the output
voltage setting. Use the following equation to calculate
the output voltage at no load condition.
MAX5060:
where RHand RLare the feedback resistor network
(see the Typical Application Circuits) and VREF = 0.6V.
MAX5061:
The error amplifier output (EAOUT), which is compared
against the output of the current amplifier (CA), may not
reduce down to zero due to the saturation voltage of its
output stage. This requires the converter to be loaded
with a minimum load to prevent it from slipping out of
regulation. The minimum load requirement can be elim-
inated by adding some DC bias voltage between CSP
and CSN. See the Typical Application Circuit (Figure 2).
Use RC1 and RC2 to generate approximately 3mV DC
bias at CSP with respect to CSN. Use the following
equation to calculate the values of RC1 and RC2.
RC VV RC
IR
CC OUT
LSENSE
12
0 002 0 25
=−×
+××
()
(. ) (. )∆
VR
R
RR
RV
OUT NL IN
F
HL
LREF() =+
×+
×1
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
20 ______________________________________________________________________________________
where ∆IL= peak-to-peak inductor current. Choose
RC2 = 10Ω, VCC = 5.1V, and RSENSE is a current-
sense resistor. Note that the current limit of MAX5061 is
reduced by 3mV / RSENSE.
The no-load output voltage depends on the RH, RF,
VREF (0.6V) and the fixed DC bias voltage at CSP -
CSN. The following equation assumes a 3mV bias volt-
age at CSP - CSN.
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward-voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current sud-
denly decreases. Allowing a larger voltage-step excur-
sion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
Voltage positioning may require the output to regulate
away from a center value. Define the center value as
the voltage where the output drops (∆VOUT/2) at one
half the maximum output current (Figure 7).
Set the voltage-positioning window (∆VOUT) using the
resistive feedback of the voltage-error amplifier (VEA).
Use the following equations to calculate the voltage-
positioning window (Figure 5):
MAX5060:
MAX5061:
RIN and RFare the input and feedback resistors of
VEA. GCis the current-loop transconductance and RS
is the current-sense resistor.
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH) and low-side (DL) drivers drive the
gates of external n-channel MOSFETs (Figures 1 and 2).
The drivers’ 4A peak sink- and source-current capability
provides ample drive for the fast rise and fall times of the
switching MOSFETs. Faster rise and fall times result in
reduced cross-conduction losses. For modern CPU volt-
age-regulating module applications, where the duty
cycle is less than 50%, choose high-side MOSFETs (Q1)
with a moderate RDS(ON) and a very low gate charge.
Choose low-side MOSFETs (Q2) with very low RDS(ON)
and moderate gate charge. Size the high-side and low-
side MOSFETs to handle the peak and RMS currents
during overload conditions.
The driver block also includes a logic circuit that provides
an adaptive nonoverlap time to prevent shoot-through
currents during transition. The typical nonoverlap time is
35ns between the high-side and low-side MOSFETs.
BST
The MAX5060 uses VDD to power the low- and high-side
MOSFET drivers. The low- and high-side drivers in the
MAX5061 are powered from VCC. The high-side driver
derives its power through a bootstrap capacitor and VDD
supplies power internally to the low-side driver. Connect a
0.47µF low-ESR ceramic capacitor between BST and LX.
Connect a Schottky rectifier from BST to VDD on the
MAX5060, or to VCC on the MAX5061. Reduce the PC
board area formed by the boost capacitor and rectifier.
∆VIxR
GxR
OUT OUT H
cF
=
∆VIR
GR
RR
R
GR
OUT OUT IN
CF
HL
L
CS
=×
××+
=
.0 0289
VV
R
V
RRV
OUT NL REF
L
REF
FHREF()[( .)]=+
−×+
01
LOAD (A)
VCNTR
NO LOAD 1/2 LOAD FULL LOAD
VOLTAGE-POSITIONING WINDOW
VCNTR +
∆VOUT/2
VCNTR -
∆VOUT/2
Figure 7. Defining the Voltage-Positioning Window
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 21
Protection
The MAX5060 includes a power-good generator
(PGOOD) for undervoltage protection (UVP), and a
reverse current-limit protection; the MAX5060/MAX5061
include a hiccup current-limit protection to prevent dam-
age to the powered electronic circuits. Additionally, the
MAX5060 includes output overvoltage protection (OVP).
PGOOD Generator (MAX5060)
A PGOOD comparator compares the differential ampli-
fier output (DIFF) against 0.90 times the set output volt-
age for undervoltage monitoring (see Figure 8). Use a
10kΩpullup resistor from PGOOD to a voltage source
less than or equal to VCC.
Current Limit
The VEA output is clamped to 930mV with respect to the
common-mode voltage (VCM). Average current-mode
control has the ability to limit the average current sourced
by the converter during a fault condition. When a fault
condition occurs, the VEA output clamps to 930mV with
respect to the common-mode voltage (0.6V) to limit the
maximum current sourced by the converter to ILIMIT =
26.9mV/RS.
The hiccup current limit overrides the average current
limit. The MAX5060/MAX5061 include hiccup current-
limit protection to reduce the power dissipation during
a fault condition. The hiccup current-limit circuit derives
inductor current information from the output of the cur-
rent amplifier. This signal is compared against one half
of VCLAMP(EA). With no resistor connected from the LIM
pin to ground, the hiccup current limit is set at 90% of
the full-load average current limit. Use REXT to increase
the hiccup current limit from 90% to 100% of the full-
load average limit (see Figures 1 and 2). The hiccup
current limit can be disabled by connecting LIM to
SGND. In this case, the circuit will follow the average
current-limit action during overload conditions.
An internal clamp (MAX5060) limits the continuous
reverse current the buck converter sinks when a higher
voltage is applied at the output. The reverse current limit
translated at the current-amplifier input is -2.3mV (typ).
The maximum reverse current the converter sinks
depends on the current-sense resistor. Normally it is
about 10% of the full load current.
Overvoltage Protection (OVP) (MAX5060)
The OVP comparator compares the OVI input to the over-
voltage threshold. The overvoltage threshold is typically
+12.7% above the internal 0.6V reference voltage. A
detected overvoltage event latches the comparator output
forcing the power stage into the OVP state. In the OVP
state, the high-side MOSFET turns off and the low-side
MOSFET latches on. Connect DIFF to OVI for differential
output sensing and overvoltage protection. Alternately,
use a separate sensing network from VOUT to SGND.
Connect OVI to the center tap of a resistor-divider from
VOUT to SGND. In this case, the center tap is compared
against 1.276V. Add an RC delay to reduce the sensitivity
of the overvoltage circuit and avoid nuisance tripping of
the converter (Figure 9). Disable the overvoltage function
by connecting OVI to SGND.
VCM
0.9 x VREF
PGOOD
DIFF
MAX5060
Figure 8. PGOOD Generator
RA
OVI
DIFF
MAX5060
EAN
RF
RIN
EAOUT
Figure 9. Overvoltage Protection Input Delay
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
22 ______________________________________________________________________________________
Parallel Operation
For applications requiring large output current, parallel
two or more MAX5060s (multiphase operation) to
increase the available output current. The paralleled
converters operate at the same switching frequency
but different phases keep the input capacitor ripple
RMS currents to a minimum. The MAX5060 provides
the clock output (CLKOUT), which is 180° out-of-phase
with respect to DH. For the MAX5061, the out-of-phase
clock can be easily generated using a simple inverter
and driving it from the LX node. Use CLKOUT to drive
the second DC-DC converter to double the effective
switching frequency and reduce the input capacitor
ripple current (see Figure 10).
To drive multiple converters out-of-phase, use a delay
circuit to set 90° of phase shift (4 paralleled converters),
or 60° of phase shift (6 converters in parallel). Designate
one converter as master and the remaining converters
as slaves. Connect the master and slave controllers in a
daisy-chain configuration as shown in Figure 11.
Choose the appropriate phase shift for minimum ripple
currents at the input and output capacitors. The master
controller senses the output differential voltage through
SENSE+ and SENSE- and generates the DIFF voltage.
Disable the voltage sensing of the slaved controllers by
leaving DIFF unconnected (floating). Figure 11 shows a
typical application circuit using four MAX5060s. This cir-
cuit provides two phases at a 12V input voltage and a
0.6V to 5V output voltage range.
VIN
VIN
CSP
DH
LX
DL
RT/SYNC
PGND SGND CLKOUT
CSN
SENSE-
EAOUT
SENSE+
MAX5060
VIN
VOUT
CSP
DH
LX
DL
PGND SGND
CSN
LOAD
RT/SYNC
MAX5060
DIFF
EAN
IN
EAOUT
DIFF
EAN
IN
Figure 10. Parallel Configuration of MAX5060
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 23
VIN
VIN
CSP
DH
LX
DL
RT/SYNC
PGND SGND CLKOUT
CSN
SENSE-
EAOUT
SENSE+
MAX5060
VIN
VOUT
CSP
DH
LX
DL
CSN
LOAD
RT/SYNC
MAX5060
DIFF
EAN
IN
VIN
CSP
DH
LX
DL
PGND SGND
CSN
EAOUT
MAX5060
DIFF
EAN
IN
RT/SYNC
EAOUT
DIFF
EAN
IN
90° PHASE DELAY
CIRCUIT
PGND SGND CLKOUT
VIN
CSP
DH
LX
DL
PGND SGND
CSN
EAOUT
MAX5060
DIFF
EAN
IN
RT/SYNC
90° PHASE DELAY
CIRCUIT
Figure 11. Parallel Configuration of Multiple MAX5060s
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
24 ______________________________________________________________________________________
Applications Information
Inductor Selection
The switching frequency, peak inductor current, and
allowable ripple at the output determine the value and
size of the inductor. Selecting higher switching frequen-
cies reduces the inductance requirement, but at the
cost of lower efficiency. The charge/discharge cycle of
the gate and drain capacitances in the switching
MOSFETs create switching losses. The situation wors-
ens at higher input voltages, since switching losses are
proportional to the square of the input voltage. The
MAX5060 can operate up to 1.5MHz, however for VIN >
+12V, use lower switching frequencies to limit the
switching losses.
Use the following equation to determine the minimum
inductance value:
Choose ∆ILequal to approximately 40% of the output
current. Since ∆ILaffects the output-ripple voltage, the
inductance value may need minor adjustment after
choosing the output capacitors. Higher values reduce
the output ripple, but at the cost of degraded transient
response. Lower values have higher output ripple but
better transient response. Also, lower inductor values
correspond to smaller magnetics.
Choose inductors from the standard high-current, surface-
mount inductor series available from various manufac-
turers. Particular applications may require custom-
made inductors. Use high-frequency core material for
custom inductors. High ∆ILcauses large peak-to-peak
flux excursion, which increases the core losses at higher
frequencies. The high-frequency operation coupled with
high ∆ILreduces the required minimum inductance and
even makes the use of planar inductors possible. The
advantages of using planar magnetics include low-profile
design, excellent current-sharing between modules due
to the tight control of parasitics, and low cost.
For example, calculate the minimum inductance at
VIN(MAX) = 13.2V, VOUT = 1.8V, ∆IL= 8A, and fSW =
330kHz:
The average-current-mode control feature of the
MAX5060/MAX5061 limits the maximum peak inductor
current and prevents the inductor from saturating. Choose
an inductor with a saturating current greater than the
worst-case peak inductor current. The hiccup current-limit
circuit is masked during startup to avoid unintentional
hiccup when large output capacitors are used.
Use the following equation to determine the worst-case
inductor current:
where RSis the sense resistor and VCL = 0.0282V.
Switching MOSFETs
When choosing a MOSFET for voltage regulators, con-
sider the total gate charge, RDS(ON), power dissipation,
and package thermal impedance. The product of the
MOSFET gate charge and on-resistance is a figure of
merit, with a lower number signifying better perfor-
mance. Choose MOSFETs optimized for high-frequen-
cy switching applications.
The average current from the MAX5060/MAX5061 gate-
drive output is proportional to the total capacitance it
drives at DH and DL. The power dissipated in the
MAX5060/MAX5061 is proportional to the input voltage
and the average drive current. See the IN, VCC, and
VDD section to determine the maximum total gate
charge allowed from the combined driver outputs.
The gate charge and drain capacitance (CV2) loss, the
cross-conduction loss in the upper MOSFET due to finite
rise/fall time, and the I2R loss due to RMS current in the
MOSFET RDS(ON) account for the total losses in the
MOSFET. Estimate the power loss (PDMOS_) caused by
the high-side and low-side MOSFETs using the following
equations:
where QG, RDS(ON), tR, and tFare the upper-switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively.
PD Q V f
VI ttf RI
MOS HI G DD SW
IN OUT R F SW DS ON RMS HI
−=××
()
+
××+
()
×
+×
()
−
.()
414 2
LV
R
I
LPEAK CL
S
L
=+ ∆
2
LkH
MIN =
()
×
××
=
−
.. .
. .
13 2 1 8 1 8
13 2 330 8 06µ
LVVV
VfI
MIN INMAX OUT OUT
INMAX SW L
=
()
×
××
−
∆
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 25
where D = VOUT/VIN, IDC = (IOUT - ∆IL/2) and IPK =
(IOUT + ∆IL/2).
where COSS is the MOSFET drain-to-source capaci-
tance.
For example, from the typical specifications in the
Applications Information section with VOUT = 1.8V, the
high-side and low-side MOSFET RMS currents are 7.8A
and 18.5A, respectively for 20A. Ensure that the ther-
mal impedance of the MOSFET package keeps the
junction temperature at least +25°C below the absolute
maximum rating. Use the following equation to calcu-
late maximum junction temperature:
TJ= (PDMOS x θJA) + TA
where θJA and TAare the junction-to-ambient thermal
impedance and ambient temperature, respectively.
Input Capacitors
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input capac-
itor. The switching frequency, peak inductor current, and
the allowable peak-to-peak voltage ripple reflected back
to the source dictate the capacitance requirement.
Increasing switching frequency or paralleling multiple out-
of-phase converters lowers the peak-to-average current
ratio, yielding a lower input capacitance requirement for
the same load current.
The input ripple is comprised of ∆VQ(caused by the
capacitor discharge) and ∆VESR (caused by the ESR of
the capacitor). Use low-ESR ceramic capacitors with
high-ripple-current capability at the input. Assume the
contributions from the ESR and capacitor discharge are
equal to 30% and 70%, respectively. Calculate the input
capacitance and ESR required for a specified ripple
using the following equation:
where IOUT is the output current of the converter.
For example, at VOUT = 1.8V, the ESR and input capac-
itance are calculated for the input peak-to-peak ripple
of 100mV or less yielding an ESR and capacitance
value of 1.25mΩand 110µF.
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple volt-
age, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
In buck converter design, the output-current waveform
is continuous and this reduces peak-to-peak ripple cur-
rent in the output capacitor equal to the inductor ripple
current. Calculate the capacitance, the ESR of the out-
put capacitor, and the RMS ripple current rating of the
output capacitor based on the following equations.
where ∆VOESR and ∆VOQ are the output-ripple contri-
butions due to ESR and the discharge of output capaci-
tor, respectively.
In the dynamic load environment, the allowable devia-
tion of output voltage during the fast transient load dic-
tates the output capacitance and ESR. The output
capacitors supply the load step until the controller
responds with a greater duty cycle. The response time
(tRESPONSE) depends on the closed-loop bandwidth of
the converter. The resistive drop across the capacitor
ESR and capacitor discharge causes a voltage drop
during a step load. Use a combination of SP polymer
and ceramic capacitors for better transient load and
ripple/noise performance.
ESR V
I
CI
Vf
OUT OESR
L
OUT L
OQ SW
=
=××
∆
∆
∆
∆8
ESR V
II
CIDD
Vf
IN ESR
OUT L
IN OUT
QSW
=
()
+
=×
()
×
−
∆
∆
∆
2
1
PD Q V f
CVf RI
IIDCIPKII
D
MOS LO G DD SW
OSS IN SW DS ON RMS LO
RMS LO DC PK
−
−
=××
()
+
×××
+×
()
=++×
()
×
()
−
−
.
()
2
314
1
3
22
22
IIDCIPKI I D
RMS HI DC PK−=++×
()
× 22
3
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
26 ______________________________________________________________________________________
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
Current Limit
In addition to the average current limit, the
MAX5060/MAX5061 also have hiccup current limit. The
hiccup current limit is set to 10% below the average
current limit to ensure that the circuit goes in hiccup
mode during continuous output short circuit.
Connecting a resistor from LIM to ground increases the
hiccup current limit, while shorting LIM to ground dis-
ables the hiccup current-limit circuit.
Average Current Limit
The average-current-mode control technique of the
MAX5060/MAX5061 accurately limits the maximum out-
put current. The MAX5060/MAX5061 sense the voltage
across the sense resistor and limit the peak inductor
current (IL-PK) accordingly. The ON cycle terminates
when the current-sense voltage reaches 25.5mV (min).
Use the following equation to calculate the maximum
current-sense resistor value:
where PDRis the power dissipation in the sense resis-
tors. Select a 5% lower value of RSto compensate for
any parasitics associated with the PC board. Also,
select a non-inductive resistor with the appropriate
power rating.
Hiccup Current Limit
The hiccup current-limit value is always 10% lower than
the average current-limit threshold, when LIM is left
unconnected. Connect a resistor from LIM to SGND to
increase the hiccup current-limit value from 90% to
100% of the average current-limit value. The average
current-limit architecture accurately limits the average
output current to its current-limit threshold. If the hiccup
current limit is programmed to be equal or above the
average current-limit value, the output current will not
reach the point where the hiccup current limit can trig-
ger. Program the hiccup current limit at least 5% below
the average current limit to ensure that the hiccup cur-
rent-limit circuit triggers during overload. See the
Hiccup Current Limit vs. REXT graph in the Typical
Operating Characteristics.
Reverse Current Limit (MAX5060)
The MAX5060 limits the reverse current in case VBUS is
higher than the preset output voltage. Calculate the
maximum reverse current based on VCLR, the reverse-
current-limit threshold and the current-sense resistor.
where IREVERSE is the total reverse current sink into the
converter and VCLR = 2.3mV (typ).
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5060/MAX5061 use
an average current-mode control scheme to regulate
the output voltage (Figure 5). IPHASE is the inner aver-
age current loop. The VEA output provides the control-
ling voltage for this current source. The inner current
loop absorbs the inductor pole reducing the order of
the outer voltage loop to that of a single-pole system.
A resistive feedback network around the VEA provides
the best possible response, since there are no capaci-
tors to charge and discharge during large-signal excur-
sions. RFand RIN determine the VEA gain. Use the
following equation to calculate the value of RF:
where GCis the current-loop transconductance and RS
is the value of the sense resistor.
When designing the current-control loop ensure that
the inductor downslope (when it becomes an upslope
at the CEA output) does not exceed the ramp slope.
This is a necessary condition to avoid sub-harmonic
oscillations similar to those in peak current-mode con-
trol with insufficient slope compensation.
RIR
GV
GR
FOUT IN
COUT
CS
=×
×
=
.
∆
0 0289
IV
R
REVERSE CLR
S
=
RI
PD R
SOUT
RS
=
=×−
0 0255
075 10 3
.
.
ESR V
I
CIt
V
OUT ESR
STEP
OUT STEP RESPONSE
Q
=
=×
∆
∆
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 27
Use the following equation to calculate the resistor RCF:
CCF provides a low-frequency pole while RCF provides
a midband zero. Place a zero (fZ) to obtain a phase
bump at the crossover frequency. Place a high-fre-
quency pole (fP) at least a decade away from the
crossover frequency to reduce the influence of the
switching noise and achieve maximum phase margin.
Use the following equations to calculate CCF and CCFF:
Power Dissipation
The TQFN-28 and TSSOP-16 are thermally enhanced
packages and can dissipate about 2.7W and 1.7W,
respectively. The high-power packages make the high-
frequency, high-current buck converter possible to
operate from a 12V or 24V bus. Calculate power dissi-
pation in the MAX5060/MAX5061 as a product of the
input voltage and the total VCC regulator output current
(ICC). ICC includes quiescent current (IQ) and gate-
drive current (IDD):
PD= VIN x ICC
ICC = IQ+ [fSW x (QG1 + QG2)]
where QG1 and QG2 are the total gate charge of the
low-side and high-side external MOSFETs at VGATE =
5V, IQis estimated from the Supply Current (IQ)
vs. Frequency graph in the Typical Operating
Characteristics, and fSW is the switching frequency of
the converter.
Use the following equation to calculate the maximum
power dissipation (PDMAX) in the chip at a given ambi-
ent temperature (TA) :
MAX5060:
PDMAX = 34.5 x (150 - TA)..............mW
MAX5061:
PDMAX = 21.3 x (150 - TA)..............mW
PC Board Layout
Use the following guidelines to layout the switching
voltage regulator.
1) Place the IN, VCC, and VDD bypass capacitors
close to the MAX5060/MAX5061.
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative termi-
nal of the input filter capacitor.
6) Run the current-sense lines CSP and CSN very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
7) Avoid long traces between the VDD (MAX5060)/VCC
(MAX5061) bypass capacitors, driver output of the
MAX5060/MAX5061, MOSFET gates, and PGND.
Minimize the loop formed by the VCC bypass
capacitors, bootstrap diode, bootstrap capacitor,
MAX5060/MAX5061, and upper MOSFET gate.
8) Place the bank of output capacitors close to the load.
9) Distribute the power components evenly across the
board for proper heat dissipation.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
11) Use 4oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PC boards
can compromise efficiency since high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
CfR
CfR
CF ZCF
CFF PCF
=×× ×
=×× ×
1
2
1
2
π
π
RfL
VR
CF SW
OUT S
≤××
×
102
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
28 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 5654
PROCESS: BiCMOS
Pin Configurations
28
27
26
25
24
23
22
8
9
10
11
12
13
14
15
16
17
18
19
20
21
7
6
5
432
1
MAX5060
THIN QFN
TOP VIEW
N.C.
PGND
DL
BST
LX
DH
N.C.
VDD
VCC
IN
SGND
SENSE+
SENSE-
SGND
CSP
CSN
DIFF
EAN
EAOUT
CLP
EXPOSED PAD
OVI
LIM
V_IOUT
RT/SYNC
EN
PGOOD
CLKOUT
SGND
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN SGND
CSP
CSN
EAN
EAOUT
CLP
LIM
RT/SYNC/EN
MAX5061
TSSOP
VCC
PGND
LX
DL
BST
DH
N.C. EXPOSED PAD
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
______________________________________________________________________________________ 29
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45°
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
L
L
DETAIL B
L
L1
e
AAAAA
MARKING
I
1
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
L
e/2
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
30 ______________________________________________________________________________________
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
MAX.
EXPOSED PAD VARIATIONS
D2
NOM.MIN. MIN.
E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30
5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
DOWN
BONDS
ALLOWED
YES3.103.00 3.203.103.00 3.20T2055-3
3.103.00 3.203.103.00 3.20
T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.20
3.00 3.10T3255-3 3 3.203.00 3.10
3.203.00 3.10T3255-4 3 3.203.00 3.10
NO
NO
NO
NO
YES
YES
YES
YES
3.203.00T1655-3 3.10 3.00 3.10 3.20 NO
NO3.203.103.003.10T1655N-1 3.00 3.20
3.353.15T2055-5 3.25 3.15 3.25 3.35 YES
3.35
3.15
T2855N-1 3.25 3.15 3.25 3.35 NO
3.353.15T2855-8 3.25 3.15 3.25 3.35 YES
3.203.10T3255N-1 3.00 NO
3.203.103.00
L
0.40
0.40
**
**
**
**
**
**
**
**
**
**
**
**
**
**
SEE COMMON DIMENSIONS TABLE
±0.15
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
I
2
2
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
3.30T4055-1 3.20 3.40 3.20 3.30 3.40 ** YES
0.0500.02
0.600.40 0.50
10
-----
0.30
40
10
0.40 0.50
5.10
4.90 5.00
0.25 0.35 0.45
0.40 BSC.
0.15
4.90
0.250.20
5.00 5.10
0.20 REF.
0.70
MIN.
0.75 0.80
NOM.
40L 5x5
MAX.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
T1655-2 ** YES3.203.103.003.103.00 3.20
T3255-5 YES3.003.103.00 3.20 3.203.10 **
exceptions
MAX5060/MAX5061
0.6V to 5.5V Output, Parallelable,
Average-Current-Mode DC-DC Controllers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
©2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
E1
1
21-0108
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY,
EXPOSED PAD
XX XX
