N25Q128A11B1241F - Numonyx - Product.Network

Micron Technology, Inc., reserves the right to change products or specifications without notice.

February 2011 Rev 6 1/183

N25Q128

128-Mbit 3 V, multiple I/O, 4-Kbyte subsector erase on boot sectors,

XiP enabled, serial flash memory with 108 MHz SPI bus interface

Features

SPI-compatible serial bus interface

108 MHz (maximum) clock frequency

2.7 V to 3.6 V single supply voltage

Supports legacy SPI pr ot oc ol an d ne w Qu ad

I/O or Dual I/O SPI protocol

Quad/Dual I/O instructions resulting in an

equivalent clock frequency up to 432 MHz:

XIP mode for all three protocols

– Configurable via volatile or non-volatile

registers: enables XiP mode directly after

power on

Program/Erase suspend instructions

Continuous read (entir e memory) via single

instruction:

–Fast Read

– Quad or Dual Outp ut Fast Read

– Quad or Dual I/O Fast Read

Flexible to fit application:

– Configurable number of dummy cycles

– Output bu ffer configu ra b le

– Fast POR instruction: decrease power-on

time

– Reset function (upon customer request)

64-byte user-lockable, one-time programmable

(OTP) area

Erase capability

– Subsector (4-Kbyte) granularity in the 8

boot sectors (bottom or top parts)

– Sector (64-Kbyte) gr anularity

Write protections

– Software write prot ec tion ap plica b le to

every 64-Kbyte sector (volatile lock bit)

– Hardw ar e writ e pr ot ection: protected area

size defined by non-volatile bits (BP0, BP1,

BP2, BP3 and TB bit)

– Additional smart protections availa ble upon

custome r re qu es t

Electronic signature

– JEDEC standard two-byte signature

(BA18h)

– Additional 2 Extended Device ID (EDID)

bytes to identify device factory options

– Unique ID code (UID) with 14 bytes read-

only, available upon customer request

More than 100,000 program/erase cycles per

sector

More than 20 years data retention

Packages (all packages RoHS compliant)

– F8 = VDFPN8 8 x 6 mm (MLP8)

– 12 = TBGA24 6 x 8 mm

– F6 = VDFPN8 6 x 5 mm (MLP)

– SF = SO16 (300 mils body width)

– SE = SO8W (SO8 208 mils body width)

Contents N25Q128 - 3 V
2/183   
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1 Serial data output (DQ1)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
2 Serial data input (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
3 Serial Clock (C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
5 Hold (HOLD) or Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
6 Write protect/enhanced program supply voltage (W/VPP), DQ2  . . . . . . .  18
7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
SPI Modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1 Extended SPI protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
2 Dual I/O SPI (DIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
3 Quad SPI (QIO-SPI) protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
Operating features   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1 Extended SPI Protocol Operating features  . . . . . . . . . . . . . . . . . . . . . . .  23
1.1 Read Operations  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2 Page programming   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.3 Dual input fast program  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4 Dual Input Extended Fast Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 Quad Input Fast Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6 Quad Input Extended Fast Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.7 Subsector erase, sector erase and bulk erase  . . . . . . . . . . . . . . . . . . . 24
1.8 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . 24
1.9 Active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 25
1.10 Hold (or Reset) condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2 Dual SPI (DIO-SPI) Protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  27
2.1 Multiple Read Identification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

N25Q128 - 3 V Contents
3/183  
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
2.2 Dual Command Fast reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Page programming   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4 Subsector Erase, Sector Erase and Bulk Erase  . . . . . . . . . . . . . . . . . . 28
2.5 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 28
2.6 Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7 Active Power and S tandby Power modes  . . . . . . . . . . . . . . . . . . . . . . . 28
2.8 HOLD (or Reset) condition   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 Quad SPI (QIO-SPI)Protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
3.1 Multiple Read Identification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Quad Command Fast reading  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 QUAD Command Page programming  . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Subsector Erase, Sector Erase and Bulk Erase  . . . . . . . . . . . . . . . . . . 30
3.5 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . 30
3.6 Read and Modify registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.7 Active Power and S tandby Power modes  . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 HOLD (or Reset) condition   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.9 VPP pin Enhanced Supply Voltage feature  . . . . . . . . . . . . . . . . . . . . . . 31
Volatile and Non Volatile Registers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1 Legacy SPI Status Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  34
1.1 WIP bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2 WEL bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3 BP3, BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.4 TB bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.5 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2 Non Volatile Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  36
2.1 Dummy clock cycles NV configuration bit s (NVCR bits from 15 to 12)  . 37
2.2 XIP NV configuration bits (NVCR bits from 11 to 9) . . . . . . . . . . . . . . . . 38
2.3 Output Driver Strength NV configuration bits (NVCR bits from 8 to 6) . . 38
2.4 Fast POR NV configuration bit (NVCR bit 5)  . . . . . . . . . . . . . . . . . . . . . 38
2.5 Hold (Reset) disable NV configuration bit (NVCR bit 4)   . . . . . . . . . . . . 38
2.6 Quad Input NV configuration bit (NVCR bit 3)  . . . . . . . . . . . . . . . . . . . . 39
2.7 Dual Input NV configuration bit (NVCR bit 2) . . . . . . . . . . . . . . . . . . . . . 39
3 Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  40
3.1 Dummy clock cycle: VCR bits 7 to 4  . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2 XIP Volatile Configuration bits (VCR bit 3) . . . . . . . . . . . . . . . . . . . . . . . 42
4 Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . .  42

Contents N25Q128 - 3 V
4/183   
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
4.1 Quad Input Command VECR<7>   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2 Dual Input Command VECR<6>  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 Reset/Hold disable VECR<4>  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4 Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3> . . . 44
4.5 Output Driver Strength VECR<2:0> . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5 Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
5.1 P/E Controller Status bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2 Erase Suspend Status bit   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3 Erase Status bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4 Program Status bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.5 VPP Status bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.6 Program Suspend Status bit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.7 Protection S tatus bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Protection modes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1 SPI Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  49
2 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . . .  49
Memory organization  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1 Extended SPI Instructions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  77
1.1 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
1.2 Read Data Bytes (READ)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
1.3 Read Data Bytes at Higher Speed (FAST_READ)   . . . . . . . . . . . . . . . . 82
1.4 Dual Output Fast Read (DOFR)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
1.5 Dual I/O Fast Read  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
1.6 Quad Output Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
1.7 Quad I/O Fast Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
1.8 Read OTP (ROTP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1.9 Write Enable (WREN)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
1.10 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
1.11 Page Program (PP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
1.12 Dual Input Fast Program (DIFP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
1.13 Dual Input Extended Fast Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.14 Quad Input Fast Program   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.15 Quad Input Extended Fast Program  . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

N25Q128 - 3 V Contents
5/183  
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
1.16 Program OTP instruction (POTP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
1.17 Subsector Erase (SSE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
1.18 Sector Erase (SE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
1.19 Bulk Erase (BE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
1.20 Program/Erase Suspend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
1.21 Program/Erase Resume  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
1.22 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
1.23 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
1.24 Read Lock Register (RDLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
1.25 Write to Lock Register (WRLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
1.26 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
1.27 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
1.28 Read NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
1.29 Write NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
1.30 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 109
1.31 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 110
1.32 Read Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 111
1.33 Write Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 111
2 DIO-SPI Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
2.1 Multiple I/O Read Identification protocol  . . . . . . . . . . . . . . . . . . . . . . . 114
2.2 Dual Command Fast Read (DCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
2.3 Read OTP (ROTP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.4 Write Enable (WREN)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
2.5 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
2.6 Dual Command Page Program (DCPP)   . . . . . . . . . . . . . . . . . . . . . . . 117
2.7 Program OTP instruction (POTP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.8 Subsector Erase (SSE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
2.9 Sector Erase (SE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
2.10 Bulk Erase (BE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.11 Program/Erase Suspend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
2.12 Program/Erase Resume   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
2.13 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.14 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
2.15 Read Lock Register (RDLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.16 Write to Lock Register (WRLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
2.17 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
2.18 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Contents N25Q128 - 3 V
6/183   
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
2.19 Read NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
2.20 Write NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.21 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 127
2.22 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 128
2.23 Read Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 129
2.24 Write Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 129
3 QIO-SPI Instructions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  130
3.1 Multiple I/O Read Identification (MIORDID) . . . . . . . . . . . . . . . . . . . . . 132
3.2 Quad Command Fast Read (QCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.3 Read OTP (ROTP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.4 Write Enable (WREN)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.5 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.6 Quad Command Page Program (QCPP) . . . . . . . . . . . . . . . . . . . . . . . 137
3.7 Program OTP instruction (POTP)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.8 Subsector Erase (SSE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3.9 Sector Erase (SE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.10 Bulk Erase (BE)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.11 Program/Erase Suspend  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.12 Program/Erase Resume   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3.13 Read Status Register (RDSR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
3.14 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
3.15 Read Lock Register (RDLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
3.16 Write to Lock Register (WRLR)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
3.17 Read Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
3.18 Clear Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
3.19 Read NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
3.20 Write NV Configuration Register  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
3.21 Read Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.22 Write Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . 153
3.23 Read Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 154
3.24 Write Volatile Enhanced Configuration Register  . . . . . . . . . . . . . . . . . 155
XIP Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
1 Enter XIP mode by setting the Non Volatile Configuration Register . . . .  158
2 Enter XIP mode by setting the Volatile Configuration Register  . . . . . . .  160
3 XIP mode hold and exit  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  161
4 XIP Memory reset after a controller reset . . . . . . . . . . . . . . . . . . . . . . . .  162

N25Q128 - 3 V Contents

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11 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

11.1 Fast POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

11.2 Rescue sequence in case of power loss during WRNVCR . . . . . . . . . . 165

12 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

13 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

14 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

15 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

16 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

List of tables N25Q128 - 3 V
8/183   
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3. Non-Volatile Con fig ur at ion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4. Maximum allowed  frequency (MHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5. Volatile Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 6. Volatile Enhanced Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7. Flag Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 8. Software protection truth table (Sectors 0 to 255, 64 Kbyte granularity)  . . . . . . . . . . . . . . 50
Table 9. Protected area sizes, Upper (TB bit = 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Protected area sizes, Lower (TB bit = 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. Memory orga n ization (uniform ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 12. Memory organization (bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 13. Memory organization (top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 14. Instruction set: extended SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 15. Read Identification data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 16. Extended Device ID table (first byte)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 17. Suspend Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 18. Operations Allowed / Disallowed During Device States . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 19. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 20. Lock Register out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 21. Lock Register in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 22. Instruction set: DIO-SPI protocol  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 23. Instruction set: QIO-SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 24. NVCR XIP bits setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 25. VCR XIP bits setting example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 26. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 27. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 28. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 29. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 30. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 31. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 32. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 33. Reset Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 34. VDFPN8 (MLP8) Very thin Dual Flat Package No lead,
8 × 6 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 35. VDFPN8 (MLP8) Very thin pitch Dual Flat Package No lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data. . . . . . 176
Table 37. SO8 wide – 8 lead plastic small outline, 208 mils body width,
package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 38. TBGA 6x8 mm 24-ball package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 39. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 40. Valid Order Information Line Items. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 41. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

N25Q128 - 3 V List of figures
9/183  
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2. VDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. SO16 connections  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. BGA connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. Extended SPI protocol example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8. Non Volatile and Volatile configuration Register Scheme  . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. Read identification instruction and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 11. Read Data Bytes instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence  . . . . . . . . . . . . . . . 83
Figure 13. Dual Output Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 14. Dual I/O Fast Read instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 15. Quad Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 16. Quad Input/ Output Fast Read instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 17. Read OTP instruction and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 18. Write Enable instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 19. Write Disable instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 20. Page Program instruction  sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 21. Dual Input Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 22. Dual Input Extended Fast Program instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 23. Quad Input Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 24. Quad Input Extended Fast Program instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 25. Program OTP instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 26. How to permanently lock the OTP bytes  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 27. Subsector Erase instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 28. Sector Erase instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 29. Bulk Erase instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Figure 30. Read Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 31. Write Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 32. Read Lock Register instruction and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 33. Write to Lock Register instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 34. Read Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 35. Clear Flag Status Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 36. Read NV Configuration Register instruction sequence  . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 37. Write NV Configuration Register instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 38. Read Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 39. Write Volatile Configuration Register instruction sequence . . . . . . . . . . . . . . . . . . . . . . . 111
Figure 40. Read Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 111
Figure 41. Write Volatile Enhanced Configuration Register instruction sequence. . . . . . . . . . . . . . . 112
Figure 42. Multiple I/O Read Identification instruction and data-out sequence DIO-SPI . . . . . . . . . . 115
Figure 43. Dual Command Fast Read instruction and data- out sequence DIO-SPI . . . . . . . . . . . . . 115
Figure 44. Read OTP instruction and data-out sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 45. Write Enable instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 46. Write Disable instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 47. Dual Command Page Progra m instruction sequence DIO-SPI, 02h  . . . . . . . . . . . . . . . . 118
Figure 48. Dual Command Page Progra m instruction sequence DIO-SPI, A2h . . . . . . . . . . . . . . . . 118

List of figures N25Q128 - 3 V
10/183   
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
Figure 49. Dual Command Page Progra m instruction sequence DIO-SPI, D2h . . . . . . . . . . . . . . . . 118
Figure 50. Program OTP instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 51. Subsector Erase instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 52. Sector Erase instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 53. Bulk Erase instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Figure 54. Program/Erase Suspend instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 55. Program/Erase Resume instruction sequence DIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 56. Read Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 57. Write Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 58. Read Lock Register instruction and data-out sequence DIO-SPI. . . . . . . . . . . . . . . . . . . 124
Figure 59. Write to Lock Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 60. Read Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 61. Clear Flag Status Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 62. Read NV Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . . . . 126
Figure 63. Write NV Configuration Register instruction sequence DIO-SPI  . . . . . . . . . . . . . . . . . . . 127
Figure 64. Read Volatile Conf igu ratio n Re gist er  instr uc tio n sequ en ce DIO-SPI . . . . . . . . . . . . . . . . 128
Figure 65. Write Volatile Configuration Register instruction sequence DIO-SPI . . . . . . . . . . . . . . . . 128
Figure 66. Read Volatile Enhanced Configuration Register instruction sequence DIO-SPI . . . . . . . 129
Figure 67. Write Volatile Enhanced Configuration Register instruction sequence DIO-SPI  . . . . . . . 130
Figure 68. Multiple I/O Read Identification instruction and data-out sequence QIO-SPI. . . . . . . . . . 133
Figure 69. Quad Command Fast Read instructio n and data-out sequence QIO-SPI, 0Bh . . . . . . . . 134
Figure 70. Quad Command Fast Read instructio n and data-out sequence QIO-SPI, 6Bh . . . . . . . . 134
Figure 71. Quad Command Fast Read instruction and data-out sequence QIO-SPI, EBh . . . . . . . . 135
Figure 72. Read OTP instruction and data-out sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 73. Write Enable instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 74. Write Disable instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 75. Quad Command Page Program instruction sequence QIO-SPI, 02h. . . . . . . . . . . . . . . . 138
Figure 76. Quad Command Page Program instruction sequence QIO-SPI, 12h. . . . . . . . . . . . . . . . 138
Figure 77. Quad Command Page Program instruction sequence QIO-SPI, 32h. . . . . . . . . . . . . . . . 139
Figure 78. Program OTP instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 79. Subsector Erase instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 80. Sector Erase instruction sequence QIO-SPI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 81. Bulk Erase instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Figure 82. Program/Erase Suspe nd instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 83. Program/Erase Resume instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 84. Read Status Register instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 85. Write Status Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Figure 86. Read Lock Register instruction and data-out sequence QIO-SPI  . . . . . . . . . . . . . . . . . . 147
Figure 87. Write to Lock Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 88. Read Flag Status Register instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 89. Clear Flag Status Register instruction sequence QIO-SPI. . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 90. Read NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 151
Figure 91. Write NV Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . . . . 152
Figure 92. Read Volatile Conf igu ratio n Re gist er  instr uc tio n sequ en ce QIO-SPI. . . . . . . . . . . . . . . . 153
Figure 93. Write Volatile Configuration Register instruction sequence QIO-SPI . . . . . . . . . . . . . . . . 154
Figure 94. Read Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 155
Figure 95. Write Volatile Enhanced Configuration Register instruction sequence QIO-SPI . . . . . . . 156
Figure 96. N25Q128 Read functionality Flow Chart  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 97. XIP mode directly after power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 98. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example). . . . . . . . . . . . . . . . . . . 161
Figure 99. Power-up timing, Fast POR selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 100. Power-up timing, Fast POR not selected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

N25Q128 - 3 V List of figures

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Figure 101. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Figure 102. Reset AC waveforms while a program or erase cycle is in progress . . . . . . . . . . . . . . . . 170

Figure 103. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Figure 104. Write protect setup and hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 172

Figure 105. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

Figure 106. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 107. VPPH timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

Figure 108. VDFPN8 (MLP8) Very thin Dual Flat Package No lead,

8 × 6 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

Figure 109. VDFPN8 (MLP8) Very thin pitch Dual Flat Package No lead,

6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Figure 110. SO16 wide - 16-lead plastic small outline, 300 mils body width, package outline . . . . . . 176

Figure 111. SO8W – 8 lead plastic small outline, 208 mils body width, package outline. . . . . . . . . . . 177

Figure 112. TBGA - 6 x 8 mm, 24-ball, mechanical package outline. . . . . . . . . . . . . . . . . . . . . . . . . . 178

Description N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

1 Description

The N25Q128 is a 128 Mbit ( 16Mb x 8) serial Flash memory, with advanced write protecti on

mechanisms. It is accessed by a high speed SPI-compatible bus and features the possibility

to work in XIP (“eXecutio n in Plac e” ) mo d e.

The N25Q128 support s inn ovative, high-perform ance quad/du al I/O instructions, th ese new

instructions allow to double or quadruple the transfer bandwidth for read and program

operations.

Furthermore the memory can be operated with 3 different protocols:

Standard SPI (Extended SPI protocol)

Dual I/O SPI

Quad I/O SPI

The S tandard SPI protocol is enriched by the new quad and dual instructions (Extende d SPI

protocol). For Dual I/O SPI (DIO-SPI) all the instructions codes, the addresses and the data

are always transmitted across two data lines. For Quad I/O SPI (QIO-SPI) the instructions

codes, the addresses and the data are always transmitted across four data lines thus

enabling a tremendous improvement in both random access time and data throughput.

The memory can work in “XIP mode”, that means the device only requires the addresses

and not the instructions to output the data. This mode dramatically reduces random access

time thus enabling many applications requiring fast code execution without shadowing the

memory content on a RAM.

The XIP mode can be used with QIO-SPI, DIO-SPI, or Extended SPI prot ocol , an d can be

entered and exited using different dedicated instructions to allow maximum flexibility: for

applications required to enter in XIP mode right after power up of the device, th is can be set

as default mode by using dedicated Non Volatile Register (NVR) bits.

It is also possible to reduce the power on sequence time with the Fast POR (Power on

Reset) feature, enabling a reduction of the latency time before the first read instruction can

be performed. Another feature is the ability to pause and resume program and erase cycles

by using dedicated Program/Erase Suspend and Resume instructions.

The N25Q128 memory offers the following additional Features to be configured by using the

Non V olatile Configuration Register (NVCR) for default /Non- V ola tile settings or by using the

Volatile and Volatile Enhanced Configuration Registers for Volatile settings:

the number of dummy cycles for fast read instructions (single, dual and, quad I/O)

according to the operating frequency

the output buffer impedance

the type of SPI protocol (extended SPI, DIO-SPI or QIO-SPI)

the required XIP mode

Fast or standard POR sequence

the Hold (Reset) functionality enabling/disabling

The memory is organized as 248 (64-Kb yte ) main sectors, in products with Bottom or Top

architecture there are 8 64 -Kbyte boot sectors, and each boot sector is further divided into

16 4-Kbyte subsectors (128 subsectors in total). The boot sectors can be erased a 4-Kbyte

subsector at a time or as a 64 -Kbyte sector at a time. The entire memor y can be also erased

at a time or by sector.

N25Q128 - 3 V Description

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

The memory can be write protected by software using a mix of volatile and non-volatile

protection features, depending on the application needs. The protection granularity is of 64-

Kbyte (sector granularity) for volatile protections.

The N25Q128 has 64 one-time- programmable bytes (OTP bytes) that can be read and

programmed using two dedicated instructions, Read OTP (ROTP) and Program OTP

(POTP), respectively. These 64 bytes can be permanently locked by a particular Program

OTP (POTP) sequence. Once they ha ve been locke d, they become read-only a nd this st ate

cannot be reversed.

Many dif ferent N25Q128 configurations are available, please refer to the ordering scheme

page for the possibilities. Additional features are available as security options (The Security

features are described in a dedicated Application Note). Please contact your nearest

Numonyx Sales office for more information.

Figure 1. Logic diagram

Note: Reset functionality is available in devices with a dedicated part number. See Section 16:

Ordering information.

Logic_Diagram_x25x

VCC

HOLD/DQ3

VSS

DQ1

DQ0

W/VPP/DQ2

Table 1. Signal names

Signal Description I/O

C Serial Clock Input

DQ0 Serial Data input I/O(1)

DQ1 Serial Data output I/O(2)

SChip Select Input

W/VPP/DQ2 Write Protect/Enhanced Program supply voltage/additional data I/O I/O(3)

HOLD/DQ3(4) Hold (Reset function available upon customer request)/additional da ta I/O I/O(3)

VCC Supply voltage –

VSS Ground –

1. Provides dual and quad I/O for Extended SPI protocol instructions, dual I/O for Dual I/O SPI protocol instructions, and

quad I/O for Quad I/O SPI protocol instructions.

2. Provides dual and quad instruction input for Extended SPI protocol, dual instruction input for Dual I/O SPI protocol, and

quad instruction input for Quad I/O SPI protocol.

3. Provides quad I/O for Extended SPI protocol instructions, and quad I/O for Quad I/O SPI protocol instructions.

4. Reset functionality available with a dedicated part number. See Section 16: Ordering information.

Description N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Note: There is an exposed central pad on the underside of the VDFPN8 package. This is pulled,

internally, to VSS, and must not be connected to any other voltage or signal line on the PCB.

Figure 2. VDFPN8 connections

1. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering

information.

Figure 3. SO16 connections

1. DU = don’t use.

2. See Package mechanical section for package dimensions, and how to identify pin-1.

3. Reset functionality available in devices with a dedicated part number. See Section 16: Ordering

information.

AI13720c

5DQ0VSS C

DQ1

SVCC

HOLD/DQ3

W/V

/DQ2

AI13721c

DU DU

VCC DUDU

DQ1 VSS

DQ0

W/VPP/DQ2

HOLD/DQ3

N25Q128 - 3 V Description

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 4. BGA connections

1. NC = No Connect.

2. See Figure 112.: TBGA - 6 x 8 mm, 24-ball, mechanical package outline.

1 2 3 4 5

DQ1

DQ0

NC NC NC NC

NC NC NC NC NC

NCNC

HOLD/DQ3

W/V

/DQ2

Signal descriptions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

2 Signal descriptions

2.1 Serial data output (DQ1)

This output signal is used to transfer data serially out of the device. Data are shifted out on

the falling edge of Serial Clock (C). When used as an Input, It is latched on the rising edge

of the Serial Clock (C).

In the Extended SPI protocol, during the Quad and Dual Input Fast Pr ogram (QIFP, DIFP)

instructions and during the Quad and Dual Input Extended Fast Program (QIEFP, DIEFP)

instructions, pin DQ1 is used also as an input.

In the Dual I/O SPI protocol (DIO-SPI) the DQ1 pin always acts as an input/output.

In the Quad I/O SPI protocol (QIO-SPI) the DQ1 pin always acts as an input/output, with the

exception of the Program or Erase cycle performed with the Enhanced Program Supply

Voltage (VPP). In this case the device temporarily goes in Extended SPI protocol. The

protocol then becomes QIO-SPI as soon as the VPP pin voltage goes low.

2.2 Serial data input (DQ0)

This input signal is used to transfer data serially into th e device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C). Data are shifted out on the falling edge of the Serial Clock (C).

In the Extended SPI protocol, during the Quad and Dual Output Fast Read (QOFR, DOFR)

and the Quad and Dual Input/Output Fast Read (QIOFR, DIOFR) instructions, pin DQ0 is

also used as an input/output.

In the DIO-SPI protocol the DQ0 pin always act s as an input/output.

In the QIO-SPI protocol, the DQ0 pin always acts as an input/output, with the exception of

the Program or Erase cycle perfor med with the VPP. In this case the device temporarily

goes in Extended SPI protocol. Then, the protocol returns to QIO-SPI as soon as the VPP

pin voltage goes low.

2.3 Serial Clock (C)

This input signal provides the timing for the serial interface. Instructions, addresses, or data

present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data

are shifted out on the falling edge of the Serial Clock (C).

2.4 Chip Select (S)

When this input signal is high, the device is deselected and serial data output (DQ1) is at

high impedance. Unless an internal program, erase or write status register cycle is in

progress, the device will be in the standby power mode (this is not the deep power-down

mode). Driving Chip Select (S) low enables the device, placing it in the active power mode.

After power-up, a falling edge on Chip Select (S) is required prior to the start of any

instruction.

N25Q128 - 3 V Signal descriptions

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2.5 Hold (HOLD) or Reset (Reset)

The Hold (HOLD) signal is used to p ause any serial commun ications with the de vice without

deselecting the de vice .

Reset functionality is present instead of Hold in devices with a dedicated part number. See

Section 16: Ordering information.

During Hold condition, the Serial Data output (DQ1) is in high impedance, and Serial Data

input (DQ0) and Serial Clock (C) are Don't Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

For devices featuring Rese t instead of Hol d functionality, the Reset (Reset) input provides a

hardware reset for the memory.

When Reset (Reset) is driven High, the memory is in the normal operating mode. When

Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output

is high impedance.

Driving Reset (Reset) Low while an internal operation is in progress will affect this operation

(write, program or erase cycle) and data may be lost.

In the Extended SPI protocol, during the QOFR, QIOFR, QIFP and the Quad Extended Fast

Program (QIEFP) instructions, the Hold (Reset) / DQ3 is used as an input/output (DQ3

functionality).

In QIO-SPI, the Hold (Reset) / DQ3 pin acts as an I/O (DQ3 functionality), and the HOLD

(Reset) functionality d isabled when the device is selected. When the device is deselected (S

signal is high), in parts with Reset functionality, it is possible to reset the device unless this

functionality is not disabled by mean of dedicated registers bits.

The HOLD (R eset) functionalit y can be disabled using bit 3 of the NVCR or bit 4 of the VECR.

Signal descriptions N25Q128 - 3 V

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2.6 Write protect/enhanced program supply voltage (W/VPP),

DQ2

W/VPP/DQ2 can be use d as :

A protection con tr ol inp ut.

A power supply pin.

I/O in Extended SPI prot oco l qu ad instruc tio ns and in QIO-SPI protoc ol inst ru ctio n s.

When the device is operated in Extended SPI protocol with single or dual instructions, the

two functions W or VPP are selected by the voltage range applied to the pin. If the W/VPP

input is kept in a low voltage range (0 V to VCC) the pin is seen as a control input. This input

signal is used to freeze the size of the area of memory that is protected against program or

erase instructions (as specified by the values in the BP[0:3] bits of the Status Reg ister. (See

Table 2.: Status register format).

If VPP is in the range of VPPH, it acts as an additional power supply during the Program or

Erase cycles (See Table 28.: Operating conditions). In this case VPP must be stable until

the Program or Erase algorithm is completed.

During the Extended SPI protocol, the QOFR and QIOFR instructions, and the QIO-SPI

protocol instru ctio n s , the pi n W /VPP/DQ2 is used as an input/output (DQ2 functionality).

Using the Extended SPI prot oc ol the QIF P, QIEFP and the QIO-SPI Program/Er a se

instructions, it is still possible to use the VPP additional power supply to speed up internal

operations. However, to enable this possibility it is necessary to set bit 3 of the Volatile

Enhanced Configuration Register to 0.

In this case the W/VPP/DQ2 pin is used as an I/O pin until the end of the instruction

sequence. After the last input data is shifted in, the application should apply VPP voltage to

W/VPP/DQ2 within 200 ms to speed up the internal operations. If the VPP voltage is not

applied within 200 ms the Program/Erase operations start with sta ndard speed.

The default value of the VECR bit 3 is 1, and the VPP functionality for Quad I/O modify

instruction is disabled.

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

N25Q128 - 3 V SPI Modes

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3 SPI Modes

These devices can be driven by a micro controller with it s SPI per ipher al runnin g in either of

the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 5, is the clock polarity when the

bus master is in standby mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0)

C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. Bus master and memory devices on the SPI bus

Shown here is an example of three devices working in Extended SPI protocol for simplicity

connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one

device drives the serial data output (DQ1) line at a time; the other devices are high

impedance. Resistors R ensures that the N25Q128 is not selected if the bus master leaves

the S line in the high impedanc e state. As the bu s ma ster m ay en te r a state where all

inputs/ou tputs are in high impedance at the same time (for example, wh en the bus master is

reset), the clock line (C) must be connected to an external pull-down resistor so that, when

all inputs/ou tputs become high impeda nce, the S line is pulled High while the C line is pulled

Low . This ensures that S and C do not become High at the sam e time, and so that the t SHCH

requirement is met. The typical value of R is 100 kΩ, assuming that the time constant R*Cp

AI13725b

SPI Bus Master

SPI memory

device

SDO

SDI

SCK

DQ1DQ0

SPI memory

device

DQ1 DQ0

SPI memory

device

DQ1DQ0

CS3 CS2 CS1

SPI interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD HOLD WHOLD

RRR

VCC

VCC VCC VCC

VSS

VSS VSS VSS

SPI Modes N25Q128 - 3 V

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(Cp = parasitic capacitance of the bus line) is shorter than the time during which the bus

master leaves the SPI bus in high impedance.

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus

master never leaves the SPI bus in the high impedance state for a time period shorter than

5 µs. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as

appropriate.

Figure 6. Extended SPI protocol example

AI1373

MSB

CPHA

DQ0

CPOL

DQ1

MSB

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4 SPI Protocols

The N25Q128 memory can work with 3 different Serial protocols:

Extended SPI protocol.

Dual I/O SPI (DIO-SPI) protocol.

Quad I/O SPI (QIO-SPI) protocol.

It is possible to choose among the three protocols by means of user volatile or non-volatile

configuration bits.It's not possible to mix Extended SPI, DIO-SPI, and QIO-SPI protocols.

The device can operate in XIP mode in all 3 protocols.

4.1 Extended SPI protocol

This is an extension of the standard (legacy) SPI protocol. Instructions are transmitted on a

single data line (DQ0), while addresses and data are transmitted by one, two or four data

lines (DQ0, DQ1, W/VPP(DQ2) and HOLD / (DQ3) according to the instruction.

When used in the Extended SPI pr otoco l, these devices can be driven by a micro controller

in either of the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

Please refer to the SPI modes for a detailed description of these two modes

4.2 Dual I/O SPI (DIO-SPI) protocol

Dual I/O SPI (DIO-SPI) protocol: instructions, addresses and I/O data are always

transmitted on two data lines (DQ0 and DQ1).

Also when in DIO-SPI mode, the device can be driven by a micro controller in either of the

two following modes:

CPOL= 0, CPHA= 0

CPOL= 1, CPHA= 1

Please refer to the SPI modes for a detailed description of these two modes.

Note: Extended SPI protocol Dual I/O instructions allow only address and data to be transmitted

over two data lines. Howeve r, DIO-SPI allows instructions, addresses, and data to be

transmitted on two data lines.

This mode can be set us in g tw o way s

Volatile: by setting bit 6 of the VECR to 0. The device enters DIO-SPI protocol

immediately after the Write Enhanced Volatile Configuration Register sequence

completes. The device returns to the default working mode (defined by NVCR) on

power on.

Default/ Non-Volatile: This is default mode on power-up. By setting bit 2 of the NVCR

to 0. The device enters DIO-SPI protocol on the subsequ ent power-on. After all

subsequent power-on sequences, the device still starts in DIO-SPI protocol unless bit 2

of NVCR is set to 1 (default value, corresponding to Extended SPI protocol) or bit 3 of

NVCR is set to 0 (corresponding to QIO-SPI protocol).

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4.3 Quad SPI (QIO-SPI) protocol

Quad SPI (QIO-SPI) protocol: instructions, addresses, and I/O data are always transmitted

on four data lines DQ0, DQ1, W/VPP(DQ2), and HOLD / (DQ3).

The exception is the Pr ogram/Erase cycle performed with the VPP, in which ca se the device

temporarily goes to Extended SPI protocol. Going temporarily into Extended SPI protocol

allows the application either to:

check the polling bits: WIP bit in the Status Register or Program/Erase Controller bit in

the Flag Status Register

perform Progr am /Er as e su sp en d fu nc tion s.

Note: As soon as the VPP pin voltage goes low, the protocol returns to the QIO-SPI protocol.

In QIO-SPI protocol the W and HOLD/ (RESET) functionality is disabled when the device is

selected (S signal low).

When used in the QIO-SPI mode, these devices can be driven by a micro controller in either

of the two following modes:

CPOL=0, CPHA=0

CPOL=1, CPHA=1

Please refer to the SPI modes for a detailed description of the 2 modes.

Note: In the Extended SPI protocol on ly Addr ess and dat a a re allowed to be tran smitted on 4 dat a

lines, However in QIO-SPI protocol, the address, data and instructions are transm itted

across 4 data lines.

This working mode is set in either bit 7 of the Volatile Enhanced Configuration Register

(VECR) or in bit 3 of the Non Volatile Configuration Register (NVCR).

This mode can be set us in g tw o way s

Volatile: by setting bit 7 of the VECR to 0, the device enters QIO-SPI protocol

immediately after the Write Enhanced Volatile Configuration Register sequence

completes. The device returns to the default working protocol (d efined by the NVCR)

on the next powe r on .

Default/ Non- Volatile: This is default protocol on power up. By setting bit 3 of the

NVCR to 0, the device enters QIO-SPI protocol on the subsequent power-on. After all

subsequent power-on sequences, the device still starts in QIO-SPI protocol unless bit 3

of the NVCR is set to 1 (default value, corresponding to Extended SPI mode).

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5 Operating features

5.1 Extended SPI Protocol Operating features

5.1.1 Read Operations

To read the memory content in Extended SPI protocol different instructions are available:

READ, Fast Read, Dual Output Fast Read, Dua l Input O utput Fast Read , Quad Outp ut Fast

Read and Quad Input Output Fast read, allowing the application to choose a n instruction to

send addresses and receive data by one, two or four data lines.

Note: In the Extended SPI protocol the instruction code is always sent on one data line (DQ0): to

use two or four data lines the user must use either the DIO-SPI or the QIO-SPI protocol

respectively.

For fast read instructions the number of dummy clock cycles is configurable by using VCR

bits [7:4] or NVCR bits [15:12].

After a successful reading instruction a reduced tSHSL equal to 20 ns is allowed to further

improve random access time (in all the other cases tSHSL should be at least 50 ns). See

Table 32.: AC Characteristics.

5.1.2 Page programming

To prog ram one data byte, two instructions are required: write enab le (WREN), which is one

byte, and a page program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal program cycle (of duration tPP).

To spread this overhead, the p age program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from ‘1’ to ‘0’), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the page program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several page

program (PP) sequences with each containing only a few bytes (see Section 5.2.3 : Page

programming and Table 32: AC Characteristics).

5.1.3 Dual input fast program

The dual input fast pr ogram (DIFP) instr uction makes it possible to pr ogram up to 256 bytes

using two input pins at the same time (by changing bits from ‘1’ to ‘0’).

For optimized timings, it is recommended to use the DIFP instr uc tio n to pr og r am all

consecutive ta rgeted bytes in a single seque nce rather using several DIFP seq uences each

containing only a few bytes (see Section 9.1.12: Dual Input Fast Program (DIFP)).

5.1.4 Dual Input Extended Fast Program

The Dual Input Extended Fast Program (DIEFP) instruction is an enhanced version of the

Dual Input Fast Program instruction, allowing to transmit address across two data lines.

For optimized timings, it is recommended to use the DIEFP instruction to program all

consecutive ta rgeted bytes in a single sequence rather than using several DIEFP

sequences, each containing only a few bytes.

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5.1.5 Quad Input Fast Program

The Quad Input Fast Program (QIFP) instruction makes it possible to program up to 256

bytes using 4 input pins at the same time (by changing bi ts from 1 to 0).

For optimized timings, it is recommended to use the QIFP instruction to program all

consecutive t a rg eted bytes in a sing le se qu enc e r ather than using several QIFP sequ ences

each containing only a few bytes.

5.1.6 Quad Input Extended Fast Program

The Quad Input Extended Fast Program (QIEFP) instruction is an enhanced version of the

Quad Input Fast Program instruction, allowing parallel input on the 4 input pins, including

the address being sent to the device.

For optimized timings, it is recommended to use the QIEFP instruction to program all

consecutive t argeted bytes in a single sequence rather than using several QIEFP

sequences each containing only a few bytes.

5.1.7 Subsector erase, sector erase and bulk erase

The page program (PP) instruction allows bits to be reset from ‘1’ to’0’. In order to do this the

bytes of memory need to be erased to all 1s (FFh).

This can be achieved a s follo ws:

a subsector at a time, using the subsector erase (SSE) instruction (only available on

the 8 boot sectors at the bottom or top addressable area of a device with a dedicated

part number); See Section 16: Ordering information;

a sector at a time, using the sector erase (SE) instruction;

throughout the en tir e mem or y, using the bulk er as e (BE) instr uc tion .

This starts an internal erase cycle (of dur a tion tSSE, tSE or tBE). The erase instruction must

be preceded by a write enable (WREN) instruction.

5.1.8 Polling during a write, program or erase cycle

A further improvement in the time to Write Status Register (WRSR), POTP, PP,

DIFP,DIEFP,QIFP, QIEFP or Erase (SSE, SE or BE) can be achieved by not waiting for the

worst case delay (tW, tPP, tSSE, tSE, or tBE). The application program can monitor if the

required internal operation is completed, by polling the dedicated register bits to establish

when the previous Write, Program or Erase cycle is complete.

The information on the m emo ry being in p rogr ess for a Pro gram, Erase, or Write instruction

can be checked either on the Write In Progress (WIP) bit of the Status Register or in the

Program/Erase Controller bit of the Flag Status Register.

Note: The Prog ram /Er ase Controller bit is the oppo site state of the WIP bit in the Status Register.

In the Flag Status Register additional information can be checked, as eventual

Program/Erase failures by mean of the Program or erase Error bits.

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5.1.9 Active power and standby power modes

When Chip Select (S) is Low, the device is selected, and in the active power mode.

When Chip Select (S) is High, the device is deselected, but could remain in the active power

mode until all internal cycles have completed (program, erase, write status register). The

device then goes in to the standby power mode. The device consumption drops to ICC1.

5.1.10 Hold (or Reset) condition

The Hold (HOLD) signal is used to pause serial communications with the device without

resetting the clocking sequence. However, taking this signal Low does not terminate any

write status register, program or erase cycle that is currently in progress.

To enter the hold condition, the device must be selected, with Chip Select (S) Low.

The hold condition starts on the falling edge of the Hold (HOLD) signal, provided that the

Serial Clock (C) is Low (as shown in Figure 7).

The hold condition ends on the rising edge of the Hold (HOLD) signal, provided that the

Serial Clock (C) is Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes

Low (this is shown in Figure 7).

During the hold condition, the serial data output (DQ1) is high impedance, and serial data

input (DQ0) and Serial Clock (C) are don’t care.

Normally, the device is kept selected, with Chip Select (S) driven Low for the whole duration

of the hold con dition. This is to ensure tha t the st ate of th e internal logic remains unchanged

from the moment of entering the hold condition.

If Chip Select (S) goes High while the device is in the Hold con dition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the hold condition.

Figure 7. Hold condition activation

Reset functionality is available instead of Hold in parts with a dedicated part number. See

Section 16: Ordering information.

Driving Reset (Reset) Low while an internal operation is in progress will affect this operation

(write, program or erase cycle) and data may be lost. On Reset going Low , the device enters

AI02029D

HOLD

Hold

condition

(standard use)

Hold

condition

(non-standard use)

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the reset mode and a time of tRHSL is then requ ired before the device can be reselected by

driving Chip Select (S) Low. For the value of tRHSL, see Table 32.: AC Characteristics. All

the lock bits are reset to 0 af ter a Reset Low pulse.

The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O

(DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP.

The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.

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5.2 Dual SPI (DIO-SPI) Protocol

In the Dual SPI (DIO-SPI) protocol all the instructions, addresses and I/O data are

transmitted on two data lines. All the functionality available in the Extended SPI protocol is

also available in the DIO-SPI protocol. The DIO-SPI instructions are comparable with the

Extended SPI instructions; however, in DIO-SPI, the instructions are multiplexed on the two

data lines, DQ0 and DQ1.

The only exceptions are the READ, Quad Read, and Program instructions, which are not

available in DIO-SPI protocol, and the RDID instruction, which is replaced in the DIO-SPI

protocol by the Multiple I/O Read Identification (MIORDID) instruction.

The Multiple I/O Read Identification Instruction reads just the standard SPI electronic ID (3

bytes), while the Exte n ded SPI pr ot oc ol R DID instruction allows access to the UID bytes.

To help the application code port from Extended SPI to DIO-SPI protocol, the instructions

available in the DIO-SPI protocol have the same operation code as the Extended SPI

protocol, the only exception being th e MI ORDID instructio n .

5.2.1 Multiple Read Identification

The Multiple I/O Read Identification (MIORDID) instruction is available to read the device

electronic ID.With respect to the RDID instruction of the Extended SPI protocol, the output

data, shifted out on the 2 data lines DQ0 and DQ1.

Since the read ID instruction in the DIO-SPI protocol is limited to 3 bytes of the standard

electronic ID, the UID bytes are not read with the MIORDID instruction

5.2.2 Dual Command Fast reading

Reading the memory data multiplexing the instruction, the addresses and the output dat a on

2 data lines ca n be achieved in DIO-SPI prot ocol by mean of the Dual Comma nd Fast Read

instruction, that has 3 instruction codes (BBh, 3Bh and 0Bh) to help the application code

porting from Extended SPI protocol to DIO-SPI protocol. Of course quad and single I/O

Read instructions are not available in DIO-SPI mode.

For Dual Command fast read instructions the number of dummy clock cycles is configurable

by using VCR bits [7:4] or NVCR bits [15:12].

After a successful reading instruction, a reduced tSHSL equal to 20ns is allowed to further

improve random access time (in all the other cases tSHSL should be at least 50 ns). See

Table 32.: AC Characteristics.

5.2.3 Page programming

Programming the me mor y by tr an sm itting the instruction, addresses and the output data on

2 data lines can be achieved in DIO-SPI protocol by using the Dual Command Page

Program instruction, that has 3 instruction codes (D2h, A2h and 02h) to help port from

Extended SPI protocol to DIO-SPI protocol

Quad and single input Program instructions are not availa ble in DIO-SPI mode.

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The DIO-SPI protocol is similar to the Extended SPI protocol i.e., to program one data byte

two instructions are required:

Write Enable (WREN), which is one byte, and a

Dual Command Page Program (DCPP) sequence, which consists of four bytes plus

data.

This is followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Dual Command Page Program (DCPP) instruction allows up to

256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are

consecutive addresses on the same page of memory.

For optimized timings, it is recommended to use the DCPP instruction to program all

consecutive targeted bytes in a single sequence versus using several DCPP sequences

with each containing only a few bytes. See Table 32.: AC Characteristics.

5.2.4 Subsector Erase, Sector Erase and Bulk Erase

Similar to the Extended SPI protocol, in the DIO-SPI protocol to erase the memory bytes to

all 1s (FFh) the Subsector Erase (SSE), the Sector Erase (SE) and the Bulk Erase (BE)

instructions are availabl e. These instructio ns sta rt an internal Erase cycle (of d uration tSSE,

tSE or tBE).

The Erase inst ru ctio n mus t be preceded by a Write Enable (WRE N) ins tru ct ion .

Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in

uniform architecture parts

5.2.5 Polling during a Write, Program or Erase cycle

Similar to the Extended SPI protocol, in the DIO-SPI protocol it is possible to monitor if the

internal write, program or erase operation is completed, by polling the dedicated register bit s

by using the Read Status Register (RDSR) or Read Flag Status Register (RFSR)

instructions, the only obvious difference is that instruction codes, addresses and output data

are transmitted across two data lines.

5.2.6 Read and Modify registers

Similar to the Extended SPI protocol, the only obvious difference is that instruction codes,

addresses and output data are transmitted across two data lines

5.2.7 Active Power and Standby Power modes

Similar to the Extended SPI protocol, when Chip Select (S) is Low, the device is selected,

and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but

could remain in the Active Power mode until all internal cycles have completed (Program,

Erase, Write Cycles). The device then goes in to the Standby Power mode. The device

consumption drops to ICC1.

5.2.8 HOLD (or Reset) condition

The HOLD (or Reset i.e. for parts having the reset functionality instead of hold pin) signal

has exactly the same behavior in DIO-SPI protocol as do in Extended SPI protocol, so

please refer to section 5.1.10, Hold (or Reset) condition” in the Extend SPI protocol section

for further details.

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5.3 Quad SPI (QIO-SPI)Protocol

In the Quad SPI (QIO-SPI) protocol all the Instructions, addresses and I/O data are

transmitted on four data lines, with the exception of the polling instructions performed during

a Program or Erase cycle performed with VPP, in this case the device temporarily goes in

Extended SPI protocol. The protocol again becomes QIO-SPI as soon as the VPP voltage

goes low.

All the functionality availabl e in the Exte nded SPI pr otocol are also a vailable in th e QIO-SPI

mode, with equivalent instruction transmitte d on the 4 data lines DQ0, DQ1, DQ2 and DQ3.

The exceptions are th e READ, Dual Re ad and Dual Program instructions, that are not

available in QIO-SPI protocol, and the RDID instruction, that is replaced in the QIO-SPI

protocol by the Multiple I/O Read Identification (MIORDID) instruction. The Multiple I/O

Read Instructi on reads just the st andard SPI e lectronic ID (3 bytes) , while with the Extended

SPI protocol RDID instruction is possible to access also the UID bytes.

To help the application code port from Extended SPI to QIO-SPI protocol, the instructions

available in the QIO-SPI protocol have the same operation code as in the Extended SPI

protocol, the only exception is the MIORDID instruction.

5.3.1 Multiple Read Identification

The Multiple I/O Read Identification (MIORDID) instruction is available to read the device

electron ic ID. With respect to the RDID instruction of the Extended SPI protocol, the output

data, shifted out on the 4 data lines DQ0, DQ1, DQ2 and DQ3.

Since in the QIO-SPI protocol the Read ID instruction is limited to 3 bytes of the standard

electronic ID, the UID bytes are not read with the MIORDID instruction.

5.3.2 Quad Command Fast reading

The Array Data can be read by the Quad Command Fast Read instruction using 3

instructions (EBh, 6Bh and 0Bh) to help the application code port from Extended SPI

protocol to DIO-SPI protocol. The instruction, address and output data are transmitted

across 4 data lines.

The Dual and Single I/O Read instructions are not available in QIO-SPI protocol.

5.3.3 QUAD Command Page programming

The memory can be programmed in QIO-SPI protocol by the Quad Command Page

Program instruction using (02h, 12h and 32h). The instruction, address and input data are

transmitted across 4 data lines

The Dual and Single I/O Program instructions are not available in QIO-SPI protocol

Programming the me mory by multiplexing the instruction, the ad dresses and the output dat a

on 4 wires can be achieved in QIO-SPI protocol by mean of the Quad Command Page

Program instruction, that has 3 instruction codes (02h, 12h and 32h) to help the application

code porting from Extended SPI protocol to QIO-SPI protocol.

Similar to the Extended SPI protocol in th e QIO- SPI pr otocol, to progr am one data byte two

instructions are required:

Write Enable (WREN), which is one byte, and

Quad Command Page Program (QCPP) sequence, which consists of instruction (one

byte), address (3 bytes) and input data.

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This is followed by the internal Program cycle (of duration tPP).

To spread this overhead, the Quad Command Page Program (QCPP) instruction allows up

to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they are

in consecutive ad dr es se s on the sa me page of memo ry.

For optimized timings, it is recommended to use the QCPP instruction to program all

consecutive targeted bytes in a single sequence versus using several QCPP sequences

with each containing only a few bytes. See Table 32.: AC Characteristics.

The QCPP instruction is transmitted across 4 data lines except when VPP is raised to

VPPH.

The VPP can be raised to VPPH to decrease programming time (provided that the bit 3 of

the VECR has been set to 0 in advance). When bit 3 of VECR is set to 0 after the Quad

Command Page Program instruction sequence has been received, the memory temporarily

goes in Extended SPI protocol, and is possible to perform polling instructions (checking the

WIP bit of the Status Register or the Program/Erase Controller bit of the Flag Status

functionality. The memory automatically comes back in QIO-SPI protocol as soon as the

VPP pin goes Low.

5.3.4 Subsector Erase, Sector Erase and Bulk Erase

Similar to the Extended SPI protocol, Subsector Erase (SSE)(1), the Sector Erase (SE) and

the Bulk Erase (BE) instructions are used to erase the memory in the QIO-SPI protocol.

These instructions start an internal Erase cycle (of duration tSSE, tSE or tBE).

The Erase inst ru ctio n mus t be preceded by a Write Enable (WRE N) ins tru ct ion .

The erase instructions are transmitted across 4 data lines unless the VPP is raised to

VPPH.

The VPP can be raised to VPPH to decrease erasing time, provided that the bit 3 of the

VECR has been set to 0 in advance. In this case, after the erase instruction sequence has

been received, the memory temporarily goes in extended SPI protocol, and it is possible to

perform polling instructions (checking the WIP bit of the Status Register or the

Program/Erase Controller bit of the Flag Status Register) or Program/Erase Suspend

instruction even if DQ2 is temporarily used in this VPP functionality. The memory

automatically comes back in QIO-SPI protocol as soon as the VPP pin goes Low.

Note: Subsector Erase is only available on the 8 Bottom (Top) boot sectors, and is not available in

uniform architecture parts

5.3.5 Polling during a Write, Program or Erase cycle

It is possible to check if the internal write, program or erase operation is completed, by

polling the dedicated register bits of the Read Status Register (RDSR) or Read Flag Status

When the Program or Erase cycle is performed with the VPP, the device temporarily goes in

single I/O SPI mode. The protocol became again QIO-SPI as soon as the VPP pin voltage

goes low.

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5.3.6 Read and Modify registers

The read and modify register instructions are available and behave in QIO-SPI protocol

exactly as they do in Extended SPI protocol, the only difference is that instruction codes,

addresses and output data are transmitted across 4 data lines.

5.3.7 Active Power and Standby Power modes

Exactly as in Extended SPI protocol, when Chip Select (S) is Low, the device is selected,

and in the Active Power mode. When Chip Select (S) is High, the device is deselected, but

could remain in the Active Power mode until all internal (Program, Erase, Write) Cycles

have completed. The device then goes in to the Standby Power mode. The device

consumption drops to ICC1.

5.3.8 HOLD (or Reset) condition

The HOLD (Hold) feature (or Reset feature, for parts having the reset functionality instead of

hold) is disabled in QIO- SPI protocol wh en the device is selected: the Hold (or Reset)/ DQ3

pin always behaves as an I/O pin (DQ3 function) when the device is deselected. For parts

with reset functionality, it is still possible to reset the memory when it is deselected (C signal

high).

5.3.9 VPP pin Enhanced Supply Voltage feature

It is possible in the QIO-SPI pr otocol to use th e VPP pin as an enhan ced supply volt age, but

the intention to use VPP as accelerated supply voltage must be declared by setting bit 3 of

the VECR to 0.

In this case, to accelerate the Program cycle the VPP pin must be raised to VPPH after the

device has received the last data to be programmed within 200ms. If the VPP is not raised

within 200ms, the program operation starts with the standard internal cycle speed as if the

Vpp high voltage were not used, and a flag error appears on Flag Status Register bit 3".

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6 Volatile and Non Volatile Registers

The device features many different registers to store, in volatile or non volatile mode, many

parameters and operating configurations:

Legacy SPI Status Register

3 configuration registers:

– Non Volatile Configuration Re gist er (NVCR), 16 bits

– Volatile Configuration Register (VCR), 8 bits

– Volatile Enhanced Configuration Register (VECR), 8 bits

The Non Volatile Configuration Register (NVCR) affects the memory configuration starting

from the successive power-on. It can be used to make the memo ry start in a determined

condition.

The VCR and VECR affect the memory configuration after every execution of the related

Write Volatile configuration Register (WRVCR) and Write Enhanced Volatile Configuration

at POR by NVCR.

As described in Figure 8.: Non Volatile and Volatile configuration Register Scheme, the

working condition of the memory is set by an internal configuration register, which is not

accessible by the us er. The working parameter s of the inte rn al co nf igu ra tio n register are

loaded from the NVCR during the boot phase of the device . In this sense the NVCR can be

seen as having the default settings of the memory.

During the normal life of the application, every time a write volatile or enhanced volatile

configuration register instr uction is performed, the new configur ation parameters set in the

volatile registers are also copied in the internal configu ration register, thus inst antly af fecting

the memory behavior. Please note that on the next power on the memory will start again in

the working protocol set by the Non Volatile Register parameters.

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Figure 8. Non Volatile and Volatile configuration Register Scheme

A Flag Status Register (FSR), 8 bits, is also available to check the status of the device,

detecting possible error s or a Program/Erase internal cycle in progress.

Each register can be read and modified by means of dedicated instructions in all the 3

protocols (Extended SPI, DIO-SPI, and QIO-SPI).

Reading time for all registers is compar able; writing time instead is very dif ferent: NVCR bits

are set as Flash Cell memory content requiring a lon ger time to perform internal writing

cycles. See Table 32.: AC Characteristics.

NVCR

( Non Vola tile Configur ati on Regi ster)

VCR (V olatil e Configura tion R egister )

and VECR ( Volat il e Enha nce d

C onf igurati on Regi ster )

iCR

(interna l Configurat ion Regis ter)

Device behaviour

during the power on phase Registers down load execut ed af ter

a WRVCR or WRVECR

instructi ons, it ov erwrit es NVCR

configurations on iCR

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6.1 Legacy SPI Status Register

The Status Register contains a number of status and control bits that can be read or set by

specific instructions: Read S t atus Register (RDSR) and Write Status Register (WRSR). This

is available in all the 3 protocols (Extended SPI, DIO-SPI, and QIO-SPI).

6.1.1 WIP bit

The Write In Progress (WIP) bit set to 1 indicates that the memory is busy with a Write

Status Register, Program or Erase cycle. 0 indicates no cycle is in progress.

6.1.2 WEL bit

The Write Ena ble Latch (WEL) bit set to 1 indicates that the internal Write Enable Latch is

set. When set to 0 the internal Write Enable Latch is reset and no Write Status Register,

Program or Erase instruction is accepted.

6.1.3 BP3, BP2, BP1, BP0 bits

The Block Protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the

area to be software protected against Program and Erase instructions. These bits are

written with the Write Status Register (WRSR) instruction. When one or more of the Block

Protect (BP3, BP2, BP1, BP0) bits is set to 1, the relevant memory area, as defined in Table

9.: Protected area sizes, Upper (TB bit = 0) and Table 10.: Protected area sizes, Lower (TB

bit = 1), becomes protected against all program and erase instructions. The Block Protect

(BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has

not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect

(BP3, BP2, BP1, BP0) bits are 0.

6.1.4 TB bit

The Top/Bottom (TB) bit is non-volatile. It can be set and reset with the Write Status Re gister

(WRSR) instruction provided that the Write Enable (WREN) instruction has been issued.

Table 2. Status register format

b7 b0

SRWD BP3 TB BP2 BP1 BP0 WEL WIP

Status register write protect

Top/bo ttom bit

Block protect bi ts

Write enable latch bit

Write in progress bit

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The Top/Bottom (TB) bit is used in conjunction with the Block Protect (BP3, BP2, BP1, BP0)

bits to de termine if the protected area defined by the Block Pr otect bits st art s from the top or

the bottom of the memory array:

When TB is reset to '0' (default value), the area protected by the Block Protect bits

starts from the top of the memory ar ray.

When TB is set to '1', the area protected by th e Block Protect bits start s from the bottom

of the memory array.

The TB bit cannot be written when the SRWD bit is set to '1' and the W pin is driven Low.

6.1.5 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjuncti on with the Write

Protect (W/VPP) signal. The S tatus Register W rite Disable (SRWD) bit and the Write Protect

(W/VPP) signal allow the device to be put in the hardware protected mode (when the Status

this mode, the non-volatile bits of the Status Register (TB, BP3, BP2, BP1, BP0) become

read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for

execution.

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6.2 Non Volatile Configuration Register

The Non Volatile Configuration Register bits determine the device memory co nfiguration

after power-on. This enables customization of the memory configuraiton to fit application

requirements.The device ship s from the factory with all bits erased to 1 (FFFFh). The Non

Volatile Configuration Register can be read and written in any of the three available SPI

protocols by the Read Non Volatile Configuration Register command and the Write Non

Volatile Configuration Register command respecitvely.

Table 3. Non-Volatile Configuration Register

Bit Parameter Value Description Note

NVCR<15:12> Dummy clock

cycles

0000 As '1111'

To optimize instruction execution

(FASTREAD, DOFR,DIOFR,QOFR,

QIOFR, ROTP) according to the frequency

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

1101 13

1110 14

1111

Target on maximum

allowed frequency fc

(108MHz) and to

guarantee backward

compatibility (default)

NVCR<11:9> XIP enabling

at POR

000 XIP for SIO Read

001 XIP for DOFR

010 XIP for DIOFR

011 XIP for QOFR

100 XIP for QIOFR

101 reserved

110 reserved

111 XIP disabled (default)

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6.2.1 Dummy clock cycles NV configuration bits (NVCR bits from 15 to 12)

The bits from 15 to 12 of the Non V o latile Configuration register store the default settings for

the dummy clock cycles number after the fast read instructions (in all the 3 available

protocols). The dummy clo ck cycles number can be set from 1 up to 15 as described here,

according to operating frequency (the higher is the operating frequency, the bigger must be

the dummy clock cycle number) to optimize the fast read instructions performance.

The default values of these bits allow the memory to be safely used with fast read

instructions at the maximum frequency (108 MHz). Please note that if the dummy clock

number is not sufficient for the operating fr equency, the memory reads wrong data.

Table 4. Maximum allowed frequency (MHz)

NVCR<8:6> Output Driver

Strength

000 reserved

Impedance at Vcc/2

001 90

010 60

011 45

100 reserved

101 20

110 15

111 30 (default)

NVCR<5> Fast POR x

READ

0 Enabled POR phase < 100us only read available

1 Disabled (default) POR phase ~ 700us all instructions

available

NVCR<4> Reset/Hold

disable 0 disabled Disable Pad Hold/Reset functionality

1 enabled (default)

NVCR<3> Quad Input

Command 0 enabled Enable command on four input lines

1 disabl e d (d efault)

NVCR<2> Dual Input

Command 0 enabled Enable command on two input lines

1 disabl e d (d efault)

NVCR<1:0> Reserved xx Don't care Default value = "11"

Table 3. Non-Volatile Configuration Register

Bit Parameter Value Description Note

Maximum allowed frequency (MHz)(1)

Dummy Clock FASTREAD DOFR DIOFR QOFR QIOFR

1 50 50394320

2 95 85595639

3 105 95 75 70 49

4 108 105 88 83 59

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6.2.2 XIP NV configuration bits (NVCR bits from 11 to 9)

The bits from 11 to 9 of the Non Volatile Configuration register store the default settings for

the XIP operation, allowing the memory to start working directly on the required XIP mode

afte r successive POR sequence: the device then accepts only address on one, two, or four

wires (skipping the instruction) depending on the NVCR XIP bits settings.

The default settings for the XIP bits of the NVCR enable the memory to start working in

Extended SPI mode after the POR sequence (XIP directly after POR is disabled).

6.2.3 Output Driver Strength NV configuration bits (NVCR bits from 8 to 6)

The bits from 8 to 6 of the Non Volatile Configuration register store th e default settings for

the output driver strength, enabling to optimize the impedance at Vcc/2 output voltage for

the specific application.

The default values of Output Driver Strength bits of the NVCR set the output impedance at

Vcc/2 equal to 30 Ohms .

6.2.4 Fast POR NV configuration bit (NVCR bit 5)

The bit 5 of the NVCR enables the FAST POR sequence to speed up the application boot

phase before the first READ instruction: if enabled, the F AST POR allows to perform th e first

read operation after less than 100us. Please note that this timing is valid only for the reading

operations: if a modify instruction is then required, after the first WREN instruction the

complete POR phase will be performed, resulting in latency time between the WREN and

the receiving of th e modify instruction (~500us). Duri ng this latency time, when the power on

second phase is running, no instruction will be accepted except the standard polling

instructions either on the Flag Status register or in the Status Register.

The default values of Fast POR bit of the NVCR is set to disable the Fast POR feature, in

this case the POR sequence requires the standard value of ~500us and after the first

WREN instruction no relevant latency time is needed.

6.2.5 Hold (Reset) disable NV configuration bit (NVCR bit 4)

The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the

Hold (Reset) / DQ3 pin as described in Table 3.: Non-Volatile Configuration Register. This

feature can be useful to avoid accidental Hold or Reset condition entries in ap plications that

never require the Hold (Reset) functionality.

The default values of Hold (Reset) bit of the NVCR is set to enable the Hold (Reset)

functionality.

5 108 108 94 94 69

6 108 108 105 105 78

7 108 108 108 108 86

8 108 108 108 108 95

9 108 108 108 108 105

10 108 108 108 108 108

1. All values are guaranteed by characterization and not 100% tested in production.

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Note: Reset functionality is available instead of Ho ld in devices with a dedicated part numb er. See

Section 16: Ordering information.

6.2.6 Quad Input NV configuration bit (NVCR bit 3)

N25Q product s ship from the factory with the Quad Input NV configuration bit set to 1. This

setting means the device ope rates in the Extend ed SPI protocol by defau lt. If this bit is reset

to 0, the device operates in the DIO-SPI protocol immediately after the next power on.

If both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the Non Volatile

Configuration Register set to 0), the memory will work in QIO-SPI.

The Quad Input NV configur ation bi t can be used to make the me mor y start working in QIO-

SPI protocol directly after the power on sequence. The products are delivered with this set

to 1, making the memory default in Extended SPI protocol, if the application set s this bit to 0

the device will enter in QIO-SPI protocol right after the next power on.

Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the

Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.

6.2.7 Dual Input NV configuration bit (NVCR bit 2)

N25Q products are delivered with the Dual Input NV configuration bit set to 1, which by

default causes the device to function in the Extended SPI protocol. If this bit is set to 0, the

device will operate in the DIO-SPI protocol immediately after the next power on.

Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the

Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.

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6.3 Volatile Configuration Register

The Volatile Configuration Register (VCR) affects the memory configuration after every

execution of Wr ite Volatile Configuration Register (WRVCR) instruction: this instruction

overwrite the memory configuration set at POR by the Non Volatile Configuration Re gis ter

(NVCR). Its purp ose is to define the dummy clock cycles number and to make the device

ready to enter in the required XIP mode.

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6.3.1 Dummy clock cycle: VCR bits 7 to 4

The bits from 7 to 4 of the Volatile Configuration Register, as the bits from 15 to 12 of the

Non-Volatile Configuration register, set the dummy clock cycles number after the fast read

instructions (in all the 3 available protocols). The dummy clock cycles number can be set

from 1 up to 15 as described in Table 5.: Volatile Configuration Register, according to

operating frequency (the higher is the operating frequency, the bigger must be the dummy

clock cycle number, according to Table 4.: Maximum allowed frequency (MHz)) to optimize

the fast read instructions performance.

Note: If the dummy clock number is not sufficient for the operating frequency, the memory reads

wrong data.

Table 5. Volatile Configuration Register

Bit Parameter Value Description Note

VCR<7:4> Dummy clock

cycles

0000 As '1111'

To optimize instruction execution

(FASTREAD, DOFR,DIOFR,QOFR,

QIOFR, ROTP) according to the frequency

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

1101 13

1110 14

1111

Target on maximum

allowed frequency fc

(108MHz) and to

guarantee backward

compatibility (default)

VCR<3> XIP

0 Ready to enter XIP mode To make the data on DQ0 during the first

dummy clock NOT “Don’t Care.” For

devices with feature set digit equal to 2 or 4

in the part number (Basic XiP), this bit is

always Don't Care"

1 XIP disabled (default)

VCR<2:0> Reserved xxx reserved Fixed value = 000b

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6.3.2 XIP Volatile Configuration bits (VCR bit 3)

The bit 3 of the Volatile Configuration Register is the XIP enabling bit, this bit must be set to

0 to enable the me mory working on XIP mode. For de vices with a featu re set digit equal to 2

or 4 in the part numb er (Basic XiP), this bit is always Don't Care, and it is possible to operate

the memory in XIP mode without setting it to 0. See Section 16: Ordering information.

6.4 Volatile Enhanced Configuration Register

The Volatile Enhanced Configuration Register (VECR) affects the memory configuration

after every execution of Write Volatile Enhanced Configuration Register (WRVECR)

instruction: this instruction overwrite the memory configuration set during the POR

sequence by the Non Volatile Configuration Register (NVCR). Its purpose is:

enabling of QIO-SPI protocol and DIO-SPI proto co l

Warning: WARNING: in case of both QIO-SPI and DIO-SPI enabled, the

memory works in QIO-SPI

HOLD (Reset) functionality disabling

To enable the VPP functionality in Quad I/O modify operations

To define output driver strength (3 bit)

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6.4.1 Quad Input Command VECR<7>

The Quad Input Command configuration bit can be used to mak e the memory start working

in QIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register

(WRVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI

protocol, If this bit is set to 0 the memory works in QIO-SPI protocol. If VECR bit 7 is set

back to 1 the memory st art working again in Extended SPI pr otocol, unless the bit 6 is set to

0 (in this case the memory start working in DIO-SPI mode).

Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7and bit 6 of the

VECR set to 0), the memory will work in QIO-SPI.

6.4.2 Dual Input Command VECR<6>

The Dual Input Command configuratio n bit can be used to make the memory start working

in DIO-SPI protocol directly after the Write Volatile Enhanced Configuration Register

(WVECR) instruction. The default value of this bit is 1, corresponding to Extended SPI

protocol, if this bit is set to 0 the memory works in DIO-SPI protocol (unless the Volatile

Enhanced Configuration Register bit 7 is also set to 0). If the Volatile Enhanced

Configuration Register bit 6 is set back to 1 the memory start working again in Extended SP I

protocol.

Table 6. Volatile Enhanced Configuration Register

Bit Parameter Value Description Note

VECR<7> Quad Input

Command 0 Enabled Enable command on four input lines

1 Disabled (default)

VECR<6> Dual Input

Command 0 Enabled Enable command on tw o input lines

1 Disabled (default)

VECR<5> Reserved x Reserved Fixed value = 0b

VECR<4> Reset/Hold

disable 0 Disabled Disable Pad Hold/Reset functionality

1 Enabled (default)

VECR<3>

Accelerator

pin enable in

QIO-SPI

protocol or in

QIFP/QIEFP

0 Enabled The bit must be considered in case of QIFP,

QIEFP, or QIO-SPI pr otocol. It is “Don’t

Care” otherwise.

1 Disabled (default)

VECR<2:0> Output Driver

Strength

000 reserved

Impedance at VCC/2

001 90

010 60

011 45

100 reserved

101 20

110 15

111 30 (default)

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Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 7 and bit 6 of the

VECR are set to 0), the memory will work in QIO-SPI.

6.4.3 Reset/Hold disable VECR<4>

The Hold (RESET) disable bit can be used to disable the Hold (Reset) functionality of the

Hold (Reset) / DQ3 pin right after the Write Volatile Enhanced Configuration Register

(WVECR) instruction. This feature can be useful to avoid accidental Hold or Reset condition

entries in applications that never require the Hold (Reset) functionality. If this bit is set to 0

the Hold (Reset) functionality is disabled, it is possible to enable it back by setting this bit to

Please note that after the next power on the Hold (Reset) functionality will be enabled again

unless the bit 4 of the Non Volatile Configuration Regis ter is set to 0.

Note: Reset functionality is available instead of Hold in devices with a de dicated part nu mber . See

Section 16: Ordering information.

6.4.4 Accelerator pin enable: QIO-SPI protocol / QIFP/QIEFP VECR<3>

The bit 3 of the Volatile Enhanced Configuration Register determine whether is possible or

not to use the Vpp acce lerating voltage to speed up internal modify operation with Quad

program and erase instructions (both in Extended or QIO-SPI protocols).

If we want to use the Vpp voltage with Quad I/O modify instructions, we must set previously

this bit to 0 (his default value is 1, in this case the Vpp pin functionality is disabled in all

Quad I/O operations: both in Extended SPI and QIO-SPI protocols).

If the Volatile Enhanced Configuration Register bit 3 is set to 0, using the QIO-SPI protocol,

afte r a Quad Command Page Program instruction or an Erase instruction is received (with

all input data in the Program case) and the memory is de-selected, the protocol temporarily

switches to Extended SPI protocol until Vpp passes from Vpph to normal I/O value (this

transition is mandatory to come back to QIO-SPI protocol), to enable the possibility to

perform polling instructions (to check if the internal modify cycle is finished by means of the

WIP bit of the Status Register or of the Program/Erase controller bit of the Flag Status

his Vpp functionality.

If the Volatile Enhanced Configuration Register bit 3 is set to 0, after any quad modify

instruction (both in Extende d SPI protocol and QIO-SPI protocol) ther e is a maximum

allowed time-out of 200ms after the last instruction input is re ceived and the memory is de-

selected to raise the Vpp signal to Vpph, otherwise the modify instruction start at normal

speed, without the Vpph enhancement, and a flag err or a ppear s on Fla g Status Register bit

6.4.5 Output Driver Strength VECR<2:0>

The bits from 2 to 0 of the VECR set the value of the output driver strength, enabling to

optimize the impedance at Vcc/2 output voltage for the specific application as described in

Table 6.: Volatile Enhanced Configuration Register.

The default values of Output Driver Strength is set by the dedicated bits of the Non Volatile

Configuration Re gis ter (N VCR ), th e parts are delivered with the output impedance at Vcc/2

equal to 30 Ohms.

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6.5 Flag Status Register

The Flag Status Register is a powerful tool to investigate the status of the device, checking

information regarding what is actually doing the memory and detecting possible error

conditions.

The Flag status register is composed by 8 bit.Three bits (Program/Erase Controller bit,

Erase Suspend bit and Program Suspend bit) are a “Status Indicator bit”, they are set and

reset automatically by the memory. Four bits (Erase error bit, Progr am error bit, VPP 1 to 0

error bit and Protection error bit) are “Error Indicators bits”, they are set by the memory

when some program or era se operation fails or the user tries to perform a forbid den

operation. The user can clear the Error Indi cators bits by mean of the Clear Flag Status

All the Flag Status Register bits can be read by mean of the Read Status Register (RFSR)

instruction.

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6.5.1 P/E Controller Status bit

The bit 7 of the Flag Status r egister represents the Program/Erase Controller Status bit, It

indicates whether there is a Progr am/Erase internal cycle active. When P/E Contro ller

Status bit is Low (FSR<7>=0) the device is busy; when the bit is High (FSR<7>=1) the

device is ready to process a new command.

This bit has the same meaning of Write In Progress (WIP) bit of the standard SPI Status

It's possible to make the polling instructions, to check if the internal modify operations are

finished, both on the Flag Statu s r egister bit 7 or on WIP bit of the Status Register.

6.5.2 Erase Suspend Status bit

The bit 6 of the Flag Status r egister represents the Erase Suspend Status bit, It indicates

that an Erase operation has been suspended or is going to be suspended.

The bit is set (FSR<6>=1) within the Erase Suspend Latency time, that is a s soon as the

Program/Erase Suspend command (PES) has been issued, therefore the device may still

complete the operation before ente ring the Suspend Mode.

The Erase Suspend Status should be considered valid when the P/E Controller bit is high

(FSR<7>=1).

When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit

returns Low (FSR<6>=0)

6.5.3 Erase Status bit

The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase

failure or a protection error when an erase operation is issued.

When the Erase Status bit is High (FSR<5>=1) after an Erase failure that means that the

P/E Controller has applied the maximum pulses number to the portion to be erased and still

failed to verify that it has correctly erased.

The Erase Status bit should be read once the P/E Controller Status bit is High.

Table 7. Flag Status Register

BIT Description Note

7 P/E Controller (not WIP) Status

6 Erase Suspend Status

5 Erase Error

4 Program Error

3 VPP Error

2 Program Suspend Status

1 Protection Error

0 RESERVED

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The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector

Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI).

Once the bit 5 is set High, it can only be reset Low (FSR<5>=0 ) by a Clear Flag Status

If set High it should be reset before a new Erase command is issued; otherwise the new

command will appear to fail.

6.5.4 Program Status bit

The bit 4 of the Flag Status Register represents the Program Status bit. It indicates:

a Program failure

an attempt to program a '1' on '0' when VPP=VPPH (only when the p attern is a multiple

of 64 bits, otherwise this bit is "Don't care").

a protection error when a program is issued

When the Program Status bit is High (FSR<4>=1) after a Program failure that means that

the P/E Controller has applied the maximum pulses number to the bytes and it still failed to

verify that the require d data have been correctly programmed.

After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if

VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4>

remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is

not a 64 bits multiple the bit 4 is Don't Care. The Prog ram S t atus bit sh ould be read on ce the

P/E Controller Status bit is High.

The Program Status bit is related to all possible program operations in the Extended SPI

protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input

Extended Fast Program, and OTP Program.

The Program Status bit is related to the following program operations in the DIO-SPI and

QIO-SPI protocols: Dual and Quad Command Page program and OTP pr ogram.

Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status

is issued, otherwise the new command will appear to fail.

6.5.5 VPP Status bit

The bit 3 of the Flag Status Register represents the VPP Status bit. It indicates an invalid

voltage on the VPP pin during Program and Erase operations. The VPP pin is sampled at

the beginning of a Program or Erase operation.

If VPP becomes invalid during an operation, that is the voltage on VPP pin is below the

VPPH Voltage (9V), the VPP Status bit goes High (FSR<3>=1) and indeterminate results

can occur.

Once set High, the VPP S t atus bit can only be reset Low (FSR<3>=0) by a Clear Flag S tatus

command is issued, otherwise the new command will appear to fail.

6.5.6 Program Suspend Status bit

The bit 2 of the Flag Status register represents the Program Suspend Status bit, It indi cates

that a Program operation has been suspended or is going to be suspended.

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The bit is set (FSR<2>=1) within the Erase Suspend Latency time, that is a s soon as the

Program/Erase Suspend command (PES) has been issued, therefore the device may still

complete the operation before ente ring the Suspend Mode.

The Program Su spend Sta tus should be considered valid when the P/E Contr oller bit is high

(FSR<7>=1).

When a Progra m/Erase Resume command (PER) is issued the Program Suspend Status bit

returns Low (FSR<2>=0)

6.5.7 Protection Status bit

The bit 1 of the Flag Status Register represe nts the Protection Status bit. It indicates th at an

Erase or Program operation has tried to modify the contents of a protected array sector, or

that a modify operation has tried to access to a locked OTP space. The Protection St atus bit

is related to all possible protection violations as follows:

The sector is protected by Software Protection Mode 1 (SPM1) Lock registers,

The sector is protected by Software Protection Mode 2 (SPM2) Block Protect Bits

(standard SPI Status Register),

An attempt to program OTP when locked,

A Write Status Register comman d (WRSR) on STD SPI Status Register when locke d by

the SRWD bit in conju nction with the Write Protect (W/VPP) signal (Hardware Protection

Mode).

Once set High, the Protection Status bit can on ly be r eset Low ( FSR<1 >=0) b y a Cle ar Fla g

Status Register command (CLFSR). If set High it should be reset before a new command is

issued, otherwise the new command will appear to fail.

N25Q128 - 3 V Protection modes

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7 Protection modes

There are protocol-related and specific hardware and software protection modes. They are

described below.

7.1 SPI Protocol-related protections

This applies to all three protocols. The environments where non-volatile memory devices

are used can be very no isy. No SPI device can operate correctly in the presence of

excessive noise. To help combat this, the N25Q128 features the following data protection

mechanisms:

Power On Reset and an internal timer (tDTW) can provide protection against

inadvertent changes while the power supply is outside the operating specification.

Program, Erase, and Write Status Register instructions are checked to ensure the

instruction includes a number of clock pulse s that is a multiple of a byte before they are

accepted for execution.

All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This b it is retur ned to its reset state

by the following events (in Extended SPI protocol mode):

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Write to Lock Register (WRLR) instruction completion

– Program OTP (POTP) instruction completion

– Page Prog ra m (PP) instr uc tion co mp le tion

– Dual Input Fast Program (DIFP) instruction completion

– Dual Input Extended Fast Program (DIEFP) instruction completion

– Quad Input Fast Program (QIFP) instruction completion

– Quad Input Extended Fast Program (QIEFP) instruction completion

– Subsector Erase (SSE) instruction completion

– Sector Erase (SE) instruction completion

– Bulk Erase (BE) instruction completion

– Write Non-Volatile Configuration Register (WRNVCR) instruction completion

This bit is also returned to its reset state after all the analogous events in DIO-SPI and QIO-

SPI protocol mode s.

7.2 Specific hardware and software protection

There are two sof tware protected modes, SPM1 and SPM2, that can be combined to protect

the memory array a s required. T he SPM2 can be locked by hard ware with the h elp of the W

input pin.

Protection modes N25Q128 - 3 V

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SPM1

The first software protected mode (SPM1) is managed by specific Lock Registers assigned

to each 64 Kbyte sector.

The Lock Registers can be read and written using the Read Lock Reg ister (RDLR) and

Write to Lock Register (WRLR) instructions.

In each Lock Register two bits control the protection of each sector: the Write Lock bit and

the Lock Down bit.

Write Lock bit: The W rite Lock bit determ ines whether the contents of the sector can be

modified (using the Progra m or Erase instructions). When the Write Lock bit is set to '1',

the sector is write protected - an y operations that attempt to change the data in the

sector will fail. When the Write Lock bit is reset to '0', the sector is not write protected by

the Lock Register, and may be modified.

Lock Down bit: The Lock Down bit provides a mechanism for protecting software data

from simple hacking and malicious attack. When the Lock Down bit is set to '1', further

modification to the Write Lock and Lock Down bits cannot be performed. A powerup is

required befo re changes to these bit s can be mad e. When the Lock Down bit is reset to

'0', the Write Lock and Lock Down bits can be changed.

The definition of th e Lock Register bits is given in Table 20.: Lock Registe r out.

SPM2

The second software protected mode (SPM2) uses the Block Protect bits (BP3, BP2, BP1,

BP0) and the Top/Bottom bit (TB bit) to allow part of the memory to be configured as read-

only. See Section 16: Ordering information.

As a second level of protection , the Write Protect signal (applied on the W/VPP pin) can

freeze the Status Register in a read-only mode. In this mode, the Block Protect bits (BP3,

BP2, BP1, BP0), the Top/Bottom (TB) bit, and the Status Register W rite Disable bit (SR WD)

are protec te d.

Table 8. Software protection truth table (Sectors 0 to 255, 64 Kbyte granularity)

Sector Lock Register Protection S tatus

Lock Down bit Write Lock bit

00Sector unprotected from Program/Erase operations, protection status

reversible.

0 1 Sector protected from Program/Erase operations, protection status reversible.

10Sector unprotected from Program/Erase operations.

Sector protection status cannot be changed except by a power-up.

11Sector protected from Program/Erase operations.

Sector protection status cannot be changed except by a power-up.

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Table 9. Protected area sizes, Upper (TB bit = 0)

Status Reg is t er Content Memory Content

TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

00000None All sectors (sectors 0 to 255)

00001Upper 256th

(1/2 Mbit, sector 255) Sectors 0 to 254

00010Upper 128th

(1 Mbit, 2 sectors: 254 to 255) Sectors 0 to 253

00011Upper 64th

(2 Mbit, 4 sectors: 252 to 255) Sectors 0 to 251

00100Upper 32nd

(4 Mbit, 8 sectors: 248 to 255) Sectors 0 to 247

00101Upper 16th

(8 Mbit, 16 sectors: 240 to 255) Sectors 0 to 239

00110Upper 8th

(16 Mbit, 32 sectors: 224 to 255) Sectors 0 to 223

00111Upper quarte r

(32 Mbit, 64 sectors: 193 to 255) Lo wer 3 quarters (sectors 0 to

191)

01000Upper half

(64 Mbit, 128 sectors: 128 to

255) Lower half (sectors 0 to 127)

01001All sectors

(128 Mbit, 256 sectors) None

01010All sectors

(128 Mbit, 256 sectors) None

01011All sectors

(128 Mbit, 256 sectors) None

01100All sectors

(128 Mbit, 256 sectors) None

01101All sectors

(128 Mbit, 256 sectors) None

01110All sectors

(128 Mbit, 256 sectors) None

01111All sectors

(128 Mbit, 256 sectors) None

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The N25Q128 is available in the following architecture versions:

Bottom version, 64 KB uniform sectors plus 8 bottom boot sectors (each with 16

subsectors),

Top version, 64 KB uniform sectors plus 8 top boot sectors (each with 16 subsectors)

Uniform version, 64 KB uniform sectors without any boot sectors and subsectors.

Table 10. Protected area sizes, Lower (TB bit = 1)

Status Reg is t er Content Memory Content

TB bit BP3 Bit PB2 Bit BP1 Bit BP0 Bit Protected Area Unprotected Area

10000None All sectors (sectors 0 to 255)

10001Lower 256th

(1/2 Mbit, sector 0) Sectors 1 to 255

10010Lower 128th

(1 Mbit, 2 sectors: 0 to 1) Sectors 2 to 255

10011Lower 64th

(2 Mbit, 4 sectors: 0 to 3) Sectors 4 to 255

10100Lower 32nd

(4 Mbit, 8 sectors: 0 to 7) Sectors 8 to 255

10101Lower 16th

(8 Mbit, 16 sectors: 0 to 15) Sectors 16 to 255

10110Lower 8th

(16 Mbit, 32 sectors: 0 to 31) Sectors 33 to 255

10111Lower quarter

(32 Mbit, 64 sectors: 0 to 63) Upper 3 quarters (sectors 64 to

255)

11000Lower half

(64 Mbit, 128 sectors: 0 to 127) Upper half (sectors 128 to 255)

11001All sectors

(128 Mbit, 256 sectors) None

11010All sectors

(128 Mbit, 256 sectors) None

11011All sectors

(128 Mbit, 256 sectors) None

11100All sectors

(128 Mbit, 256 sectors) None

11101All sectors

(128 Mbit, 256 sectors) None

11110All sectors

(128 Mbit, 256 sectors) None

11111All sectors

(128 Mbit, 256 sectors) None

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8 Memory organization

The memory is organized as:

16,777,216 bytes (8 bits each)

256 sectors (64 Kbytes each)

In Bottom and Top versions: 8 bottom (top) 64 Kbytes boot sectors with 16 subsectors

(4 Kbytes) and 248 standard 64 KB sectors

65,536 pages (256 bytes each)

64 OTP bytes located outside the main memory array

Each pag e can be individually programme d (bits are progra mmed from 1 to 0). The device is

Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable, Subsector

Erase is allowed on the 8 boot sectors (for devices with bottom or top architecture).

Figure 9. Block diagram

AI13722a

HOLD

W/VPP Control Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter

256 Byte

Data Buer

256 bytes (page size)

X Decoder

Y Decoder

Status

00000h

FFFFFFh

000FFh

64 OTP bytes

DQ1

DQ0

DQ3

DQ2

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Table 11. Memory organization (uniform) (page 1 of 8)

Sector Address range

255 FF0000 FFFFFF

254 FE0000 FEFFFF

253 FD0000 FDFFFF

252 FC0000 FCFFFF

251 FB0000 FBFFFF

250 FA0000 FAFFFF

249 F90000 F9FFFF

248 F80000 F8FFFF

247 F70000 F7FFFF

246 F60000 F6FFFF

245 F50000 F5FFFF

244 F40000 F4FFFF

243 F30000 F3FFFF

242 F20000 F2FFFF

241 F10000 F1FFFF

240 F00000 F0FFFF

239 EF0000 EFFFFF

238 EE0000 EEFFFF

237 ED0000 EDFFFF

236 EC0000 ECFFFF

235 EB0000 EBFFFF

234 EA0000 EAFFFF

233 E90000 E9FFFF

232 E80000 E8FFFF

231 E70000 E7FFFF

230 E60000 E6FFFF

229 E50000 E5FFFF

228 E40000 E4FFFF

227 E30000 E3FFFF

226 E20000 E2FFFF

225 E10000 E1FFFF

224 E00000 E0FFFF

223 DF0000 DFFFFF

222 DE0000 DEFFFF

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221 DD0000 DDFFFF

220 DC0000 DCFFFF

219 DB0000 DBFFFF

218 DA0000 DAFFFF

217 D90000 D9FFFF

216 D80000 D8FFFF

215 D70000 D7FFFF

214 D60000 D6FFFF

213 D50000 D5FFFF

212 D40000 D4FFFF

211 D30000 D3FFFF

210 D20000 D2FFFF

209 D10000 D1FFFF

208 D00000 D0FFFF

207 CF0000 CFFFFF

206 CE0000 CEFFFF

205 CD0000 CDFFFF

204 CC0000 CCFFFF

203 CB0000 CBFFFF

202 CA0000 CAFFFF

201 C90000 C9FFFF

200 C80000 C8FFFF

199 C70000 C7FFFF

198 C60000 C6FFFF

197 C50000 C5FFFF

196 C40000 C4FFFF

195 C30000 C3FFFF

194 C20000 C2FFFF

193 C10000 C1FFFF

192 C00000 C0FFFF

191 BF0000 BFFFFF

190 BE0000 BEFFFF

189 BD0000 BDFFFF

188 BC0000 BCFFFF

187 BB0000 BBFFFF

Table 11. Memory organization (uniform) (page 2 of 8)

Sector Address range

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186 BA0000 BAFFFF

185 B90000 B9FFFF

184 B80000 B8FFFF

183 B70000 B7FFFF

182 B60000 B6FFFF

181 B50000 B5FFFF

180 B40000 B4FFFF

179 B30000 B3FFFF

178 B20000 B2FFFF

177 B10000 B1FFFF

176 B00000 B0FFFF

175 AF0000 AFFFFF

174 AE0000 AEFFFF

173 AD0000 ADFFFF

172 AC0000 ACFFFF

171 AB0000 ABFFFF

170 AA0000 AAFFFF

169 A90000 A9FFFF

168 A80000 A8FFFF

167 A70000 A7FFFF

166 A60000 A6FFFF

165 A50000 A5FFFF

164 A40000 A4FFFF

163 A30000 A3FFFF

162 A20000 A2FFFF

161 A10000 A1FFFF

160 A00000 A0FFFF

159 9F0000 9FFFFF

158 9E0000 9EFFFF

157 9D0000 9DFFFF

156 9C0000 9CFFFF

155 9B0000 9BFFFF

154 9A0000 9AFFFF

153 990000 99FFFF

152 980000 98FFFF

Table 11. Memory organization (uniform) (page 3 of 8)

Sector Address range

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151 970000 97FFFF

150 960000 96FFFF

149 950000 95FFFF

148 940000 94FFFF

147 930000 93FFFF

146 920000 92FFFF

145 910000 91FFFF

144 900000 90FFFF

143 8F0000 8FFFFF

142 8E0000 8EFFFF

141 8D0000 8DFFFF

140 8C0000 8CFFFF

139 8B0000 8BFFFF

138 8A0000 8AFFFF

137 890000 89FFFF

136 880000 88FFFF

135 870000 87FFFF

134 860000 86FFFF

133 850000 85FFFF

132 840000 84FFFF

131 830000 83FFFF

130 820000 82FFFF

129 810000 81FFFF

128 800000 80FFFF

127 7F0000 7FFFFF

126 7E0000 7EFFFF

125 7D0000 7DFFFF

124 7C0000 7CFFFF

123 7B0000 7BFFFF

122 7A0000 7AFFFF

121 790000 79FFFF

120 780000 78FFFF

119 770000 77FFFF

118 760000 76FFFF

117 750000 75FFFF

Table 11. Memory organization (uniform) (page 4 of 8)

Sector Address range

Memory organization N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

116 740000 74FFFF

115 730000 73FFFF

114 720000 72FFFF

113 710000 71FFFF

112 700000 70FFFF

111 6F0000 6FFFFF

110 6E0000 6EFFFF

109 6D0000 6DFFFF

108 6C0000 6CFFFF

107 6B0000 6BFFFF

106 6A0000 6AFFFF

105 690000 69FFFF

104 680000 68FFFF

103 670000 67FFFF

102 660000 66FFFF

101 650000 65FFFF

100 640000 64FFFF

99 630000 63FFFF

98 620000 62FFFF

97 610000 61FFFF

96 600000 60FFFF

95 5F0000 5FFFFF

94 5E0000 5EFFFF

93 5D0000 5DFFFF

92 5C0000 5CFFFF

91 5B0000 5BFFFF

90 5A0000 5AFFFF

89 590000 59FFFF

88 580000 58FFFF

87 570000 57FFFF

86 560000 56FFFF

85 550000 55FFFF

84 540000 54FFFF

83 530000 53FFFF

82 520000 52FFFF

Table 11. Memory organization (uniform) (page 5 of 8)

Sector Address range

N25Q128 - 3 V Memory organization

59/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

81 510000 51FFFF

80 500000 50FFFF

79 4F0000 4FFFFF

78 4E0000 4EFFFF

77 4D0000 4DFFFF

76 4C0000 4CFFFF

75 4B0000 4BFFFF

74 4A0000 4AFFFF

73 490000 49FFFF

72 480000 48FFFF

71 470000 47FFFF

70 460000 46FFFF

69 450000 45FFFF

68 440000 44FFFF

67 430000 43FFFF

66 420000 42FFFF

65 410000 41FFFF

64 400000 40FFFF

63 3F0000 3FFFFF

62 3E0000 3EFFFF

61 3D0000 3DFFFF

60 3C0000 3CFFFF

59 3B0000 3BFFFF

58 3A0000 3AFFFF

57 390000 39FFFF

56 380000 38FFFF

55 370000 37FFFF

54 360000 36FFFF

53 350000 35FFFF

52 340000 34FFFF

51 330000 33FFFF

50 320000 32FFFF

49 310000 31FFFF

48 300000 30FFFF

47 2F0000 2FFFFF

Table 11. Memory organization (uniform) (page 6 of 8)

Sector Address range

Memory organization N25Q128 - 3 V

60/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

46 2E0000 2EFFFF

45 2D0000 2DFFFF

44 2C0000 2CFFFF

43 2B0000 2BFFFF

42 2A0000 2AFFFF

41 290000 29FFFF

40 280000 28FFFF

39 270000 27FFFF

38 260000 26FFFF

37 250000 25FFFF

36 240000 24FFFF

35 230000 23FFFF

34 220000 22FFFF

33 210000 21FFFF

32 200000 20FFFF

31 1F0000 1FFFFF

30 1E0000 1EFFFF

29 1D0000 1DFFFF

28 1C0000 1CFFFF

27 1B0000 1BFFFF

26 1A0000 1AFFFF

25 190000 19FFFF

24 180000 18FFFF

23 170000 17FFFF

22 160000 16FFFF

21 150000 15FFFF

20 140000 14FFFF

19 130000 13FFFF

18 120000 12FFFF

17 110000 11FFFF

16 100000 10FFFF

15 F0000 FFFFF

14 E0000 EFFFF

13 D0000 DFFFF

12 C0000 CFFFF

Table 11. Memory organization (uniform) (page 7 of 8)

Sector Address range

N25Q128 - 3 V Memory organization

61/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11 B0000 BFFFF

10 A0000 AFFFF

9 90000 9FFFF

8 80000 8FFFF

7 70000 7FFFF

6 60000 6FFFF

5 50000 5FFFF

4 40000 4FFFF

3 30000 3FFFF

2 20000 2FFFF

1 10000 1FFFF

0 0 FFFF

Table 12. Memory organization (bottom) (page 1 of 9)

Sector Subsector Address range

255 - FF0000 FFFFFF

254 - FE0000 FEFFFF

253 - FD0000 FDFFFF

252 - FC0000 FCFFFF

251 - FB0000 FBFFFF

250 - FA0000 FAFFFF

249 - F90000 F9FFFF

248 - F80000 F8FFFF

247 - F70000 F7FFFF

246 - F60000 F6FFFF

245 - F50000 F5FFFF

244 - F40000 F4FFFF

243 - F30000 F3FFFF

242 - F20000 F2FFFF

241 - F10000 F1FFFF

240 - F00000 F0FFFF

239 - EF0000 EFFFFF

238 - EE0000 EEFFFF

237 - ED0000 EDFFFF

236 - EC0000 ECFFFF

Table 11. Memory organization (uniform) (page 8 of 8)

Sector Address range

Memory organization N25Q128 - 3 V

62/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

235 - EB0000 EBFFFF

234 - EA0000 EAFFFF

233 - E90000 E9FFFF

232 - E80000 E8FFFF

231 - E70000 E7FFFF

230 - E60000 E6FFFF

229 - E50000 E5FFFF

228 - E40000 E4FFFF

227 - E30000 E3FFFF

226 - E20000 E2FFFF

225 - E10000 E1FFFF

224 - E00000 E0FFFF

223 - DF0000 DFFFFF

222 - DE0000 DEFFFF

221 - DD0000 DDFFFF

220 - DC0000 DCFFFF

219 - DB0000 DBFFFF

218 - DA0000 DAFFFF

217 - D90000 D9FFFF

216 - D80000 D8FFFF

215 - D70000 D7FFFF

214 - D60000 D6FFFF

213 - D50000 D5FFFF

212 - D40000 D4FFFF

211 - D30000 D3FFFF

210 - D20000 D2FFFF

209 - D10000 D1FFFF

208 - D00000 D0FFFF

207 - CF0000 CFFFFF

206 - CE0000 CEFFFF

205 - CD0000 CDFFFF

204 - CC0000 CCFFFF

203 - CB0000 CBFFFF

202 - CA0000 CAFFFF

201 - C90000 C9FFFF

Table 12. Memory organization (bottom) (page 2 of 9)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

63/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

200 - C80000 C8FFFF

199 - C70000 C7FFFF

198 - C60000 C6FFFF

197 - C50000 C5FFFF

196 - C40000 C4FFFF

195 - C30000 C3FFFF

194 - C20000 C2FFFF

193 - C10000 C1FFFF

192 - C00000 C0FFFF

191 - BF0000 BFFFFF

190 - BE0000 BEFFFF

189 - BD0000 BDFFFF

188 - BC0000 BCFFFF

187 - BB0000 BBFFFF

186 - BA0000 BAFFFF

185 - B90000 B9FFFF

184 - B80000 B8FFFF

183 - B70000 B7FFFF

182 - B60000 B6FFFF

181 - B50000 B5FFFF

180 - B40000 B4FFFF

179 - B30000 B3FFFF

178 - B20000 B2FFFF

177 - B10000 B1FFFF

176 - B00000 B0FFFF

175 - AF0000 AFFFFF

174 - AE0000 AEFFFF

173 - AD0000 ADFFFF

172 - AC0000 ACFFFF

171 - AB0000 ABFFFF

170 - AA0000 AAFFFF

169 - A90000 A9FFFF

168 - A80000 A8FFFF

167 - A70000 A7FFFF

166 - A60000 A6FFFF

Table 12. Memory organization (bottom) (page 3 of 9)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

64/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

165 - A50000 A5FFFF

164 - A40000 A4FFFF

163 - A30000 A3FFFF

162 - A20000 A2FFFF

161 - A10000 A1FFFF

160 - A00000 A0FFFF

159 - 9F0000 9FFFFF

158 - 9E0000 9EFFFF

157 - 9D0000 9DFFFF

156 - 9C0000 9CFFFF

155 - 9B0000 9BFFFF

154 - 9A0000 9AFFFF

153 - 990000 99FFFF

152 - 980000 98FFFF

151 - 970000 97FFFF

150 - 960000 96FFFF

149 - 950000 95FFFF

148 - 940000 94FFFF

147 - 930000 93FFFF

146 - 920000 92FFFF

145 - 910000 91FFFF

144 - 900000 90FFFF

143 - 8F0000 8FFFFF

142 - 8E0000 8EFFFF

141 - 8D0000 8DFFFF

140 - 8C0000 8CFFFF

139 - 8B0000 8BFFFF

138 - 8A0000 8AFFFF

137 - 890000 89FFFF

136 - 880000 88FFFF

135 - 870000 87FFFF

134 - 860000 86FFFF

133 - 850000 85FFFF

132 - 840000 84FFFF

131 - 830000 83FFFF

Table 12. Memory organization (bottom) (page 4 of 9)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

65/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

130 - 820000 82FFFF

129 - 810000 81FFFF

128 - 800000 80FFFF

127 - 7F0000 7FFFFF

126 - 7E0000 7EFFFF

125 - 7D0000 7DFFFF

124 - 7C0000 7CFFFF

123 - 7B0000 7BFFFF

122 - 7A0000 7AFFFF

121 - 790000 79FFFF

120 - 780000 78FFFF

119 - 770000 77FFFF

118 - 760000 76FFFF

117 - 750000 75FFFF

116 - 740000 74FFFF

115 - 730000 73FFFF

114 - 720000 72FFFF

113 - 710000 71FFFF

112 - 700000 70FFFF

111 - 6F0000 6FFFFF

110 - 6E0000 6EFFFF

109 - 6D0000 6DFFFF

108 - 6C0000 6CFFFF

107 - 6B0000 6BFFFF

106 - 6A0000 6AFFFF

105 - 690000 69FFFF

104 - 680000 68FFFF

103 - 670000 67FFFF

102 - 660000 66FFFF

101 - 650000 65FFFF

100 - 640000 64FFFF

99 - 630000 63FFFF

98 - 620000 62FFFF

97 - 610000 61FFFF

96 - 600000 60FFFF

Table 12. Memory organization (bottom) (page 5 of 9)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

66/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

95 - 5F0000 5FFFFF

94 - 5E0000 5EFFFF

93 - 5D0000 5DFFFF

92 - 5C0000 5CFFFF

91 - 5B0000 5BFFFF

90 - 5A0000 5AFFFF

89 - 590000 59FFFF

88 - 580000 58FFFF

87 - 570000 57FFFF

86 - 560000 56FFFF

85 - 550000 55FFFF

84 - 540000 54FFFF

83 - 530000 53FFFF

82 - 520000 52FFFF

81 - 510000 51FFFF

80 - 500000 50FFFF

79 - 4F0000 4FFFFF

78 - 4E0000 4EFFFF

77 - 4D0000 4DFFFF

76 - 4C0000 4CFFFF

75 - 4B0000 4BFFFF

74 - 4A0000 4AFFFF

73 - 490000 49FFFF

72 - 480000 48FFFF

71 - 470000 47FFFF

70 - 460000 46FFFF

69 - 450000 45FFFF

68 - 440000 44FFFF

67 - 430000 43FFFF

66 - 420000 42FFFF

65 - 410000 41FFFF

64 - 400000 40FFFF

63 - 3F0000 3FFFFF

62 - 3E0000 3EFFFF

61 - 3D0000 3DFFFF

Table 12. Memory organization (bottom) (page 6 of 9)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

67/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

60 - 3C0000 3CFFFF

59 - 3B0000 3BFFFF

58 - 3A0000 3AFFFF

57 - 390000 39FFFF

56 - 380000 38FFFF

55 - 370000 37FFFF

54 - 360000 36FFFF

53 - 350000 35FFFF

52 - 340000 34FFFF

51 - 330000 33FFFF

50 - 320000 32FFFF

49 - 310000 31FFFF

48 - 300000 30FFFF

47 - 2F0000 2FFFFF

46 - 2E0000 2EFFFF

45 - 2D0000 2DFFFF

44 - 2C0000 2CFFFF

43 - 2B0000 2BFFFF

42 - 2A0000 2AFFFF

41 - 290000 29FFFF

40 - 280000 28FFFF

39 - 270000 27FFFF

38 - 260000 26FFFF

37 - 250000 25FFFF

36 - 240000 24FFFF

35 - 230000 23FFFF

34 - 220000 22FFFF

33 - 210000 21FFFF

32 - 200000 20FFFF

31 - 1F0000 1FFFFF

30 - 1E0000 1EFFFF

29 - 1D0000 1DFFFF

28 - 1C0000 1CFFFF

27 - 1B0000 1BFFFF

26 - 1A0000 1AFFFF

Table 12. Memory organization (bottom) (page 7 of 9)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

68/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25 - 190000 19FFFF

24 - 180000 18FFFF

23 - 170000 17FFFF

22 - 160000 16FFFF

21 - 150000 15FFFF

20 - 140000 14FFFF

19 - 130000 13FFFF

18 - 120000 12FFFF

17 - 110000 11FFFF

16 - 100000 10FFFF

15 - F0000 FFFFF

14 - E0000 EFFFF

13 - D0000 DFFFF

12 - C0000 CFFFF

11 - B0000 BFFFF

10 - A0000 AFFFF

9 - 90000 9FFFF

8 - 80000 8FFFF

127 7F000 7FFFF

...

112 70000 70FFF

111 6F000 6FFFF

...

96 60000 60FFF

95 5F000 5FFFF

...

80 50000 50FFF

79 4F000 4FFFF

...

64 40000 40FFF

63 3F000 3FFFF

...

48 30000 30FFF

47 2F000 2FFFF

...

32 20000 20FFF

Table 12. Memory organization (bottom) (page 8 of 9)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

69/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31 1F000 1FFFF

...

16 10000 10FFF

15 F000 FFFF

...

00FFF

Table 13. Memory organization (top)

Sector Subsector Address range

255

127 FFF000 FFFFFF

...

112 FF0000 FF0FFF

254

111 FEF000 FEFFFF

...

96 FE0000 FE0FFF

253

95 FDF000 FDFFFF

...

80 FD0000 FD0FFF

252

79 FCF000 FCFFFF

...

64 FC0000 FC0FFF

251

63 FBF000 FBFFFF

...

48 FB0000 FB0FFF

250

47 FAF000 FAFFFF

...

32 FA0000 FA0FFF

249

31 F9F000 F9FFFF

...

16 F90000 F90FFF

248

15 F8F000 F8FFFF

...

0 F80000 F80FFF

247 - F70000 F7FFFF

246 - F60000 F6FFFF

245 - F50000 F5FFFF

Table 12. Memory organization (bottom) (page 9 of 9)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

70/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

244 - F40000 F4FFFF

243 - F30000 F3FFFF

242 - F20000 F2FFFF

241 - F10000 F1FFFF

240 - F00000 F0FFFF

239 - EF0000 EFFFFF

238 - EE0000 EEFFFF

237 - ED0000 EDFFFF

236 - EC0000 ECFFFF

235 - EB0000 EBFFFF

234 - EA0000 EAFFFF

233 - E90000 E9FFFF

232 - E80000 E8FFFF

231 - E70000 E7FFFF

230 - E60000 E6FFFF

229 - E50000 E5FFFF

228 - E40000 E4FFFF

227 - E30000 E3FFFF

226 - E20000 E2FFFF

225 - E10000 E1FFFF

224 - E00000 E0FFFF

223 - DF0000 DFFFFF

222 - DE0000 DEFFFF

221 - DD0000 DDFFFF

220 - DC0000 DCFFFF

219 - DB0000 DBFFFF

218 - DA0000 DAFFFF

217 - D90000 D9FFFF

216 - D80000 D8FFFF

215 - D70000 D7FFFF

214 - D60000 D6FFFF

213 - D50000 D5FFFF

212 - D40000 D4FFFF

211 - D30000 D3FFFF

210 - D20000 D2FFFF

Table 13. Memory organization (top)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

71/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

209 - D10000 D1FFFF

208 - D00000 D0FFFF

207 - CF0000 CFFFFF

206 - CE0000 CEFFFF

205 - CD0000 CDFFFF

204 - CC0000 CCFFFF

203 - CB0000 CBFFFF

202 - CA0000 CAFFFF

201 - C90000 C9FFFF

200 - C80000 C8FFFF

199 - C70000 C7FFFF

198 - C60000 C6FFFF

197 - C50000 C5FFFF

196 - C40000 C4FFFF

195 - C30000 C3FFFF

194 - C20000 C2FFFF

193 - C10000 C1FFFF

192 - C00000 C0FFFF

191 - BF0000 BFFFFF

190 - BE0000 BEFFFF

189 - BD0000 BDFFFF

188 - BC0000 BCFFFF

187 - BB0000 BBFFFF

186 - BA0000 BAFFFF

185 - B90000 B9FFFF

184 - B80000 B8FFFF

183 - B70000 B7FFFF

182 - B60000 B6FFFF

181 - B50000 B5FFFF

180 - B40000 B4FFFF

179 - B30000 B3FFFF

178 - B20000 B2FFFF

177 - B10000 B1FFFF

176 - B00000 B0FFFF

175 - AF0000 AFFFFF

Table 13. Memory organization (top)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

72/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

174 - AE0000 AEFFFF

173 - AD0000 ADFFFF

172 - AC0000 ACFFFF

171 - AB0000 ABFFFF

170 - AA0000 AAFFFF

169 - A90000 A9FFFF

168 - A80000 A8FFFF

167 - A70000 A7FFFF

166 - A60000 A6FFFF

165 - A50000 A5FFFF

164 - A40000 A4FFFF

163 - A30000 A3FFFF

162 - A20000 A2FFFF

161 - A10000 A1FFFF

160 - A00000 A0FFFF

159 - 9F0000 9FFFFF

158 - 9E0000 9EFFFF

157 - 9D0000 9DFFFF

156 - 9C0000 9CFFFF

155 - 9B0000 9BFFFF

154 - 9A0000 9AFFFF

153 - 990000 99FFFF

152 - 980000 98FFFF

151 - 970000 97FFFF

150 - 960000 96FFFF

149 - 950000 95FFFF

148 - 940000 94FFFF

147 - 930000 93FFFF

146 - 920000 92FFFF

145 - 910000 91FFFF

144 - 900000 90FFFF

143 - 8F0000 8FFFFF

142 - 8E0000 8EFFFF

141 - 8D0000 8DFFFF

140 - 8C0000 8CFFFF

Table 13. Memory organization (top)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

73/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

139 - 8B0000 8BFFFF

138 - 8A0000 8AFFFF

137 - 890000 89FFFF

136 - 880000 88FFFF

135 - 870000 87FFFF

134 - 860000 86FFFF

133 - 850000 85FFFF

132 - 840000 84FFFF

131 - 830000 83FFFF

130 - 820000 82FFFF

129 - 810000 81FFFF

128 - 800000 80FFFF

127 - 7F0000 7FFFFF

126 - 7E0000 7EFFFF

125 - 7D0000 7DFFFF

124 - 7C0000 7CFFFF

123 - 7B0000 7BFFFF

122 - 7A0000 7AFFFF

121 - 790000 79FFFF

120 - 780000 78FFFF

119 - 770000 77FFFF

118 - 760000 76FFFF

117 - 750000 75FFFF

116 - 740000 74FFFF

115 - 730000 73FFFF

114 - 720000 72FFFF

113 - 710000 71FFFF

112 - 700000 70FFFF

111 - 6F0000 6FFFFF

110 - 6E0000 6EFFFF

109 - 6D0000 6DFFFF

108 - 6C0000 6CFFFF

107 - 6B0000 6BFFFF

106 - 6A0000 6AFFFF

105 - 690000 69FFFF

Table 13. Memory organization (top)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

74/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

104 - 680000 68FFFF

103 - 670000 67FFFF

102 - 660000 66FFFF

101 - 650000 65FFFF

100 - 640000 64FFFF

99 - 630000 63FFFF

98 - 620000 62FFFF

97 - 610000 61FFFF

96 - 600000 60FFFF

95 - 5F0000 5FFFFF

94 - 5E0000 5EFFFF

93 - 5D0000 5DFFFF

92 - 5C0000 5CFFFF

91 - 5B0000 5BFFFF

90 - 5A0000 5AFFFF

89 - 590000 59FFFF

88 - 580000 58FFFF

87 - 570000 57FFFF

86 - 560000 56FFFF

85 - 550000 55FFFF

84 - 540000 54FFFF

83 - 530000 53FFFF

82 - 520000 52FFFF

81 - 510000 51FFFF

80 - 500000 50FFFF

79 - 4F0000 4FFFFF

78 - 4E0000 4EFFFF

77 - 4D0000 4DFFFF

76 - 4C0000 4CFFFF

75 - 4B0000 4BFFFF

74 - 4A0000 4AFFFF

73 - 490000 49FFFF

72 - 480000 48FFFF

71 - 470000 47FFFF

70 - 460000 46FFFF

Table 13. Memory organization (top)

Sector Subsector Address range

N25Q128 - 3 V Memory organization

75/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

69 - 450000 45FFFF

68 - 440000 44FFFF

67 - 430000 43FFFF

66 - 420000 42FFFF

65 - 410000 41FFFF

64 - 400000 40FFFF

63 - 3F0000 3FFFFF

62 - 3E0000 3EFFFF

61 - 3D0000 3DFFFF

60 - 3C0000 3CFFFF

59 - 3B0000 3BFFFF

58 - 3A0000 3AFFFF

57 - 390000 39FFFF

56 - 380000 38FFFF

55 - 370000 37FFFF

54 - 360000 36FFFF

53 - 350000 35FFFF

52 - 340000 34FFFF

51 - 330000 33FFFF

50 - 320000 32FFFF

49 - 310000 31FFFF

48 - 300000 30FFFF

47 - 2F0000 2FFFFF

46 - 2E0000 2EFFFF

45 - 2D0000 2DFFFF

44 - 2C0000 2CFFFF

43 - 2B0000 2BFFFF

42 - 2A0000 2AFFFF

41 - 290000 29FFFF

40 - 280000 28FFFF

39 - 270000 27FFFF

38 - 260000 26FFFF

37 - 250000 25FFFF

36 - 240000 24FFFF

35 - 230000 23FFFF

Table 13. Memory organization (top)

Sector Subsector Address range

Memory organization N25Q128 - 3 V

76/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34 - 220000 22FFFF

33 - 210000 21FFFF

32 - 200000 20FFFF

31 - 1F0000 1FFFFF

30 - 1E0000 1EFFFF

29 - 1D0000 1DFFFF

28 - 1C0000 1CFFFF

27 - 1B0000 1BFFFF

26 - 1A0000 1AFFFF

25 - 190000 19FFFF

24 - 180000 18FFFF

23 - 170000 17FFFF

22 - 160000 16FFFF

21 - 150000 15FFFF

20 - 140000 14FFFF

19 - 130000 13FFFF

18 - 120000 12FFFF

17 - 110000 11FFFF

16 - 100000 10FFFF

15 - F0000 FFFFF

14 - E0000 EFFFF

13 - D0000 DFFFF

12 - C0000 CFFFF

11 - B0000 BFFFF

10 - A0000 AFFFF

9 - 90000 9FFFF

8 - 80000 8FFFF

7 - 70000 7FFFF

6 - 60000 6FFFF

5 - 50000 5FFFF

4 - 40000 4FFFF

3 - 30000 3FFFF

2 - 20000 2FFFF

1 - 10000 1FFFF

0- 0 FFFF

Table 13. Memory organization (top)

Sector Subsector Address range

N25Q128 - 3 V Instructions

77/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9 Instructions

The device can work in three different protocols: Extended SPI, DIO-SPI and QIO-SPI.

Each protocol has a dedicated instruction set, and each instruction set features the same

functionality:

Read, program and erase the memory and the 64 byte OTP area,

Suspend and resume the program or erase operations,

Read and modify all the registers and to read the device ID: please note that in this

case there is a small functionality dif ference among the single and the multiple I/O read

ID instructions. See Section 9.2.1: Multiple I/O Read Identification protocol and

Section 9.3.1: Multiple I/O Read Identification (MIORDID).

The application can choose in every time of the device life which protocol to use by setting

the dedicated bits either in the Non Volatile Configu ration Re giste r or the Volatile Enhanced

Configuration Register.

Note: In multiple SPI protocols, all instructions, addresses, and dat a are p arallel on two lines (DIO-

SPI protocol) or four lines (QIO-SPI protocol).

All instructions, addresses and data are shifted in and out of the device, most significant bit

first.

Serial Data input(s) is (are) sampled on the first rising edge of Serial Clock (C) after Chip

Select (S) is driven Low. Then, the one-byte instr uction code must be shifted in to the

device, most significant bit first, on Serial Data input(s), each bit being latched on the rising

edges of Serial Clock (C). Instruction code is shifted into the device just on DQ0 in Extended

SPI protocol, on DQ0 and DQ1 in DIO-SPI protocol and on DQ0, DQ1, DQ2, and DQ3 in

QIO-SPI protoc ol.

In standard mode every instruction sequence starts with a one-byte instruction code.

Depending on the instruction, this might be followed by address bytes, or by data bytes, or

by both or none.

In XIP modes only read operation and exit XIP mode can be pe rformed, and to read the

memory content no instru ctions code are needed: the device directly receives addresses

and after a configurable number of dummy clock cycles it outputs the required data.

9.1 Extended SPI Instructions

In Extended SPI protocol instruction set the inst ruction code is always shifted into the device

just on DQ0 pin, while dep ending on the instruction addr esses and input/output dat a can run

on single, two or four wires.

In the case of a Read Instructions Data Bytes (READ), Read Data Bytes at Higher Speed

(FAST_READ), Dual Output Fast Read (DOFR), Dual Input/Output Fast Read (DIOFR),

Quad Output Fast Read (QOFR), Quad Input/Output Fast Read (QIOFR), Read OTP

(ROTP), Read Lock Registers (RDLR), Read Status Register (RDSR), Read Flag Status

Identification (RDID) instruction, the shifted-in instru ction sequence is followed by a dat a-out

sequence. Chip Select (S) can be driven High af ter any bit of the dat a-out sequence is being

shifted out.

Instructions N25Q128 - 3 V

78/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

In the case of a Page Program (PP), Program OTP (POTP), Dual Input Fast Program

(DIFP), Dual Input Extended Fast Program (DIEFP), Quad Input Fast Program (QIFP),

Quad Input Extended Fast Program (QIEFP), Subsector Erase (SSE), Sector Erase (SE),

Bulk Erase (BE), W rite Status Register (WRSR), Clear Flag Sta tus Register (CLFSR), W rite

to Lock Register (WRLR), Write Configuration Register (WRVCR), Write Enhanced

Configuration Register (WRVECR), Write NV Configuration Register (WRNVCR), Write

Enable (WREN) or Write Disable (WRDI) instruction, Chip Select (S) must be driven High

exactly at a byte bo u nda ry, otherwis e th e inst ruction is rejected, and is not executed. That

is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)

being driven Low is an exact multiple of eight.

All attempts to access the memory array are ignored during:

– Write Status Register cycle

– Write Non Volatile Configuration Register

– Program cycle

– Erase cycle

The following continue unaffected, with one exception:

– Internal Write Status Register cycle,

– Write Non Volatile Configuration Register,

– Program cycle,

– Erase cycle

The only exception is the Program/Erase Suspend instruction (PES), that can be used to

pause all the program and the er as e cycles except for:

– Program OTP (POTP),

– Bulk Erase,

– Write Status Registe r

– Write Non Volatile Configuration Register.

The suspended program or erase cycle can be resumed by the Program/Erase Resume

instruction (PER). During the program/erase cycles, the polling instructions (both on the

Status reg iste r and on th e Fl ag St atus re gister ) are also a cce pted to allo w th e a pplica tion to

check the end of the internal modify cycles.

Note: These polling instructions don't affect the internal cycles performing.

N25Q128 - 3 V Instructions

79/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 14. Instruction set: extended SPI protocol (page 1 of 2)

Instruction De sc r iption One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code (HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

RDID Read Identification 1001 111x 9Eh / 9Fh 0 0 1 to 20

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 8 (1) 1 to ∞

DOFR Dual Output Fast Read 0011 1011 3Bh 3 8 (1) 1 to ∞

DIOFR Dual Input/Output Fast Read 1011 1011 BB 3 8 (1) 1 to ∞

QOFR Quad Output Fast Read 0110 1011 6Bh 3 8 (1) 1 to ∞

QIOFR Quad Input/Output Fast Read 1110 1011 EBh 3 10 (1 1 to ∞

ROTP Read OTP (Read of OTP area) 0100 1011 4Bh 3 8 (1) 1 to 65

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

PP Page Program 0000 0010 02h 3 0 1 to 256

DIFP Dual Input Fast Program 101 0 0010 A2h 3 0 1 to 256

DIEFP Dual Input Extended Fast Program 1101 0010 D2h 3 0 1 to 256

QIFP Quad Input Fast Program 0011 0010 32h 3 0 1 to 256

QIEFP Quad Input Extended Fast Program 0001 0010 12h 3 0 1 to 256

POTP Program OTP (Program of OTP area) 0100 0010 42h 3 0 1 to 65

SSE (2) SubSe ctor Erase 0010 0000 20h 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

PER Program/Erase Resume 0111 1010 7Ah 0 0 0

PES Program/Erase Suspend 0111 0101 75h 0 0 0

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

RDLR Read Lock Register 111 0 1000 E8h 3 0 1 to ∞

WRLR Write to Lock Register 1110 0101 E5h 3 0 1

RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞

CLFSR Clear Flag St atus Register 0101 0000 50h 0 0 0

RDNVCR Read NV Configuration Register 1011 0101 B5h 0 0 2

WRNVCR Write NV Confi guration Register 1011 0001 B1h 0 0 2

RDVCR Read Volatile Configu r ation Register 1000 0101 85h 0 0 1 to ∞

WRVCR Write Volatile Con fig uration Register 1000 0001 81h 0 0 1

Instructions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

1) The Number of dummy clock cycles is configurable by user

2) Subsector erase instruction is only available in Bottom or Top parts

9.1.1 Read Identification (RDID)

The Read Identification (RDID) instruction allows to read the device identification data:

– Manufacturer identification (1 byte)

– Device identification (2 bytes)

– A Unique ID code (UID) (17 bytes, of which 14 factory programmed upon

customer request).

The manufacturer identification is assigned by JEDEC, and has the value 20h. The device

identification is assigned by the device manufacturer, and indicates the memory type in the

first byte (BAh), and the memory ca pacity o f the d evice in the seco nd byte (18h) . The UID is

composed by 17 read only bytes, containing the length of the following data in the first byte

(set to 10h), 2 bytes of Extended Device ID (EDID) to identify the specific device

configuration (Top, Bottom or uniform architecture, Hold or Reset functionality), and 14

bytes of the optional Customized Factory Data (CFD) content. The CFD bytes can be

factory programmed with customers data upon their demand. If the customers do not make

requests , the devices are shipped with all the CFD bytes programmed to zero (00h).

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is

not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. After this, the 24-bit device identification, stored in the

memory, the 17 bytes of UID content will be shifted out on Serial Data output (DQ1). Each

bit is shifted out during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 10.

The Read Identification (RDID) instr uction is terminated by driving Chip Select (S) High at

any time during data output.

RDVECR Read Volatile Enhanced

Configuration Register 0110 0101 65h 0 0 1 to ∞

WRVECR Write Volatile Enhanced

Configuration Register 0110 0001 61h 0 0 1

Table 14. Instruction set: extended SPI protocol (page 2 of 2)

Instruction De sc r iption One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code (HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in

the S tan dby Power mode, the device waits to be selected, so that it can receive , decode and

execute instructions.

Figure 10. Read identification instruction and data-out sequence

9.1.2 Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low . The instruction code for the Read

Data Bytes (READ) instruction is followed b y a 3- byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that

address, is shifted out on Serial Data output (DQ1), each bit being shifted out, at a

maximum frequency fR, during the falling edge of Serial Clock (C).

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip

Select (S) can be drive n High a t any time du ring data output. Any Read Dat a Byte s (READ)

Table 15. Read Identification data-out sequence

Manufacturer

Identification Device identification UID

Memory type Memory capacity EDID+CFD length EDID CFD

20h BAh 18h 10h 2 bytes 14 bytes

Table 16. Extended Device ID table (first byte)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Reserved Reserved VCR XIP bit setting:

0 = required,

1 = not required

Hold/Reset function:

0 = HOLD,

1 = Reset

Addressing:

0 = by Byte,

Architecture:

00 = Uniform,

01 = Bottom,

11 = Top

DQ0

213456789101112131415

Instruction

AI06809d

DQ1

Manufacturer identification

High Impedance

MSB

Device identification

MSB

15 14 13 3 2 1 0

16 17 18 28 29 30 31

MSB

UID

Instructions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

instruction, while an Erase or Program cycle is in progress, is rejected without having any

effects on the cycle that is in progress.

Figure 11. Read Data Bytes instruction and data-out sequence

9.1.3 Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low . The instruction code for the Read

Data Bytes at Higher S peed (FAST_READ) instruction is followed by a 3-byte address (A23-

A0) and a configurable number of dummy clock cycles, each bit being latched-in during the

rising edge of Serial Clock (C).

Then the memory contents, at that address, are shifted out on Serial Data output (DQ1) at a

maximum frequency fC, during the falling edge of Serial Clock (C).

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read wi th a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the address counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driven High at any time d uring dat a output. Any

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase or Program

cycle is in progress, is rejected without having any effects on the cycle that is in progress.

DQ0

AI13736b

DQ1

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data out 1

Instruction 24-bit address (1)

MSB

Data out 2

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 12. Read Data Bytes at Higher Speed instruction and data-out sequence

9.1.4 Dual Output Fast Read (DOFR)

The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at

Higher Spee d (FAST_READ) instruct ion , exc ep t th at th e da ta are shifted out on two pin s

(pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one

doubles the data transfer bandwidth compared to the Read Data Bytes at Higher Speed

(FAST_READ) instruction.

The device is first selected by driving Chip Select (S) Low. The instruction code for the Dual

Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable

number of dummy clock cycles, each bit being latched-in during the rising edge of Serial

Clock (C). Then the memory content s, at that addr ess, are shif ted out on DQ0 and DQ1 at a

maximum frequency Fc, during the falling edge of Serial Clock (C).

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address af ter each byte of data is shif ted out on DQ0 and DQ1. The whole

memory can, therefore, be read with a single Dual Output Fast Read (DOFR) instruction.

When the highest address is reached, the address counter rolls over to 00 0000h, so that

the read sequence can be continued indefinitely.

DQ0

Read_Data_Bytes_Fast_Speed

DQ1

21 345678910 28293031

2221 3210

High Impedance

Instruction 24-bit a ddres s *

DQ0

DQ1

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy cycles

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

*Address bit A23 is “Don’t Care.”

Instructions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 13. Dual Output Fast Read instruction sequence

9.1.5 Dual I/O Fast Read

The Dual I/O Fast Read (DIOFR) instruction is very similar to the Dual Output Fast Read

(DOFR), except that the address bits are shifted in on two pins (pin DQ0 and pin DQ1)

instead of only one.

21 3 4 5 6 7 8 9 10 28 29 30 310

23 22 21 3 2 1 0

Mode 3

Mode 2

DQ0

DQ1 High Impedance

Instruction 24-bit addres s

DQ0

DQ1

32 33 34 36 37 38 39 40 41 42 43 44 45 46

753175 1

DATA OUT 1

Dummy cycles

MSB

7531 7531

MSB MSB

6420 64 02

642064 02

MSB MSB

DAT A OU T 2 DAT A OU T 3 DAT A OU T n

Dual_Output_Data_Fast_Read

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 14. Dual I/O Fast Read instruction sequence

9.1.6 Quad Output Fast Read

The Quad Output Fast Read (QOFR) instruction is very similar to the Dual Output Fast

Read (DOFR) instruction, except that the data are shifted out on four p ins (pin DQ0, pin

DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3 (1) instead of only two. Outputting the data on

four pins instead of one doubles the data tran sfer bandwidth compared to the Dual Output

Fast Read (DOFR) instruction.

The device is first selected by driving Chip Select (S) Low . The instruction code for the Quad

Output Fast Read instruction is followed by a 3-byte address (A23-A0) and a configurable

number of dummy clock cycles, each bit being latched-in during the rising edge of Serial

Clock (C). Then the memory content s, at that address, are shifted out on pin DQ0, pin DQ1,

pin W/VPP/DQ2 and pin HOLD/DQ3 (1) at a maximum fr equency fC, duri ng the falling edge

of Serial Clock (C).

The instruction sequence is shown in Figure 15.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out on pin DQ0, pin DQ1, pin

W/VPP/DQ2 and pin HOLD/DQ3 (1). The whole memory can, therefore, be read with a

single Quad Output Fast Read (QOFR) instruction.

21 345678910

11 12 13 14

6420

Mode 3

Mode 0

DQ1

Instruction

23 24 25 27 28 29 30 31 32 33 34 35 36 37

IO switches from Input to Output

Dual_IO_Fast_Rea

753175 1

37531

6420

7531

64 02642064 02

15 16 17 18 19 20

753175317531

6420 6420

Address Dummy Cycles

Byte 1 Byte 3

Byte 2 Byte 4

Instructions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

When the highest address is reached, the address counter rolls over to 00 0000h, so that

the read sequence can be continued indefinitely.

Note: Reset functionality is available instead of Hold in devices with a de dicated part nu mber . See

Section 16: Ordering information.

Figure 15. Quad Output Fast Read instruction sequence

9.1.7 Quad I/O Fast Read

The Quad I/O Fast Read (QIOFR) instruction is very similar to the Quad Output Fast Read

(QOFR), excep t that th e ad d re ss bits are shifted in on four pins (pin DQ0 , pin DQ 1, pin

W/VPP/DQ2 and pin HOLD/DQ3 (1)) instead of only one.

Note: Reset functionality is available instead of Hold in devices with a de dicated part nu mber . See

Section 16: Ordering information.

DQ0

DQ1

21 3456789

10 36 37 38 39

22 21 3 2 1 0

don’t care

instruction address dummy

byte 1 byte 2

I/O switches from input to output

DQ2

don’t care

DQ3

40404

5151

626

7373

‘1’

48 49 50 51

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 16. Quad Input/ Output Fast Read instruction sequence

9.1.8 Read OTP (ROTP)

The device is first selected by driving Chip Select (S) Low . The instruction code for the Read

OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a configurable

number of dummy clock cycles. Each bit is latched in on the rising edge of Serial Clock (C).

Then the memory contents at that address are shifted ou t on Serial Data output (DQ1).

Each bit is shif ted ou t at the maxim um frequenc y, fCmax, on the falling edge of Ser ial Clock

(C). The instruction sequence is shown in Figure 17.

The address is automatically incr emented to the next higher address afte r each byte of dat a

is shifted out.

There is no rollover mechanism with the Re ad OTP (ROTP) instruction. This means that the

Read OTP (ROTP) instruction must be sent with a maximum of 65 bytes to read. All other

bytes outsid e the OTP area are “Don’t Care.”

The Read OTP (ROTP) instruction is term i na ted by driving Chip Select (S ) High. Chip

Select (S) can be driven High at any time during data output. Any Read OTP (ROTP)

instruction issued while an Er ase or Progra m cycle is in prog ress, is rejected without having

any effect on the cycle that is in progress.

21 345678910

11 12 13 14

Mode 3

Mode 0

Instruction

Quad_IO_Fast_Read

15 16 24

21 22 23

4040 40 044

25 27

5151

Q1 Don’t Care

Byte 1

51 155

73 377

7373

62266

6262

Q2 Don’t Care

Byte 2Dummy (ex.: 10)

A23-16 A15-8 A7-0

Q3 ‘1’

IO switches from Input to Output

Instructions N25Q128 - 3 V

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Figure 17. Read OTP instruction and data-out sequence

9.1.9 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.

The Write Ena ble Latch (WEL) bit must be set prior to every Program or Erase instructions:

Page Program (PP), Dual Input Fast Program (DIFP), Dual Input Extended Fast Program

(DIEFP), Quad Input Fast Program (QIFP), Quad Input Extended Fast Program (QIEFP),

Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector

Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Volatile Configuration

NV Configuration Register (WRNVCR) instruction.

The Write Enable (WREN) instruction i s entered by driving Chip Select (S) Low , sending the

instruction code, and then driving Chip Select (S) High.

When the Fast POR feature is selected (Non Volatile Configuration Register bit 5) after the

first Write Enable instruction, the device enters in a latency time (~500 us), necessary to

internally complete the POR sequence with the modify algorithms. (See Section 11.1: Fast

POR.) During the POR latency time all the instructions are ignored with the exce ption of the

polling instructions (to check if the internal cycle is finished by mean of the WIP bit of the

Read _OT

21 345678910 28293031

22 21 3 2 1 0

High Impedance

Instruction 24-bit a ddres s

DQ1

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy cycles

MSB

76543210

DATA OUT n

MSB MSB

765432 0

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

Status Register o r of the Pr og ra m/Erase co ntro ller bit of the Fla g St atus regi st er ): t o ve rif y if

the POR sequence is completed is possible to check the WIP bit in the Status Register or

the Program/Erase Controller bit in the Flag St atus Register, please note that the

Program/Erase Controller bit in the Flag status register has the reverse logical polarity with

respect to the Status Register WIP bit.

At the end of the POR sequence the WEL bit is low, so the next modify instruction can be

accepted.

Figure 18. Write Enable instruction sequence

9.1.10 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

DQ0

AI13731

DQ1

21 34567

High Impedance

Instruction

Instructions N25Q128 - 3 V

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The Write Enable Latch (WEL) bit is reset under the following conditions:

Power-up

Write Disable (WRDI) instruction completion

Write Status Register (WRSR) instruction completion

Write to Lock Register (WRLR) instruction completion

Write Non Volatile Configuration Register (WRNVCR) instruction completion

Write Volatile Configuration Register (WRVCR) instruction completion

Write Volatile Enhanced Configuration Register (WRVECR) instruction completion

Page Program (PP) instruction completion

Dual Input Fast Program (DIFP) ins truction completion

Dual Input Extended Fast Program (DIEFP) instruction completion

Quad Input Fast Program (QIFP) instruction completion

Quad Input Extended Fast Program (QIEFP) instruction completion

Program OTP (POTP) instruction completion

Subsector Erase (SSE) instruction completion

Sector Erase (SE) instruction completion

Bulk Erase (BE) instruction completion

Figure 19. Write Disable instruction sequence

9.1.11 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory

(changing bits from 1 to 0). Befo re it can be acce p ted , a Write Enable (WREN) instruction

must previously have been executed. After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code, three address bytes and at least one data byte on Serial Data input

(DQ0). If the 8 least significant address bit s (A7-A0) are not all zero, all transmitted dat a that

go beyond the end of the current page are programmed from the start address of the same

DQ0

AI13732

DQ1

21 34567

High Impedance

Instruction

N25Q128 - 3 V Instructions

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page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

If more than 25 6 bytes are sent to the device, p reviously latched dat a ar e discarded a nd the

last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted bytes in a single sequence versus using several Page

Program (PP) sequences with each containing only a few bytes. See Ta b l e 32.: AC

Characteristics.

Chip Select (S) must be driven High after the eighth bit of the last data byte has be en

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Page Program cycle is in progress, the S tatus Register

and the Flag Status Register ma y be read to check if the internal modify cycle is finished. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a pag e that belongs to a hardware or software

protected sector is not executed.

Page Program cycle can be paused by mean of Program/Erase Suspend (PES) instruction

and resumed by mean of Program/Erase Resume (PER) instruction.

Instructions N25Q128 - 3 V

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Figure 20. Page Program instr uction sequence

9.1.12 Dual Input Fast Program (DIFP)

The Dual Input Fast Program (DIFP) instruction is very similar to the Page Program (PP)

instruction, except that the data are entered on two pins (pin DQ0 and pin DQ1) instead of

only one. Inputting the data on two pins instead of one doubles the data transfer bandwidth

compared to the Page Progra m (PP) instruc tio n.

The Dual Input Fast Program (DIFP) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code, three address bytes on Serial Data input (DQ0), and at

least one data byte on Serial Data I/Os (DQ0, DQ1).

If the 8 least significant ad dr ess bits (A7-A0) are not all zero, all transm itt ed data that go

beyond the end of the current page are programmed from the start address of the same

page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

If more than 25 6 bytes are sent to the device, p reviously latched dat a ar e discarded a nd the

last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes in the same page.

For optimized timings, it is recommended to use the Dual Input Fast Program (DIFP)

instruction to program all consecutive targeted bytes in a single sequence rather to using

DQ0

AI13739b

4241 43 44 45 46 47 48 49 50 52 53 54 5540

DQ0

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address (1)

765432 0

Data byte 1

765432 0

Data byte 2

765432 0

Data byte 3 Data byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See

Table 32.: AC Characteristics.

Chip Select (S) must be driven High after the eighth bit of the last data byte has be en

latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,

the Status Register and the Flag Status Register may be read to check if the internal modify

cycle is finished. At some unspecified time before the cycle is completed, the Write Enable

Latch (WEL) bit is rese t.

A Dual Input Fast Program (DIFP) instruction applied to a page that belongs to a hardware

or software protected sector is not executed.

Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES)

instruction and resumed by mean of Program/Erase Resume (PER) instruction.

Figure 21. Dual Input Fast Program instruction sequence

AI14229

DQ0

21 345678910 28293031

22 21 3 2 1 0

Instruction 24-bit addres s

DQ0

3433 35 36 37 38 39 40 41 42 44 45 46 4732 43

642064 0

2642064 0

26420

MSB MSB MSB

DQ1 High Impedance

6420

DQ1 7531 1753 753

MSB

31 1

MSB

7531 7531

MSB

DAT A IN 1 DAT A IN 4 DAT A IN 5 DAT A IN 256DAT A IN 3DAT A IN 2

Instructions N25Q128 - 3 V

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.13 Dual Input Extended Fast Program

The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input

Fast Program (DIFP), except that the address bits are shif ted in on two pins (pin DQ0 and

pin DQ1) instead of only one.

Figure 22. Dual Input Extended Fast Program instruction sequence

9.1.14 Quad Input Fast Program

The Quad Input Fast Program (QIFP) instruction is very similar to the Dual Input Fast

Program (DIFP) instruction, except that the data are entered on four pins (pin DQ0, pin

DQ1, pin W/VPP/DQ2 and pin HOLD/ (DQ3) instead of only two. Inputting the data on four

pins instead of two doubles the data transfer bandwidth compared to the Dual Input Fast

Program (DIFP) instruction.

The Quad Input Fast Program (QIFP) instruction is entered by drivin g Chip Select (S) Low,

followed by the instruction code, three address bytes on Serial Data input (DQ0), and at

least one data byte on Serial Data I/Os (DQ0, DQ1, DQ2, DQ3).

If the 8 least significant ad dr ess bits (A7-A0) are not all zero, all transm itt ed data that go

beyond the end of the current page are programmed from the start address of the same

page (from the ad dress whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

21 345678910

11 12 13 14

6420

Mode 3

Mode 0

DQ0

DQ1

Instruction

DQ0

DQ1

18 19 20 22 23 24 25 26 27 28 29 30 31 32 33

Dual_Input_Extended_Fast_Program

753175 1

37531

6420

642064 02

15 16 17 18 19 20

753175317531

6420 6420

Address Dummy Cycles

MSB

6420

7531

MSB

Data In 4

Data In 1 Data In 3

Data In 2

64 02

7531

MSB

Data In 256

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

If more than 256 bytes are sent to the device, previously latched data are discarded and the

last 256 dat a bytes are guaranteed to be programmed correctly within the same page. If less

than 256 data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes in the same page.

For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP)

instruction to program all consecutive targeted bytes in a single sequence rather to using

several Quad Input Fast Program (QIFP) sequen ces each contai ning only a few bytes See

Table 32.: AC Characteristics.

Chip Select (S) must be driven High after the eighth bit of the last data byte has be en

latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress,

the Status Register may be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self -timed Page Program cycle, and 0 when it is

completed. At some unspecified time before th e cycle is completed, the Write Enable Latch

(WEL) bit is reset. Alternately, it is possible to read the Flag Status Register to check if the

internal modify cycle is finished.

A Quad Input Fast Program ( QIFP) instruction applied to a pa ge that belo ngs to a hardware

or software protected sector is not executed.

A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend

(PES) instruction and resumed by mean of Program/Erase Resume (PER ) instruction.

Figure 23. Quad Input Fast Program instruction sequence

9.1.15 Quad Input Extended Fast Program

The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad

Input Fast Program (QIFP), except that the addr ess bits are shif ted in on four pins (p in DQ0,

pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instea d of only one.

Quad_Input_Fast_Program

23 22 21

5151

Instruction

Don’t Care

MSB

51 15

73 37

Q3 73

62 26

Q2 62

6262

Don’t Care

‘1’

Data In

21 345678910037

34 35 36

28 29 30 31 32 33 39

38 40

41 43

32104

04040440

04 0

MSB

MSBMSB MSB

MSB

7373

Don’t Care

24-bit address Data In Data In

213

456

Instructions N25Q128 - 3 V

96/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 24. Quad Input Extended Fast Program instruction sequence

9.1.16 Program OTP instruction (POTP)

The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP

memory area (by ch anging bit s from 1 to 0, only). Befo re it can be accep ted, a W rite Enable

(WREN) instruction must previously have been executed. After the Write Enable (WREN)

instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.

The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the

instruction opcode, three address bytes and at least one data byte on Serial Data input

(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been

latched in, otherwise th e Program OTP instruction is not executed.

There is no rollover mechanism with the Progra m OTP (POTP) instruction. This mean s that

the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,

once all 65 bytes have been latched in, any following byte will be discarded.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Reg ister

may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress

(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At

some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is

reset. Alternately, it is possible to read the Flag Status Register to check if the internal

modify cycle is finished.

To lock the OTP memory:

Bit 0 of the OTP control byte, that is byte 64, is used to perman ently lock the OTP memory

array.

When bit 0 of byte 64 = '1', the 64 bytes of the OTP memor y array can be prog rammed.

When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read- only and

cannot be programmed anymore.

Quad_Input_Extended_Fast_Program

Instruction

Don’t Care

MSB

Q2 Don’t Care

‘1’

Data In

21 3456789100

C2017 18 19

11 12 13 14 15 16 22

21 23 25

24 26

MSB

MSB MSB

MSB

24-bit address Data In Data In

134

20 16 12 804

40404040440

04 0

62626262662

26 2

51515151551

15 1

21 17 13 9

22 18 14 10

23 19 15 37

73737373773

37 3

MSB

N25Q128 - 3 V Instructions

97/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Once a bit of the OTP memory has been programmed to '0', it can no longer be set to '1'.

Therefore, as soon as bit 0 of byte 64 (control byte) is set to '0', the 64 bytes of the OTP

memory array become read-only in a permanent way.

Any Program OTP (POTP) instruction issued while an Erase or Program cycle is in progress

is rejected without having any effect on the cycle that is in progress. A Program OTP cycle

cannot be paused by a Program/Erase Suspend (PES) instruction.

Figure 25. Program OTP instruction sequence

DQ0

AI13575

4241 43 44 45 46 47 48 49 50 52 53 54 5540

DQ0

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address

765432 0

Data byte 1

765432 0

Data byte 2

765432 0

Data byte 3 Data byte n

765432 0

MSB MSB

MSB MSB MSB

Instructions N25Q128 - 3 V

98/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 26. How to permanently lock the OTP bytes

9.1.17 Subsector Erase (SSE)

For devices with bottom or top architec ture, at the bottom (or top) of the addressable area

there are 8 boo t sect or s, ea ch one hav ing 16 4Kbytes subsectors. The Subsector Erase

(SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be

accepted, a Write Enable (WREN) instruction must previously have bee n executed. After

the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable

Latch (WEL).

The Subsector Erase (SSE) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code, and three ad dress bytes on Serial Data input (DQ0). Any address

inside the subsector is a valid address for the Subsector Erase (SSE) instruction. Chip

Select (S) must be driven Low for the entire duration of the sequence.

Chip Select (S) must be driven High after the eighth bit of the last addre ss by te ha s be en

latched in, otherwise the Subsector Erase (SSE) instruction is not executed. As soon as

Chip Select (S) is driven High, the self-timed Subsector Erase cycle (whose duration is

tSSE) is initiated. While the Subsector Erase cycle is in progress, the Status Register may

be read to check the value of the Write In Progress (WIP) bit. The Write In Prog re ss (WIP)

bit is 1 during the self-timed Subsector Erase cycle, and is 0 when it is completed. At some

unspecified time be fo re the cycle is comp let e, the Write Enable La tch (W EL ) bit is reset .

Alternately , it is possible to read the Flag S tatus Register to check if the internal modify cycle

is finished.

A Subsector Erase (SSE) instruction issued to a sector that is hardware or software

protected, is not executed. Any Subsector Erase (SSE) instruction, while an Erase or

Program cycle is in progress, is rejected without having any effects on the cycle that is in

progress. Any Subsector Erase (SSE) instruction in devices with uniform architecture

(meaning no boot sectors with subsectors) is rejected without having any effects on the

device. A Subsector Erase cycle can be paused by a Program/Erase Suspend ( PES)

instruction and resumed by a Program/Erase Resume (PER) instruction.

Byte

0Byte

1Byte

2Byte

Byte

X X X X X X X bit 0

OTP control byte64 data bytes

Bit 1 to bit 7 are not programmable

When bit 0 = 0

the 64 OTP bytes

become read only

ai13587

N25Q128 - 3 V Instructions

99/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 27. Subsector Erase instruction sequence

9.1.18 Sector Erase (SE)

The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device set s the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code, and three address bytes on Serial Data input (DQ0). Any address inside

the sector is a valid address for the Sector Erase (SE) instruction. Chip Select (S) must be

driven Low for the entire duration of the sequence.

Chip Select (S) must be driven High after the eighth bit of the last addre ss by te ha s be en

latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progr ess (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspecified

time before the cycle is completed, the Write En able Latch (WEL) bit is reset. Alternately, it

is possible to read the Flag Status Register to check if the internal modify cycle is finished.

A Sector Erase (SE) instruction issued to a sector that is hardware or software protected is

not executed

A Sector Erase cycle can be paused by mean of Program/Erase Suspend (PES) instruction

and resumed by mean of Program/Erase Resume (PER) instruction.

24 B it A ddres s

DQ0

Sub sect or_Erase

21 3456789 293031

Instruction

23 22 20

MSB

Instructions N25Q128 - 3 V

100/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 28. Sector Erase instruction sequence

9.1.19 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data input (DQ0). Chip Select (S) must be driven Low for the

entire duration of the sequence.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Bulk Erase instructio n is not executed. As soon as Chip Select (S)

is driven High, the self-timed Bulk Erase cycle (whose d uration is tBE) is initiated. While the

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Wr ite In Progress (WIP) bit is 1 during the self-timed Bulk

Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (W EL) bit is re set. Alternately, it is possible to read the

Flag Status Register to check if the internal modify cycle is finished.

The Bulk Erase (BE) instruction is ignored if one or more sectors are hardware or software

protected. The Bulk Erase cycle cannot be paused by a Program/Erase Suspend (PES)

instruction.

Figure 29. Bulk Erase instruction sequence

24 B it Addres s

DQ0

Sect or_Er ase

21 3456789 293031

Instruction

23 22 2 0

MSB

DQ0

AI13743

21 345670

Instruction

N25Q128 - 3 V Instructions

101/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.20 Program/Erase Suspend

The Program/Erase Suspend instruction allows the controller to interrupt a Program or an

Erase instruction, in particular: Sector Erase, Subsector Erase, Page Program, Dual Input

Page Program, Dual Input Extended Page program, Quad Input Page Program and Quad

Input Extended Page progra m can be suspended and re sumed.

Note: Bulk Erase, Wr ite Status Register, Write Non Vola tile Configuration register, and Program

OTP cannot be suspended.

After a Program/Erase Suspend instr uction the bit 2 of the Flag Status register is

immediately set to 1 and, after a latency time, both the WIP bit of the Status Register and

the Program/Er ase controlle r bit (Not WIP) of the Flag S tatus Register are cleared (to 0 and

to 1 respectively).

The Suspended state is reset if a power-off is performed or after resume.

After a sector erase instruction has been suspended, another erase instruction is not

allowed; however, it is possible to perform program and reading instructions on all the

sectors except the one whose era se cycle is suspended . Any read instruction issued on this

sector outputs Don't Care data.

After a subsector erase instruction has be en suspended, neither an erase instruction or a

program instruction is allowed; only a read instruction is allowed on all sectors except the

one containing the subsector whose erase cycle is suspended. Any read instruction issued

on this sector outputs Don't Care data.

After a program instruction has been suspended, neither a program instruction or an erase

instructions is allowed; however, it is possible to perform a read instruction on all pages

except the one whose program cycle is suspended . Any read instruction issued on this page

outputs Don't Care data.

It is possible to nest a suspend instruction inside a suspend ins truction just once. For

example, you can send to the device an erase instruction and suspend it, and then send a

program instruction and suspend it also. With these two insructions suspended, the next

Program/Erase Resume Instruction resumes the latter instruction, and a seco nd

Program/Erase Resume Instruction resumes the former (or first) instruction.

Table 17. Suspend Parameters

Parameter Condition Typ Max Unit Note

Erase to

Suspend Sector Erase or Erase Resume to

Erase Suspend 500 µs Timing not internally controlled

Program to

Suspend Program Resume to Program

Suspend 5 µs T iming not internally controlled

SSErase to

Suspend Sub Sector Erase or Sub Sector

Erase Resume to Erase Suspend 50 µs Timing not internally controlled

Suspend

Latency Program 7 µs Any Read instruction accepted

Sub Sector Erase 15 µs Any Read instruction accepted

Erase 15 µs Any instruction accepted but SE,

SSE, BE, WRSR, WRNVCR, POTP

Instructions N25Q128 - 3 V

102/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Note: The device can be in only one st ate at a time , su ch as Standby, Program, Erase, an d so on .

Device states are shown in Table 18.: Operations Allowed / Disallowed During Device

States.

9.1.21 Program/Erase Resume

After a Pr ogram/Erase suspend instruction, a Program/Erase Resume instruction is

required to continue performing the suspended Program or Erase sequence.

Program/Erase Resume instruction is ignored if the device is not in a Program/Erase

Suspended st atus. The WIP bit of the Status Register and Program/Er ase controller bit ( Not

WIP) of the Flag Status Register both switch to the bu sy state (1 and 0 respectively) after

Program/Erase Resume instruction until the Program or Erase sequence is completed.

In this case the next Program/Erase Resume Instruction re sumes the more recent

suspended modify cycles, another Pr ogram/Eras e Resume Instruction is needed to r esume

also the former one.

Table 18. Operations Allowed / Disallowed During Device States

Operation

Device States an d Sector (Same/Other) in Which Operation is Allowed/Disallowed (Yes/No)

Standby State Program State Erase State

(SE/SSE)

Subsector

Erase

Suspended

State

Program

Suspended

State

Erase

Suspended

State

Sector Sector Sector Sector Sector Sector

Same Other Same Other Same Other Same Other Same Other Same Other

All Reads

except RDSR /

RFSR Yes Yes No No No No Yes(1) Yes Yes Yes Yes(1) Yes

Array Program:

PP / DIFP /

QIFP / DIEFP /

QIEFP

Yes Yes No No No No No No No No No Yes

Sector EraseYesYesNoNo NoNoNoNoNoNoNoNo

Sub-Sector

Erase Yes Yes No No No No No No No No No No

WRLR / POTP /

BE / WRSR /

WRNVCR Yes No No No No No

WRVCR /

WRVECR Yes No No Yes Yes Yes

RDSR / RFSR Yes Yes Yes Yes Yes Yes

Program /

Erase Suspend No Yes Yes No No No

1. The Read operation is accepted but the data output is not guaranetted until the program or erase has completed.

N25Q128 - 3 V Instructions

103/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.22 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Erase or Write Status

check the Write In Progress (WIP) bit (or the Program/Erase controller bit o f th e Flag St atus

Status Register co ntinuously, as shown here.

Figure 30. Read Status Register instruction sequence

9.1.23 Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

been executed. Af ter the write enable (WREN) instruction has been decoded and executed,

the device sets the write enable latch (WEL).

The write status register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on serial data input (DQ0). The write

status register (WRSR) instruction has no effect on b1 and b0 of the status register.

Chip Select (S) must be driven High after the eighth bi t of the dat a byte has been latched in.

If not, the write status register (WRSR) instruction is not executed. As soon as Chip Select

(S) is driven High, the self-timed write status register cycle (whose duration is tW) is

initiated. While the write status register cycle is in progress, the status register may still be

read to check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1

during the self-timed write status register cycle, and is 0 when it is completed. When the

cycle is completed, the write enable latch (WEL) is reset.

The write status register (WRSR) instruction allows the user to change the values of the

block protect (BP3, BP2, BP1, BP0) bits and the Top/Bottom (TP) bit, to define the size of

the area that is to be treated as read-only, as defined Table 9.: Protected area sizes, Upper

(TB bit = 0) and Table 10.: Protected area sizes, Lower (TB bit = 1). The write status register

(WRSR) instruction also allows the user to set and reset the status register write disable

(SRWD) bit in accordance with the Write Protect (W/VPP) signal. The status register write

disable (SRWD) bit and Write Protect (W/VPP) signal allow the device to be put in the

hardware protected mode (HPM). The write status register (WRSR) instruction is not

executed once the hardware protected mode (H PM) is entered.

DQ0

21 3456789101112131415

Instruction

AI13734

DQ1 76543210

Status register out

High Impedance

MSB

76543210

Status register out

MSB

Instructions N25Q128 - 3 V

104/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 31. Write Status Regist er instruction sequence

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the Status Register provided that the Write Enable

Latch (WEL) bit has previo usly been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect ( W/VPP) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to '1', two

cases need to be considered, depending on the state of Write Protect (W/VPP):

If Write Protect (W/VPP) is driven High, it is possible to write to the Status Register

provided that the Write Enable Latch (WEL) bit has previously been set by a Write

Enable (WREN) instruction.

If Write Protect (W/VPP) is driven Low, it is not possible to write to the Status Register

even if the Write Enable Latch (WEL) bit has been set previously by a Write Enable

(WREN) instruction. Therefore, all data bytes in the memory area that are software

protected (SPM2) by the Block Protect (BP3, BP2, BP1, BP0) bits and the Top/Bottom

(T/B) bit of the Status Register are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected mode (HPM) can be

entered in either of the following ways:

setting the Status Register Write Disable (SRWD) bit after driving Write Protect

(W/VPP) Low

driving Write Protect (W/VPP) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected mode (HPM) once entered is to pull Write

Protect (W/VPP) High.

If Write Protect (W/VPP) is permanently tied High, the Hardware Protected mode (HPM) can

never be activat ed , an d on ly the Software Protected mode (SPM2) using the Block Protect

(BP3, BP2, BP1, BP0) bits and the Top/Bottom (T/B) bit of the Status Register can be used.

DQ0

AI13735

DQ1

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

N25Q128 - 3 V Instructions

105/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.24 Read Lock Register (RDLR)

The device is first selected by driving Chip Select (S) Low . The instruction code for the Read

Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any

location inside the con cerned sector. Each address bit is latched-in durin g the rising edge of

Serial Clock (C). Then the value of the Lock Register is shifted out on Serial Data output

(DQ1), each bit being shifted out, at a maximum frequency fC, during the falling edge of

Serial Clock (C).

The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at

any time during data output.

Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 32. Read Lock Register instruction and data-out sequence

Table 19. Protection modes

W / VPP

Signal SRWD

bit Mode Write protection of the status

Memory content

Protected area (1) Unprotected area (1)

Software

protected

(SPM2)

Status register is writeable, if the

WREN instruction has set the WEL

bit.

The values in the SRWD, TB, BP3,

BP2, BP1, and BP0 bits can be

changed.

Protected against PP,

DIFP, DIEFP, QIFP,

QIEFP, SSE, SE and

BE instructions.

Ready to accept PP,

DIFP, DIEFP, QIFP,

QIEFP, SSE, and SE

instructions.

01Hardware

protected

(HPM)

Status Register is hardwa re write

protected. The values in the

SRWD, TB, BP3, BP2, BP1 and

BP0 bits cannot be changed

PP, DIFP, DIEFP,

QIFP, QIEFP, SSE,

SE and BE

instructions.

PP, DIFP, DIEFP,

QIFP, QIEFP, SSE,

and SE instructions.

1. As defined by the values in the Block Protect (TB, BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 2:

Status register format.

AI13738

21 345678910 2829303132333435

2221 3210

36 37 38

76543 10

High Impedance Lock register out

Instruction 24-bit address

MSB

Instructions N25Q128 - 3 V

106/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.25 Write to Lock Register (WRLR)

The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock

Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed. After the Write Enable (WREN) instruction has been decoded, the

device sets the Write Enable Latch (WEL).

The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code, three address bytes (pointing to any address in the

targeted sector and one data byte on Serial Data input (DQ0). The instruction sequence is

shown in Figure 22. Chip Select (S) must be driven High after the eigh th bit of the dat a byte

has been latched in, otherwise the Write to Lock Register (WRLR) instruction is not

executed.

Lock Register bits are volatile, and therefore do not require time to be written. When the

Write to Lock Register (WRLR) instruction has been succ essfully executed, the Write

Enable Latch (WEL) bit is reset after a delay time less than tSHSL minimum value.

Any Write to Lock Register (WRLR) instruction while an Erase or Program cycle is in

progress is rejected without having any effects on the cycle that is in progress.

Figure 33. Write to Lock Register instruction sequence

Table 20. Lock Register out(1)

Bit B it name Value Function

b7-b2 Reserved

b1 Sector Lock

Down ‘1’ The Write Lock and Lock Down bits cannot be changed. Once a ‘1’ is written to the

Lock Down bit it cannot be cleared to ‘0’, except by a power-up.

‘0’ The Write Lock and Lock Down bits can be changed by writing new values to them.

b0 Sector

Write Lock

‘1’ Program and Erase operations in this sector will not be executed. The memory

contents will not be changed.

‘0’ Program and Erase operations in this sector are executed and will modify the sector

contents.

1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.

AI13740

DQ0

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-bit address

765432 0

Lock register

MSB MSB

N25Q128 - 3 V Instructions

107/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9.1.26 Read Flag Status Register

The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be

read. The Status Register may be read at any time, even while a Program or Erase is in

progress. When one of these cycles is in progress, it is recommended to check the P/E

Controller bit (Not WIP) bit before sending a new instruction to the device. It is also possible

to read the Flag Register co ntinuously, as shown here.

Figure 34. Read Flag Status Register instruction sequence

9.1.27 Clear Flag Status Register

The Clear Flag Status Regi ster (CLFSR) instructio n reset th e error Flag Status Register bit s

(Erase Error bit, Prog ram Erro r bit, VPP Err or bit, Pr otection Error bit). It is not necessary to

set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit

will be unchanged after this command is executed.

Tab le 21. Lock Register in (1)

1. Values of (b1, b0) after power-up are defined in Section 7: Protection modes.

Sector Bit Value

All sectors

b7-b2 ‘0’

b1 Sector Lock Down bit value (refer to Table 20)

b0 Sector Write Lock bit value (refer to Table 20)

DQ0

21 3456789101112131415

Instruction

Read_Flag_SR

DQ1 76543210

Flag Status Register Out

High Impedance

MSB

76543210

Flag Status Register Out

MSB

Instructions N25Q128 - 3 V

108/183

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 35. Clear Flag Status Register instruction sequence

9.1.28 Read NV Configuration Register

The Read Non V olatile Conf iguration Register (RDNVCR) instruction allows the Non V o latile

Configuration Register to be read.

Figure 36. Read NV Configuration Register instruction seque nce

9.1.29 Write NV Configuration Register

The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to

be written to the Non Volatile Configuration register. Before it can be accepted, a write

enable (WREN) instruction must pre vio us ly hav e be en exec u ted. After the write en ab le

(WREN) instruction ha s be en de co de d a nd exec uted, the de vice sets the write enable latch

(WEL).

The Write Non Volatile Configuration register (WRNVCR) instruction is entered by driving

Chip Select (S) Low , followed by the instruction code and the data bytes on serial data input

(DQ0). Chip Select (S) must be driven High after the 16th bit of the data bytes has been

latched in. If not, the Write Non Volatile Configuration register (WRNVCR) instruction is not

DQ0

Clear_Flag_SR

DQ1

21 345678

High Impedance

Instruction

MSB

DQ0

21 3456789101112131415

Instruction

Read_NVCR

DQ1 76543210

NVCR Out

High Impedance

LS Byte

15 14 13 12 11 10 9 8

NVCR Out

MS Byte

16 17 18 19 20 21 22 23

N25Q128 - 3 V Instructions

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

executed. As soo n as Ch ip Sele ct (S ) is driven High, the self-timed write NV configuration

While the Write Non Volatile Configuration register cycle is in progress, it is possible to

monitor the end of the process by polling status Register write in progress (WIP) bit or the

Flag Status Register Program/Erase Controller bit. The write in progress (WIP) bit is 1

during the self-timed Write Non Volatile Configuration register cycle, and is 0 when it is

completed. When the cycle is complete d, the write enable latch (WEL) is reset.

The Write Non Volatile Configuration register (WRNVCR) instruction allows the user to

change the values of all the Non Volatile Configuration Register bits, described in Table 3.:

Non-Volatile Configuration Register.

The Write Non Volatile Configuration Register impacts the memory behavior only after the

next power on sequence.

Figure 37. Write NV Configuration Register instruction sequence

9.1.30 Read Volatile Configuration Register

The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile

Configuration Register to be read. See Table 5.: Volatile Configuratio n Register.

DQ0

Write_NVCR

DQ1

21 3456789101112131415

High Impedance

Instruction NVCR In

765432 0

LS Byte

15 14 13 12

16 17 18 19 20

Byte Byte

MS Byte

11 10 9 8

21 22 23 24

Instructions N25Q128 - 3 V

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Figure 38. Read Volatile Configuration Register instruction sequence

9.1.31 Write Volatile Configuration Register

The Write Volatile Configuration register (WRVCR) instruction allows new values to be

written to the Volatile Configuration register. Before it can be accepted, a write enable

(WREN) instruction must have been executed. After the write enable (WREN) instruction

has been decoded and executed, the device sets the write enable latch (WEL).

In case of Fast POR, the WREN instruction is not required be ca us e a W REN ins tru ct ion

gets the device out from the Fast POR state.

The Write Volatile Configuration register (WRVCR ) instruction is entered by driving Chip

Select (S) Low, followed by the ins t ruction code and the da ta byte on seri al da ta input

(DQ0).

Chip Select (S) must be driven High af ter the e ighth b it o f the data byte has been latched in.

If not, the Write Volatile Configuration register (WRVCR) instruction is not executed.

When the new data are latched, the write enable latch (WEL) is reset.

The Write Volatile Configuration register (WR VCR) instruction allows the u ser to change the

values of all the Volatile Configuration Register bits, described in Table 5.: Volatile

Configuration Register.

The Write Volatile Configuration Register impacts the memory behavior right after the

instruction is received by the device.

DQ0

21 3456789101112131415

Instruction

Read_VCR

DQ1 76543210

Volatile Conguration

High Impedance

MSB

76543210

MSB

Volatile Conguration

N25Q128 - 3 V Instructions

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Figure 39. Write Volatile Configuration Register instruction sequence

9.1.32 Read Volatile Enhanced Configuration Register

The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the

Volatile Configuration Register to be read.

Figure 40. Read Volatile Enhanced Configuration Register instruction sequence

9.1.33 Write Volatile Enhanced Configuration Register

The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new

values to be written to the Volatile Enhanced Configuration register. Before it can be

accepted, a write enable (WREN) instruction must previously have been executed. After the

write enable (WREN) instruction has been decoded a nd execute d, the device sets the write

enable latch (WEL). In case of Fast POR, the WREN instruction is not required because a

WREN instruction gets the device out from the Fast POR state (s ee Section 11.1: Fast

POR).

DQ0

Write_VCR

DQ1

21 3456789101112131415

High Impedance

Instruction Volatile Conguration

765432 0

MSB

DQ0

21 3456789101112131415

Instruction

Read_VECR

DQ1 76543210

Volatile Enhanced

Conguration Register Out

High Impedance

MSB

76543210

MSB

Volatile Enhanced

Conguration Register Out

Instructions N25Q128 - 3 V

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The Write Volatile Enhanced Configuration r egister (WRVECR) instruction is entered by

driving Chip Select (S) Low , followed by th e instruction code and the da ta byte on serial dat a

input (DQ0).

Chip Select (S) must be driven High af ter the e ighth b it o f the data byte has been latched in.

If not, the Write Volatile Enhanced Configuration register (WRVECR) instruction is not

executed.

When the new data are latched, the write enable latch (WEL) is reset.

The Wr ite V olatile Enhanced Configur ation register (WR VECR) instruction allows the user to

change the values of all the Volatile Enhanced Configuration Register bits, described in

Table 6.: Volatile Enhanced Configuration Register.

The Wr ite V olatile Enhance d Configuration Register imp acts the memory be havior right af ter

the instruction is received by the device.

Figure 41. Write Volatile Enhanced Configuration Register instruction sequence

9.2 DIO-SPI Instructions

In DIO-SPI protocol, instructions, addr esses and input/Output dat a always run in p arallel on

two wires: DQ0 and DQ1.

In the case of a Dual Command Fast Read (DCFR), Read OTP (ROTP), Read Lock

Registers (RDLR), Read Status Register (RDSR), Read Flag Status Re gister (RFSR), Read

NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),

Read Volatile Enhanced Configuration Register (RDVECR) and Multiple I/O Read

Identification (MIORDID) instruction, the shifted-in instruction sequence is followed by a

data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a Dual Command Page Program (DCPP), Program OTP (POTP), Subsector

Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),

Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register

DQ0

Write_VECR

DQ1

21 3456789101112131415

High Impedance

Instruction VECR In

765432 0

MSB

N25Q128 - 3 V Instructions

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(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRV CR),

Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration

Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is

rejected, and is not executed.

All attempts to access the memory array during a Write Status Register cycle, a Write Non

Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the

internal Write Status Register cycle, Write Non Volatile Configuration Register, Program

cycle or Erase cycle continues unaffected, the only exception is the Program/Erase

Suspend instruction (PES), that can be used to pause all the program and the erase cycles

but the Program OTP (POTP), Write Status Register (WRSR), Bulk Erase (BE), and Write

Non Volatile Configuration Register. The suspended program or erase cycle can be

resumed by mean of the Program/Erase Resume instruction (PER). During the

program/erase cycles also the polling instructions (to check if the internal modify cycle is

finished by mean of the WIP bit of the Status Register or of the Pr ogra m/Erase contr oller bit

of the Flag Status register) are also accepted to allow the application checking the end of

the internal modify cycles, of course these polling instructions don't affect the internal cycles

performing.

Table 22. Instruction set: DIO-SPI protocol (page 1 of 2)

Instruction Description One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code

(HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

MIORDID Multiple I/O read identification 1010 1111 AFh 0 0 1 to 3

DCFR Dual Command Fast Read

0000 1011 0Bh 3 8 (1) 1 to ∞

0011 1011 3Bh 3 8(1) 1 to ∞

1011 1011 BBh 3 8 (1) 1 to ∞

ROTP Read OTP 0100 1011 4Bh 3 8 (1) 1 to 65

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

DCPP Dual Command Page Program

0000 0010 02h 3 0 1 to 256

1010 0010 A2h 3 0 1 to 256

1 101 0010 D2h 3 0 1 to 256

POTP Program OTP 0100 0010 42h 3 0 1 to 65

SSE (2) SubSector Erase 0010 000 0 20h 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

PER Program/Erase Resume 0111 1010 7Ah 0 0 0

PES Program/Erase Suspend 0111 0101 75h 0 0 0

RDSR Read Status Registe r 0000 010 1 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

RDLR Read Lock Register 1110 1000 E8h 3 0 1 to ∞

Instructions N25Q128 - 3 V

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1) The number of Dummy Clock cycles is configurable by the user

2) SSE is only available in devices with Bottom or Top architecture.

9.2.1 Multiple I/O Read Identification protocol

The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the

device identification data in the DIO-SPI protocol:

– Manufacturer identification (1 byte)

– Device identification (2 bytes)

Unlike the RDID instructio n of th e Exte n ded SPI pr ot oc ol, th e Mu ltip le In pu t/ Ou tp ut

instruction cannot read the Unique ID code (UID) (17 bytes). For further details on the

manufacturer and device identification codes please refer to Section 9.1.1: Read

Identification (RDID).

Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or

Program cycle is in progress, is not decoded, and has no effect on the cycle that is in

progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit

device identification, stored in the memory, will be shifted out on again in parallel on DQ1

and DQ0. Each two bit s are shifted out during the fa lling edge of Serial Clock (C).

The Read Identification (RDID) instr uction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in

the Standby Power mode, the device waits to be selected, so that it can receive, decode,

and execute instructions.

WRLR Write to Lock Register 1110 0101 E5h 3 0 1

RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞

CLFSR Clear Flag Status Register 0101 0000 50h 0 0 0

RDNVCR Read NV Configuration Register 1011 0101 B5h 0 0 2

WRNVCR Write NV Configuration Register 1011 0001 B1h 0 0 2

RDVCR Read Volatile Configuration Register 1000 0101 85h 0 0 1 to ∞

WRVCR Write Volatile Configuration Register 1000 0001 81h 0 0 1

RDVECR Read Volatile Enhanced Configuration

WRVECR Write Volatile Enhanced Configuration

Table 22. Instruction set: DIO-SPI protocol (page 2 of 2)

Instruction Description One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code

(HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

N25Q128 - 3 V Instructions

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Figure 42. Multiple I/O Read Identification instruction and data-out sequence DIO-

SPI

9.2.2 Dual Command Fast Read (DCFR)

The Dual Command Fast Read (DCFR) instruction allows to read th e memory in DIO-SPI

protocol, parallelizing the instruction code, the address and the output data on two pins

(DQ0 and DQ1). The Dual Command Fast Read (DCFR) instruction can be issued, when

the device is set in DIO-SPI mode, by sending to the memory indifferently one of the 3

instructions codes: 0Bh, 3Bh or BBh , the ef fe ct is exactly the same. The 3 instruction codes

are all accepted to help the applicat ion code porting from Extended SPI protocol to DIO-SPI

protocol.

Except for the parallelizing on two pins of the instruction code, the Dual Comm and Fast

Read instruction functionality is exactly the same as the Dual I/O Fast Re ad of the Extended

SPI protocol.

Note: The dummy bits can not be parallelized since these clock cycles are requested to perform

the internal reading operation.

Figure 43. Dual Command Fast Read instruction and data-out sequence DIO-SPI

213456780

910

11 12 13 14 15

AFh MAN.

code

DEV.

code

SIZE

code

6420

7531

DQ0

DQ1

6420

7531

6420

7531

Dual_Command_Fast_Read

Ins truction 24-B it A ddres s

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

6420

7531

MSBMSB

75 1

64 0

Data Out 1

64 0

Data Out n

75 1

12 13 14 1521 345678 9 10 11

016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Dummy cycles

Instructions N25Q128 - 3 V

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9.2.3 Read OTP (ROTP)

The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the DIO-SPI

protocol. The instruction functionality is exactly the same as the Read OTP instruction of the

Extended SPI protocol; the only difference is that in the DIO-SPI protocol instruction code,

address and output dat a are all parallelized on the two pins DQ0 and DQ1.

Note: The dummy bits can not be parallelized since these clock cycles are requested to perform

the internal reading operation.

Figure 44. Read OTP instruction and data-out sequence DIO-SPI

9.2.4 Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit.

Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the

instruction functionality is exactly the same as the W rite Enable (WREN) instruction of the

Extended SPI protocol.

Figure 45. Write Enable instruction sequence DIO-SPI

Dual_Read_OTP

Instruction 24-B it Addres s

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

6420

7531

MSBMSB

75 1

64 0

Data Out 1

64 0

Data Out n

75 1

12 13 14 1521 345678 9 10 11

016 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

Dummy cycles

DQ0

Dual_Write_Enable

DQ1

2134

Instruction

N25Q128 - 3 V Instructions

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9.2.5 Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.

Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the

instruction functionality is exactly the same as the W rite Disable (WRDI) instruction of the

Extended SPI protocol, please refer to Section 9.1.10: Write Disable (WRDI) for further

details.

Figure 46. Write Disable instruction sequence DIO-SPI

9.2.6 Dual Command Page Program (DCPP)

The Dual Command Page Program (DCPP) instruction allows to program the memory

content in DIO-SPI protocol, parallelizing th e instruction code, the address and the input

data on two pins (DQ0 and DQ1). Before it can be accepted, a Write Enable (WREN)

instruction must previously have been executed. The Dual Command Page Program

(DCPP) instruction can be issued, when the device is set in DIO-SPI mode, by sending to

the memory ind ifferently on e of the 3 ins tru ctions codes: 02h, A2h or D2h, the effect is

exactly the same. The 3 instruction codes are all accepted to help the application code

porting from Extended SPI protocol to DIO-SPI protocol.

Apart for the parallelizing on two pins of the instruction code, the Dual Command Page

Program instruction functionality is exac tly the same as the Dual Input Extended Fast

Program of the Extended SPI protocol.

Dual_Write_Disab

2134

Instruction

Instructions N25Q128 - 3 V

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Figure 47. Dual Command Page Program instruction sequence DIO-SPI, 02h

Figure 48. Dual Command Page Program instruction sequence DIO-SPI, A2h

Figure 49. Dual Command Page Program instruction sequence DIO-SPI, D2h

Dual_Page_Program_02h

Ins truction 24-B it A ddres s

12 13 14 15

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

16 17 18 19

75 1

64 0

Data By te 2

64 0

Data By te 2 56

75 1

20 21 22 23

Data By te 1

1036

1037

1038

1039

Dual_Page_Program_A2h

Ins truction 24-B it A ddres s

12 13 14 15

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

16 17 18 19

75 1

64 0

Data By te 2

64 0

Data By te 2 56

75 1

20 21 22 23

Data By te 1

1036

1037

1038

1039

Dual_Page_Program_D2h

Ins truction 24-B it Addres s

12 13 14 15

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

16 17 18 19

75 1

64 0

Data By te 2

64 0

Data By te 25 6

75 1

20 21 22 23

Data By te 1

1036

1037

1038

1039

N25Q128 - 3 V Instructions

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9.2.7 Program OTP instruction (POTP)

The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP

memory area (by ch anging bit s from 1 to 0, only). Befo re it can be accep ted, a W rite Enable

(WREN) instruction must previously have been executed.

Except for the parallelizing of the instruction code, address and input data on the two pins

DQ0 and DQ1, the ins tru ction functionality (as well as the locking OTP method) is exactly

the same as the Program OTP (POTP) instruction of the Extended SPI protocol, please

refer to Section 9.1.16: Program OTP instruction (POTP) for further details.

Figure 50. Program OTP instruction sequence DIO-SPI

9.2.8 Subsector Erase (SSE)

For devices with bottom or top architec ture, at the bottom (or top) of the addressable area

there are 8 boo t sect or s, ea ch one hav ing 16 4Kbytes subsectors. The Subsector Erase

(SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector. Before it can be

accepted, a Write Enable (WREN) instruction must previously have been executed.

Except for the parallelizing of the instr uction co de and the ad dress on the two pins DQ0 and

DQ1, the instruction functionality is exactly the same as the Subsector Erase (SSE)

instruction of the Extended SPI protocol, please refer to Section 9.1.17: Subsector Erase

(SSE) for further details.

Ins truction 24-B it A ddres s Data By te 1

12 13 14 15

Dual_Program_OTP

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

16 17 18 19

75 1

375 1

64 0

Data By te 2 Data Byte n

20 21 22 23 24 25 26 27

Instructions N25Q128 - 3 V

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Figure 51. Subsector Erase instruction sequence DIO-SPI

9.2.9 Sector Erase (SE)

The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

Except for the parallelizing of the instr uction co de and the ad dress on the two pins DQ0 and

DQ1, the instruction functionality is exactly the same as the Sector Erase (SE) instruction of

the Extended SPI prot ocol, please refer to Section 9.1.18: Sector Erase (SE) for further

details.

Figure 52. Sector Erase instruction sequence DIO-SPI

Instruction 24-B it Addres s

12 13 14 15

Dual_Subsector_Era

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

6420

7531

Instruction 24-B it Addres s

12 13 14 15

Dual_Sector_Era

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

6420

7531

N25Q128 - 3 V Instructions

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9.2.10 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write

Enable (WREN) ins tru ct ion mu st pr eviously have been exec uted.

Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the

instruction functionality is exactly the same as the Bulk Erase (BE) instruction of the

Extended SPI protocol, please refer to Section 9.1.19: Bulk Erase (BE) for further details.

Figure 53. Bulk Erase instruction sequen ce DIO-SPI

9.2.11 Program/Erase Suspend

The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program

or an Erase instruction, in particular: Subsector Erase (SSE), Sector Erase (SE) and Dual

Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),

Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and

Program OTP (POTP) cannot be suspended.

Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the

instruction functionality is exactly the same as the Program/Erase Suspend (PES)

instruction of the Extended SPI protocol.

DQ0

Dual_Bulk_Era

2130

Instruction

DQ1

Instructions N25Q128 - 3 V

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Figure 54. Program/Erase Suspend instruction sequence DIO-SPI

9.2.12 Program/Erase Resume

After a Pr ogram/Erase suspend instruction, a Program/Erase Resume instruction is

required to continue performing the suspended Program or Erase sequence.

Except for the parallelizing of the instruction code on the two pins DQ0 and DQ1, the

instruction functionality is exactly the same as the Program/Erase Resume (PER)

instruction of the Extended SPI protocol, please refer to Section 9.1.21: Program/Erase

Resume for further details.

Figure 55. Program/Erase Resume instruction sequence DIO-SPI

Dual_Program_Erase_Suspen

21340

Instruction

Dual_Program_Erase_Resum

21340

Instruction

N25Q128 - 3 V Instructions

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9.2.13 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. Except

for the parallelizing of the instruction code and the output data on the two pins DQ0 and

DQ1, the instruction functionality is exactly the same as the Read Status Register (RDSR)

instruction of the Extended SPI protocol, please refer to Section 9.1.22: Read Status

Figure 56. Read Status Register instruction sequence DIO-SPI

9.2.14 Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

been executed. Except for the parallelizing of the instruction code and the input data on the

two pins DQ0 and DQ1, the instruction functionality and the protection feature management

is exactly the same as the Write Status Register (WRSR) instruction of the Extended SPI

protocol, please refer to Section 9.1.23: Write status register (WRSR) for further details.

Figure 57. Write Status Register instruction sequence DIO-SPI

Status Register Out

DQ0

DQ1

Dual_Read_SR

Instruction Byte Byte

21 345678 9 10 11

6420

7531

6420

7531

Status Register In

DQ0

DQ1

Dual_Write_SR

Instruction Byte

21 345670

6420

7531

Instructions N25Q128 - 3 V

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9.2.15 Read Lock Register (RDLR)

The Read Lock Register instruction is used to read the lock register content.

Except for the paralle lizing of the instruction code, the address and the output data on the

two pins DQ0 and DQ1, the instruction functionality is exactly the same as the Read Lock

Read Lock Register (RDLR) for further details.

Figure 58. Read Lock Register instruction and data-out sequence DIO-SPI

9.2.16 Write to Lock Register (WRLR)

The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock

Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed.

Except for the parallelizing of the instruction code, the address and the input data on the two

pins DQ0 and DQ1, the instruction functionality is exactly the same as the Write to Lock

Write to Lock Register (WRLR) for further details.

Ins truction 24-B it Addres s Lock R egister Out

12 13 14 15

Dual_Read_L

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

12 13 14 15

N25Q128 - 3 V Instructions

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Figure 59. Write to Lock Register instruction sequence DIO-SPI

9.2.17 Read Flag Status Register

The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be

read.

Except for the parallelizing of the instruction code and the output data on the two pins DQ0

and DQ1, the instruction functionality is exactly th e same as the Read Flag Status Register

(RFSR) instruction of the Extended SPI protocol, please refer to Section 9.1.26: Read Flag

Status Register for further details.

Figure 60. Read Flag Status Register instruction sequence DIO-SPI

Ins truction 24-B it Addres s Lock Register In

12 13 14 15

Dual_Write_L

21 345678 9 10 11

22 20 18 16

23 21 19 17

14 12 10 8

15 13 11 9

642064 0

753175 1

12 13 14 15

Dual_Read_Flag_SR

Flag Status Register Out

DQ0

DQ1

Instruction

Byte Byte

21 345678 9 10 11

6420

7531

6420

7531

Instructions N25Q128 - 3 V

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9.2.18 Clear Flag Status Register

The Clear Flag Status Regi ster (CLFSR) instructio n reset th e error Flag Status Register bit s

(Erase Error bit, Prog ram Erro r bit, VPP Err or bit, Pr otection Error bit). It is not necessary to

set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit

will be unchanged after this command is executed.

Figure 61. Clear Flag Status Register instruction sequence DIO-SPI

9.2.19 Read NV Configuration Register

The Read Non V olatile Conf iguration Register (RDNVCR) instruction allows the Non V o latile

Configuration Register to be read.

Figure 62. Read NV Configuration Register instruction seque nce DIO-SPI

DQ0

DQ1

Dual_Clear_Flag_SR

Instruction

2130

NVCR Out

LS Byte MS Byte

DQ0

DQ1

Dual_Read_NVCR

Instruction Byte Byte

21 345678 9 10 11

6420

7531

14 12 10 8

15 13 11 9

N25Q128 - 3 V Instructions

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9.2.20 Write NV Configuration Register

The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to

be written to the Non Volatile Configuration register. Before it can be accepted, a write

enable (WREN) instruction must previou sly ha ve been executed.

Except for the paralle lizing of the instruction code and the input data on the two pins DQ0

and DQ1, the instruction functionality is exactly the same as the W rite Non Volatile

Configuration Register (WNVCR) instruction of the Extended SPI protocol, please refer to

Section 9.1.29: Write NV Configuration Register for further details.

Figure 63. Write NV Configuration Register instruction sequence DIO-SPI

9.2.21 Read Volatile Configuration Register

The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile

Configuration Register to be read. See Table 5.: Volatile Configuratio n Register.

NVCR In

LS Byte MS Byte

DQ0

DQ1

Dual_Write_NVCR

Instruction Byte Byte

21 345678 9 10 11

6420

7531

14 12 10 8

15 13 11 9

Instructions N25Q128 - 3 V

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Figure 64. Read Volatile Configuration Register instruction sequence DIO-SPI

9.2.22 Write Volatile Configuration Register

The Write Volatile Configuration register (WRVCR) instruction allows new values to be

written to the Volatile Configuration register. Before it can be accepted, a write enable

(WREN) instruction must have been executed previously. In case of Fast POR, the WREN

instruction is not required because a WREN instruction gets the device out from the Fast

POR state (See Section 11.1: Fast POR).

Except for the paralle lizing of the instruction code and the input data on the two pins DQ0

and DQ1, the instruction functionality is exa ctly the same as the W rite Volatile Configuration

Write Volatile Configuration Register for further details.

Figure 65. Write Volatile Configuration Register instruction sequence DIO-SPI

Dual_Read_VCR

Volatile Conguration

DQ0

DQ1

Instruction Byte Byte

21 345678 9 10 11

6420

7531

6420

7531

Volatile Conguration

DQ0

DQ1

Instruction Byte

21 345678 9 10 11

6420

7531

N25Q128 - 3 V Instructions

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9.2.23 Read Volatile Enhanced Configuration Register

The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the

Volatile Configuration Register to be read.

Figure 66. Read Volatile Enhanced Configuration Register instruction sequence

DIO-SPI

9.2.24 Write Volatile Enhanced Configuration Register

The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new

values to be written to the Volatile Enhanced Configuration register. Before it can be

accepted, a write enable (WREN) instruction must previously have been executed. In case

of Fast POR, the WREN instruction is not required because a WREN instruction gets the

device out from the Fast POR state (See Section 11.1: Fast POR).

Except for the paralle lizing of the instruction code and the input data on the two pins DQ0

and DQ1, the instruction functionality is exactly the same as the Write Volatile Enhanced

Configuration Register (WRVECR) instruction of the Exten ded SPI protocol, please refer to

Section 9.1.33: Write Volatile Enhanced Configuration Register for fu rther details.

Volatile Enhanced

Conguration Register Out

Dual_Read_VECR

DQ0

DQ1

Instruction Byte Byte

21 345678 9 10 11

6420

7531

6420

7531

Instructions N25Q128 - 3 V

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Figure 67. Write Volatile Enhanced Configuration Register instruction sequence

DIO-SPI

9.3 QIO-SPI Instructions

In QIO-SPI protocol, i nstructions, addresses and Input/Output dat a always run in p arallel on

four wires: DQ0, DQ1, DQ2 and DQ3 with the already mentioned exception of the modify

instruction (erase and program) performed with the VPP=VPPh.

In the case of a Quad Command Fast Read (QCFR), Read OTP (ROTP), Read Lock

Registers (RDLR), Read Status Register (RDSR), Read Flag Status Re gister (RFSR), Read

NV Configuration Register (RDNVCR), Read Volatile Configuration Register (RDVCR),

Read Volatile Enhanced Configuration Register (RDVECR) and Multiple Read I/O

Identification (MIORDID) instruction, the shifted-in instruction sequence is followed by a

data-out sequence. Chip Select (S) can be driven High after any bit of the data-out

sequence is being shifted out.

In the case of a Quad Command Page Program (QCPP) , Program OTP (POTP), Subsector

Erase (SSE), Sector Erase (SE), Bulk Erase (BE), Program/Erase Suspend (PES),

Program/Erase Resume (PER), Write Status Register (WRSR), Clear Flag Status Register

(CLFSR), Write to Lock Register (WRLR), Write Volatile Configuration Register (WRV CR),

Write Volatile Enhanced Configuration Register (WRVECR), Write NV Configuration

Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is

rejected, and is not executed.

All attempts to access the memory array during a Write Status Register cycle, a Write Non

Volatile Configuration Register, a Program cycle or an Erase cycle are ignored, and the

internal Write Status Register cycle, Write Non Volatile Configuration Register, Program

cycle or Erase cycle continues unaffected, the only exception is the Program/Erase

Suspend instruction (PES), that can be used to pause all the program and the erase cycles

but the Program OTP (POT), Write Status Register (WRSR), Bulk Erase (BE), and Write

Non Volatile Configuration Register. The suspended program or erase cycle can be

resumed by mean of the Program/Erase Resume instruction (PER). During the

program/erase cycles also the polling instructions (to check if the internal modify cycle is

Volatile Enhanced

Conguration Register In

DQ0

DQ1

Instruction Byte

21 345678 9 10 11

6420

7531

N25Q128 - 3 V Instructions

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finished by mean of the WIP bit of the Status Register or of the Pr ogra m/Erase contr oller bit

of the Flag Status register) are also accepted to allow the application checking the end of

the internal modify cycles, of course these polling instructions don't affect the internal cycles

performing.

Table 23. Instruction set: QIO-SPI protocol (page 1 of 2)

Instruction Description One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code

(HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

MIORDID Multiple I/O read identification 1010 1111 AFh 0 0 1 to 3

QCFR Quad Command Fast Read

0000 1011 0Bh 3 10 (1) 1 to ∞

0110 1011 6Bh 3 10 (1) 1 to ∞

1110 1011 EBh 3 10 (1) 1 to ∞

ROTP Read OTP (Read of OTP area) 0100 1011 4Bh 3 10 (1) 1 to 65

WREN W rite Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

QCPP Quad Command Page Program

0000 0010 02h 3 0 1 to 256

0011 0010 32h 3 0 1 to 256

0001 0010 12h 3 0 1 to 256

POTP Program OTP (Program of OTP

area) 0100 0010 42h 3 0 1 to 65

SSE(2) SubSector Erase 0010 0000 20h 3 0 0

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

PER Program/Erase Resume 0111 1010 7Ah 0 0 0

PES Program/Erase Suspend 0111 0101 75h 0 0 0

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR W r ite Status Register 0000 0001 01h 0 0 1

RDLR Read Lock Register 1110 1000 E8h 3 0 1 to ∞

WRLR Write to Lock Register 1110 0101 E5h 3 0 1

RFSR Read Flag Status Register 0111 0000 70h 0 0 1 to ∞

CLFSR Clear Flag Status Register 0101 0000 50h 0 0 0

RDNVCR Read NV Configuration Registe r 1011 0101 B5h 0 0 2

WRNVCR Write NV Configuration Register 1011 0001 B1h 0 0 2

RDVCR Read Volatile Configuration Register 1000 0101 85h 0 0 1 to ∞

WRVCR Write Volatile Configuration Register 1000 0001 81h 0 0 1

Instructions N25Q128 - 3 V

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1) The number of Dummy Clock cycles is configurable by the user.

2) SSE is only available in devices with Bottom or Top architecture

9.3.1 Multiple I/O Read Identification (MIORDID)

The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the

device identification data in the QIO-SPI protocol:

Manufacturer identification (1 byte)

Device identification (2 bytes)

Unlike the RDID instructio n of th e Exte n ded SPI pr ot oc ol, th e Mu ltip le In pu t/ Ou tp ut

instruction can not read the Unique ID code (UID) (17 bytes).

For further details on the manufacturer and device identification codes, see 9.1.1: Read

Identification (RDID).

Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or

Program cycle is in progress, is not decoded, and has no effect on the cycle that is in

progress.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in parallel on the 4 pins DQ0, DQ1, DQ2 and DQ3. After this, the

24-bit device identification, stored in the memory, will be shifted out on again in parallel on

DQ0, DQ1, DQ2 and DQ3. The identification bits are shifted out 4 at a time during the falling

edge of Serial Clock (C).

The Read Identification (RDID) instr uction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in

the S tan dby Power mode, the device waits to be selected, so that it can receive , decode and

execute instructions.

Multiple I/O Read Identification (MIORDID) instruction sequ e nc e an d da ta-out seque nce

QIO-SPI.

RDVECR Read Volatile Enhanced

Configuration Register 011 0 0101 65h 0 0 1 to ∞

WRVECR W r ite Volatile Enhanced

Configuration Register 0110 0001 61h 0 0 1

Table 23. Instruction set: QIO-SPI protocol (page 2 of 2)

Instruction Description One-byte

Instruction

Code (BIN)

One-byte

Instruction

Code

(HEX)

Address

bytes

Dummy

clock

cycle

Data

bytes

N25Q128 - 3 V Instructions

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Figure 68. Multiple I/O Read Identification instruction and data-out sequence QIO-

SPI

9.3.2 Quad Command Fast Read (QCFR)

The Quad Command Fast Read (QCFR) instruction allows to read the memory in QIO-SPI

protocol, parallelizing the instruction code, the address and the output data on four pins

(DQ0, DQ1, DQ2 and DQ3). The Quad Command Fast Read (QCFR) instruction can be

issued, after the device is set in QIO-SPI mode, by sending to the memory indifferently one

of the 3 instructions codes: 0Bh, 6Bh or EBh, the effect is exactly the same. The 3

instruction codes are all accepted to help the application code porting from Extended SPI

protocol to QIO- SPI pr otocol.

Apart for the parallelizing on four pins of the instru ctio n code, th e Qu ad Com m an d Fas t

Read instruction functionality is exactly the same as the Quad I/O Fast Read of the

Extended SPI protocol, please refer to Section 9.1.7: Quad I/O Fast Read for further details.

Quad_Multi_Read_IO

21 3456780

910

11 12 13 14 15

5151 51

6262 62

7373 73

DQ0 4040 40

DQ1

DQ2

DQ3

AFh MAN.

code

DEV.

code

SIZE

code

Instructions N25Q128 - 3 V

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Figure 69. Quad Command Fast Read instruction and data-out sequence QIO-SPI,

0Bh

Figure 70. Quad Command Fast Read instruction and data-out sequence QIO-SPI,

6Bh

21 3456780

Mode 3

Mode 0

Quad_Command_Fast_Read_0B

910

5151

40 04

51 15

73 37

Q3 7373

DQ2 6262

62 26

Byte 1 Byte 2

Dummy (ex.: 10)

A23-16 A15-8 A7-0

4040

IO switches from Input to Output

Instruction

404040

515151

626262

737373

15 16 17 18 20

19 21 23

22 24

Byte 3 Byte 4

25 26 27

4040

Byte 5 Byte 6

21 3456780

Mode 3

Mode 0

Quad_Command_Fast_Read_EB

910

5151

40 04

51 15

73 37

Q3 7373

DQ2 6262

62 26

Byte 1 Byte 2

Dummy (ex.: 10)

A23-16 A15-8 A7-0

4040

IO switches from Input to Output

Instruction

404040

515151

626262

737373

15 16 17 18 20

19 21 23

22 24

Byte 3 Byte 4

25 26 27

4040

Byte 5 Byte 6

N25Q128 - 3 V Instructions

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Figure 71. Quad Command Fast Read instruction and data-out sequence QIO-SPI,

EBh

9.3.3 Read OTP (ROTP)

The Read OTP (ROTP) instruction is used to read the 64 bytes OTP area in the QIO-SPI

protocol. The instruction functionality is exactly the same as the Read OTP instruction of the

Extended SPI protocol. The only difference is that in the QIO-SPI protocol instruction code,

address and output dat a are all parallelized o n the four pins DQ0, DQ1, DQ2 and DQ3.

Note: The dum m y byt e bits can not be parallelized: 8 clo ck c ycle s ar e re qu es te d to per fo rm the

internal reading operation.

21 3456780

Mode 3

Mode 0

Quad_Command_Fast_Read_EB

910

5151

40 04

51 15

73 37

Q3 7373

DQ2 6262

62 26

Byte 1 Byte 2

Dummy (ex.: 10)

A23-16 A15-8 A7-0

4040

IO switches from Input to Output

Instruction

404040

515151

626262

737373

15 16 17 18 20

19 21 23

22 24

Byte 3 Byte 4

25 26 27

4040

Byte 5 Byte 6

Instructions N25Q128 - 3 V

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Figure 72. Read OTP instruction and data-out sequence QIO-SPI

9.3.4 Write Enable (WREN)

The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Except for the

parallelizing of the instruction code on the four pins DQ 0, DQ 1, DQ2 an d DQ3, the

instruction functionality is exactly the same as the Write Enable instruction of the Extended

SPI protocol, plea se refe r to Section 9.1.9: Write Enable (WREN) for further details.

Figure 73. Write Enable instruction sequence QIO-SPI

Quad_Read_OT

Data

out 1 Data

out n

21 3456780

910

40 04

51 15

73 37

Q3 73

Q2 62

62 26

Dummy (ex.: 10)

Instruction

404040

515151

626262

737373

15 16 17 18 20

19 21 23

Quad_Write_Enab

Instruction

DQ1

DQ3

DQ2

DQ0

N25Q128 - 3 V Instructions

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9.3.5 Write Disable (WRDI)

The Write Disable (WRDI) instruction resets the Write Enable Latch (WEL) bit.

Except for the paralle lizing of the instruction code on the four pins DQ0, DQ1, DQ2 and

DQ3, the instruction functionality is exactly the same as the Write Disable (WRDI)

instruction of the Extended SPI protocol, please refer to Section 9.1.10: Write Disable

(WRDI) for further details.

Figure 74. Write Disable instruction sequence QIO-SPI

9.3.6 Quad Command Page Program (QCPP)

The Quad Command Page Program (QCPP) instruction allows pro gramming the memory

content in QIO-SPI protocol, parallelizing the instruction code, th e ad dr ess, an d the inp u t

data on four pins (DQ0, DQ1, DQ2 and DQ3). Before it can be accepted, a Write Enable

(WREN) instruction must previously have been executed. The Quad Command Page

Program (QCPP) instruction can be issued, when the device is se t in QIO-SPI mode, by

sending to the memory indifferently one of the 3 instructions codes: 02h, 12h or 32h, the

effect is exactly the same. The 3 instruction codes are all accepted to help the application

code porting from Extended SPI protocol to QIO-SPI protocol.

Apart for the parallelizing on four pins of the instru ctio n code, th e Qu ad Com m an d Page

Program instruction functionality is exac tly the same as the Quad Input Extended Fast

Program of the Extended SPI protocol.

Quad_Write_Disab

Instruction

DQ1

DQ3

DQ2

DQ0

Instructions N25Q128 - 3 V

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Figure 75. Quad Command Page Program instruction sequence QIO-SPI, 02h

Figure 76. Quad Command Page Program instruction sequence QIO-SPI, 12h

21 345678910

11 12 13 14

Mode 3

Mode 0

Quad_Command_Page_Program_02h

15 517

514515516 519

518

5151

Data In

DQ2 62

6262

24-bit address

MSB

20 16 12 8

21 17 13 9

22 18 14 10

23 19 15 11

4040 40

51 15 15

622626

73 3737

40 0404

5151

73737373

MSBMSB

MSB

Data In

254 255 256

1234

21 345678910

11 12 13 14

Mode 3

Mode 0

Quad_Command_Page_Program_12h

5151

Data In

DQ2 62

6262

24-bit address

MSB

20 16 12 8

21 17 13 9

22 18 14 10

23 19 15 11

4040 40

51 15 15

622626

73 3737

40 0404

5151

73737373

MSBMSB

MSB

Data In

254 255 256

1234

517

514515516 519

518

N25Q128 - 3 V Instructions

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Figure 77. Quad Command Page Program instruction sequence QIO-SPI, 32h

9.3.7 Program OTP instruction (POTP)

The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP

memory area (by ch anging bit s from 1 to 0, only). Befo re it can be accep ted, a W rite Enable

(WREN) instruction must previously have been executed.

Except for the paralle lizing of the instruction code, address and input data on the four pins

DQ0, DQ1, DQ2 and DQ3, the instruction functionality (as well as the locking OTP method)

is exactly the same as the Program OTP (POTP) instruction of the Extended SPI protocol,

please refer to Section 9.1.16: Program OTP inst ruction (POTP) for further details.

21 345678910

11 12 13 14

Mode 3

Mode 0

Quad_Command_Page_Program_12

5151

Data In

DQ2 62

6262

24-bit address

MSB

20 16 12 8

21 17 13 9

22 18 14 10

23 19 15 11

4040 40

51 15 15

622626

73 3737

40 0404

5151

73737373

MSBMSB

MSB

Data In

254 255 256

1234

517

514515516 519

518

Instructions N25Q128 - 3 V

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Figure 78. Program OTP instruction sequence QIO-SPI

9.3.8 Subsector Erase (SSE)

For devices with a ded icated part number, at the bottom (or top) of the addressable area

there are 8 boot sectors, each one having 16 4Kbytes subsectors. (See Section 16:

Ordering information.) The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside

the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must

previously have been executed.

Except for the paralle lizing of the instruction code and the address on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly th e same as the Subsector Erase

(SSE) instruction of the Extended SPI protocol, please refer to Section 9 .1.17: Subsector

Erase (SSE) for further details.

Quad_Program_OTP

Instruction 24-B it Addres s

Q0 20 16 12 8 40

23 19 15 11 73

Q2 22 18 14 10

DQ1 21 17 13 9 51

DQ3

4040

5151

7373

6262

21 3456780

910

11 12 13 14

Data

byte1 Data

by te 2 Data

by te n

N25Q128 - 3 V Instructions

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Figure 79. Subsector Erase instruction sequence QIO-SPI

9.3.9 Sector Erase (SE)

The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

Except for the paralle lizing of the instruction code and the address on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase

(SE) instruction of the Extended SPI protocol, please refer to Section 9.1.18: Sector Erase

(SE) for further details.

Figure 80. Sector Erase instruction sequence QIO-SPI

Instruction 24-B it Addres s

Q0 20 16 12 8 40

Q3 23 19 15 11 73

Q2 22 18 14 10

Q1 21 17 13 9 51

21 34567890

Quad_Subsector_Erase

Quad_Sector_Era

Instruction 24-B it Addres s

Q0 20 16 12 8 40

Q3 23 19 15 11 73

Q2 22 18 14 10

Q1 21 17 13 9 51

21 34567890

Instructions N25Q128 - 3 V

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9.3.10 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to '1' (FFh). Before it can be accepted, a Write

Enable (WREN) ins tru ct ion mu st pr eviously have been exec uted.

Except for the paralle lizing of the instruction code on the four pins DQ0, DQ1, DQ2 and

DQ3, the instruction functionality is exactly the same as the Bulk Erase (BE) instruction of

the Extended SPI prot ocol, please refer to Section 9.1.19: Bulk Erase (BE) for further

details.

Figure 81. Bulk Erase instruction sequence QIO-SPI

9.3.11 Program/Erase Suspend

The Program/Erase Suspend (PES) instruction allows the controller to interrupt a Program

or an Erase instruction, in particular: Subsector Erase (SSE), Sector Erase (SE) and Dual

Command Page Program (DCPP) can be suspended and resumed while Bulk Erase (BE),

Write Status Register (WRSR), Write Non Volatile Configuration Register (WRNVCR), and

Program OTP (POTP) cannot be suspended.

Except for parallelizing the instruction code on four pins DQ0, DQ1, DQ2 and DQ3, the

instruction functionality is exactly the same as the Program/Erase Suspend (PES)

instruction of the Extended SPI protocol.

Quad_Bulk_Era

Instruction

DQ0

DQ1

DQ2

DQ3

N25Q128 - 3 V Instructions

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Figure 82. Program/Erase Suspend instruction sequence QIO-SPI

9.3.12 Program/Erase Resume

After a Pr ogram/Erase suspend instruction, a Program/Erase Resume instruction is

required to continue performing the suspended Program or Erase sequence.

Except for the paralle lizing of the instruction code on the four pins DQ0, DQ1, DQ2 and

DQ3, the instruction functionality is exactly the same as the Program/Erase Resume (PER)

instruction of the Extended SPI protocol, please refer to Section 9.1.21: Program/Erase

Resume for further details.

Quad_Program_Erase_Suspen

Instruction

DQ3

DQ2

Instructions N25Q128 - 3 V

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Figure 83. Program/Erase Resume instruction sequence QIO-SPI

9.3.13 Read Status Register (RDSR)

The Read Status Regis ter (RDSR) instruction allows the Status Register to be read.

Except for the parallelizing of the instruction code and the output data on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Status

Read Status Register (RDSR) for further details.

Quad_Program_Erase_Resum

Instruction

DQ3

DQ2

N25Q128 - 3 V Instructions

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Figure 84. Read Status Register instruction sequence QIO-SPI

9.3.14 Write status register (WRSR)

The write status register (WRSR) instruction allows new values to be written to the status

been executed.

The instruction code and the input data are sent on four pins DQ0, DQ1, DQ2 and DQ3. The

instruction functionality is exactly the same as the W rite Status Register (WRSR) instruction

of the Extended SPI protocol (See Section 9.1.23: Write status r egister ( WRSR)). However,

the protection feature management is different. In particular, once SRWD bit is set to '1' the

device enters in the hardware protected mode (HPM) independently from Write Protect

(W/VPP) signal value. To exit the HPM mode is needed to switch temporarily to the

Extended SPI protocol.

Quad_Read_SR

21 3 4 5 6 7 8 9 10 11 12 13 14 15

Status Register Out

DQ0

DQ1

DQ3

DQ2

Instruction

4040 40

5151 51

6262 62

7373 73

40 04

51 15

73 37

62 26

4040

5151

6262

7373

16 17 18

Instructions N25Q128 - 3 V

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Figure 85. Write Status Register instruction sequence QIO-SPI

9.3.15 Read Lock Register (RDLR)

The Read Lock Register instruction is used to read the lock register content.

Except for the paralle lizing of the instruction code, the address and the output data on the

four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the

Read Lock Register (RDLR) instruction of the Extended SPI protocol, please refer to

Section 9.1.24: Read Lock Register (RDLR) for further details.

Quad_Write_SR

Status Register In

2130

DQ2

DQ0

DQ3

DQ1

N25Q128 - 3 V Instructions

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Figure 86. Read Lock Register instruction and data-out sequence QIO-SPI

9.3.16 Write to Lock Register (WRLR)

The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock

Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously

have been executed.

Except for the parallelizing of the instruction code, the address and the input data on the

four pins DQ0, DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the

Write to Lock Register (WRLR) instruction of the Extended SPI protocol, please refer to

Section 9.1.25: Write to Lock Register (WRLR) for further details.

Quad_Read_L

21 3 4 5 6 7 8 9 10 11 12 13 14 15

Lock R egister Out

DQ2

Instruction

20 16 12 8 40

21 17 13 9 51

22 18 14 10 62

23 19 15 11 73

5151

40 04

51 15

73 377373

6262

62 26

4040

24-bit addres s

Instructions N25Q128 - 3 V

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Figure 87. Write to Lock Register instruction sequence QIO-SPI

9.3.17 Read Flag Status Register

The Read Flag Status Register (RFSR) instruction allows the Flag Status Register to be

read.

Except for the parallelizing of the instruction code and the output data on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Read Flag

Status Register (RFSR) instruction of the Extended SPI protocol, please refer to

Section 9.1.26: Read Flag Status Register for further details.

Quad_Write_L

Instruction 24-B it Addres s Lock Register In

Q0 20 16 12 8 40

Q3 23 19 15 11 73

Q2 22 18 14 10

Q1 21 17 13 9 51

21 34567890

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Figure 88. Read Flag Status Register instruction sequence QIO-SPI

9.3.18 Clear Flag Status Register

The Clear Flag Status Regi ster (CLFSR) instructio n reset th e error Flag Status Register bit s

(Erase Error bit, Prog ram Erro r bit, VPP Err or bit, Pr otection Error bit). It is not necessary to

set the WEL bit before the Clear Flag Status Register instruction is executed. The WEL bit

will be unchanged after this command is executed.

Quad_Read_Flag_SR

21 3456780

Mode 3

Mode 0

DQ0

DQ1

910

DQ3

DQ2

Instruction

4040 40

5151 51

6262 62

7373 73

11 12 13 14 15

5151

40 04

51 15

73 377373

6262

62 26

4040

Flag Status Register Out

Instructions N25Q128 - 3 V

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Figure 89. Clear Flag Status Register instruction sequence QIO-SPI

9.3.19 Read NV Configuration Register

The Read Non V olatile Conf iguration Register (RDNVCR) instruction allows the Non V o latile

Configuration Register to be read.

Quad_Clear_Flag_SR

Instruction

DQ3

DQ1

DQ2

DQ0

N25Q128 - 3 V Instructions

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Figure 90. Read NV Configuration Register instruction sequence QIO-SPI

9.3.20 Write NV Configuration Register

The Write Non Volatile Configuration register (WRNVCR) instruction allows new values to

be written to the Non Volatile Configuration register. Before it can be accepted, a write

enable (WREN) instruction must previou sly ha ve been executed.

Except for the parallelizing of the instruction code and the input data on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Non

Volatile Configuration Register (WRNVCR) instruction of the Extended SPI protocol, please

refer to Section 9.1.29: Write NV Configuration Register for further details.

Quad_Read_NVCR

21 345

Instruction

LS Byte MS Byte

DQ0

DQ1

DQ3

4 0 12 8

5 1 13 9

6 2 14 10

7 3 15 11

DQ2

Nonvolatile Conguration

Instructions N25Q128 - 3 V

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Figure 91. Write NV Configuration Register instruction sequen ce QIO-SPI

9.3.21 Read Volatile Configuration Register

The Read Volatile Configuration Register (RDVCR) instruction allows the Volatile

Configuration Register to be read.

Quad_Write_NVCR

21345

Instruction

Nonvolatile Conguration

LS Byte MS Byte

DQ0

DQ1

DQ3

DQ2

4 0 12 8

5 1 13 9

6 2 14 10

7 3 15 11

N25Q128 - 3 V Instructions

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Figure 92. Read Volatile Configuration Register instruction sequence QIO-SPI

9.3.22 Write Volatile Configuration Register

The Write Volatile Configuration register (WRVCR) instruction allows new values to be

written to the Volatile Configuration register. Before it can be accepted, a write enable

(WREN) instruction must previously have been executed. In case of Fast POR, the WREN

instruction is not required because a WREN instruction gets the device out from the Fast

POR state (See Section 11.1: Fast POR).

Except for the parallelizing of the instruction code and the input data on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile

Configuration Register (WRVCR) instruction of the Extended SPI protocol, please refer to

Section 9.1.31: Write Volatile Configuration Register for further details.

Quad_Read_VCR

21 3 4 5 6 7 8 9 10 11 12 13 14 15

Volatile Conguration Register Out

DQ0

DQ1

DQ3

DQ2

Instruction

4040 40

5151 51

6262 62

7373 73

5151

40 04

51 15

73 377373

6262

62 26

4040

Instructions N25Q128 - 3 V

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Figure 93. Write Volatile Configuration Register instruction sequence QIO-SPI

9.3.23 Read Volatile Enhanced Configuration Register

The Read Volatile Enhanced Configuration Register (RDVECR) instruction allows the

Volatile Configuration Register to be read.

Volatile Conguration

Quad_Write_VCR

2130

DQ0

DQ1

DQ3

DQ2

N25Q128 - 3 V Instructions

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Figure 94. Read Volatile Enhanced Configuration Register instruction sequence

QIO-SPI

9.3.24 Write Volatile Enhanced Configuration Register

The Write Volatile Enhanced Configuration register (WRVECR) instruction allows new

values to be written to the Volatile Enhanced Configuration register. Before it can be

accepted, a write enable (WREN) instruction must previously have been executed. In case

of Fast POR the WREN instruction is not required because a WREN instruction gets the

device out from the Fast POR state (See Section 11.1: Fast POR).

Except for the parallelizing of the instruction code and the input data on the four pins DQ0,

DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Write Volatile

Enhanced Configuration Register (WRVECR) instruction of the Extended SPI prot oc ol,

please refer to Section 9.1.33: Write Volatile Enhanced Configuration Register for further

details.

Quad_Read_VECR

21 3 4 5 6 7 8 9 10 11 12 13 14 15

Volatile Enhanced

Conguration Register Out

DQ0

DQ1

DQ3

DQ2

Instruction

4040 40

5151 51

6262 62

7373 73

5151

40 04

51 15

73 377373

6262

62 26

4040

Instructions N25Q128 - 3 V

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Figure 95. Write Volatile Enhanced Configuration Register instruction sequence

QIO-SPI

Quad_Write_VECR

213

Volatile Enhanced

Conguration Register In

DQ0

DQ1

DQ3

DQ2

Instruction

N25Q128 - 3 V XIP Operations

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10 XIP Operations

XIP (eXecution in Place) mode is available in each protocol: Extended SPI, DIO-SPI, and

QIO-SPI. XIP mode allows the memory to be read simply by sending an address to the

device and then receiving the data on one, two, or four pins in parallel, depending on the

customer requirements. It offers maximum flexibility to the application, saves instruction

overhead, and allows a dramatic reduction to the Random Access time.

You can enable XIP mode in two ways:

Using the Volatile Configuration Register: this is dedicated to applications that boot in

SPI mode (Extended SPI, DIO-SPI or QIO-SPI) and then during the application life

need to switch to XIP mode to directly execute some code in the flash.

Using the Non Volatile Configura tion Register: this is dedicated to applications that

need to boot directly in XIP mode.

Setting to 0 the bit 3 of the V olatile Configuration Register the device is ready to enter in XIP

mode right after the next fast read instruction (by 1, 2 or 4 pin).

While acting on the Non Volatile Configuration Register (bit 11 to bit 9, depending on which

XIP type is required, single, dual or quad I/O) the memory enters in the selected XIP mode

only after the next power-on sequence. The Non Volatile Configuration Register XIP

configuration bit s allows the mem ory to start directly in the required XIP mode (Sin gle, Dua l

or Quad) after the power on.

The XIP mode status must be confirmed forcing the XIP confirmation bit to "0", the XIP

confirmation bit is the value on the DQ0 pin during the first dummy clock cycle after the

address in XIP reading instr u ctio n. Forcin g th e bit "1" on DQ0 du rin g the firs t du mmy clo ck

cycle after the address (XIP Confirmation bit) the memory retur ns in the previous stand ard

read mode, that means it will codify as an instruction code the next byte received on the

input pin(s) after the next chip select. Instead, if the XIP mode is confirmed (by forcing the

XIP confirmation bit to 0), af ter the device ne xt de-selection and selection cycle, the memory

codify the first 3 bytes received on the inputs pin(s) as a new address.

Besides not confirming the XIP mode dur ing the first dummy clock cycle, it is possible to exit

the XIP mode by mean of a dedicated rescue sequence.

Note: For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not

necessary to set the Volatile Configuration Register bit 3 to enter XIP mode: it is possible to

enter XIP mode directly by setting XIP Confirmation bit to 0 during the first dummy clock

cycle after a fast read instruction.See Section 16: Ordering information.

XIP Operations N25Q128 - 3 V

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Figure 96. N25Q128 Read functionality Flow Chart

10.1 Enter XIP mode by setting the Non Volatile Configuration

To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary

to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern

corresponding to the required XIP mode by mean of the Write Non Volatile Configuration

This instruction doesn't affect the XIP state until the next Power on sequence. In this case,

after the next power on sequence, the memory directly accept addresses and then, after the

dummy clock cycles (configurable) , outputs the data as described in Table 24.: NVCR XIP

bits setting example. For example to enable fast POR and XIP on QIOFR in normal SPI

protocol with six dummy clock cycles the following pattern must be issued:

S P I s tandard m ode (no

XiP, VCR <3> = 1) S P I m ode (no X IP ) but

ready to ent er X IP

VCR<3> = 0 ?

Read Instruct ions ?

XiP Confirmation

bit = 0 ?

Power On

NVCR Check

I s X I P enabl ed ?

XIP mode

XiP Confirmation

bit = 0 ?

Yes

Yes No

Yes

N25Q128 - 3 V XIP Operations

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Figure 97. XIP mode directly after power on

Note: Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP

mode and return to standard read mode.

Table 24. NVCR XIP bits setting example

B1h

(WRNVCR

opcode) + 0110 100 111 0 1 11 xx

6 dummy cycles

for fast read

instructions

XIP set as

default; Quad

I/O mode

Output Buffer

driver strength

default

FAST POR

enabled

Hold/Reset

not disabled

Extended

SPI protocol

Don’t

Care

NVCR check: XIP enabled

VSI

(<100μ)

DQ0

Quad_XIP_After_Power-On

21 345678910

11 12 13 14

Mode 3

Mode 0

15 16

DQ1

DQ2

DQ3

4040

5151

7373

6262

Dummy (ex.: 6)

A23-16 A15-8 A7-0

40 044

Byte 1

51 155

73 377

62266

Byte 2

IO switches from Input to Output

XIP Operations N25Q128 - 3 V

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10.2 Enter XIP mode by setting the Volatile Configuration Register

To use the V olatile Configu ration Register method to enter XIP mode, it is necessary to write

a 0 to bit 3 of the Volatile Configuration Register to make the device ready to enter XIP

mode (2). This instruction doesn't permit to enter XIP state directly: a Fast Read instruction

(either Single, Dual or Quad) is need ed once to start the XIP Reading.

After the Fast Read instruction (Single, Dual or Quad) the XIP confirmation bit must be set

to 0. (first bit on DQ0 during the first dummy cycle after the address has been received),

Then after the next de-select and select cycle (S pin set to 1 and then to 0) the memory

codify the first 3 bytes received on the input pin(s) directly as an address, without any

instruction code, and after the dummy clock cycles (configurable) directly outputs the data.

For example to enable the XIP (without enter) with six dummy clock cycles, the pattern in

Table 25.: VCR XIP bits setting example must be issued, an d after that it is possible to enter,

for example, in XIP mode fro m extended SPI read mode by me an of Quad Input Output Fast

Read instruction, as described in Table 25.: VCR XIP bits setting exampl e.

Note: For devices with a feature set digit equal to 2 or 4 in the part number (Basic XiP), it is not

necessary to set the Volatile Configuration Register bit 3 to enter in XIP mod e: it is possible

to enter directly in XIP mode by setting XIP Confirmation bit to 0 during the first dummy

clock cycle after a fast read instruction. See Section 16: Ordering information.

Table 25. VCR XIP bits setting example

81h (WRVCR opcode) + 0110 0 000

6 dummy

cycles

Ready for

XIP

Reserved

N25Q128 - 3 V XIP Operations

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Figure 98. XiP: enter by VCR 2/2 (QIOFR in normal SPI protocol example)

Note: Xb is the XIP Confirmation bit, and it should be set to '0' to keep XIP state or '1' to exit XIP

mode and return to standard read mode.

10.3 XIP mode hold and exit

The XIP mode does require at least one addition al clock cycle to allow the XIP Confirmatio n

bit to be sent to the memory on DQ0 during the first dummy clock cycle.

The device decodes the XIP Confirmation bit with the scheme:

XIP Confirmation bit=0 means to hold XIP Mode

XIP Confirmation bit=1 means to exit XIP Mode and comes back to read mode, th at

means codifying the first byte after the next chip select as an instruction code.

In Dual I/O XIP mode, the values of DQ1 during the first dummy clock cycle after the

addresses is always Don't Care.

In Quad I/O XIP mode, the values of DQ3, DQ2 and DQ1 during the first dummy clock cycle

after the addresses are always Don't Care.

In Dual and Single I/O XIP mode, in presence of the RESET pin enabled (in devices with a

dedicated part number), a low pulse on that pin resets the XIP protocol as defined by the

Volatile Configuration Register, reporting the memor y at the state of last power up, as

defined by the Non Volatile Configuration Register. In Quad I/O XiP modes, it is possible to

reset the memory (for devices with a dedicated part number) only when the device is

deselected. See Section 16: Ordering information.

21 345678910

11 12 13 14

Mode 3

Mode 0

Instruction

XIP_VCR

15 16

4040

17 18 20

19 22

21 23

5151

Q1 Don’t Care

Byte 1

7373

6262

Q2 Don’t Care

40 044

51 155

73 377

62266

Byte 2Dummy (ex.: 6)

A23-16 A15-8 A7-0

Q3 ‘1’

IO switches from Input to Output

XIP Operations N25Q128 - 3 V

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10.4 XIP Memory reset after a controller reset

If during the application life the system controller is reset during operation, and the device

features the RESET functionality (in devices with a dedicated part number), and the feature

has not been disabled, af ter the controller reset s, the memory returns to POR st ate and

there is no issue. See Section 16: Ordering information.

In all the other cases, it is possible to exit the memory from the XIP mode by sending the

following rescue sequence at the first chip selection after a system reset:

DQ0= '1' for:

7 clock cycles within S low (S becomes high before 8th clock cycle)

+ 13 clock cycles within S low (S becomes high before 14th clock cycle)

+ 25 clock cycles within S low (S becomes high before 26th clock cycle)

The global effect is only to exit from XIP without any other reset.

N25Q128 - 3 V Power-up and power-down

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11 Power-up and power-down

At power-up and power-down, the device must not be selected: S must follow the voltage

applied on VCC until VCC reaches the correct value:

VCC(min) at power-up

VSS at power-down

A safe configuration is provided in Section 3: SPI Modes.

To avoid data corruption and inadvertent write oper ations during power-up, a power on

reset circuit is included. The logic inside the device is held to reset during the following:

VCC is less than the POR threshold voltage

VWI - all operations are disabled

Device does not respond to any instruction

During a standard power-up phase without Fast POR, the device ignores all instructions but

RDSR and RFSR; these instructions can be used to check the memory internal state

according to power-up timing shown here. After power-up, the device is in the following

state:

The device is in the Standby Power mode

The Write Enab le Latch (WEL) bit is reset

The Write In Progress (WIP) bit is reset

The Lock Registers are configured as: (Write Lock bit, Lock Down bit) = (0,0).

Normal precautions must be taken for supply line decoupling to stabilize the VCC supply.

Each device in a system should have the VCC line decoupled by a suitable capacitor close

to the package pins. Generally, this capacitor is of the order of 100 nF.

At power-down, when VCC drops from the operating voltage to below the Power On Reset

threshold voltage, VWI, all ope ratio ns are disabled and th e de vice does no t re sp on d to any

instruction. If a power-down occurs while a Program or Erase cycle is in progress, some

data corruption may result. VPPH must be applied only when VCC is stable and in the

VCC(min) to VCC(max) voltage range.

Figure 99. Power-up timing, Fast POR selected

Vcc

time

VCC(max)

VCC(min)

VWI

Chip selection not allowed

Polling allowed Al l re ad , WRCR,

WRECR a ll owe d

tVTR

Polling

allowed

De vi ce fu ll y a cces s i b le

WREN issued

tDTW

SPI prot ocol

Chip

reset Start ing protoc ol defined by NVCR

WIP = 1

WEL = 0 WIP = 0

WEL = 0 WI P = 1

WEL = 1 WIP = 0

WEL = 1

Power-up and power-down N25Q128 - 3 V

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Figure 100. Power-up timing, Fas t POR not selected

11.1 Fast POR

The Fast POR feature is available to speed up the power-on sequence for applications that

only require reading the memory after the power on sequence (no modify instructions).

If enabled, the Fast POR allows read operations and Volatile Configuration Register and

Volatile Enhanced Configuration Register modifica tions after less than 100us, providing a

substantially faster application boot phase.

In any case, even if the Fast POR sequence is selected, it is still possible to execute a

modify instruction (erase or program) issuing a WREN instruction. In this case the device

will have a latency time (~500us) after the first WREN instruction to complete POR

sequence. During this latency time, when the power on second phase is running, no

instruction will be accepted except for the polling instruction. During the power on second

phase, both WEL & WIP bits are set to 1. At the end of POR sequence only th e WEL bit is

still set to 1.

To select or deselect the Fast POR feature, a Write non Volatile Configuration Register

(WRNVCR) instruction is needed to properly set the dedicated bit (bit 5) of the Non Volatile

Configuration Register.

Table 26. Power-up timing and VWI threshold

Symbol Parameter Min Max Unit

tVTR(1)

1. These parameters are characterized only.

VCC(min) to Read when Fast POR is selected 100 µs

tDTW(1) T i me d el a y to write instruction when Fast POR is selected 500 µs

tVTW(1) VCC(min) to device fully accessible 600 µs

VWI(1) Write inhibit voltage 1.5 2.5 V

Vcc

time

VCC(max)

VCC(min)

VWI

Chip selection not allowed

Polling allo wed

tVTW =t

VTR + tDTW

Device fully accessible

SPI protocol

Chip

reset

WIP = 1

WEL = 0

Start ing prot ocol defined by NVCR

WIP = 0

WEL = 0

N25Q128 - 3 V Power-up and power-down

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11.2 Rescue sequence in case of power loss during WRNVCR

If a power loss occurs during a Write Non Volatile Configuration Register instruction, after

the next power on the device could eventually wake up in a not determined state, for

example a not required protocol or XIP mode. In that case a particular rescue sequence

must be used to recover the device at a fixed state (Extended SPI protocol without XIP) until

the next power up. Then to fix the problem definitively is recommended to run the Write Non

Volatile configuration Register again.

The rescue sequence is composed of two parts that have to be run in the correct order.

During all the sequence the TSHSL must be 50ns at least. The sequence is:

DQ0 (PAD DATA) equal to '1' for:

7 clock cycles within S low (S becomes high before 8th clock cycle)

+ 13 clock cycles within S low S becomes high before 14th clock cycle)

+ 25 clock cycles within S low (S becomes high before 26th clock cycle)

To exit from XIP.

DQ0 (PAD DATA) and DQ3 (PAD HOLD) equal to '1' for:

8 clock cycles within S low (S becomes high before 9th clock cycle) to force Normal SPI

protocol.

Initial delivery state N25Q128 - 3 V

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12 Initial delivery state

The device is delivered with the memory arr ay erased: all bits are set to 1 (each byte

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

13 Maximum rating

Stressing the device outside the ratings listed here may cause permanent damage to the

device. These are stress ratings only, and operation of the device at these, or any other

conditions outside those indicated in the operating sections of this specification, is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 27. Absolute maximum ratings

Symbol Parameter Min Max Unit

TSTG Storage temperature –65 150 °C

TLEAD Lead te mp erature during solderin g see(1)

1. Compliant with JEDEC Std. J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous

Substances (RoHS) 2002/95/EU.

°C

VIO Input and output voltage (with respect to ground) –0.6 VCC +0.6 V

VCC Supply voltage –0.6 4.0 V

VPP Fast program/erase voltage –0.2 10.0 V

VESD Electrostatic discharge voltage (human body model)(2)

2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

–2000 2000 V

N25Q128 - 3 V DC and AC parameters

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14 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characterist ics of th e de vice. The parameters in the DC and AC characteristics tables that

follow are derived from tests performed under the measurement conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurement conditions when relying on the quoted parameters.

1) Output Buffers are configurable by user.

Figure 101. AC measurement I/O waveform

1) For dual/quad operations 0V

2) For dual/quad operations VCC.

Table 28. Operating conditions

Symbol Parameter Min Typ Max Unit

VCC Supply voltage 2.7 3.6 V

VPPHSupply volt a g e on VPP 8.5 9.5 V

TAAmbient operating temperature –40 85 °C

Table 29. AC measurement conditions

Symbol Parameter Min Max Unit Notes

CLLoad capacitance 30(1) pF

—

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8VCC V(1)

1. 0.2VCC (for dual and quad operations 0V) to 0.8VCC (for dual and quad operations VCC).

Input timing reference voltages 0.3VCC to 0.7VCC V

Output timing reference voltages VCC / 2 V

Table 30. Capacitance(1)

1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 54 MHz.

Symbol Parameter Test condition Min Max Unit

CIN/OUT Input/output capacitance

(DQ0/DQ1/DQ2/DQ3) VOUT = 0 V 8 pF

CIN Input capacitance (other pins) VIN = 0 V 6 pF

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

I n p u t an d o u tp u t

timing re fe re n c e le ve ls

I nput le ve ls

0.5VCC

(1)

(2)

DC and AC parameters N25Q128 - 3 V

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Table 31. DC Characteristics

Symbol Parameter T est condition (in addiction

to those in Table 28.:

Operating conditio ns)Min Max Unit

ILI Input leakage current ± 2 µA

ILO Output leakage current ± 2 µA

ICC1 Standby current S = VCC, VIN = VSS or VCC 100 µA

ICC3

Operating current (Fast Read Single I/O)

C = 0.1VCC / 0.9VCC at 108

MHz, DQ1 = open 15 mA

C = 0.1VCC / 0.9VCC at 54

MHz, DQ1 = open 6mA

Operating current (Fast Read Dual I/O) C = 0.1VCC / 0.9VCC at

108 MHz 18 mA

Operating current (Fast Read Quad I/O) C = 0.1VCC / 0.9VCC at

108 MHz 20 mA

ICC4 Operating current (Page Program Single,

Dual and Quad I/O) S = VCC 20 mA

ICC5 Operating current (WRSR) S= VCC 20 mA

ICC6 Operating current (SE) S = VCC 20 mA

VIL Input low voltage – 0.5 0.3VCC V

VIH Inpu t high voltage 0.7VCC VCC+0.4 V

VOL Output low voltage IOL = 1.6 mA 0.4 V

VOH O utput high voltage IOH = –100 uA VCC–0.2 V

N25Q128 - 3 V DC and AC parameters

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Note: The AC Characteristics data is preliminary.

Table 32. AC Characteristics (page 1 of 2)

Symbol Alt. Parameter Min Typ(2) Max Unit

fC fC Clock frequency for the all the

instructions (Extended SPI, DIO-SPI and

QIO-SPI protocol) but the READ instruction D.C. 108 MHz

fR Clock frequency for read instructions D.C. 54 MHz

tCH(1) tCLH Clock High time 4 ns

tCL(2) tCLL Clock Low time 4 ns

tCLCH(3) Clock rise time(4) (peak to peak) 0.1 V/ns

tCHCL(3) Clock fall time(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S active setup time (rela tive to C) 4 ns

tCHSL 4 ns

tDVCH tDSU Data in setup time 2 ns

tCHDX tDH Data in hold time 3 ns

tCHSH S active hold time (relative to C) 4 ns

tSHCH S not active setup time (relative to C) 4 ns

tSHSL tCSH

S deselect time after a correct read

instruction 20 ns

S deselect time after a not correct read or

after any different instruction 50 ns

tSHQZ(3) tDIS Output disable time 8 ns

tCLQV tV Clock Low to Output valid under 30 pF 7 ns

Clock Low to Output valid under 10 pF 5 ns

tCLQX tHO Output hold time 1 ns

tHLCH HOLD setup time (relative to C) 4 ns

tCHHH HOLD hold time (relative to C) 4 ns

tHHCH HOLD setup time (relative to C) 4 ns

tCHHL HOLD hold time (relative to C) 4 ns

tHHQX(3) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(3) tHZ HOLD to Output High-Z 8 ns

tWHSL(5) Write protect setup time 20 ns

tSHWL(5) Write protect hold time 100 ns

DC and AC parameters N25Q128 - 3 V

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Figure 102. Reset AC waveforms while a program or erase cycle is in progress

See Table 33.: Reset Conditions.

tVPPHSL(6) Enhanced program supply voltage High

(VPPH) to Chip Select Low for Single and

Dual I/O Page Program 200 ns

tW Write status register cycle time 1.3 8 ms

tCFSR Clear flag status register cycle time 40 ns

tWNVCR Write non volatile configuration register

cycle time 0.2 3 s

tWVCR Write volatile configuration register cycle

time 40 ns

tWRVECR Write volatile enhanced

configurationregister cycle ti me 40 ns

tPP(7) Page program cycle time (n bytes) int(n/8) ×

0.015(8) 5ms

Program OTP cycle time (64 bytes) 0.2 ms

tSSE Subsector erase cycle time 0.2 2 s

tSE Sector erase cycle time 0.7 3 s

tSE Sector erase VPP = VPPH 0.6 3 s

tBE Bulk erase cycle time 170 250 s

tBE VPP = VPPH 160 250 s

1. tCH + tCL must be greater than or equal to 1/ fC.

2. Typical values given for TA = 25 °C

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set to '1'.

6. VPPH should be kept at a valid level until the program or erase operation has completed and its result (success or failure)

is known.

7. When using the page program (PP) instruction to program consecutive bytes, optimized timings are obtained with one

sequence including all the bytes versus several sequences of only a few bytes (1 < n < 256).

8. int(A) corresponds to the upper integer part of A. For example int(12/8) = 2, int(32/8) = 4 int(15.3) =16.

Table 32. AC Characteristics (page 2 of 2)

Symbol Alt. Parameter Min Typ(2) Max Unit

Reset tRLRH

tRHSLtSHRV

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Figure 103. Serial input timing

Table 33. Reset Conditions

Symbol Alt. Parameter Conditions Min Typ Max Unit

tRLRH(1)(2) tRST Reset pulse width 50 ns

tRHSL(1) tREC Reset Recovery

Time

Device selected (S low), while decoding

any modify instruction, during all read

operations, CLFSR, WRDI, WREN,

WRLR, WRVCR, WRVECR.

40 ns

Under completion of an internal erase or

program cycle related to POTP, PP, DIEFP,

DIFP, QIEFP, QIFP, SE, BE, PER, PES. 30 µs

Under completion of an SSE operation. tSSE ms

Under completion of an WRSR operation. tWms

Under completion of an WRNVCR

operation. tWNVCR ms

Under completion of the first WREN issued

when Fast POR selected. tDTW µs

Device deselected (S high) and in XiP

mode. 40 ns

Device deselected (S high) and in S tandby

mode. 40 ns

tSHRV(1) S# deselect to R

valid Deselect to R valid in Quad Output or in

QIO-SPI. 2ns

1. All values are guaranteed by characterization and not 100% tested in production.

2. The device reset is possible but not guaranteed if tRLRH < 50 ns.

DQ0

AI13728

MSB IN

DQ1

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

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Figure 104. Write protect setup and hold timing during WRSR when SRWD=1

Figure 105. Hold timing

High Impedance

W/VPP

tWHSL tSHWL

AI07439c

DQ1

AI13746

DQ0

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

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Figure 106. Output timing

Figure 107. VPPH timing

DQ1

AI13729

LS B OUT

DQ0 ADDR.

LS B IN

tSHQZ

tCH

tCL

tCLQX

tCLQV

tCLQX

tCLQV

DQ0

PPH

ai13726-b

tVPPHSL

End of command

(identied by WIP polling)

Package mechanical N25Q128 - 3 V

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15 Package mechanical

In order to meet environmental requirements, Numonyx offers these devices in RoHS

compliant packages. These packa ges have a lead-free second level interconnect. The

category of second level interc onn ect is mar ked o n the package and on the inner box label,

in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label.

Figure 108. VDFPN8 (MLP8) Very thin Dual Flat Package No lead,

8 × 6 mm, package outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 34. VDFPN8 (MLP8) Very thin Dual Flat Package No lead,

8 × 6 mm, package mechanical data

Symbol Millimeters Inches

Typ Min Max Typ Min Max

A 0.85 1.00 0.033 0.039

A1 0.00 0.05 0.000 0.002

b 0.40 0.35 0.48 0.016 0.014 0.019

D8.00 0.315

D2 5.16 (1)

1. D2 Max must not exceed (D – K – 2 × L).

0.203

ddd 0.05 0.002

E6.00 0.236

E2 4.80 0.189

e1.27– –0.050– –

K 0.82 0.032

L 0.50 0.45 0.60 0.020 0.018 0.024

L1 0.15 0.006

N8 8

VDFPN-02

A1 ddd

N25Q128 - 3 V Package mechanic al

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Figure 109. VDFPN8 (MLP8) Very thin pitch Dual Flat Package No lead,

6 × 5 mm, package outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 35. VDFPN8 (MLP8) Very thin pitch Dual Flat Package No lead,

6 × 5 mm, package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.0335 0.0315 0.0394

A1 — 0.00 0.05 — 0.0000 0.0020

A2 0.65 — — 0.0256 — —

A3 0.20 — — 0.0079 — —

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 — — 0.2362 — —

D1 5.75 — — 0.2264 — —

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 — — 0.1969 — —

E1 4.75 — — 0.1870 — —

E2 4.00 3.80 4.30 0.1575 0.1496 0.1693

e 1.27 — — 0.0500 — —

R1 0.10 0.00 — 0.0039 0.0000 —

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

Q — — 12° — — 12°

aaa — — 0.15 — — 0.0059

bbb — — 0.10 — — 0.0039

ddd — — 0.05 — — 0.0020

70-ME

AA3

eE2

ddd

bbb

CAB

aaa CAA

aaa CB

0.10 CA

0.10 CB

Package mechanical N25Q128 - 3 V

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Figure 110. SO16 wide - 16-lead plastic small outline, 300 mils body width, package

outline

1. Drawing is not to scale.

Table 36. SO16 wide - 16-lead plastic small outline, 300 mils body width,

mechanical data

Symbol Millimeters Inches

Typ Min Max Typ Min Max

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 10.10 10.50 0.398 0.413

E 7.40 7.60 0.291 0.299

e1.27– –0.050– –

H 10.00 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.40 1.27 0.016 0.050

θ0° 8° 0° 8°

ddd 0.10 0.004

SO-H

LA1

ddd

h x 45˚

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Figure 111. SO8W – 8 lead plast ic small ou tline, 20 8 mils bod y width, p ack age out line

1. Drawing is not to scale.

Table 37. SO8 wide – 8 lead plastic small outline, 208 mils body width,

package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A — — 2.50 — 0.098

A1 — 0.00 0.25 — 0.000 0.010

A2 — 1.51 2.00 — 0.059 0.079

b 0.40 0.35 0.51 0.016 0.014 0.020

c 0.20 0.10 0.35 0.008 0.004 0.014

CP — — 0.10 — — 0.004

D——6.05——0.238

E — 5.02 6.22 — 0.198 0.245

E1 — 7.62 8.89 — 0.300 0.350

e1.27— —0.050— —

k — 0° 10° — 0° 10°

L — 0.50 0.80 — 0.020 0.031

N8 8

6L_ME

LA1 k

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Figure 112. TBGA - 6 x 8 mm, 24-ball, mechanical package outline

1. Drawing is not to scale.



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Table 38. TBGA 6x8 mm 24-ball package dimensions

MIN NOM MAX

A1.20

A1 0.20

A2 0.79

Øb 0.35 0.40 0.45

D 5.90 6.00 6.10

D1 4.00

E 7.90 8.00 8.10

E1 4.00

eD 1.00

eE 1.00

FD 1.00

FE 2.00

MD 5

ME 5

n 24 balls

aaa 0.15

bbb 0.10

ddd 0.10

eee 0.15

fff 0.08

Control unit: mm

Ordering information N25Q128 - 3 V

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16 Ordering information

Note: For information on unlisted line items or on any aspect of this device, contact your nearest

Numonyx Sales Office.

Table 39. Ordering information scheme

Example: N25Q128 A 1 3 B F8 4 0 E

Device type

N25Q = serial Flash memory, Quad I/O, XiP

Device de ns ity

128 = 128 Mbit

Technology

A = 65 nm

Feature set

1 = Byte addressability, Hold pin, Numonyx XiP

2 = Byte addressability, Hold pin, Basic XiP

3 = Byte addressability, Reset pin, Numonyx XiP

4 = Byte addressability, Reset pin, Basic XiP

Operating voltage

3 = VCC = 2.7 V to 3.6 V

Block Structure

B = Bottom

T = Top

Package

F8 = VDFPN8 8 x 6 mm (MLP8) (RoHS com pl i a nt )

SF = SO16 (300 mils width) (RoHS compliant)

12 = TBGA24 6 x 8 mm (RoHS compliant)

F6 = VDFPN8 6 x 5 mm (MLP 6 x 5) (RoHS compliant)

SE = SO8W (SO8 208 mils body width) (RoHS compliant)

Temperature and test flow

4 = Industrial temperature range, –40 to 85 °C

Device tested with standard test flow

A = Automotive temperature range, –40 to 125 °C

Device tested with high reliability certified test flow

H = Industrial temperature range, –40 to 85 °C

Device tested with high reliability certified test flow

Security features (1)

0 = No extra security

Packing option s

E = T ray packing

F = Tap e and reel packing

G = Tube packing

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Note: Packing information details: E= tray, F= tape-n-reel, G= tube (16th digit of part number).

1. Additional secure options are available upon customer request.

Table 40. Valid Order Information Line Items

Part Number Features Block

Structure Package Temperature and

Test Flow Security

N25Q128A13BF840E

N25Q128A13BF840F Byte addressability,

Hold pin, Numonyx XiP Bottom VDFPN8

8x6 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A23BF840E

N25Q128A23BF840F Byte addressability,

Hold pin, Basic XiP Bottom VDFPN8

8x6 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A13TF840E

N25Q128A13TF840F Byte addressability,

Hold pin, Numonyx XiP Top VDFPN8

8x6 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A23TF840E

N25Q128A23TF840F Byte addressability,

Hold pin, Basic XiP Top VDFPN8

8x6 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A13B1240E

N25Q128A13B1240F Byte addressability,

Hold pin, Numonyx XiP Bottom TBGA24

6x8 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A23B1240E

N25Q128A23B1240F Byte addressability,

Hold pin, Basic XiP Bottom TBGA24

6x8 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A13T1240E

N25Q128A13T1240F Byte addressability,

Hold pin, Numonyx XiP Top TBGA24

6x8 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A23T1240E

N25Q128A23T1240F Byte addressability,

Hold pin, Basic XiP Top TBGA24

6x8 mm Industrial te mp;

Standard test flow No extra

security

N25Q128A13BSF40F

N25Q128A13BSF40G Byte addressability,

Hold pin, Numonyx XiP Bottom SO16 (300

mils width) Industrial temp;

Standard test flow No extra

security

N25Q128A23BSF40F

N25Q128A23BSF40G Byte addressability,

Hold pin, Basic XiP Bottom SO16 (300

mils width) Industrial temp;

Standard test flow No extra

security

N25Q128A13TSF40F

N25Q128A13TSF40G Byte addressability,

Hold pin, Numonyx XiP Top SO16 (300

mils width) Industrial temp;

Standard test flow No extra

security

N25Q128A23TSF40F

N25Q128A23TSF40G Byte addressability,

Hold pin, Basic XiP Top SO16 (300

mils width) Industrial temp;

Standard test flow No extra

security

Revision history N25Q128 - 3 V

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17 Revision history

Table 41. Document revision history

Date Revision Changes

29-Jan.-2009 1 Initial release.

12-May.-2009 2

Added the TBGA ballout an d package information;

Made technical edits to the following sections:

– Program/Erase Suspend

– Protection Modes table

– Read and Write Volatile Configuration Register sections

– Fast POR

– Power Up Timing graphics

– Order information table

3-Sept-2009 3

10-Feb-2010 4

Corrected typographical error “iA” to “uA” for VOH in DC Characteristics.

Made the following specification changes in AC Characteristics:

– tW: changed Max from 15 s to 8 ms.

– tWNVCR: changed typ from 1 to 0.2 and max from 15 to 3.

– tPP: changed typ from int(n/8) x 0.025 to int(n/8) x 0.015.

– tSSE: changed typ from 150 ms to 0.2 s and max from 500 ms to 2 s.

– tSE: changed typ from 1 s to 0.7 s.

– tBE: changed typ from 256 s to 170 s and max from 770 s to 250 s.

11-Oct-2010 5

Added the following packages:

– F6 = VDFPN8 6 x 5 mm (MLP 6 x 5) (RoHS compliant)

– SE = SO8W (SO8 208 mils body width) (RoHS compliant)

Changed the Typical specification for Erase to Suspend and Subsector

Erase to Suspend in Table 18.: Operations Allowed / Disallowed During

Device States..

Added tBE with VPP = VPPH to Table 32.: AC Characteristics.

Added tSE with sector erase VPP=VPPH, typ=0.6, max=3 unit=s Table

32.: AC Characteristics..

Made miscellaneous text edits.

4-Feb-2011 6 Removed uniform boot sector information from Ordering Information.

N25Q128 - 3 V

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8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Commen t Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set

forth herein.

Although considered final, these specifications are subject to change, as further product development and data

characterization sometimes occur.