www.fairchildsemi.com
REV. 1.0.7 1/5/04
Features
•Pin and Function Backward Compatible with FAN53168
and FAN53180 Controllers
• Precision Multi-Phase DC-DC Core Voltage Regulation
– ±10mV Output Voltage Accuracy Over Temperature
• Differential Remote Voltage Sensing
• Selectable 2, 3, or 4 Phase Operation
•Selectable VRM9 or VRM10 Operation
• Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
• Lossless Inductor Current Sensing for Loadline
Compensation
–External Temperature Compensation
• Accurate Load-Line Programming (Meets Intel®
VRM/VRD10.0 and 10.X CPU Specifications)
• Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
• Convenient 12V Supply Biasing
• 6-bit Voltage Identification (VID) Input
– .8375V to 1.600V in 12.5mV Steps
– Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
• Adjustable Over Current Protection with Programmable
Latch-Off Delay. Latch-Off Function may be Disabled
•Over-Voltage Protection – Internal OVP Crowbar
Protection
Applications
• Computer DC/DC Converter VRM/VRD10.0
• Computer DC/DC Converter VRM/VRD10.X
• Computer DC/DC Converter VRM/VRD9.X
• High Current, Low Voltage DC/DC Rail
General Description
The FAN5019 is a multi-phase DC-DC controller for imple-
menting high-current, low-voltage, CPU core power regula-
tion circuits. It is part of a chipset that includes external
MOSFET drivers and power MOSFETS. The FAN5019
drives up to four synchronous-rectified buck channels in par-
allel. The multi-phase buck converter architecture uses inter-
leav ed switching to multiply ripple frequenc y by the number
of phases and reduce input and output ripple currents. Lower
ripple results in fewer components, lower component cost,
reduced power dissipation, and smaller board area.
The FAN5019 features a high bandwidth control loop to
provide optimal response to load transients. The FAN5019
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, av eraged and used to set the loadline
of the output via programmable "droop". The droop is tem-
perature compensated to achieve precise loadline character-
istics over the entire operating range. Additionally,
individual phase current is measured using the RDS(ON) of
the low-side MOSFETs. This information is used to dynam-
ically balance/steer per-phase current. The phase currents
are also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protec-
tion and power -good circuitry combine to ensure reliable and
safe operation. The operating temperature range is 0°C to
+85°C and the operating voltage is a single +12V supply,
which simplifies the design. The FAN5019 is available in a
TSSOP-28 package.
Block Diagram
FAN5019
VIN
VIN
Φ1
Φ4
VOUT
Φ3
Φ2
FAN5009
FAN5009
FAN5019
6-Bit VID Controller 2-4 Phase VRM10.X Controller
FAN5019 PRODUCT SPECIFICATION
2REV. 1.0.7 1/5/04
Pin Assignments
Pin Definitions
Pin Number Pin Name Pin Function Description
1–5 VID [4:0] VID inputs. Determines the output voltage via the internal DAC. These inputs
comply to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open
results in logic high. Leaving VID[4:0] open results in a "No CPU" condition
disabling the PWM outputs.
6 VID5/SEL VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for
VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9)
voltage. The truth table is as follows:
VVID5/SEL held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3)
VViD5/SEL < Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and
VViD5/SEL pin is used as VID5 input.
7 FBRTN Feedback Return. Error Amp and DAC reference point.
8FBFeedback Input. Inverting input for Error Amp this pin is used for external
compensation. This pin can also be used to introduce DC offset voltage to the
output.
9 COMP Error Amp output. This pin is used for external compensation.
10 PWRGD Power Good output. This is an open-drain output that asserts when the output
voltage is within the specified tolerance. It is expected to be pulled up to an external
voltage rail.
11 EN Enable. Logic signal that enables the controller when logic high.
12 DELAY Soft-start and Current Limit Delay. An external resistor and capacitor sets the
softstart ramp rate and the over-current latch off delay.
13 RT Switching Frequency Adjust. This pin adjusts the output PWM switching
frequency via an external resistor.
14 RAMPADJ PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of
the internal PWM ramp.
15 ILIMIT Current Limit Adjust. An external resistor sets the current limit threshold for the
regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit
is active. It is also used to enable the drivers.
DELAY
VID4
VID3
VID2
VID1
VID0
COMP
CSCOMP
PWRGD
EN
CSSUM
RT
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
FBRTN
ILIMIT
FB
CSREF
RAMPADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAN5019
TSSOP-28
SW1
PWM2
SW4
VID5/SEL
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 3
16 CSREF Current Sense Reference. Non-Inverting input of the current sense amp. Sense
point for the output voltage used for OVP and PWRGD.
17 CSSUM Current Sense Summing node. Inverting input of the current sense amp.
18 CSCOMP Current Sense Compensation node. Output of the current sense amplifier. This
pin is used, in conjunction with CSSUM to set the output droop compensation and
current loop response.
19 GND Ground. Signal ground for the device.
20–23 SW[4:1] Phase Current Sense/Balance inputs. Phase-to-phase current sense and
balancing inputs. Unused phases should be left open.
24–27 PWM[4:1] PWM outputs. CMOS outputs for driving external gate drivers such as the
FAN53418 or FAN5009. Unused phases should be grounded.
28 VCC Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass
with a 1µF MLCC capacitor.
Pin Definitions (continued)
Pin Number Pin Name Pin Function Description
FAN5019 PRODUCT SPECIFICATION
4REV. 1.0.7 1/5/04
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Thermal Information
Recommended Operating Conditions (See Figure 8)
Note:
1: ΘJA is defined as 1 oz. copper PCB with 1 in2 pad.
Parameter Min. Max. Units
Supply Voltage: VCC to GND -0.3 +15 V
Voltage on FBRTN pin -0.3 +0.3 V
Voltage on SW1-SW4 (<250ns duration) -5 +25 V
Voltage on SW1-SW4 (>=250ns duration) -0.3 +15 V
Voltage on RAMPADJ, CSSUM -0.3 VCC+0.3 V
Voltage on any other pin -0.3 +5.5 V
Parameter Min. Typ Max. Units
Operating Junction Temperature (TJ)0+150 °C
Storage Temperature –65 +150 °C
Lead Soldering Temperature, 10 seconds +300 °C
Vapor Phase, 60 seconds +215 °C
Infrared, 15 seconds +220 °C
Power Dissipation (PD) @ TA = 25°C 2 W
Thermal Resistance (ΘJA)* 50 °C/W
Parameter Conditions Min. Typ. Max. Units
Supply Voltage VCC VCC to GND 10.2 12 13.8 V
Ambient Operating Temperature 0 +85 °C
Operating Junction Temperature (TJ)0+125
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 5
Electrical Specifications
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter Symbol Conditions Min. Typ. Max. Units
Error Amplifier
Output Voltage Range VCOMP •0.5 3.5 V
Accuracy VFB Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
VRM10
VRM9 •
•-10
-12 +10
+12 mV
Line Regulation ∆VFB VCC=10V to 14V 0.05 %
Input Bias Current IFB •-13 -15 -17 µA
FBRTN Current IFBRTN •150 180 µA
Output Current IO(ERR) FB forced to VOUT – 3% 300 500 µA
Gain Bandwidth Product GBW COMP = FB 20 MHz
DC Gain CCOMP = 10pF 77 dB
VID Inputs
Input Low Voltage VIL(VID) VRM10
VRM9 •
•0.4
0.8 V
V
Input High Voltage VIH(VID) VRM10
VRM9 •
•0.8
2.0 V
V
Input Current, VID Low IIL(VID) VID(X) = 0V •-30 -20 µA
Input Current, VID High IIH(VID) VID(X) = 1.25V •-2 2 µA
Pull-up Resistance RVID Internal •35 60 115 kΩ
Internal Pull-up Voltage VRM10
VRM9 •
•1.0
2.2 1.15
2.4 1.26
2.6 V
V
VID T ransition Delay Time2VID Code Change to FB Change •400 ns
“No CPU” Detection
Turn-off Delay Time2VID Code Change to 11111X to PWM
going low •400 ns
VID Table Select Vtblsel To select VRM9 table
To select VRM10 table (becomes VID5) •
•43.5 V
V
Oscillator
Frequency fOSC •200 4000 kHz
Frequency V ariation fPHASE TA = +25°C, RT = 250kΩ, 4-Phase
TA = +25°C, RT = 115kΩ, 4-Phase
TA = +25°C, RT = 75kΩ, 4-Phase
•155 200
400
600
245 kHz
kHz
kHz
Output Voltage VRT RT = 100kΩ to GND •1.9 2.0 2.1 V
RAMPADJ Pin Accuracy VRAMPADJ VRAMPADJ = Vdac = +2K • (Vin–Vdac)/
(Rr+2k) •-50 +50 mV
RAMPADJ Input Current IRAMPADJ Current into RAMPADJ pin 0 100 µA
Current Sense Amplifier
Offset Voltage V OS(CSA) CSSUM–CSREF, Test Circuit 1 •-1.5 +1.5 mV
Input Bias Current IBIAS(CSA) •-50 +50 nA
Gain Bandwidth Product GBW COMP = FB 10 MHz
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
FAN5019 PRODUCT SPECIFICATION
6REV. 1.0.7 1/5/04
DC Gain 77 dB
Input Common Mode
Range CSSUM and CSREF •03V
Positioning Accuracy ∆VFB COMP = FB, Test Circuit 2 •-84 -80 -76 mV
Output Voltage Range ICSCOMP = ±100µA •0.1 3.3 V
Output Current IO(CSA) FB forced to VOUT – 3% Source/Sink 300 375 µA
Current Balance Circuit
Input Operating Range VSW(X)CM •-600 +200 mV
Input Resistance RSW(X) SW(X) = 0V •20 30 40 kΩ
Input Current ISW(X) SW(X) = 0V •4710µA
Input Current Matching ∆ISW(X) SW(X) = 0V •-5 +5 %
Current Limit Comparator
ILIMIT Output Voltage
Normal Mode
In Shutdown VILIMIT(NM)
VILIMIT(SD) RILIMIT = 250kΩ
IILIMIT = -100µA •
•2.9 3 3.1
400 V
mV
Output Current, Normal
Mode IILIMIT(NM) RILIMIT = 250kΩ12 µA
Maximum Output Current VIILIMIT = 3V •60 µA
Current Limit Threshold
Voltage VCL VCSREF–VCSCOMP
, RILIMIT = 250kΩ•105 125 150 mV
Current Limit Setting Ratio VCL/IILIMIT 10.4 mV/µA
Latch-off Delay Threshold VDELAY In Current Limit •1.7 1.8 1.9 V
Latch-off Delay Time tDELAY RDELAY = 250kΩ, CDELAY = 4.7nF 600 µs
Soft Start
Output Current,
Soft start Mode IDELAY(SS) During Start-up, DELAY < 2.8V •15 20 25 µA
Soft Start Delay Time TDELAY(SS) RDELAY = 250kΩ, CDELAY = 4.7nF,
VID = 011111 (1.475V) 400 µs
Enable Input
Input Low Voltage VIL(EN) •0.4 V
Input High Voltage VIH(EN) •0.8 V
Input Current, EN Low IIL(EN) EN = 0V •-1 1 µA
Input Current, EN High IIH(EN) EN = 1.25V •10 25 µA
Power Good Comparator
Under voltage Threshold VPWRGD(UV) Relative to DAC Output •-325 -250 -200 mV
Over voltage Threshold VPWRGD(OV) Relative to DAC Output •90 150 200 mV
Output Low Voltage VOL(PWRGD) IPWRGD(SINK) = 4mA •225 400 mV
Electrical Specifications (continued)
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter Symbol Conditions Min. Typ. Max. Units
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 7
Power Good Delay Time
Initial Start Up
VID Code Changing
VID Code Static
•1
100 250
200
10 ms
µs
ns
Crowbar Trip Point VCROWBAR Relative to Nominal DAC Output •90 150 200 mV
Crowbar Reset Point Relative to FBRTN •450 550 650 mV
Crowbar Delay Time
VID Code Changing
VID Code Static
tCROWBAR Over voltage to PWM Going Low •100 250
400 500
600 µs
ns
PWM Outputs
Output Voltage Low VOL(PWM) IPWM(SINK) = 400µA •160 500 mV
Output Voltage High V OH(PWM) IPWM(SOURCE) = 400µA •455.5 V
Input Supply
DC Supply Current EN = Logic High •510mA
UVLO Threshold VUVLO Vcc Rising (Vcc = 12V input) •6.5 6.9 7.8 V
UVLO Hysteresis •0.7 V
UVLO Threshold F alling •5.6 7.0
Electrical Specifications (continued)
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter Symbol Conditions Min. Typ. Max. Units
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
FAN5019 PRODUCT SPECIFICATION
8REV. 1.0.7 1/5/04
Internal Block Diagram
Phase
Current
Balancing
Circuit
VID
DAC
REF
Current
Limit
Circuit
Oscillator
UVLO
Shutdown
& Bias
11
28
19
1314
CMP
Soft
Start
2/3/4 Phase Driver
Logic
EN
RESET
SET
RESET
RESET
RESET
CURRENT
LIMIT
CROWBAR
12
CMP
CMP
CMP
CSA
Error
Amp
24
25
26
27
20
21
22
23
+
-
15
7 654321
18
16
17
10
EN
8
9
DELAY
VID4 VID3 VID2 VID1 VID0 VID5
COMP
PWRGD
EN
RT
FBRTN
FB
RAMPADJ
CSCOMP
CSSUM
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
ILIMIT
CSREF
SW1
PWM2
SW4
Delay
CMP
CMP
DAC
-250mV
CSREF
DAC
+150mV
2K
3.75V
Sel VRM9 Table
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 9
Typical Characteristics
Test Circuits
TPC 1. Master Clock Frequency
TPC 2. Supply Current vs. Master Clock Frequency
3.5
4
3
2.5
2
1.5
1
0.5
01000 200
RESISTOR’S RT VALUE (kΩ)
MASTER CLOCK FREQUENCY (MHz)
300 400
5.2
5.3
5.1
5.0
4.9
4.8
4.7
4.6 1.00 2.0
MASTER CLOCK FREQUENCY (MHz)
SUPPLY CURRENT (mA)
3.0 4.00.5 1.5 2.5 3.5
TA = 25°C
4-Phase Operation
VCC
28
18
19
17
16 CSREF
CSSUM
CSCOMP
GND
CSA
100nF
39kΩ
1kΩ
1V
+12V
40
CSCOMP–1V
VOS =
Test Circuit 1. Current Sense Amplifier VOS
VCC
28
18
19
17
16 CSREF
CSSUM
CSCOMP
GND
CSA
100nF200kΩ
1V
+12V
9
8
10kΩ
FB
COMP
200k Ω
80mV
VIDFB
VFB
V
−=
∆
Test Circuit 2. Voltage Positioning
VID4
VID0
VID1
VID2
VID3
VID5
FAN5019
VCC1VID4
8
11
10
9
12
14
13
6
5
4
7
3
2
28
21
18
19
20
17
15
16
23
24
25
22
26
27
RAMPADJ
RT
DELAY
EN
PWRGD
COMP
FB
FBRTN
VID5
VID0
VID1
VID2
VID3
ILIMIT
CSREF
CSSUM
CSCOMP
GND
SW4
SW3
SW2
SW1
PWM4
PWM3
PWM2
PWM1
250kΩ
100nF
4.7nF 250kΩ
20kΩ
1µF
100nF+12V
1kΩ
Test Circuit 3. Closed Loop Output Voltage Accuracy
FAN5019 PRODUCT SPECIFICATION
10 REV. 1.0.7 1/5/04
Application Circuit
Figure 1. Typical Application – 3-phase, 65A (DC), 74A (Peak) VRD/VRM10 Design
U1 FAN5009
4
6
2
3
8
1
5
7
HDRVVCC
PGND BOOT
SW
LDRVPWM
OD
+12V
U4 FAN5019
VCC
1VID4
8
11
10
9
12
14
13
6
5
4
7
3
2
28
21
18
19
20
17
15
16
23
24
25
22
26
27RAMPADJ
RT
DELAY
EN
PWRGD
COMP
FBFBRTN
VID5/SEL
VID0
VID1
VID2
VID3
ILIMIT
CSREF
CSSUM
CSCOMP
GND
SW4
SW3
SW2
SW1
PWM4
PWM3
PWM2
PWM1
Q4
L1
Q5
Q1
C
X
Vcc CORE
0.8375V - 1.600V
74A DC, 93A Peak
C
IN
+12V
C
DLY
R
TH
*
R
T
R
DLY
C
FB
R
A
C
A
R
B
C
B
C
CS
R
CS1
R
SW1
R
SW3
R
SW2
R
CS2
R
PH1
R
PH2
R
PH3
C1
C4
C8
R19
C12
4
6
2
3
8
1
5
7
HDRVVCC
PGND BOOT
SW
LDRVPWM
OD
Q6
L2
Q7
Q2
+12V
C2
C5
C9
R20
C13
4
6
2
3
8
1
5
7
HDRVVCC
PGND BOOT
SW
LDRVPWM
OD
Q8
L3
Q9
Q3
+12V
C3
C6
C10
R21
C14
R
LIM
C7
R
R
R1
R5
L4
V
IN
V
IN
V
IN
PWRGD
EN
C
Z
R
B1
U3 FAN5009
U2 FAN5009
Note:
The design shown in this datasheet should be used as a reference only. Please contact your Fairchild sales representative for the latest information.
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 11
Bill of Materials
Table 1. FAN5019 VRM/VRD10 Application Bill of Materials for Figure 1
Note:
The design shown in this datasheet should be used as a reference only. Please contact your Fairchild sales representative
for the latest information.
Ref Qty Description Manufacturer/Number
U4 1 VRM10, Multi-Phase Controller Fairchild FAN5019
U1–3 3 Sync MOSFET Driver, 12V/12V Fairchild FAN5009
Q1–3 3 N-MOSFET, 30V, 50A, 8mΩ Fairchild FDD6696
Q4–9 6 N-MOSFET, 30V, 75A, 5mΩ Fairchild FDD6682
L1–3 3 Inductor, 650nH, 26A, 1.6mΩ Micrometals T50-8B/90, 5T, 16AWG
L4 1 Inductor, 630nH, 15A, 1.7mΩ Inter-Technical AK1418160052A-R63M
R1 1 10Ω, 5%
RR RDLY, RT3 301kΩ, 1%
R5 1 15.0kΩ, 1%
RPH1–3 3 100kΩ, 1%
RA, RCS2 2 24.9kΩ, 1%
RB1 1 10Ω, 1%
RB1 1.33kΩ, 1%
RSW1–3 3 0Ω, 5%
RCS1 1 37.4kΩ, 1%
RLIM 1 200kΩ, 1%
R19–21 3 1.5Ω, 5%
RTH 1 NTC Thermistor, 100kΩ, 5% Panasonic ERT-J1V V104J
C1–7 7 1.0µF, 25V, 10% X7R
C8–10 3 0.1µF, 50V, 10% X7R
C12–14, CCS 4 4700pF, 25V, 10% X7R
CDLY 1 0.047µF, 25V, 10% X7R
CB1 2200pF, 25V, 10% X7R
CA1 470pF, 50V, 10% X7R
CFB 1 100pF, 50V, 5% NPO
CX8 820µF, 2.5V, 20% 7mΩ, POLY Fujitsu FP-2R5RE821M
CZ22 10µF, 6.3V, 20% X5R
CIN 6 470µF, 16V, 20%, 36mΩ, Alum-Elec Rubycon 16MBZ470M
FAN5019 PRODUCT SPECIFICATION
12 REV. 1.0.7 1/5/04
Table 2. VRM10 VID Codes
VID4 VID3 VID2 VID1 VID0 VID5 VOUT (nominal)
11111XNo CPU
0101000.8375 V
0100110.8500 V
0100100.8625 V
0100010.8750 V
0100000.8875 V
0011110.9000 V
0011100.9125 V
0011010.9250 V
0011000.9375 V
0010110.9500 V
0010100.9625 V
0010010.9750 V
0010000.9875 V
0001111.0000 V
0001101.0125 V
0001011.0250 V
0001001.0375 V
0000111.0500 V
0000101.0625 V
0000011.0750 V
0000001.0875 V
1111011.1000 V
1111001.1125 V
1110111.1250 V
1110101.1375 V
1110011.1500 V
1110001.1625 V
1101111.1750 V
1101101.1875 V
1101011.2000 V
1101001.2125 V
1100111.2250 V
1100101.2375 V
1100011.2500 V
1100001.2625 V
1011111.2750 V
1011101.2875 V
1011011.3000 V
1011001.3125 V
1010111.3250 V
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 13
1010101.3375 V
1010011.3500 V
1010001.3625 V
1001111.3750 V
1001101.3875 V
1001011.4000 V
1001001.4125 V
1000111.4250 V
1000101.4375 V
1000011.4500 V
1000001.4625 V
0111111.4750 V
0111101.4875 V
0111011.5000 V
0111001.5125 V
0110111.5250 V
0110101.5375 V
0110011.5500 V
0110001.5625 V
0101111.5750 V
0101101.5875 V
0101011.6000 V
Table 2. VRM10 VID Codes (continued)
VID4 VID3 VID2 VID1 VID0 VID5 VOUT (nominal)
FAN5019 PRODUCT SPECIFICATION
14 REV. 1.0.7 1/5/04
Table 3. VRM9 VID Codes
VID4 VID3 VID2 VID1 VID0 VOUT (nominal)
11111No CPU
111101.100 V
111011.125 V
111001.150 V
110111.175 V
110101.200 V
110011.225 V
110001.250 V
101111.275 V
101101.300 V
101011.325 V
101001.350 V
100111.375 V
100101.400 V
100011.425 V
100001.450 V
011111.475 V
011101.500 V
011011.525 V
011001.550 V
010111.575 V
010101.600 V
010011.625V
010001.650V
001111.675V
001101.700V
001011.725V
001001.750V
000111.775V
000101.800V
000011.825V
000001.850V
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 15
General Description
Note: The information in this section is intended to assist the
user in their design and understanding of the FAN5019
functionality. For clarity and ease of understanding, device
parameters have been included in the text. In the event of
discrepancies between values stated in this section and the
actual specification tables, the specification tables shall be
deemed correct.
Theory of Operation
The FAN5019 combines a multi-mode, fixed frequency
PWM control with multi-phase logic outputs for use in
2, 3 and 4 phase synchronous buck CPU core supply power
converters. If VID5 is pulled up to a voltage greater than
VTBLSEL, then the DAC code corresponds to VRM9.
Multi-phase operation is important for producing the high
currents and low v oltages demanded by today’s microproces-
sors. Handling the high currents in a single-phase converter
would place high thermal demands on the components in the
system such as the inductors and MOSFETs. The internal
6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifications.
The multi-mode control of the FAN5019 ensures a stable,
high performance topology for:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
•Tight load line regulation and accuracy
• High current output from having up to 4 phase operation
• Reduced output ripple due to multi-phase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation for tailoring design to low cost or
high performance
Number of Phases
The number of operational phases and their phase relation-
ship is determined by internal circuitry which monitors the
PWM outputs. Normally , the FAN5019 operates as a 4-phase
PWM controller. Grounding the PWM4 pin programs three
phase operation; grounding the PWM3 and PWM4 pins
programs 2-phase operation.
When the FAN5019 is initially enabled, the controller out-
puts a voltage on PWM3 and PWM4 that is approximately
550 mV. An internal comparator checks each pin’s voltage
versus a threshold of 400mV. If the pin is grounded, then it
will be below the threshold and the phase will be disabled.
The output impedance of the PWM pin is approximately
5kΩ. Any external pull-down resistance connected to the
PWM pin should not be less than 25kΩ to ensure proper
operation. The phase detection is made prior to starting
normal operation. After this time, if the PWM output was not
grounded, then it will operate normally. If the PWM output
was grounded, then it will remain off.
The PWM outputs become logic-level output devices once
normal operation starts, and are intended for driving e xternal
gate drivers. Since each phase is monitored independently,
operation approaching 100% duty cycle is possible. Also,
more than one output can be on at a time for overlapping
phases.
Master Clock Frequency
The clock frequency of the FAN5019 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph shown in TPC 1. To determine the fre-
quency per phase, the clock is divided by the number of
phases in use. If PWM4 is grounded, then divide the master
clock by 3 and if both PWM3 and 4 are grounded, then
divide by 2. If all phases are in use, divide by 4.
Output Voltage Differential Sensing
The FAN5019 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
amplifier to maintain a worst-case specification of ±10 mV
differential sensing error with a VID input of 1.600 V ov er its
full operating output voltage and temperature range. The
output voltage is sensed between the FB and FBRTN pins.
FB should be connected through a resistor to the regulation
point, usually the remote sense pin of the microprocessor.
FBRTN should be connected directly to the remote sense
ground point. The internal VID DAC and precision reference
are referenced to FBRTN, which has a typical current of
150µA, to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
Output Current Sensing
The FAN5019 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detec-
tion. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the
low side MOSFET. This amplifier can be configured several
ways depending on the objectives of the system:
• Output inductor DCR sensing without thermistor for
lowest cost
• Output inductor DCR sensing with thermistor for
improved accuracy with tracking of inductor temperature
• Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF
pin, which is connected to the output voltage. The inputs to
the amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
FAN5019 PRODUCT SPECIFICATION
16 REV. 1.0.7 1/5/04
inductors) to the inverting input, CSSUM. The feedback
resistor between CSCOMP and CSSUM sets the gain of the
amplifier, and a filter capacitor is placed in parallel with this
resistor. The gain of the amplifier is programmable by adjust-
ing the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF –CSCOMP. This difference signal is
used internally to offset the VID D AC for v oltage positioning
and as a differential input for the current limit comparator.
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage.
Also, the sensing gain is determined by external resistors so
that it can be made extremely accurate and flexible.
Active Impedance Control Mode
For controlling the output voltage droop as a function of
output current, a voltage signal proportional to the total
inductor currents is created by the current sense amplifier
(CSA). The ratio of this voltage to the output current is
determined by external components to allo w it to be adjusted
to set the required load line. Inside the chip the CSA output
voltage is subtracted from the DAC voltage which then is
used for the reference to the error amplifier. As the output
current increases the reference to the error amp decreases
causing the output voltage to decrease accordingly.
Current Control Mode and Thermal Balance
The FAN5019 has individual inputs for each phase which are
used for monitoring the current in each phase. This informa-
tion is combined with an internal ramp to create a current
balancing feedback system that has been optimized for initial
current balance accuracy and dynamic thermal balancing
during operation. This current balance information is inde-
pendent of the average output current information used for
positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the sup-
ply voltage for feed-forward control for changes in the sup-
ply. A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the applications section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 4) can be used
for adjusting FET thermal and current balance. Zero ohm
placeholder resistors should be provided in the initial layout
to allow the phase balance to be adjusted during design fine
tuning.
To increase the current in any given phase, make RSW for
that phase larger (mak e RSW = 0 for the hottest phase and do
not change during balancing). Increasing RSW to only 500Ω
will make a substantial increase in phase current. Increase
each RSW value by small amounts to achieve balance,
starting with the coolest phase first.
Voltage Control Mode
A high gain-bandwidth voltage mode error amplifier is used
for the voltage-mode control loop. The control input voltage
to the positive input is set via the VID 6-bit logic code
according to the voltages listed in Table 1. This voltage is
also offset by the droop voltage for active positioning of the
output voltage as a function of current, commonly known as
active voltage positioning. The output of the amplifier is the
COMP pin, which sets the termination voltage for the inter-
nal PWM ramps.
The negative input (FB) is tied to the output sense location
with a resistor RB and is used for sensing and controlling the
output voltage at this point. A current source from the FB pin
flowing through RB is used for setting the no-load offset
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop com-
pensation is incorporated in the feedback network between
FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20µA current source. The output voltage follows the ramp-
ing voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
CDLY, with a secondary effect from RDLY. Refer to the appli-
cations section for detailed information on setting CDLY.
If EN is taken low or VCC drops below UVLO, the DELAY
cap is reset to ground to be ready for another soft start cycle.
Figure 1 shows a typical start-up sequence for the FAN5019.
Over Current Limit and Latch-off Protection
The FAN5019 compares a programmable current limit set
point to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation,
the voltage on ILIMIT is 3V. The current through the exter-
nal resistor is internally scaled to give a current limit thresh-
old of approximately 10.4mV/µA. If the difference in
voltage between CSREF and CSCOMP rises above the cur-
rent limit threshold, the internal current limit amplifier will
control the internal COMP voltage to maintain the average
output current at the limit.
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 17
After the limit is reached, the 3V pull-up on the DELAY pin
is disconnected, and the external delay capacitor is dis-
charged through the e xternal resistor . A comparator monitors
the DELAY voltage and shuts off the controller when the
voltage drops below 1.8V. The current limit latch off delay
time is therefore set by the RC time constant discharging
from 3V to 1.8V. The application section discusses the
selection of CDLY and RDLY.
Because the controller continues to cycle the phases during
the latch-off delay time, if the short is removed before the
1.8V threshold is reached, the controller will return to nor-
mal operation. The recovery characteristic depends on the
state of PWRGD. If the output voltage is within the PWRGD
window, the controller resumes normal operation. However,
if short circuit has caused the output voltage to drop below
the PWRGD threshold, then a soft-start cycle is initiated.
The latch-off function can be reset by either c ycling VCC to
the FAN5019, or by cycling the Enable pin low for a short
time. To disable the short circuit latch off function, the
external resistor to ground should be left open, and a 1MΩ
resistor should be connected from VCC to the DELAY pin.
This prev ents the DELAY capacitor from discharging, so the
1.8V threshold is never reached. The resistor will have an
impact on the soft-start time because the current through it
will add to the internal 20µA current source.
During start-up when the output voltage is below 200mV, a
secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2V. This will limit the
voltage drop across the low side MOSFETs through the
current balance circuitry.
There is also an inherent per phase current limit that will pro-
tect individual phases in the case where one or more phases
may stop functioning because of a faulty component. This
limit is based on the maximum normal-mode COMP voltage.
Dynamic VID
The FAN5019 incorporates the ability to dynamically
change the VID input while the controller is running. This
allows the output voltage to change while the supply is run-
ning and supplying current to the load. This is commonly
referred to as VID-on-the-fly (OTF). A VID-OTF can occur
under either light load or heavy load conditions. The proces-
sor signals the controller by changing the VID inputs in mul-
tiple steps from the start code to the finish code. This change
can be either positive or negative.
When a VID input changes state, the FAN5019 detects the
change and ignores the D A C inputs for a minimum of 400ns.
This time is to prevent a false code due to logic skew while
the six VID inputs are changing. Additionally, the first VID
change initiates the PWRGD and CROWBAR blanking
functions for a minimum of 250µs to prevent a false
PWRGD or CROWBAR event. Each VID change will reset
the internal timer. Figure 4 shows the VID on-the-fly perfor-
mance when the output voltage is stepping up and the output
current is switching between minimum and maximum values
which is the worst-case situation.
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 5,
VID Change = 5mV, 5µs, 50 steps, IOUT Change = 5A to 65A
Figure 2. Start-Up Waveforms Figure 3. Overcurent Latch Off Waveform
Circuit of Figure 5 Circuit of Figure 5
Channel 1 – Vout, Channel 2 – Vcc Channel 1 – Vcc, Channel 2 – Vout
Channel 3 – OD, Channel 4 – Delay pin Channel 3 – OD, Channel 4 – Delay pin
FAN5019 PRODUCT SPECIFICATION
18 REV. 1.0.7 1/5/04
Power Good Monitoring
The Power Good comparator monitors the output v oltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indi-
cates that the output voltage is within the nominal limits
specified in the specifications table based on the VID volt-
age setting. PWRGD will go low if the output voltage is out-
side of this specified range. PWRGD is blanked during a
VID O TF e v ent for a period of 250µs to pre vent f alse signals
during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output v oltage e xceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 550mV.
Turning on the low-side MOSFETs pulls down the output
voltage as the reverse current builds up in the inductors.
If the output overvoltage is due to a short of the high side
MOSFET, this action will current limit the input supply
or blow its fuse, protecting the microprocessor from
destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher then its
logic threshold for the FAN5019 to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN5019 is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be con-
nected to the output disable pins of the FAN5009 drivers.
Because ILIMIT is grounded, this disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important to prevent discharging of the output capacitors
when the controller is shut off. If the driver outputs were not
disabled, then a negative voltage could be generated on the
output due to the high current discharge of the output
capacitors through the inductors.
Application Information
The design parameters for a typical Intel VRD10.x
compliant CPU application are as follows:
• Input voltage (VIN) = 12V
• VID setting voltage (VVID) = 1.500V
• Duty cycle (D) = 0.125
• Nominal output voltage at no load (VONL) = 1.480V
• Nominal output voltage at 65 A load (VOFL) = 1.3955V
• Static output voltage drop based on a 1.3 mΩ load line
(RO) from no load to full load
•(V
D) = VONL – VOFL = 1.480V – 1.3955V = 84.5mV
• Maximum Output Current (IO) = 65A
• Maximum Output Current Step (∆IO) = 60A
• Number of Phases (n) = 3
• Switching frequency per phase (fSW) = 228 kHz
Setting the Clock Frequency
The FAN5019 uses a fixed-frequency control architecture
with the frequency being set by an external timing resistor
(RT). The clock frequency and the number of phases deter-
mine the switching frequency per phase, which relates
directly to switching losses and the sizes of the inductors and
input and output capacitors. With n = 3 for three phases, a
clock frequency of 684kHz sets the switching frequency of
each phase, fSW, to 228kHz, which represents a practical
trade-off between the switching losses and the sizes of the
output filter components. TPC 1 shows that to achieve a
684kHz oscillator frequency, the correct value for RT is
301kΩ. Alternatively, the value for RT can be calculated
using:
where 5.0pF and 110nS are internal IC component values.
For good initial accurac y and frequency stability, it is recom-
mended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay
Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The first step is to set CDLY for the
soft-start ramp. This ramp is generated with a 20µA internal
current source. The value of RDLY will have a second order
impact on the soft-start time because it sinks part of the cur-
rent source to ground. However, as long as RDLY is kept
greater than 200kΩ, this effect is minor. The value for CDLY
can be approximated using:
( )
nSpFfn
R
SW
T11051−××
=(1)
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 19
Where tSS is the desired soft-start time. Assuming an RDLY
of 301kΩ and a desired a soft-start time of 3ms, CDLY is
35nF. A close standard value for CDLY is 47nF. Once CDLY
has been chosen, RDLY can be calculated for the current limit
latch-off time using:
If the result for RDLY is less than 200kΩ, then a smaller soft-
start time should be considered by recalculating the equation
for CDLY or a longer latch-off time should be used. In no
case should RDLY be less than 200kΩ. In this example, a
delay time of 8ms gives RDLY = 334kΩ. A close
standard 1% value is 301kΩ.
Inductor Selection
The choice of inductance value for the inductor determines
the ripple current in the inductor. Less inductance leads to
more ripple current, which increases the output ripple volt-
age and conduction losses in the MOSFETs, but allo ws using
smaller-size inductors and, for a specified peak-to-peak
transient deviation, less total output capacitance. Conversely ,
a higher inductance means lower ripple current and reduced
conduction losses, but requires larger-size inductors and
more output capacitance for the same peak-to-peak transient
deviation. In any multi-phase converter, a practical value for
the peak-to-peak inductor ripple current is less than 50% of
the maximum DC current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.
Equation 5 can be used to determine the minimum induc-
tance based on a given output ripple voltage:
Solving Equation 5 for a 10 mVp-p output ripple voltage
yields:
If the ripple voltage ends up less than that designed for, the
inductor can be made smaller until the ripple value is met.
This will allow optimal transient response and minimum
output decoupling.
The smallest possible inductor should be used to minimize
the number of output capacitors. Choosing a 650nH inductor
is a good choice for a starting point and gives a calculated
ripple current of 8.86A. The inductor should not saturate at
the peak current of 26.1A and should be able to handle the
sum of the power dissipation caused by the average current
of 21.7A in the winding and core loss.
Another important factor in the inductor design is the DC
Resistance (DCR), which is used for measuring the phase
currents. A large DCR will cause excessive power losses,
while too small a value will lead to increased measurement
error. A good rule of thumb is to have the DCR be about
1 to 1 1/2 times the droop resistance (RO). For our example,
we are using an inductor with a DCR of 1.6 mΩ.
Designing an Inductor
Once the inductance and DCR are known, the next step is
either to design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design
goals. It is also important to have the inductance and DCR
tolerance specified to keep the accuracy of the system con-
trolled. Using 15% for the inductance and 8% for the DCR
(at room temperature) are reasonable tolerances that most
manufacturers can meet.
The first decision in designing the inductor is to choose the
core material. There are several possibilities for providing
low core loss at high frequencies. Two examples are the
powder cores (e.g., Kool-Mm® from Magnetics, Inc. or
Micrometals) and the gapped soft ferrite cores (e.g., 3F3
or 3F4 from Philips). Low frequency powdered iron cores
should be avoided due to their high core loss, especially
when the inductor value is relatively low and the ripple
current is high.
The best choice for a core geometry is a closed-loop types,
such as pot cores, PQ, U, and E cores, or toroids. A good
compromise between price and performance are cores with a
toroidal shape.
There are many useful references for quickly designing a
power inductor, such as:
Magnetics Design References
1. Magnetic Designer Software Intusoft
(www.intusoft.com)
2. Designing Magnetic Components for High-Frequency
DC-DC Converters, by William T. McLyman,
Kg Magnetics, Inc. ISBN 1883107008
VID
SS
DLY
VID
DLY
V
t
R
V
AC ×
×
−= 2
20µ
(2)
DLY
DELAY
DLY
Ct
R
×
=96.1
(3)
()
Lf DV
I
SW
O
R×
−×
=1
(4)
()()
RIPPLESW
OVID
Vf DnRV
L××−××
≥1 (5)
()
nH
mVkHz
mV
L
534
10228 375.013.15.1 =
×−×Ω×
≥
FAN5019 PRODUCT SPECIFICATION
20 REV. 1.0.7 1/5/04
Selecting a Standard Inductor
The companies listed below can provide design consultation
and deliver power inductors optimized for high power
applications upon request.
Power Inductor Manufacturers
• Coilcraft
(847)639-6400
www.coilcraft.com
• Coiltronics
(561)752-5000
www.coiltronics.com
• Sumida Electric Company
(510) 668-0660
www.sumida.com
•Vishay Intertechnology
(402) 563-6866
www.vishay.com
Output Droop Resistance
The design requires that the regulator output voltage
measured at the CPU pins drops when the output current
increases. The specified voltage drop corresponds to a DC
output resistance (RO).
The output current is measured by summing together the
voltage across each inductor and then passing the signal
through a low-pass filter. This summer-filter is the CS
amplifier configured with resistors RPH(X) (summers), and
RCS and CCS (filter). The output resistance of the regulator is
set by the following equations, where RL is the DCR of the
output inductors:
One has the flexibility of choosing either RCS or RPH(X).
It is best to select RCS equal to 100kΩ, and then solve for
RPH(X) by rearranging Equation 6.
Next, use Equation 7 to solve for CCS:
It is best to hav e a dual location for CCS in the layout so stan-
dard values can be used in parallel to get as close to the v alue
desired. For this example, choosing CCS to be 4.7nF is a
good choice. For best accuracy, CCS should be a 5% or 10%
NPO capacitor. A close standard 1% value for RPH(X) is
100kΩ.
Inductor DCR Temperature Correction
With the inductor’s DCR being used as the sense element,
and copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor’s wind-
ing. Fortunately, copper has a well-known temperature coef-
ficient (TC) of 0.39%/°C.
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the
temperature variation of the inductor’s DCR. Due to the non-
linear nature of NTC thermistors, resistors RCS1 and RCS2
are needed (see Figure 5) to linearize the NTC and produce
the desired temperature tracking.
Figure 5. Temperature Compensation Circuit
The following procedure and e xpressions will yield v alues to
use for RCS1, RCS2, and RTH (the thermistor value at 25°C)
for a given RCS value.
1. Select an NTC to be used based on type and value. Since
we do not hav e a v alue yet, start with a thermistor with a
value close to RCS. The NTC should also have an initial
tolerance of better than 5%.
2. Based on the type of NTC, find its relative resistance
value at two temperatures. The temperatures to use that
work well are 50°C and 90°C. We will call these resis-
tance values A (A is RTH(50°C)/RTH(25°C)) and B (B is
RTH(90°C)/RTH(25°C)). Note that the NTC’ s relati ve v alue
is always 1 at 25°C.
3. Next, find the relative value of RCS required for each of
these temperatures. This is based on the percentage
change needed, which we will initially make 0.39%/°C.
We will call these r1 and r2 where:
L
XPH
CS
OR
RR
R×= )(
(6)
CSL
CS RR L
C×
= (7)
CS
O
L
XPH R
R
R
R×=
)(
Ω=Ω×
Ω
Ω
=kk
m
m
RXPH 123100
3.1 6.1
)(
nF
km nH
CCS 06.4
1006.1 650 =
Ω×Ω
=
18
17
16 CSREF
CSSUM
CSCOMP
CSA
CCS
1.8nF
RCS1
RCS2
RTH
RPH1
RPH3 RPH2
Keep this path as
short as possible
and well away from
Switch Node lines
Place as close as
possible to nearest
inductor or low-side
MOSFET
To Switch Nodes
To VOUT
sense
()( )
2511
1
1−×+
=TTC
r
()( )
2511
2
2−×+
=TTC
r
TC = 0.0039
T1 = 50°C
T2 = 90°C
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 21
4. Compute the relative values for RCS1, RCS2, and RTH
using:
5. Calculate RTH = rTH x RCS, then select the closest value
of thermistor available. Also compute a scaling factor k
based on the ratio of the actual thermistor value used
relative to the computed one:
6. Finally, calculate values for RCS1 and RCS2 using the
following:
For this example, RCS has been chosen to be 100kΩ, so we
start with a thermistor value of 100kΩ. Looking through
available 0603 size thermistors, we find a Panasonic
ERT-J1VV104J NTC thermistor with A = 0.2954 and
B = 0.05684. From these we compute RCS1 = 0.3304,
RCS2 = 0.7426 and RTH = 1.165. Solving for RTH yields
116.5 kΩ, so we choose 100kΩ, making k = 0.8585. Finally,
we find RCS1 and RCS2 to be 28.4kΩ and 77.9kΩ. Choosing
the closest 1% resistor values yields a choice of 35.7kΩ and
73.2kΩ.
Output Offset
Intel’s specification requires that at no load the nominal out-
put voltage of the regulator be offset to a lower value than
the nominal voltage corresponding to the VID code. The off-
set is set by a constant current source flowing out of the FB
pin (IFB) and flowing through RB. The value of RB can be
found using Equation 11:
The closest standard 1% resistor value is 1.33 kΩ.
COUT Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
The first thing is to select the total amount of ceramic capac-
itance. This is based on the number and type of capacitor to
be used. The best location for ceramics is inside the socket,
with 12 to 18 of size 1206 being the physical limit. Others
can be placed along the outer edge of the socket as well.
Combined ceramic values of 200µF–300µF are recom-
mended, usually made up of multiple 10µF or 22µF
capacitors. Select the number of ceramics and find the total
ceramic capacitance (CZ).
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-the-
fly voltage stepping of the output (v oltage step VV in time tV
with error VERR) and a lo wer limit based on meeting the crit-
ical capacitance for load release for a given maximum load
step ∆IO:
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be
less than two times the droop resistance, RO. If the CX(MIN)
is larger than CX(MAX), the system will not meet the VID
on-the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).
For our example, 22 10µF 1206 MLC capacitors
(CZ = 220µF) were used. The VID on-the-fly step change is
250mV in 150µs with a setting error of 2.5mV. Solving for
the bulk capacitance yields:
)()1()1( )1()1()(
21
1221
2BArABrBA rABrBArrBA
rCS −−×−×−×−× ×−×+×−×−××−
=
212
1
11)1(
CSCS
CS
rr A
r
A
r
−
−
−
−
= (8)
12
1
111
CSCS
TH
rr
r−
−
=
)(
)(
CALCULATEDTH
ACTUALTH
R
R
k= (9)
11 CSCSCS rkRR ××= (10)
()( )()
22 1CSCSCS rkkRR ×+−×=
FB
ONLVID
B
IVV
R−
= (11)
Ω=
−
=k
AVV
RB33.1
15 480.15.1 µ
−
×× ∆×
≥Z
VIDO
O
MINXC
VRn IL
C)( (12)
Z
O
V
VID
V
VID
V
O
MAXXC
L
nKR
V
V
t
V
V
RnKL
C−
−
×+××≤ 11
2
22
)(
(13)
where
−= V
VERR
V
V
Kln
FAN5019 PRODUCT SPECIFICATION
22 REV. 1.0.7 1/5/04
mFF
Vm AnH
CMINX45.6220
5.13.13 60650
)( =
−
×Ω× ×
≥µ
( )
m
F
F
nHmV mVs
Vm
mVnH
CMAXX9.232201
650250 3.16.435.1150
1
5.13.16.43
250650 2
2
2
)( =−
−
×Ω××××
+×
×Ω×× ×
≤µ
µ
where K=4.6
Using eight 820µF A1-Polys with a typical ESR of 8mΩ,
each yields CX = 6.56µF with an RX = 1.0mΩ. One last
check should be made to ensure that the ESL of the bulk
capacitors (LX) is low enough to limit the initial high-
frequency transient spike. This can be tested using:
In this example, LX is 375pH for the eight A1-Poly capaci-
tors, which satisfies this limitation. If the LX of the chosen
bulk capacitor bank is too large, the number of MLC capaci-
tors must be increased. One should note for this multi-mode
control technique, “all-ceramic” designs can be used as
long as the conditions of Equations 11, 12 and 13 are
satisfied.
Power MOSFETs
For this e xample, the N-channel power MOSFETs ha ve been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are VGS(TH), QG, CISS, CRSS and RDS(ON).
The minimum gate drive voltage (the supply voltage to the
FAN5009) dictates whether standard threshold or logic-lev el
threshold MOSFETs must be used. With VGATE ~10V,
logic-level threshold MOSFETs (VGS(TH) < 2.5V) are
recommended. The maximum output current IO determines
the RDS(ON) requirement for the low-side (synchronous)
MOSFETs. With the FAN5019, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (nSF). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output
current (IO):
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required RDS(ON) for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50ºC, a safe
limit for PSF is 1W–1.5W at 125ºC junction temperature.
Thus, for our example (65A maximum), we find RDS(SF)
(per MOSFET) < 8.7mΩ. This RDS(SF) is also at a junction
temperature of about 125ºC, so we need to make sure we
account for this when making this selection. For our exam-
ple, we selected two lower side MOSFETs at 8.6mΩ each at
room temperature, which gives 8.4mΩ at high temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10% is
recommended), to prevent accidental turn-on of the synchro-
nous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5009). The
output impedance of the driver is about 2Ω and the typical
MOSFET input gate resistances are about 1Ω–2Ω, so a total
gate capacitance of less than 6000pF should be adhered to.
Since there are two MOSFETs in parallel, we should limit
the input capacitance for each synchronous MOSFET to
3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switch-
ing losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and of f, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where nMF is the total number of
main MOSFETs:
Here, RG is the total gate resistance (2Ω for the FAN5009
and about 1Ω for typical high speed switching MOSFETs,
making RG = 3Ω) and CISS is the input capacitance of the
main MOSFET. It is interesting to note that adding more
main MOSFETs (nMF) does not really help the switching
loss per MOSFET since the additional gate capacitance
slows down switching. The best way to reduce switching
loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the ON-resistance of the
MOSFET:
2
O
RCL
ZX
×≤
(14)
()
pHmFL
X
3723.1220
2
=Ω×≤µ
( )
)(
22
12
1
1SFDS
SF
R
SF
O
SF R
nIn
n
I
DP ×
×
×+
×−= (15)
ISS
MF
G
MF
OCC
SWMFS
C
n
n
R
nIV
fP ×××
×
××= 2
)( (16)
)(
22
)( 12
1MFDS
MF
R
MF
O
MFCR
nIn
n
I
DP ×
×
×+
×= (17)
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 23
Typically, for main MOSFETs, one wants the highest
speed (low CISS) device, but these usually have higher
ON-resistance. One must select a device that meets the total
power dissipation (about 1.5 W for a single D-PAK) when
combining the switching and conduction losses.
For our e xample, we hav e selected a Fairchild FD6696 as the
main MOSFET (three total; nMF = 3), with a Ciss = 2058 pF
(max) and RDS(MF) = 15m (max at TJ = 125ºC) and an
Fairchild FDD6682 as the synchronous MOSFET (six total;
nSF = 6), with Ciss = 2880pF (max) and RDS(SF) = 11.9mΩ
(max at TJ = 125ºC). The synchronous MOSFET Ciss is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at IO = 65A and IR = 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last thing to look at is the power dissipation in the dri v er
for each phase. This is best described in terms of the QG for
the MOSFETs and is giv en by the following, where QGMF is
the total gate charge for each main MOSFET and Q GSF is the
total gate charge for each synchronous MOSFET:
Also shown is the standby dissipation factor (ICC times the
VCC) for the driv er. For the FAN5009, the maximum dissipa-
tion should be less than 400 mW. For our example, with
ICC = 7 mA, QGMF = 24nC (max) and QGSF = 31nC (max),
we find 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN5009 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. The value of this resistor is chosen to
provide the best combination of thermal balance, stability,
and transient response. The following expression is used for
determining the optimum value:
where AR is the internal ramp amplifier gain, AD is the
current balancing amplifier gain, RDS is the total low-side
MOSFET ON-resistance, and CR is the internal ramp
capacitor value. A close standard 1% resistor value is 301k Ω.
The internal ramp voltage magnitude can be calculated
using:
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output v oltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
For this example, the overall ramp signal is found to be
0.974V.
Current Limit Set Point
To select the current limit set point, we need to find the
resistor value for RLIM. The current limit threshold for the
FAN5019 is set with a 3V source (VLIM) across RLIM with
a gain of 10.4mV/mA (ALIM). RLIM can be found using the
following:
For v alues of RLIM greater than 500kΩ, the current limit may
be lower than e xpected, so some adjustment of R LIM may be
needed. Here, ILIM is the average current limit for the output
of the supply. For our example, choosing 120A for ILIM, we
find RLIM to be 200kΩ, for which we chose 200kΩ as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
For the FAN5019, the maximum COMP voltage
(VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS)
is 1.2V, and the current balancing amplifier gain (AD) is 5.
Using VR of 0.765V, and RDS(MAX) of 5.95mΩ (low-side
ON-resistance at 125°C), we find a per-phase limit of 40.44A.
()
CCCCGSFSFGMFMF
SW
DRV VIQnQn
n
f
P×
+×+××
×
=2 (18)
RDSD
R
RCRA LA
R
××× ×
=3 (19)
Ω=
×Ω×× ×
=k
pFmnH
RR291
595.553 6502.0
()
SWRR
VIDR
RfCR VDA
V×× ×−×
=1 (20)
()
V
kHzpFkV
VR765.0
2285301 5.1125.012.0 =
××Ω ×−×
=
( )
××× ×−×
−
=
OXSW
R
RT
RCfn Dn
V
V12
1
(21)
OLIM
LIMLIM
LIM RI VA
R
×
×
= (22)
2
)(
)( R
MAXDSD
BIASRMAXCOMP
PHLIM I
RA
VVV
I
−
×−−
≅ (23)
FAN5019 PRODUCT SPECIFICATION
24 REV. 1.0.7 1/5/04
()
VIDOX
RT
VID
RTL
DSDOE VRCn VDnL
VVR
RARnR ××× ××−××
+
×
+×+×= 12 (25)
( )
X
O
O
X
OXA RRR
R
L
RRCT '
'−
×+−×= (26)
( )
s
mmm
m
pH
mmmFTAµ79.4
0.1 6.03.1
3.1
375
6.03.156.6 =
ΩΩ−Ω
×
Ω
+Ω−Ω×=
()
XOXB CRRRT ×−+= ' (27)
()
Ω=
×Ω×× ×−××
+
×Ω
+Ω×+Ω×= m
VmmF VnH
VVm
mmRE3.55
5.13.156.63 974.0375.016502
5.1 974.06.1
95.553.13
This limit can be adjusted by changing the ramp voltage VR.
But make sure not to set the per-phase limit lower than the
average per-phase current (ILIM/n).
There is also a per phase initial duty cycle limit determined
by:
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN5019 allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (RO). With the resistive output impedance,
the output voltage will droop in proportion with the load
current at any load current sle w rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
With the multimode feedback structure of the FAN5019, one
needs to set the feedback compensation to make the con-
verter’s output impedance work in conjunction with the out-
put decoupling to meet this goal. There are se v eral poles and
zeros created by the output inductor and decoupling capaci-
tors (output filter) that need to be compensated for.
A type-III compensator on the voltage feedback is adequate
for proper compensation of the output filter. The e xpressions
given in Equations 25–29 are intended to yield an optimal
starting point for the design; some adjustments may be nec-
essary to account for PCB and component parasitic effects
(see the Tuning Procedure for the FAN5019 section).
The first step is to compute the time constants for all of the
poles and zeros in the system:
where, for the FAN5019, R’ is the PCB resistance from the
bulk capacitors to the ceramics and where RDS is approxi-
mately the total low-side MOSFET ON resistance per phase
at 25ºC. For this example, AD is 5, VRT equals 0.974V, R’ is
approximately 0.6mΩ (assuming a 4-layer motherboard) and
LX is 375pH for the eight Al-Poly capacitors.
The compensation values can then be solved for using the
following:
RT
BIASMAXCOMP
MAX
V
VV
D
D
−
×=
)( (24)
()
smFmmmTBµ97.156.63.16.00.1 =×Ω−Ω+Ω=
EVID
SW
DSD
RT
C
RV
f
RA
LV
T×
××
−×
=2 (28)
s
m
V
kHz
m
nHV
TCµ86.6
3.555.1 2282 95.65
650974.0 =
Ω×
×Ω×
−×
=
( )
OZOX
OZX
DRCRRC
RCC
T×+−× ××
='
2 (29)
()
()
ns
mFmmmF
mFmF
TD500
3.12206.03.156.6 3.122056.6 2=
Ω×+Ω−Ω× Ω××
=µ
µ
BE
AO
A
RR
TRn
C×××
=
(30)
pF
km
sm
CA253
33.13.55 79.43.13 =
Ω×Ω ×Ω×
=
µ
Ω=== k
pF
s
C
T
R
A
C
A1.27
253
86.6
µ
(31)
nF
k
s
R
T
C
B
B
B48.1
33.1 97.1 =
Ω
== µ (32)
pF
k
ns
R
T
C
A
D
FB 5.18
1.27
500 =
Ω
== (33)
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 25
Choosing the closest standard values for these components
yields: CA = 390pF, RA = 16.9kΩ, CB = 1.5nF, and CFB =
33pF.
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of
the high-side MOSFET is approximately a square wa ve with
a duty ratio equal to n (VOUT/VIN) and an amplitude of one-
nth of the maximum output current. To prevent lar ge voltage
transients, a low ESR input capacitor sized for the maximum
rms current must be used. The maximum rms capacitor cur-
rent is given by:
Figure 6. Typical Transient Response for Design Example
Note that the capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Sev eral
capacitors may be placed in parallel to meet size or height
requirements in the design. In this example, the input
capacitor bank is formed by three 2200µF, 16V Nichicon
capacitors with a ripple current rating of 3.5A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1A/µs, an additional small inductor (L > 1µH
@ 15A) should be inserted between the converter and the
supply bus. That inductor also acts as a filter between the
converter and the primary power source.
Tuning Procedure for the FAN5019
DC Load line Setting
1. Build circuit based on compensation values computed
from design spreadsheet.
2. Hook up DC load to circuit, turn on and verify opera-
tion. Also check for jitter at no-load and full-load.
3. Measure output voltage at no-load (VNL). Verify it is
within tolerance.
Figure 7. Efficiency vs. Output Current
(Circuit of Figure 5)
4. Measure output voltage at full-load cold (VFLCOLD).
Let board soak for ~10 minutes at full-load and measure
output (VFLHOT). If there is a change of more than a
couple of millivolts, adjust RCS1 and RCS2 using
Equations 35 and 37.
5. Repeat Step 4 until cold and hot voltage measurements
remain the same.
6. Measure output voltage from no-load to full-load using
5 Amp steps. Compute the loadline slope for each
change and then average to get overall loadline slope
(ROMEAS).
7. If ROMEAS is off from RO by more than 0.05 mΩ,
use the following to adjust the RPH values:
8. Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9. Once complete with DC loadline adjustment, do not
change RPH, RCS1, RCS2, or RTH for rest of procedure.
1
1−
×
××= Dn
IDI
OCRMS
(34)
AAI
CRMS
5.101
125.03 1
65125.0 =−
×
××=
()
()
FLHOTNL
FLCOLDNL
OLDCSNEWCS VV VV
R
R
−
−
×= )(2)(2 (35)
80
100
60
40
20
020040
OUTPUT CURRENT (A)
EFFICIENCY (%)
6010 30 50
O
OMEAS
OLDPHNEWPH
R
R
R
R
×=
)()(
(36)
FAN5019 PRODUCT SPECIFICATION
26 REV. 1.0.7 1/5/04
(37)
()
( )
)25()25(
)(1)(2)(2
)25(
)(1
)25(
)(
)( 1
1
CTHCTH
OLDCSNEWCSOLDCS
CTH
OLDCS
CTH
OLDCS
NEWCS
ooo
o
RRRRRRR
RR
R−
−×−+× +
=
10. Measure the output ripple at no-load and full-load with
scope and make sure it is within spec.
AC Loadline Setting
11. Remove DC load from circuit and hook up dynamic
load.
12. Hook up scope to output voltage and set to DC coupling
with a time scale at 100µs/div.
13. Set dynamic load for a transient step of about 40A at
1kHz with 50% duty cycle.
14. Measure output waveform (may have to use DC offset
on scope to see waveform). Try to use vertical scale of
100 mV/div or finer.
15. You will see a waveform that looks something like
Figure 8. Use the horizontal cursors to measure VACDRP
and VDCDRP as shown.
DO NOT MEASURE THE UNDERSHOOT OR OVER-
SHOOT THAT HAPPENS IMMEDIATELY AFTER THE
STEP.
Figure 8. AC Loadline Waveform
16. If the VACDRP and VDCDRP are different by more than a
couple of millivolts, use Equation 38 to adjust CCS. Y ou
may need to parallel different values to get the right one
since there are limited standard capacitor values avail-
able (it is a good idea to have locations for two capaci-
tors in the layout for this).
17. Repeat Steps 11 to 13 and repeat adjustments if
necessary. Once complete, do not change CCS for the
rest of the procedure.
18. Set dynamic load step to maximum step size (do not use
a step size larger than needed) and v erify that the output
waveform is square (which means VACDRP and
VDCDRP are equal). NOTE: MAKE SURE LOAD
STEP SLEW RATE AND TURN-ON ARE SET FOR A
SLEW RATE OF ~150–250A/µs (for example, a load
step of 50A should take 200ns–300ns) WITH NO
OVERSHOOT. Some dynamic loads will have an
excessive turn-on o v ershoot if a minimum current is not
set properly (this is an issue if using a VTT tool).
Initial Transient Setting
19. With dynamic load still set at maximum step size,
expand scope time scale to see 2µs/div to 5µs/div. You
will see a waveform that may have two overshoots and
one minor undershoot (see Figure 9). Here, VDROOP is
the final desired value.
Figure 9. Transient Setting Waveform
20. If both ov ershoots are larger than desired, try making the
following adjustments in this order. (NOTE: If these
adjustments do not change the response, you are limited
by the output decoupling.) Check the output response
each time you make a change as well as the switching
nodes (to make sure it is still stable).
a. Make ramp resistor larger by 25% (RRAMP).
b. For VTRAN1, increase CB or increase switching fre-
quency.
c. For VTRAN2, increase RA and decrease CA by 25%.
21. For load release (see Figure 10), if VTRANREL is larger
than VTRAN1 (see Figure 9), you do not have enough
output capacitance. You will either need more capaci-
tance or to make the inductor values smaller (if you
change inductors, you need to start the design ov er using
the spreadsheet and this tuning procedure).
DCDRP
ACDRP
OLDCSNEWCS V
V
CC ×= )()( (38)
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 27
Figure 10. Transient Setting Waveform
Since the FAN5019 turns off all of the phases (switches
inductors to ground), there is no ripple voltage present
during load release. Thus, you do not have to add headroom
for ripple, allowing your load release VTRANREL to be lar ger
than VTRAN1 by that amount and still be meeting spec. If
VTRAN1 and VTRANREL are less than the desired final droop,
this implies that capacitors can be remov ed. When removing
capacitors, make sure to check the output ripple voltage as
well to make sure it is still within spec.
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
Key layout issues are illustrated in Figure 11.
Figure 11. Layout Recommendations
General Recommendations
•For good results, at least a four-layer PCB is
recommended. This should allow the needed versatility
for control circuitry interconnections with optimal
placement, power planes for ground, input, and output
power, and wide interconnection traces in the rest of the
power delivery current paths. Keep in mind that each
square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
• Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
• If critical signal lines (including the output voltage sense
lines of the FAN5019) must cross through power circuitry,
it is best if a signal ground plane can be interposed
between those signal lines and the traces of the power
circuitry to serves as a shield to minimize noise injection
into the signals..
• An analog ground plane should be used both around and
under the FAN5019 for ground connections to the
components associated with the controller. This plane
should be tied to the nearest output decoupling capacitor
ground and should not tie to any other power circuitry to
prevent power currents from flowing in it.
• The components around the FAN5019 should be located
close to the controller with short traces. The most
important traces to keep short and away from other traces
are the FB and CSSUM pins.
• The output capacitors should be connected as close as
possible to the load (or connector) that receiv es the power
(e.g., a microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic.
Power Circuitry
•The switching power path should be routed on the PCB to
encompass the shortest possible length in order to
minimize radiated switching noise energy (i.e., EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire
PC system as well as noise related operational problems
in the power converter control circuitry. The switching
power path is the loop formed by the current path through
the input capacitors and the power MOSFETs including
all interconnecting PCB traces and planes. The use of
short and wide interconnection traces is especially critical
in this path for two reasons: it minimizes the inductance in
the switching loop, which can cause high-energy ringing,
and it accommodates the high current demand with
minimal voltage loss. Avoid crossing any signal lines o ver
the switching power path loop, described below.
FAN5019 PRODUCT SPECIFICATION
28 REV. 1.0.7 1/5/04
• Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. Make a mirror image of any
pad being used to heatsink the MOSFETs on the opposite
side of the PCB to achieve the best thermal dissipation to
the air around the board. To further improve thermal
performance, the largest possible pad area should be used.
• The output power path should also be routed to
encompass a short distance. The output power path is
formed by the current path through the inductor, the
output capacitors, and the load.
•For best EMI containment, a solid power ground plane
should be used as one of the inner layers extending fully
under all the power components.
Signal Circuitry
• The output voltage is sensed and regulated between the
FB pin and the FBRTN pin (which connects to the signal
ground at the load). In order to avoid differential mode
noise pickup in the sensed signal, the loop area should be
small. Thus the FB and FBRTN traces should be routed
adjacent to each other atop the power ground plane back
to the controller.
• The feedback traces from the switch nodes should be
connected as close as possible to the inductor . The CSREF
signal should be connected to the output voltage at the
nearest inductor to the controller.
PRODUCT SPECIFICATION FAN5019
REV. 1.0.7 1/5/04 29
Mechanical Dimensions
28-Pin TSSOP
9.7 ± 0.1
15
– B –
0.1 C
PIN # 1 IDENT 14 ALL Lead Tips
0.2
LAND PATTERN RECOMMENDATION
0.65 0.42
BA
– A –
4.4 ± 0.1
1.78
4.16
7.72
0.51 TYP
28
3.2
6.4
1.2 MAX
ALL LEAD TIPS
0.65 0.19–0.30
0.13
0.90 See Detail A
0.09–0.20
0.10 ± 0.05
0°–8°
R0.31
R0.16
.025
GAGE PLANE
SEATING PLANE
DETAIL A
0.61 ± 0.1
DIMENSIONS ARE IN MILLIMETERS
NOTES:
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANsI Y14.5M, 1982
1.00
12.00° Top & Botom
+0.15
–0.10
BCA
– C –
FAN5019 PRODUCT SPECIFICATION
1/5/04 0.0m 005
Stock#DS30005019
2003 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
Ordering Information
Part Number Temperature Range Package Packing
FAN5019MTC 0°C to +85°C TSSOP-28 Rail
FAN5019MTCX 0°C to +85°C TSSOP-28 Tape and Reel
