K4D261638K 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.3 July 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. * Samsung Electronics reserves the right to change products or specification without notice. - 1 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM Revision History Revision Month Year History 0.0 January 2006 - Target Spec - Defined target specification 1.0 September 2006 - Added the Current Spec - Added the IBIS Data 1.1 October 2006 - Added and Revised the IBIS Data 1.2 November 2006 - Added power up comment 1.3 July 2007 - Revised voltage comment of power up sequence - 2 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 1.0 FEATURES * 2.5V + 5% power supply for device operation * 2 DQS's ( 1DQS / Byte ) * 2.5V + 5% power supply for I/O interface * Data I/O transactions on both edges of Data strobe * SSTL_2 compatible inputs/outputs * DLL aligns DQ and DQS transitions with Clock transition * 4 banks operation * Edge aligned data & data strobe output * MRS cycle with address key programs * Center aligned data & data strobe input -. Read latency 2,3(clock) * DM for write masking only -. Burst length (2, 4 and 8) * Auto & Self refresh -. Burst type (sequential & interleave) * 32ms refresh period (4K cycle) * All inputs except data & DM are sampled at the positive going * Lead free 66pin TSOP-II (RoHS compliant) * Maximum clock frequency up to 250MHz edge of the system clock * Maximum data rate up to 500Mbps/pin * Differential clock input * Wrtie-Interrupted by Read Function 2.0 ORDERING INFORMATION Part NO. Max Freq. Max Data Rate K4D261638K-LC40 250MHz 500Mbps/pin K4D261638K-LC50 200MHz 400Mbps/pin Interface Package SSTL_2 66pin TSOP-II * K4D261638K-TC is the Leaded package part number. * For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V. 3.0 GENERAL DESCRIPTION FOR 2M x 16Bit x 4 Bank DDR SDRAM The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. - 3 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 4.0 PIN CONFIGURATION (Top View) VDD 1 66 VSS DQ0 2 65 DQ15 VDDQ 3 64 VSSQ DQ1 4 63 DQ14 DQ2 5 62 DQ13 VSSQ 6 61 VDDQ DQ3 7 60 DQ12 DQ4 8 59 DQ11 VDDQ 9 58 VSSQ DQ5 10 57 DQ10 DQ6 11 56 DQ9 VSSQ 12 55 VDDQ DQ7 13 54 DQ8 NC 14 53 NC VDDQ 15 52 VSSQ LDQS 16 51 UDQS NC 17 50 NC VDD 18 49 VREF NC 19 48 VSS LDM 20 47 UDM WE 21 46 CK CAS 22 45 CK RAS 23 44 CKE CS 24 43 NC NC 25 42 NC BA0 26 41 A11 BA1 27 40 A9 AP/A10 28 39 A8 A0 29 38 A7 A1 30 37 A6 A2 31 36 A5 A3 32 35 A4 VDD 33 34 VSS 66 PIN TSOP(II) (400mil x 875mil) (0.65 mm Pin Pitch) PIN DESCRIPTION CK,CK Differential Clock Input BA0, BA1 Bank Select Address CKE Clock Enable A0 ~A11 Address Input CS Chip Select DQ0 ~ DQ15 Data Input/Output RAS Row Address Strobe VDD Power CAS Column Address Strobe VSS Ground WE Write Enable VDDQ Power for DQ's L(U)DQS Data Strobe VSSQ Ground for DQ's L(U)DM Data Mask NC No Connection RFU Reserved for Future Use - 4 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ's and DM's that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. LDQS,UDQS Input/Output Data input and output are synchronized with both edge of DQS. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. LDM,UDM Input Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. DQ0 ~ DQ15 Input/Output BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU Data inputs/Outputs are multiplexed on the same pins. No connection/ This pin is recommended to be left "No connection" on the device Reserved for future use *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. - 5 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 6.0 BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank) 16 Intput Buffer I/O Control CK, CK Data Input Register Serial to parallel Bank Select LWE LDMi 2Mx16 16 Output Buffer 2-bit prefetch Sense AMP 2Mx16 32 x16 DQi 2Mx16 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Programming Register LRAS LCBR DLL Strobe Gen. LCKE Row Decoder Refresh Counter Row Buffer ADDR Address Register CK,CK 2Mx16 Data Strobe LWE LCAS LWCBR CK,CK LDMi Timing Register CK,CK CKE CS RAS CAS WE - 6 /19 - LDM UDM Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 7.0 FUNCTIONAL DESCRIPTION 7.1 Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. *1 *1,2 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before or with VDDQ . - Apply VDDQ before or with VREF & VTT - The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and the power voltage ramps are without any slope reversal 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. Power up & Initialization Sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ~ precharge ALL Banks EMRS MRS DLL Reset 1st Auto Refresh precharge ALL Banks ~ tRP tRFC tRFC 200 Clock min. Inputs must be stable for 200us 2nd Auto Refresh ~ ~ ~ 2 Clock min. 2 Clock min. Mode Register Set Any Command ~ 2 Clock min. ~ ~ tRP Command ~ CK,CK * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. - 7 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 7.2 MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. BA1 BA0 RFU*1 0 A11 A10 A9 RFU*1 DLL A8 A7 DLL TM A6 A5 DLL Reset 0 No 1 Yes A3 CAS Latency BT A1 Address Bus A0 Burst Length mode A3 Type 0 Normal 0 Sequential 1 Test 1 Interleave A7 CAS Latency Mode Register Burst Length BA0 An ~ A0 A6 A5 A4 Latency 0 MRS 0 0 0 Reserved 1 EMRS 0 0 1 0 1 0 0 1 1 0 1 *1 : RFU(Reserved for future use) should stay "0" during MRS cycle. A2 Burst Type Test Mode A8 A4 A2 A1 Reserved 0 0 2 0 0 1 3 0 1 0 Reserved 0 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved A0 Burst Type Sequential Interleave 0 Reserve Reserve 1 2 2 0 4 4 1 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve MRS Cycle 0 1 2 3 4 5 6 7 8 CK, CK Command NOP Precharge All Banks NOP NOP MRS NOP Any Command NOP NOP tMRD=2 tCK tRP *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. - 8 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 7.3 EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA1 BA0 RFU*1 1 BA0 A11 A10 A9 A8 A7 A6 A5 D.I.C RFU*1 A4 A3 RFU*1 A2 A1 A0 D.I.C DLL Output Driver Impedence Control A0 Address Bus Extended Mode Register An ~ A0 A6 A1 DLL Enable 0 MRS 0 0 Full 0 Enable 1 EMRS 0 1 Weak 1 Disable 1 1 Matced *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. - 9 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 7.4 WRITE INTERRUPTED BY A READ A burst write can be interrupted by a read command of any bank. The DQ's must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command. < Burst Length=8, CAS Latency=3 > 0 1 2 3 4 5 6 7 8 NOP NOP READ NOP CK CK CMD NOP WRITE NOP NOP NOP tWPRES NOP tWR tDQSSmax DQS NOP tWPREH DQ s Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7 Dout 0 DM The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory. 1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay is 1 clock cycle is disallowed 2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting Read operation and the input data word which immediately follows the interrupting Read operation 3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow the buses to turn around before the DDR SDRAM drives them during a read operation. 4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM. 5. Refer to "3.3.2 Burst write operation" 8.0 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 2.0 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. - 10 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 9.0 AC & DC OPERATING CONDITIONS 9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65C) Symbol Min Typ Max Unit Note Device Supply voltage Parameter VDD 2.375 2.50 2.625 V 1, 7 Output Supply voltage VDDQ 2.375 2.50 2.625 V 1, 7 Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V 2 Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3 Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V 4 Input logic low voltage VIL -0.30 - VREF-0.15 V 5 Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA Output logic low voltage VOL - - Vtt-0.76 V IOL=+15.2mA Input leakage current IIL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V. 9.2 DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65C) Parameter Symbol Test Condition Version -40 -50 Unit Note ICC1 Burst Lenth=2 tRC tRC(min) IOL=0mA, tCC= tCC(min) 200 180 mA 1, 2 Precharge Standby Current in Power-down mode ICC2P CKE VIL(max), tCC= tCC(min) 45 40 mA 1, 2 Precharge Standby Current in Non Power-down mode ICC2N CKE VIH(min), CS VIH(min), tCC= tCC(min). 70 60 mA 1, 2 Active Standby Current power-down mode ICC3P CKE VIL(max), tCC= tCC(min) 85 70 mA 1, 2 Active Standby Current in in Non Power-down mode ICC3N CKE VIH(min), CS VIH(min), tCC= tCC(min) . 135 110 mA 1, 2 Operating Current (One Bank Active) Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 350 300 mA 1, 2 Refresh Current ICC5 tRC tRFC(min) 200 180 mA 1, 2,3 Self Refresh Current ICC6 CKE 0.2V 10 10 mA 1, 2 Note : 1. Measured with output open. 2. Current meassured at VDD(max). 3. Refresh period is 32ms. - 11 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 9.3 AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ VIL - - VREF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2 Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V. 9.4 AC OPERATING TEST CONDITIONS (VDD=2.5V+ 5%*2 , TA= 0 to 65C) Parameter Input reference voltage for CK(for single ended) Value Unit Note 0.50*VDDQ V 1 1.5 V CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels(VIH/VIL) 1.0 V/ns VREF+0.35/VREF-0.35 V VREF V Vtt V Input timing measurement reference level Output timing measurement reference level Output load condition See Fig.1 Note : 1. In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK's crossing point. 2. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V. Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ (Fig. 1) Output Load Circuit - 12 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 9.5 CAPACITANCE (VDD=2.5V, TA= 25C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) CIN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1) CIN2 1.0 4.0 pF Input capacitance( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ15) COUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) CIN4 1.0 6.5 pF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Symbol Value Unit Decoupling Capacitance between VDD and VSS Parameter CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other. All VSS pins are connected in chip. All VSSQ pins are connected in chip. 9.6 AC CHARACTERISTICS Parameter CK cycle time Symbol CL=2 -50 Min Max Min Max 7.5 10 7.5 10 Unit tCK 4.0 10 5.0 10 ns tCH 0.45 0.55 0.45 0.55 tCK CK low level width tCL 0.45 0.55 0.45 0.55 tCK tDQSCK -0.6 0.6 -0.7 0.7 ns Output access time from CK Note ns CK high level width DQS out access time from CK CL=3 tCK -40 tAC -0.6 0.6 -0.7 0.7 ns Data strobe edge to Dout edge tDQSQ - 0.4 - 0.45 ns Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK Read postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.85 1.15 0.8 1.2 tCK DQS-In setup time tWPRES 0 - 0 - ns DQS-in hold time tWPREH 0.35 - 0.3 - tCK DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 tCK Address and Control input setup tIS 0.9 - 1.0 - ns Address and Control input hold tIH 0.9 - 1.0 - ns DQ and DM setup time to DQS tDS 0.4 - 0.45 - ns DQ and DM hold time to DQS tDH 0.4 - 0.45 - ns Clock half period tHP tCLmin or tCHmin - tCLmin or tCHmin - ns 1 Data output hold time from DQS tQH tHP-0.4 - tHP-0.45 - ns 1 1 Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax - 13 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM AC CHARACTERISTICS (II)_Continued Parameter Symbol -40 -50 Unit Min Max Min Max tRC 52 - 55 - Refresh row cycle time tRFC 60 - 70 Row active time tRAS 36 100K 40 100K ns RAS to CAS delay for Read tRCDRD 16 - 15 - ns RAS to CAS delay for Write tRCDWR 8 - 10 - ns tRP 16 - 15 - ns tRRD 12 - 10 Row cycle time Row precharge time Row active to Row active Last data in to Row precharge @Normal Precharge Note ns ns 2 ns tWR 3 - 3 - tCK 1 Last data in to Row precharge @Auto Precharge tWR_A 3 - 3 - tCK 1 Last data in to Read command tCDLR 2 - 2 - tCK 1 Col. address to Col. address tCCD 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - tCK Auto precharge write recovery + Precharge tDAL 7 - 6 - tCK Exit self refresh to read command tXSR 200 - 200 - tCK tPDEX 3tCK+tIS - 3tCK+tIS - ns tREF - 7.8 - 7.8 us Power down exit time Refresh interval time Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM. 2. tRCDWR should be always greater or equal to 2tCK. AC CHARACTERISTICS (III)_Continued (Unit : Number of Clock) K4D261638K-LC40 Frequency Cas Latency 250MHz ( 4.0ns ) 3 200MHz ( 5.0ns ) 3 133MHz ( 7.5ns ) 3 or 2 tRC 13 11 7 tRFC 15 14 8 tRAS 9 8 5 tRCDRD tRCDWR 4 2 3 2 3 2 tRP 4 3 3 tRRD 3 2 2 tDAL 7 6 4 Unit tCK tCK tCK K4D261638K-LC50 Frequency Cas Latency 200MHz ( 5.0ns ) 3 133MHz ( 7.5ns ) 3 or 2 tRC 11 8 tRFC 14 10 tRAS 8 6 tRCDRD tRCDWR 3 2 2 2 tRP 3 2 tRRD 2 2 tDAL 6 4 Unit tCK tCK - 14 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 10.0 SIMPLIFIED TIMING Simplified Timing @ BL=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CK, CK BA[1:0] BAa A8/AP BAa BAa BAa Ra BAa Ra Ca BAb Rb Ra ADDR Ra (A0~A7 ,A9~A11) BAb Ca Rb Cb WE DQS Da0 Da1 Da2 Da3 DQ Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 DM COM ACT_A WR_A PRECH tRCD ACT_A WR_A ACT_B WR_B tRP tRAS tRC tRRD Multi Bank Interleaving Write Burst (@ BL=4) Normal Write Burst (@ BL=4) - 15 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM IBIS : Pull up Voltage 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 Pullup Current(mA) 100% Min 100% Max 0.00 0.00 -1.00 -0.76 -5.64 -6.16 -10.08 -11.56 -14.40 -16.68 -18.40 -21.60 -22.32 -26.64 -26.00 -31.32 -29.40 -35.96 -32.52 -40.24 -35.44 -44.36 -37.92 -48.40 -40.20 -51.92 -42.08 -55.36 -43.76 -58.32 -45.16 -61.00 -46.28 -63.40 -47.24 -65.48 -48.12 -67.20 -48.88 -68.76 -49.56 -70.08 -50.20 -71.24 -50.76 -72.24 -51.36 -73.16 -51.41 -73.96 -51.63 -74.72 -51.71 -75.40 -51.92 -76.04 Pullup Current(mA) 60% Min 60% Max 0.00 0.00 -1.16 -1.00 -5.40 -5.92 -9.40 -10.80 -13.32 -15.48 -17.00 -20.08 -20.40 -24.40 -23.76 -28.68 -26.72 -32.72 -29.48 -36.60 -32.00 -40.36 -34.20 -43.92 -36.20 -47.04 -37.80 -49.96 -39.20 -52.60 -40.40 -54.92 -41.40 -57.00 -42.28 -58.76 -43.00 -60.24 -43.68 -61.60 -44.28 -62.72 -44.84 -63.72 -45.32 -64.60 -45.80 -65.36 -46.10 -66.16 -46.31 -66.76 -46.49 -67.40 -46.61 -67.92 Pullup Current(mA) 30% Min 30% Max 0.00 0.00 -1.28 -1.24 -4.20 -4.72 -7.00 -8.08 -9.64 -11.28 -12.04 -14.40 -14.44 -17.44 -16.68 -20.32 -18.64 -23.12 -20.40 -25.72 -22.04 -28.20 -23.44 -30.52 -24.64 -32.52 -25.64 -34.40 -26.48 -36.04 -27.20 -37.48 -27.84 -38.64 -28.32 -39.72 -28.76 -40.64 -29.20 -41.40 -29.60 -42.04 -29.88 -42.64 -30.20 -43.16 -30.48 -43.68 -30.65 -44.08 -30.81 -44.52 -30.97 -44.88 -31.10 -45.24 0 -10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Pull up Current (mA) -20 100% Min 100% Max 60% Min 60% Max 30% Min 30% Max -30 -40 -50 -60 -70 -80 Voltage (V) - 16 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM IBIS : Pull down Voltage 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 Pulldown Current(mA) 100% Min 100% Max 0.00 0.00 1.24 0.84 6.72 7.28 12.00 13.68 17.16 19.88 21.84 25.88 26.16 31.52 30.32 37.12 33.92 42.44 37.00 47.28 39.68 51.80 41.76 55.84 43.32 59.24 44.48 62.12 45.36 64.40 46.00 66.16 46.44 67.48 46.88 68.56 47.20 69.28 47.56 69.88 47.88 70.40 48.12 70.84 48.36 71.20 48.60 71.56 48.80 71.88 49.04 72.16 49.24 72.40 49.48 72.64 Pulldown Current(mA) 60% Min 60% Max 0.00 0.00 1.24 0.96 5.96 6.48 10.48 12.12 14.80 17.44 18.80 22.60 22.56 27.48 26.04 32.20 28.96 36.64 31.56 40.80 33.72 44.52 35.32 47.72 36.52 50.48 37.44 52.72 38.04 54.48 38.60 55.88 39.00 56.84 39.32 57.64 39.68 58.24 39.88 58.72 40.12 59.12 40.36 59.44 40.56 59.72 40.76 60.00 40.96 60.28 41.16 60.48 41.36 60.72 41.52 60.92 Pulldown Current(mA) 30% Min 30% Max 0.00 0.00 1.36 1.24 4.64 5.24 7.72 9.04 10.68 12.76 13.44 16.24 15.92 19.64 18.08 22.84 20.00 25.80 21.52 28.40 22.72 30.76 23.64 32.64 24.24 34.20 24.76 35.40 25.12 36.24 25.36 37.00 25.60 37.48 25.84 37.88 26.00 38.20 26.20 38.48 26.32 38.68 26.48 38.88 26.60 39.08 26.76 39.24 26.84 39.40 26.96 39.60 27.12 39.68 27.20 39.84 Pull down 80 60 100% Min 100% Max 60% Min 60% Max 30% Min 30% Max 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Current (mA) 70 Voltage (V) - 17 /19 - Rev. 1.3 July 2007 K4D261638K 128M GDDR SDRAM 0.65TYP 0.650.08 0.300.08 (10x) NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS'Y OUT QUALITY - 18 /19 - (10.76) 0.10 MAX [ 0.075 MAX ] (0.50) 0.45~0.75 25 ) (4x ) 1.20MAX 1.000.10 0.125 +0.075 -0.035 (R 0.2 5) (0.71) (R 0. (10x) 5) 0.05 MIN 22.220.10 (R 0 .1 15 ) 0.2100.05 0.6650.05 (1.50) 0. (0.80) #33 (10x) (R (1.50) (10x) #1 11.760.20 (0.80) #34 10.160.10 #66 (0.50) Units : Millimeters 0.25TYP 0x~8x Rev. 1.3 July 2007