K4D261638K-LC50 - Samsung - Product.Network

- 1 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

Revision 1.3

July 2007

2M x 16Bit x 4 Banks

Graphic Double Data Rate

Synchronous DRAM

128Mbit GDDR SDRAM

Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,

EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL

INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

- 2 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

Revision History

Revision Month Year History

0.0 January 2006 - Target Spec

- Defined target specification

1.0 September 2006 - Added the Current Spec

- Added the IBIS Data

1.1 October 2006 - Added and Revised the IBIS Data

1.2 November 2006 - Added power up comment

1.3 July 2007 - Revised voltage comment of power up sequence

- 3 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

The K4D261638K is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fab-

ricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-

mance up to 1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable

burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

• 2.5V + 5% power supply for device operation

• 2.5V + 5% power supply for I/O interface

• SSTL_2 compatible inputs/outputs

• 4 banks operation

• MRS cycle with address key programs

-. Read latency 2,3(clock)

-. Burst length (2, 4 and 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going

edge of the system clock

• Differential clock input

• Wrtie-Interrupted by Read Function

• 2 DQS’s ( 1DQS / Byte )

• Data I/O transactions on both edges of Data strobe

• DLL aligns DQ and DQS transitions with Clock transition

• Edge aligned data & data strobe output

• Center aligned data & data strobe input

• DM for write masking only

• Auto & Self refresh

• 32ms refresh period (4K cycle)

• Lead free 66pin TSOP-II (RoHS compliant)

• Maximum clock frequency up to 250MHz

• Maximum data rate up to 500Mbps/pin

FOR 2M x 16Bit x 4 Bank DDR SDRAM

2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM

with Bi-directional Data Strobe and DLL

* K4D261638K-TC is the Leaded package part number.

* For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V.

Part NO. Max Freq. Max Data Rate Interface Package

K4D261638K-LC40 250MHz 500Mbps/pin SSTL_2 66pin TSOP-II

K4D261638K-LC50 200MHz 400Mbps/pin

1.0 FEATURES

2.0 ORDERING INFORMATION

3.0 GENERAL DESCRIPTION

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128M GDDR SDRAMK4D261638K

4.0 PIN CONFIGURATION (Top View)

PIN DESCRIPTION

CK,CK Differential Clock Input BA0, BA1 Bank Select Address

CKE Clock Enable A0 ~A11 Address Input

CS Chip Select DQ0 ~ DQ15 Data Input/Output

RAS Row Address Strobe VDD Power

CAS Column Address Strobe VSS Ground

WE Write Enable VDDQ Power for DQ’s

L(U)DQS Data Strobe VSSQ Ground for DQ’s

L(U)DM Data Mask NC No Connection

RFU Reserved for Future Use

66 PIN TSOP(II)

(400mil x 875mil)

(0.65 mm Pin Pitch)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

BA0

RAS

CAS

LDM

VDDQ

DQ7

VDD

AP/A10

BA1

LDQS

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

A11

CKE

UDM

VREF

VSSQ

DQ8

VSS

UDQS

VSS

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128M GDDR SDRAMK4D261638K

*1 : The timing reference point for the differential clocking is the cross point of CK and CK.

For any applications using the single ended clocking, apply VREF to CK pin.

Symbol Type Function

CK, CK*1 Input

The differential system clock Input.

All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are

sampled on both edges of the DQS.

CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating

the clock, CKE low indicates the Power down mode or Self refresh mode.

CS Input

CS enables the command decoder when low and disabled the command decoder when high.

When the command decoder is disabled, new commands are ignored but previous operations

continue.

RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row

access & precharge.

CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables col-

umn access.

WE Input Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

LDQS,UDQS Input/Output

Data input and output are synchronized with both edge of DQS.

For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on

DQ8-DQ15.

LDM,UDM Input

Data in Mask. Data In is masked by DM Latency=0 when DM is

high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons

to the data on DQ8-DQ15.

DQ0 ~ DQ15 Input/Output Data inputs/Outputs are multiplexed on the same pins.

BA0, BA1Input Selects which bank is to be active.

A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins.

Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.

VDD/VSS Power Supply Power and ground for the input buffers and core logic.

VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity.

VREF Power Supply Reference voltage for inputs, used for SSTL interface.

NC/RFU No connection/

Reserved for future use This pin is recommended to be left "No connection" on the device

5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION

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128M GDDR SDRAMK4D261638K

6.0 BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank)

Bank Select

Timing Register

Address Register

Refresh Counter

Row Buffer

Row Decoder Col. Buffer

Data Input Register

Serial to parallel

2Mx16

Sense AMP

2-bit prefetch

Output BufferI/O Control

Column Decoder

Latency & Burst Length

Programming Register

Strobe

Gen.

CK,CK

ADDR

LCKE

CK,CK CKE CS RAS CAS WE LDM

LDMi

CK,CK

LCAS

LRAS LCBR LWE

LWCBR

LRAS

LCBR

CK, CK

32 16

LWE

LDMi

x16

DQi

Data Strobe

Intput Buffer

DLL

UDM

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128M GDDR SDRAMK4D261638K

7.1 Power-Up Sequence

7.0 FUNCTIONAL DESCRIPTION

DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and keep CKE at low state (All other inputs may be undefined)

- Apply VDD before or with VDDQ .

- Apply VDDQ before or with VREF & VTT

- The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min and

the power voltage ramps are without any slope reversal

2. Start clock and maintain stable condition for minimum 200us.

3. The minimum of 200us after stable power and clock(CK,CK), apply NOP and take CKE to be high .

4. Issue precharge command for all banks of the device.

5. Issue a EMRS command to enable DLL

*1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL.

*1,2 7. Issue precharge command for all banks of the device.

8. Issue at least 2 or more auto-refresh commands.

9. Issue a mode register set command with A8 to low to initialize the mode register.

Power up & Initialization Sequence

Command

012345678910111213141516171819

tRP 2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

RFC

1st Auto

Refresh

RFC

EMRS MRS

2 Clock min.

DLL Reset

precharge

ALL Banks

Inputs must be

stable for 200us

200 Clock min.

2 Clock min.

CK,CK

* When the operating frequency is changed, DLL reset should be required again.

After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

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128M GDDR SDRAMK4D261638K

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing

mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different appli-

cations. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper

operation. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with

CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS,

RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in

the mode register. The mode register contents can be changed using the same command and clock cycle requirements during opera-

tion as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length

uses A0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is

used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various

burst length, addressing modes and CAS latencies.

Address Bus

Mode Register

CAS Latency

A6A5A4Latency

0 0 0 Reserved

0 0 1 Reserved

010 2

011 3

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Burst Length

A2A1A0

Burst Type

Sequential Interleave

0 0 0 Reserve Reserve

001 2 2

010 4 4

011 8 8

1 0 0 Reserve Reserve

1 0 1 Reserve Reserve

1 1 0 Reserve Reserve

1 1 1 Reserve Reserve

Burst Type

A3Type

0 Sequential

1 Interleave

*1 : RFU(Reserved for future use)

should stay "0" during MRS cycle.

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

RFU*1 0RFU*1 DLL TM CAS Latency BT Burst Length

BA0An ~ A0

0MRS

1EMRS

DLL

A8 DLL Reset

0No

1Yes

Test Mode

A7mode

0 Normal

1Test

7.2 MODE REGISTER SET(MRS)

*1 : MRS can be issued only at all banks precharge state.

*2 : Minimum tRP is required to issue MRS command.

MRS Cycle

Command

CK, CK

Precharge NOP NOPMRS NOPNOP

201 534 867

Any

NOP All Banks Command

tRP tMRD=2 tCK

NOP

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128M GDDR SDRAMK4D261638K

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the

extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL.

The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank

precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and

BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting

driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended

mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as

long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins

except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

A0DLL Enable

0 Enable

1 Disable

BA0An ~ A0

0MRS

1EMRS

Address Bus

Extended

*1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

RFU*1 1RFU*1 D.I.C RFU*1 D.I.C DLL

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Mode Register

7.3 EXTENDED MODE REGISTER SET(EMRS)

A6 A1 Output Driver Impedence Control

00 Full

0 1 Weak

11 Matced

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128M GDDR SDRAMK4D261638K

A burst write can be interrupted by a read command of any bank. The DQ’s must be in the high impedance state at least one clock

cycle before the interrupting read data appear on the outputs to avoid data contention. When the read command is registered, any

residual data from the burst write cycle must be masked by DM. The delay from the last data to read command (tCDLR) is required to

avoid the data contention DRAM inside. Data that are presented on the DQ pins before the read command is initiated will actually be

written to the memory. Read command interrupting write can not be issued at the next clock edge of that of write command.

CMD

< Burst Length=8, CAS Latency=3 >

NOP WRITE NOP NOP NOPNOP READ NOPNOP

DQS

′

Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Dout 0

Din 6 Din 7

DQSSmax

2 0 1 5 3 4 8 6 7

WPRES

The following function established how a Read command may interrupt a Write burst and which input data is not written into the memory.

1. For Read commands interrupting a Write burst, the minimum Write to Read command delay is 2 clock cycles. The case where the Write to Read delay

is 1 clock cycle is disallowed

2. For Read commands interrupting a Write burst, the DM pin must be used to mask the input data words whcich immediately precede the interrupting

Read operation and the input data word which immediately follows the interrupting Read operation

3. For all cases of a Read interrupting a Write, the DQ and DQS buses must be released by the driving chip (i.e., the memory controller) in time to allow

the buses to turn around before the DDR SDRAM drives them during a read operation.

4. If input Write data is masked by the Read command, the DQS input is ignored by the DDR SDRAM.

5. Refer to "3.3.2 Burst write operation"

WPREH

NOPNOP

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V

Voltage on VDD supply relative to Vss VDDQ -0.5 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD2.0 W

Short circuit current IOS 50 mA

8.0 ABSOLUTE MAXIMUM RATINGS

7.4 WRITE INTERRUPTED BY A READ

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128M GDDR SDRAMK4D261638K

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C)

Note :

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF

may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise.

3. Vtt of the transmitting device must track VREF of the receiving device.

4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate.

6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V.

7. For K4D261638K-LC50, VDD & VDDQ = 2.375V to 2.7V.

Parameter Symbol Min Typ Max Unit Note

Device Supply voltage VDD 2.375 2.50 2.625 V 1, 7

Output Supply voltage VDDQ 2.375 2.50 2.625 V 1, 7

Reference voltage VREF 0.49*VDDQ - 0.51*VDDQ V2

Termination voltage Vtt VREF-0.04 VREF VREF+0.04 V 3

Input logic high voltage VIH VREF+0.15 - VDDQ+0.30 V 4

Input logic low voltage VIL -0.30 - VREF-0.15 V 5

Output logic high voltage VOH Vtt+0.76 - - V IOH=-15.2mA

Output logic low voltage VOL --V

tt-0.76 V IOL=+15.2mA

Input leakage current IIL -5 - 5 uA 6

Output leakage current IOL -5 - 5 uA 6

9.1 POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out)

9.0 AC & DC OPERATING CONDITIONS

Recommended operating conditions Unless Otherwise Noted ( TA=0 to 65°C)

Note :

1. Measured with output open.

2. Current meassured at VDD(max).

3. Refresh period is 32ms.

Parameter Symbol Test Condition Version Unit Note

-40 -50

Operating Current

(One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min)

IOL=0mA, tCC= tCC(min) 200 180 mA 1, 2

Precharge Standby Current

in Power-down mode ICC2PCKE ≤ VIL(max), tCC= tCC(min) 45 40 mA 1, 2

Precharge Standby Current

in Non Power-down mode ICC2NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min). 70 60 mA 1, 2

Active Standby Current

power-down mode ICC3PCKE ≤ VIL(max), tCC= tCC(min) 85 70 mA 1, 2

Active Standby Current in

in Non Power-down mode ICC3NCKE ≥ VIH(min), CS ≥ VIH(min),

tCC= tCC(min) . 135 110 mA 1, 2

Operating Current

( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst,

All Banks activated. 350 300 mA 1, 2

Refresh Current ICC5 tRC ≥ tRFC(min) 200 180 mA 1, 2,3

Self Refresh Current ICC6 CKE ≤ 0.2V 10 10 mA 1, 2

9.2 DC CHARACTERISTICS

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128M GDDR SDRAMK4D261638K

Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C)

Note :

1. VID is the magnitude of the difference between the input level on CK and the input level on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

3. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V.

Parameter Symbol Min Typ Max Unit Note

Input High (Logic 1) Voltage; DQ VIH VREF+0.35 - - V

Input Low (Logic 0) Voltage; DQ VIL --V

REF-0.35 V

Clock Input Differential Voltage; CK and CK VID 0.7 - VDDQ+0.6 V 1

Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*VDDQ+0.2 V 2

9.4 AC OPERATING TEST CONDITIONS

9.3 AC INPUT OPERATING CONDITIONS

RT=50Ω

Output

CLOAD=30pF

(Fig. 1) Output Load Circuit

Z0=50Ω

VREF

=0.5*VDDQ

Vtt=0.5*VDDQ

(VDD=2.5V+ 5%*2 , TA= 0 to 65°C)

Note :

1. In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point.

2. For K4D261638J-LC50, VDD & VDDQ = 2.375V to 2.7V.

Parameter Value Unit Note

Input reference voltage for CK(for single ended) 0.50*VDDQ V1

CK and CK signal maximum peak swing 1.5 V

CK signal minimum slew rate 1.0 V/ns

Input Levels(VIH/VIL)V

REF+0.35/VREF-0.35 V

Input timing measurement reference level VREF V

Output timing measurement reference level Vtt V

Output load condition See Fig.1

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128M GDDR SDRAMK4D261638K

DECOUPLING CAPACITANCE GUIDE LINE

9.5 CAPACITANCE

Recommended decoupling capacitance added to power line at board.

1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other. All VSS pins are connected in chip. All VSSQ pins are connected in chip.

Parameter Symbol Value Unit

Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF

Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF

(VDD=2.5V, TA= 25°C, f=1MHz)

Parameter Symbol Min Max Unit

Input capacitance( CK, CK )CIN1 1.0 5.0 pF

Input capacitance(A0~A11, BA0~BA1)CIN2 1.0 4.0 pF

Input capacitance( CKE, CS, RAS,CAS, WE )CIN3 1.0 4.0 pF

Data & DQS input/output capacitance(DQ0~DQ15)COUT 1.0 6.5 pF

Input capacitance(DM0 ~ DM3) CIN4 1.0 6.5 pF

Note 1 :

- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with

that data strobe are coincidentally valid.

- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then

the clock duty cycle applied to the device is better than 45/55%

- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV

- tQHmin = tHP-X where

. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)

. X=A frequency dependent timing allowance account for tDQSQmax

Parameter Symbol -40 -50 Unit Note

Min Max Min Max

CK cycle time CL=2 tCK 7.5 10 7.5 10 ns

CL=3 tCK 4.0 10 5.0 10 ns

CK high level width tCH 0.45 0.55 0.45 0.55 tCK

CK low level width tCL 0.45 0.55 0.45 0.55 tCK

DQS out access time from CK tDQSCK -0.6 0.6 -0.7 0.7 ns

Output access time from CK tAC -0.6 0.6 -0.7 0.7 ns

Data strobe edge to Dout edge tDQSQ - 0.4 - 0.45 ns 1

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK

Read postamble tRPST 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.85 1.15 0.8 1.2 tCK

DQS-In setup time tWPRES 0 - 0 - ns

DQS-in hold time tWPREH 0.35 - 0.3 - tCK

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK

DQS-In high level width tDQSH 0.4 0.6 0.4 0.6 tCK

DQS-In low level width tDQSL 0.4 0.6 0.4 0.6 tCK

Address and Control input setup tIS 0.9 - 1.0 - ns

Address and Control input hold tIH 0.9 - 1.0 - ns

DQ and DM setup time to DQS tDS 0.4 - 0.45 - ns

DQ and DM hold time to DQS tDH 0.4 - 0.45 - ns

Clock half period tHP

tCLmin

tCHmin

tCLmin

tCHmin

-ns1

Data output hold time from DQS tQH tHP-0.4 - tHP-0.45 - ns 1

9.6 AC CHARACTERISTICS

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128M GDDR SDRAMK4D261638K

AC CHARACTERISTICS (II)_Continued

Note :

1. For normal write operation, even numbers of Din are to be written inside DRAM.

2. tRCDWR should be always greater or equal to 2tCK.

Parameter Symbol -40 -50 Unit Note

Min Max Min Max

Row cycle time tRC 52 - 55 - ns

Refresh row cycle time tRFC 60 - 70 ns

Row active time tRAS 36 100K 40 100K ns

RAS to CAS delay for Read tRCDRD 16 - 15 - ns

RAS to CAS delay for Write tRCDWR 8 - 10 - ns 2

Row precharge time tRP 16 - 15 - ns

Row active to Row active tRRD 12 - 10 ns

Last data in to Row precharge @Normal Precharge tWR 3 - 3 - tCK 1

Last data in to Row precharge @Auto Precharge tWR_A 3 - 3 - tCK 1

Last data in to Read command tCDLR 2 - 2 - tCK 1

Col. address to Col. address tCCD 1 - 1 - tCK

Mode register set cycle time tMRD 2 - 2 - tCK

Auto precharge write recovery + Precharge tDAL 7 - 6 - tCK

Exit self refresh to read command tXSR 200 - 200 - tCK

Power down exit time tPDEX 3tCK+tIS - 3tCK+tIS - ns

Refresh interval time tREF - 7.8 - 7.8 us

AC CHARACTERISTICS (III)_Continued

(Unit : Number of Clock)

K4D261638K-LC40

Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit

250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK

200MHz ( 5.0ns ) 3 11 14 8 3 2 3 2 6 tCK

133MHz ( 7.5ns ) 3 or 2 7 8 5 3 2 3 2 4 tCK

K4D261638K-LC50

Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit

200MHz ( 5.0ns ) 3 11 14 8 3 2 3 2 6 tCK

133MHz ( 7.5ns ) 3 or 2 8 10 6 2 2 2 2 4 tCK

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128M GDDR SDRAMK4D261638K

Simplified Timing @ BL=4

Normal Write Burst

(@ BL=4)

Multi Bank Interleaving Write Burst

(@ BL=4)

012345678 13 14 15 16 17 18 19 20 219101112 22

COM

DQS

CK, CK

A8/AP

ADDR

(A0~A7

BA[1:0]

Da0 Da1 Da2 Da3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3

ACT_A WR_A PRECH ACT_A WR_A ACT_B WR_B

tRCD

tRAS

tRP

tRC tRRD

BAa BAa BAa BAa BAa BAb BAb

Ca Cb

RaRa

Ra Ca Ra

,A9~A11)

10.0 SIMPLIFIED TIMING

- 16 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

IBIS : Pull up

Voltage 100% Min 100% Max 60% Min 60% Max 30% Min 30% Max

0.00 0.00 0.00 0.00 0.00 0.00 0.00

0.10 -1.00 -0.76 -1.16 -1.00 -1.28 -1.24

0.20 -5.64 -6.16 -5.40 -5.92 -4.20 -4.72

0.30 -10.08 -11.56 -9.40 -10.80 -7.00 -8.08

0.40 -14.40 -16.68 -13.32 -15.48 -9.64 -11.28

0.50 -18.40 -21.60 -17.00 -20.08 -12.04 -14.40

0.60 -22.32 -26.64 -20.40 -24.40 -14.44 -17.44

0.70 -26.00 -31.32 -23.76 -28.68 -16.68 -20.32

0.80 -29.40 -35.96 -26.72 -32.72 -18.64 -23.12

0.90 -32.52 -40.24 -29.48 -36.60 -20.40 -25.72

1.00 -35.44 -44.36 -32.00 -40.36 -22.04 -28.20

1.10 -37.92 -48.40 -34.20 -43.92 -23.44 -30.52

1.20 -40.20 -51.92 -36.20 -47.04 -24.64 -32.52

1.30 -42.08 -55.36 -37.80 -49.96 -25.64 -34.40

1.40 -43.76 -58.32 -39.20 -52.60 -26.48 -36.04

1.50 -45.16 -61.00 -40.40 -54.92 -27.20 -37.48

1.60 -46.28 -63.40 -41.40 -57.00 -27.84 -38.64

1.70 -47.24 -65.48 -42.28 -58.76 -28.32 -39.72

1.80 -48.12 -67.20 -43.00 -60.24 -28.76 -40.64

1.90 -48.88 -68.76 -43.68 -61.60 -29.20 -41.40

2.00 -49.56 -70.08 -44.28 -62.72 -29.60 -42.04

2.10 -50.20 -71.24 -44.84 -63.72 -29.88 -42.64

2.20 -50.76 -72.24 -45.32 -64.60 -30.20 -43.16

2.30 -51.36 -73.16 -45.80 -65.36 -30.48 -43.68

2.40 -51.41 -73.96 -46.10 -66.16 -30.65 -44.08

2.50 -51.63 -74.72 -46.31 -66.76 -30.81 -44.52

2.60 -51.71 -75.40 -46.49 -67.40 -30.97 -44.88

2.70 -51.92 -76.04 -46.61 -67.92 -31.10 -45.24

Pullup Current(mA) Pullup Current(mA) Pullup Current(mA)

Pull up

-80

-70

-60

-50

-40

-30

-20

-10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Voltage (V)

Current (mA

)

100% Min

100% Max

60% Min

60% Max

30% Min

30% Max

- 17 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

IBIS : Pull down

V o l t a g e 1 0 0 % M i n 1 0 0 % M a x 6 0 % M i n 6 0 % M a x 3 0 % M i n 3 0 % M a x

0.00 0.00 0.00 0.00 0.00 0.00 0.00

0.10 1.24 0.84 1.24 0.96 1.36 1.24

0.20 6.72 7.28 5.96 6.48 4.64 5.24

0.30 12.00 13.68 10.48 12.12 7.72 9.04

0.40 17.16 19.88 14.80 17.44 10.68 12.76

0.50 21.84 25.88 18.80 22.60 13.44 16.24

0.60 26.16 31.52 22.56 27.48 15.92 19.64

0.70 30.32 37.12 26.04 32.20 18.08 22.84

0.80 33.92 42.44 28.96 36.64 20.00 25.80

0.90 37.00 47.28 31.56 40.80 21.52 28.40

1.00 39.68 51.80 33.72 44.52 22.72 30.76

1.10 41.76 55.84 35.32 47.72 23.64 32.64

1.20 43.32 59.24 36.52 50.48 24.24 34.20

1.30 44.48 62.12 37.44 52.72 24.76 35.40

1.40 45.36 64.40 38.04 54.48 25.12 36.24

1.50 46.00 66.16 38.60 55.88 25.36 37.00

1.60 46.44 67.48 39.00 56.84 25.60 37.48

1.70 46.88 68.56 39.32 57.64 25.84 37.88

1.80 47.20 69.28 39.68 58.24 26.00 38.20

1.90 47.56 69.88 39.88 58.72 26.20 38.48

2.00 47.88 70.40 40.12 59.12 26.32 38.68

2.10 48.12 70.84 40.36 59.44 26.48 38.88

2.20 48.36 71.20 40.56 59.72 26.60 39.08

2.30 48.60 71.56 40.76 60.00 26.76 39.24

2.40 48.80 71.88 40.96 60.28 26.84 39.40

2.50 49.04 72.16 41.16 60.48 26.96 39.60

2.60 49.24 72.40 41.36 60.72 27.12 39.68

2.70 49.48 72.64 41.52 60.92 27.20 39.84

Pulldown Current(mA)Pulldown Current(mA) Pulldown Current(mA)

Pull down

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Voltage (V)

Current (mA

)

100% Min

100% Max

60% Min

60% Max

30% Min

30% Max

- 18 /19 - Rev. 1.3 July 2007

128M GDDR SDRAMK4D261638K

Units : Millimeters

0.30

0.08

0.65TYP(0.71)

22.22

0.10

0.125

(0.80)

10.16

0.10

#1 #33

#66 #34

(1.50)

0.65

0.08

1.00

0.10

1.20MAX

(0.50) (0.50)(10.76)

11.76

0.20

(10

)(10

)

+0.075

-0.035

(0.80)

0.10 MAX

0.075 MAX

[]

0.05 MIN

(10

)

(10

)

(R0.15)

0.210

0.05

0.665

0.05

(R0.15)

)

(R0.25)

0.45~0.75

0.25TYP

NOTE

1. ( ) IS REFERENCE

2. [ ] IS ASS’Y OUT QUALITY