LT3093 -20V, 200mA, Ultralow Noise, Ultrahigh PSRR Negative Linear Regulator FEATURES DESCRIPTION Ultralow RMS Noise: 0.8VRMS (10Hz to 100kHz) nn Ultralow Spot Noise: 2.2nV/Hz at 10kHz nn Ultrahigh PSRR: 73dB at 1MHz nn Output Current: 200mA nn Wide Input Voltage Range: -1.8V to -20V nn Single Capacitor Improves Noise and PSRR nn 100A SET Pin Current: 1% Initial Accuracy nn Single Resistor Programs Output Voltage nn Programmable Current Limit nn Low Dropout Voltage: 190mV nn Output Voltage Range: 0V to -19.5V nn Programmable Power Good and Fast Start-Up nn Bipolar Precision Enable/UVLO Pin nn VIOC Pin Controls Upstream Regulator to Minimize Power Dissipation and Optimize PSRR nn Minimum Output Capacitor: 4.7F Ceramic nn 12-Lead MSOP and 3mm x 3mm DFN Packages The LT(R)3093 is a high performance low dropout negative linear regulator featuring ADI's ultralow noise and ultrahigh PSRR architecture for powering noise sensitive applications. The device can be easily paralleled to further reduce noise, increase output current and spread heat on a PCB. nn APPLICATIONS RF and Precision Power Supplies Very Low Noise Instrumentation nn High Speed/High Precision Data Converters nn Medical Applications: Diagnostics and Imaging nn Post-Regulator for Switching Supplies nn nn The LT3093 supplies 200mA at a typical 190mV dropout voltage. Operating quiescent current is nominally 2.35mA and drops to 3A in shutdown. The device's wide output voltage range (0V to -19.5V) error amplifier operates in unity-gain and provides virtually constant output noise, PSRR, bandwidth, and load regulation independent of the programmed output voltage. Additional features are a bipolar enable pin, programmable current limit, fast startup capability and programmable power good to indicate output voltage regulation. The regulator incorporates a tracking function to control an upstream supply to maintain a constant voltage across the LT3093 to minimize power dissipation and optimize PSRR. The LT3093 is stable with a minimum 4.7F ceramic output capacitor. Built-in protection includes internal current limit with foldback and thermal limit with hysteresis. The LT3093 is available in thermally enhanced 12-Lead MSOP and 3mm x 3mm DFN Packages. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Power Supply Ripple Rejection 4.7F 33.2k 50k 9.76k 120 3.3V LT3093 SET PG + EN/UV 4.7F VIN -5V GND ILIM PGFB OUTS OUT 90 4.7F VOUT -3.3V IOUT(MAX) -200mA - PSRR (dB) 200k 105 450k 75 60 45 VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F IL = -200mA 30 15 100A IN 0 3093 TA01a PIN NOT USED IN THIS CIRCUIT: VIOC 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3093 TA01b Rev. 0 Document Feedback For more information www.analog.com 1 LT3093 TABLE OF CONTENTS Features............................................................................................................................. 1 Applications........................................................................................................................ 1 Typical Application ................................................................................................................ 1 Description......................................................................................................................... 1 Absolute Maximum Ratings...................................................................................................... 3 Pin Configuration.................................................................................................................. 3 Order Information.................................................................................................................. 4 Electrical Characteristics......................................................................................................... 4 Typical Performance Characteristics........................................................................................... 7 Pin Functions......................................................................................................................15 Block Diagram.....................................................................................................................16 Applications Information........................................................................................................17 Typical Application...............................................................................................................29 Package Description.............................................................................................................30 Typical Application...............................................................................................................32 Related Parts......................................................................................................................32 2 Rev. 0 For more information www.analog.com LT3093 ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage with Respect to GND Pin............................-22V, 0.3V EN/UV Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 30V with Respect to GND Pin.....................................22V PG Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 30V with Respect to GND Pin............................-0.3V, 22V PGFB Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 30V with Respect to GND Pin.....................................22V ILIM Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 22V VIOC Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 22V with Respect to GND Pin............................-22V, 0.3V SET Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 22V with Respect to GND Pin.....................................22V SET Pin Current (Note 4)...................................... 10mA OUTS Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 22V with Respect to GND Pin.....................................22V OUTS Pin Current (Note 4).................................... 10mA SET-to-OUTS Differential (Note 5)...........................22V OUT Pin Voltage with Respect to IN Pin (Note 2)..................-0.3V, 22V with Respect to GND Pin.....................................22V OUT-to-OUTS Differential (Note 6)...........................22V Output Short-Circuit Duration........................... Indefinite Operating Junction Temperature Range (Note 3) E-, I-Grades........................................ -40C to 125C H-Grade.............................................. -40C to 150C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) MSE Package Only............................................. 300C PIN CONFIGURATION TOP VIEW TOP VIEW IN 1 12 OUT IN 2 11 OUT EN/UV 3 PG 4 PGFB 5 ILIM 6 13 IN IN IN EN/UV PG PGFB ILIM 10 OUTS 9 GND 8 SET 7 VIOC 1 2 3 4 5 6 13 IN 12 11 10 9 8 7 OUT OUT OUTS GND SET VIOC MSE PACKAGE 12-LEAD PLASTIC MSOP DD PACKAGE 12-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 150C, JA = 34C/W, JC = 5.5C/W EXPOSED PAD (PIN 13) IS IN, MUST BE SOLDERED TO PCB TJMAX = 150C, JA = 33C/W, JC = 8C/W EXPOSED PAD (PIN 13) IS IN, MUST BE SOLDERED TO PCB Rev. 0 For more information www.analog.com 3 LT3093 ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3093EDD#PBF LT3093EDD#TRPBF LHJQ 12-Lead (3mm x 3mm) Plastic DFN -40C to 125C LT3093IDD#PBF LT3093IDD#TRPBF LHJQ 12-Lead (3mm x 3mm) Plastic DFN -40C to 125C LT3093HDD#PBF LT3093HDD#TRPBF LHJQ 12-Lead (3mm x 3mm) Plastic DFN -40C to 150C LT3093EMSE#PBF LT3093EMSE#TRPBF 3093 12-Lead Plastic MSOP -40C to 125C LT3093IMSE#PBF LT3093IMSE#TRPBF 3093 12-Lead Plastic MSOP -40C to 125C LT3093HMSE#PBF LT3093HMSE#TRPBF 3093 12-Lead Plastic MSOP -40C to 150C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) PARAMETER CONDITIONS MIN Input Voltage Range Minimum IN Pin Voltage (Note 8) SET Pin Current (ISET) VIN = -2.3V, ILOAD = 1mA, VOUT = -1.5V -20V < VIN < -2.3V, -19.5V < VOUT <0V, -1mA > ILOAD > -200mA (Note 7) TYP ILOAD = -200mA l -20 ILOAD = -200mA, VIN UVLO Rising VIN UVLO Hysteresis l -2.3 -1.8 130 l 99 98 100 100 Fast Start-Up SET Pin Current VPGFB = -286mV, VIN = -2.3V, VSET = -1.5V Output Offset Voltage VOS (VOUT - VSET) (Note 9) VIN = -2.3V, ILOAD = 1mA, VOUT = -1.5V -20V < VIN < -2.3V, -19.5V < VOUT <0V, -1mA > ILOAD > -200mA (Note 7) l -1 -2 Line Regulation: ISET Line Regulation: VOS VIN = -2.3V to -20V, ILOAD = -1mA, VOUT = -1.5V VIN = -2.3V to -20V, ILOAD = -1mA, VOUT = -1.5V (Note 9) l l -5 -6 Load Regulation: ISET Load Regulation: VOS ILOAD = -1mA to -200mA, VIN = -2.3V, VOUT = -1.5V ILOAD = -1mA to -200mA, VIN = -2.3V, VOUT = -1.5V (Note 9) Change in ISET with VSET Change in VOS with VSET Change in ISET with VSET Change in VOS with VSET VSET = -1.5V to -19.5V, VIN = -20V, ILOAD = -1mA VSET = -1.5V to -19.5V, VIN = -20V, ILOAD = -1mA (Note 9) VSET = 0V to -1.5V, VIN = -20V, ILOAD = -1mA VSET = 0V to -1.5V, VIN = -20V, ILOAD = -1mA (Note 9) Dropout Voltage (Note 10) ILOAD = -1mA, -50mA MAX UNITS -2.3 V V mV 101 102 1.8 A A mA 1 2 mV mV 0.5 0.1 5 6 nA/V V/V l 0.1 0.03 0.5 nA mV l l l l 100 0.02 150 0.15 850 0.5 500 2 nA mV nA mV 185 225 275 mV mV 185 230 280 mV mV 190 240 330 mV mV 4 5.5 6.5 15 mA mA mA mA mA l ILOAD = -100mA l ILOAD = -200mA l GND Pin Current VIN = VOUT(NOMINAL) (Note 11) ILOAD = -10A ILOAD = -1mA ILOAD = -50mA ILOAD = -100mA ILOAD = -200mA Output Noise Spectral Density (Notes 9, 12) ILOAD = -200mA, Frequency = 10Hz, COUT = 4.7F, CSET = 0.47F, VOUT = -3.3V ILOAD = -200mA, Frequency = 10Hz, COUT = 4.7F, CSET = 4.7F, -19.5V VOUT -1.5V ILOAD = -200mA, Frequency = 10kHz, COUT = 4.7F, CSET = 0.47F, -19.5V VOUT -1.5V ILOAD = -200mA, Frequency = 10kHz, COUT = 4.7F, CSET = 0.47F, -1.5V VOUT 0V 700 70 2.2 6 nV/Hz nV/Hz nV/Hz nV/Hz Output RMS Noise (Notes 9, 12) ILOAD = -200mA, BW = 10Hz to 100kHz, COUT = 4.7F, CSET = 0.47F, VOUT = -3.3V ILOAD = -200mA, BW = 10Hz to 100kHz, COUT = 4.7F, CSET = 4.7F, -19.5V VOUT -1.5V ILOAD = -200mA, BW = 10Hz to 100kHz, COUT = 4.7F, CSET = 4.7F, -1.5V VOUT 0V 3 0.8 1.8 VRMS VRMS VRMS 4 l l l l 2.35 2.4 3.1 3.8 7 Rev. 0 For more information www.analog.com LT3093 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 3) PARAMETER CONDITIONS Reference Current RMS Output Noise (Notes 9, 12) BW = 10Hz to 100kHz Ripple Rejection -18V VOUT -1.5V VIN - VOUT = 2V (Avg) (Notes 9, 12) VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = -200mA, COUT = 4.7F, CSET = 4.7F VRIPPLE = 500mVP-P, fRIPPLE = 10kHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 100kHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 1MHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 10MHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F 108 94 75 74 45 dB dB dB dB dB Ripple Rejection -1.5V VOUT 0V VIN - VOUT = 2V (Avg) (Notes 9, 12) VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = -200mA, COUT = 4.7F, CSET = 4.7F VRIPPLE = 500mVP-P, fRIPPLE = 10kHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 100kHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 1MHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F VRIPPLE = 500mVP-P, fRIPPLE = 10MHz, ILOAD = -200mA, COUT = 4.7F, CSET = 0.47F 108 90 72 78 45 dB dB dB dB dB EN/UV Pin Threshold Positive EN/UV Trip Point Rising (Turn-On), VIN = -2.3V Negative EN/UV Trip Point Rising (Turn-On), VIN = -2.3V EN/UV Pin Hysteresis Positive EN/UV Trip Point Hysteresis, VIN = -2.3V Negative EN/UV Trip Point Hysteresis, VIN = -2.3V EN/UV Pin Current VEN/UV = 0V, VIN = -20V VEN/UV = -1.5V, VIN = -20V VEN/UV = -20V, VIN = -20V VEN/UV = 1.5V, VIN = -20V VEN/UV = 20V, VIN = 0V Quiescent Current in Shutdown (VEN/UV = 0V) VIN = -6V, VPG = Open Internal Current Limit (Note 14) VIN = -2.3V, VOUT = 0V VIN = -12V, VOUT = 0V VIN = -20V, VOUT = 0V MIN TYP MAX 8 nARMS l 1.20 1.26 1.35 l -1.33 -1.26 -1.20 200 215 l l -1 -35 l -0.5 -18.5 8 25 3 l l 220 l 20 400 240 50 UNITS V V mV mV 1 45 A A A A A 8 10 A A 80 mA mA mA Programmable Current Limit Programming Scale Factor: -20V < VIN < -2.3V (Note 13) VIN = -2.3V, VOUT = 0V, RILIM = 7.5k VIN = -2.3V, VOUT = 0V, RILIM = 37.5k 1.95 260 55 l l PGFB Trip Point PGFB Trip Point Rising l PGFB Hysteresis PGFB Trip Point Hysteresis 7 PGFB Pin Current VIN = -2.3V, VPGFB = -300mV 30 100 nA PG Output Low Voltage IPG = 100A l 17 50 mV PG Leakage Current VPG = 20V l 1 A VIOC Amplifier Gain -20V VIN -2.3V, VOUT -1.5V VIOC Sink Current VIN - VOUT = -2V, VVIOC = -1V 288 300 A * k mA mA 312 mV 1 l VIOC Voltage for Low VIN = -2.3V, VOUT > -1.5V Output Voltages (Note 15) mV V/V 100 A -0.8 V Minimum Load Current (Note 16) VOUT > -1.5V 10 Thermal Shutdown TJ Rising Hysteresis 167 8 C C Start-Up Time RSET = 49.9k, VOUT(NOM) = -5V, ILOAD = -200mA, CSET = 0.47F, VIN = -6V, VPGFB = -6V RSET = 49.9k, VOUT(NOM) = -5V, ILOAD = -200mA, CSET = 4.7F, VIN = -6V, VPGFB = -6V RSET = 49.9k, VOUT(NOM) = -5V, ILOAD = -200mA, CSET = 4.7F, VIN = -6V, RPG1 = 50k, RPG2 = 700k (with Fast Start-Up to 90% of VOUT) 55 550 10 ms ms ms Thermal Regulation 10ms Pulse l -0.01 A %/W Rev. 0 For more information www.analog.com 5 LT3093 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Parasitic diodes exist internally between the EN/UV, ILIM, PG, PGFB, SET, GND, VIOC, OUTS and OUT pins and the IN pin. Do not drive these pins more than 0.3V below the IN pin during a fault condition. These pins must remain at a voltage more positive than IN during normal operation. Note 3: The LT3093 is tested and specified under pulse load conditions such that TJ TA. The LT3093E is tested at TA = 25C and performance is guaranteed from 0C to 125C. Performance of the LT3093E over the full -40C and 125C operating temperature range is assured by design, characterization, and correlation with statistical process controls. The LT3093I is guaranteed over the full -40C to 125C operating junction temperature range. The LT3093H is 100% tested at the 150C operating temperature. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125C. Note 4: SET and OUTS pins are clamped using diodes and two 400 series resistors. For less than 5ms transients, this clamp circuitry can carry more than the rated current. Note 5: Maximum SET and OUTS pin current requirement must be satisfied. Note 6: Maximum OUT-to-OUTS differential is guaranteed by design. Note 7: Maximum junction temperature limits operating conditions. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current, especially due to the internal current limit foldback which starts to decrease current limit at VOUT - VIN > 7V. If operating at maximum output current, limit the input voltage range. If operating at maximum input voltage, limit the output current range. 6 Note 8: The EN/UV pin threshold must be met to ensure device operation. Note 9: OUTS ties directly to OUT. Note 10: Dropout voltage is the minimum input-to-output differential voltage needed to maintain regulation at a specified output current. The dropout voltage is measured when output is 1% out of regulation. This definition results in a higher dropout voltage compared to hard dropout-- which is measured when VIN = VOUT(NOMINAL). For output voltages between 0V and -1.8V, dropout voltage is limited by the minimum input voltage specification. Note 11: GND pin current is tested with VIN = VOUT(NOMINAL) and a current source load. Therefore, the device is tested while operating in dropout. This is the worst-case GND pin current. GND pin current decreases at higher input voltages. Note that GND pin current does not include SET pin or ILIM pin current, but they are included in quiescent current. Note 12: Adding a capacitor across the SET pin resistor decreases output voltage noise. Adding this capacitor bypasses the SET pin resistor's thermal noise as well as the reference current's noise. The output noise then equals the error amplifier noise. Use of a SET pin bypass capacitor also increases start-up time. Note 13: The current limit programming scale factor is specified while the internal backup current limit is not active. Note that the internal current limit has foldback protection for VOUT - VIN differentials greater than 7V. Note 14: The internal backup current limit circuitry incorporates foldback protection that decreases current limit for VOUT - VIN > 7V. Some level of output current is provided at all VOUT - VIN differential voltages. Consult the Typical Performance Characteristics graph for current limit vs VIN - VOUT. Note 15: The VIOC amplifier outputs a voltage equal to VIN - VOUT or VIN + 1.5V (when VOUT is between 0V and -1.5V). See Block Diagram and Applications Information for further information. Note 16: For output voltages between 0V and -1.5V, the LT3093 requires a 10A minimum load current for stability. Rev. 0 For more information www.analog.com LT3093 TYPICAL PERFORMANCE CHARACTERISTICS 101.0 2.0 N = 5668 VIN = -2.3V IL = -1mA VOUT = -1.5V 100.4 100.2 100.0 99.8 99.6 99.4 99.0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 98 3093 G01 Offset Voltage 1.0 0.5 0 -0.5 -1.0 99 100 101 ISET DISTRIBUTION (A) -2.0 -75 -50 -25 102 3093 G03 Offset Voltage (VOUT - VSET) 1.0 IL = -1mA VOUT = -1.5V 100.8 IL = -1mA 0.8 VOUT = -1.5V 0.6 100.4 100.2 100.0 99.8 99.6 -55C 25C 125C 150C 99.4 99.2 -1 0 1 VOS DISTRIBUTION (mV) 2 100.6 -55C 25C 125C 150C 100.4 100.0 99.8 99.6 99.4 99.2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 OUTPUT VOLTAGE (V) 3093 G07 -0.4 -55C 25C 125C 150C -1.0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 INPUT VOLTAGE (V) 2.0 3093 G06 Offset Voltage (VOUT - VSET) VIN = -20V IL = -1mA 1.5 1.0 Load Regulation 18 -55C 25C 125C 150C 0.5 16 14 0 -0.5 0.175 0.150 8 0.125 6 2 -1.5 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 OUTPUT VOLTAGE (V) 3093 G08 0.200 10 4 0 0.225 12 -1.0 -2.0 0.250 VIN = -2.3V VOUT = -1.5V IL = -1mA to -200mA -2 -75 -50 -25 0.100 VOS VOS (mV) 100.2 0.0 -0.2 3093 G05 OFFSET VOLTAGE (mV) VIN = -20V IL = -1mA 100.8 0.2 -0.8 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 INPUT VOLTAGE (V) 3093 G04 SET Pin Current 101.0 0 0.4 -0.6 ISET (nA) -2 OFFSET VOLTAGE (mV) SET PIN CURRENT (A) 100.6 99.0 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G02 SET Pin Current 101.0 N = 5668 SET PIN CURRENT (A) VIN = -2.3V IL = -1mA VOUT = -1.5V -1.5 99.2 99.0 Offset Voltage (VOUT - VSET) 1.5 OFFSET VOLTAGE (mV) 100.6 SET PIN CURRENT (A) SET Pin Current SET Pin Current 100.8 TA = 25C, unless otherwise noted. 0.075 0.050 ISET 0.025 0 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G09 Rev. 0 For more information www.analog.com 7 LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current VEN/UV = 0V 45 QUIESCENT CURRENT (A) 2.5 2.0 1.5 1.0 40 35 30 25 20 15 VIN = -20V 10 0.5 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) DROPOUT VOLTAGE (mV) QUIESCENT CURRENT (mA) 2.0 1.5 1.0 -55C 25C 125C 150C 0.5 0 -1 -2 -3 -4 OUTPUT VOLTAGE (V) 150 100 0 -5 -55C 25C 125C 150C 0 40 80 120 160 OUTPUT CURRENT (mA) 1 0 -75 -50 -25 IL = -1mA IL = -100mA IL = -150mA IL = -200mA 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G16 8 GND PIN CURRENT (mA) GND PIN CURRENT (mA) 2 100 50 0 -75 -50 -25 200 GND GND Pin Pin Current Current 8 5 4 3 -55C 25C 125C 150C 1 0 0 RSET = 33.2k 7 6 2 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G15 VIN = -5V RSET = 33.2k 7 3 IL = -1mA 150 GND Pin Current 8 4 IL = -200mA 200 3093 G14 VIN = -5V RSET = 33.2k 5 RSET = 33.2k 250 50 6 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 INPUT VOLTAGE (V) Dropout Voltage 300 200 GND Pin Current 7 0 3093 G12 RSET = 33.2k 3093 G13 8 1.0 0 250 2.5 0 1.5 Typical Dropout Voltage 300 VIN = -6V VEN/UV = VIN IL = -10A 3.0 2.0 3093 G11 Quiescent Current 3.5 2.5 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G10 4.0 3.0 0.5 VIN = -2.3V 5 0 -75 -50 -25 VEN/UV = VIN IL = -10A RSET = 15k 3.5 DROPOUT VOLTAGE (mV) 3.0 Quiescent Current 4.0 QUIESCENT CURRENT (mA) VIN = -2.3V VEN/UV = VIN IL = -10A RSET = 15k 3.5 QUIESCENT CURRENT (mA) Quiescent Current 50 -25 -50 -75 -100 -125 -150 -175 -200 OUTPUT CURRENT (mA) 3093 G17 GND PIN CURRENT (mA) 4.0 TA = 25C, unless otherwise noted. RL = 16.5 6 5 RL = 33 4 3 RL = 66 2 RL = 3.3k 1 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 INPUT VOLTAGE (V) 3093 G18 Rev. 0 For more information www.analog.com LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Negative EN/UV Turn-On Threshold Minimum Input Voltage -1.75 -1.50 -1.25 -1.00 -0.75 -0.50 RISING UVLO FALLING UVLO 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 1.36 -1.34 -1.32 -1.30 -1.28 -1.26 -1.24 -1.22 -1.20 VIN = -2.3V VIN = -20V -1.18 -1.16 -75 -50 -25 3093 G19 150 100 POSITIVE HYSTERESIS NEGATIVE HYSTERESIS 1.22 1.20 1.18 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G21 Internal Current Limit RILIM = 0 450 VOUT = 0V 8 4 0 -4 -8 -55C 25C 125C 150C -12 250 200 150 100 50 0 -75 -50 -25 Programmable Current Limit 400 350 400 350 300 250 200 150 -55C 25C 125C 150C 100 50 0 25 50 75 100 125 150 TEMPERATURE (C) 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G24 RILIM = 0 450 20 VIN = -7.5V 300 3093 G23 VIN = -20V RILIM = 0 VOUT = 0V 40 VIN = -2.5V 350 Internal Current Current Limit Limit Internal 60 0 25 50 75 100 125 150 TEMPERATURE (C) 400 500 80 VIN = -2.3V VIN = -20V 1.16 -75 -50 -25 -20 -20 -16 -12 -8 -4 0 4 8 12 16 20 EN/UV PIN VOLTAGE (V) CURRENT LIMIT (mA) CURRENT LIMIT (mA) 1.24 12 -16 Internal Current Limit 0 -75 -50 -25 1.26 500 3093 G22 100 1.28 CURRENT LIMIT (mA) 200 120 1.30 VIN = -5V (VEN/UV 0V) VIN = -20V (VEN/UV < 0V) 16 EN/UV PIN CURRENT (A) EN/UV PIN HYSTERESIS (mV) VIN = -2.3V 0 -75 -50 -25 1.32 EN/UV Pin Current 20 250 50 0 25 50 75 100 125 150 TEMPERATURE (C) 1.34 3093 G20 EN/UV Pin Hysteresis 300 POSITIVE EN/UV TURN-ON THRESHOLD (V) -2.00 Positive EN/UV Turn-On Threshold -1.36 CURRENT LIMIT (mA) INPUT UVLO THRESHOLD (V) -2.25 NEGATIVE EN/UV TURN-ON THRESHOLD (V) -2.50 -0.25 TA = 25C, unless otherwise noted. 0 0 3093 G26 3093 G25 300 250 200 150 100 50 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 INPUT-TO-OUTPUT DIFFERENTIAL (V) RILIM = 7.5k VOUT = 0V VIN = -2.3V VIN = -8V 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G27 Rev. 0 For more information www.analog.com 9 LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Programmable Current Limit 90 -310 RILIM = 37.5k VOUT = 0V -308 70 60 50 40 30 20 VIN = -2.3V VIN = -8V 10 0 -75 -50 -25 VIN = -2.3V 0 25 50 75 100 125 150 TEMPERATURE (C) -300 -298 -296 180 150 120 90 60 -292 30 -290 -75 -50 -25 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G29 -1 -306 -302 -300 -298 PG Output Low Voltage 50 VIN = -2.3V -2 40 -3 35 -4 30 -5 -6 25 20 -7 15 -294 -8 10 -292 -9 5 -296 -290 -75 -50 -25 -10 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) ISET During Start-Up with Fast Start-Up Enabled 3.0 VIN = -2.3V VPGFB = -314mV VPG = 5V 2.5 ISET During Start-Up with Fast Start-Up Enabled 2.50 VIN = -2.3V VPGFB = -286mV VSET = -1.5V 120 100 80 2.00 1.75 1.5 1.0 60 40 1.50 1.25 1.00 0.75 0.50 0.5 20 0.25 0 25 50 75 100 125 150 TEMPERATURE (C) 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G35 3093 G34 10 VPGFB = -286mV VOUT = -1.3V 2.25 2.0 ISET (mA) IPG (nA) 140 0 -75 -50 -25 3093 G33 ISET (mA) 160 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G32 PG Pin Leakage Current 180 0 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G31 200 VIN = -2.3V VPGFB = -286mV IPG = 100A 45 VPG (mV) VIN = -2.3V 0 25 50 75 100 125 150 TEMPERATURE (C) 3093 G30 PGFB Hysteresis PGFB HYSTERESIS (mV) PGFB RISING THRESHOLD (mV) 210 -294 0 -304 VIN = -2.3V VILIM = 0V 240 -302 PGFB Rising Threshold -308 ILIM Pin Current 270 -304 3093 G28 -310 300 -306 ILIM PIN VOLTAGE (mV) CURRENT LIMIT (mA) 80 ILIM Pin Voltage ILIM PIN CURRENT (A) 100 TA = 25C, unless otherwise noted. 0 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 VIN-TO-VSET DIFFERENTIAL (V) 3093 G36 Rev. 0 For more information www.analog.com LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Output Overshoot Recovery Source Current Output Overshoot Recovery Source Source Current Current 4.0 3.0 2.5 2.0 1.5 1.0 -55C 25C 125C 150C 0.5 0 0 -5 -10 -15 VOUT - VSET (mV) VIN = -5V RSET = 33.2k VOUT - VSET = -20mV 3.5 3.0 2.5 2.0 1.5 1.0 VIOC SOURCE CURRENT (A) VIOC VOLTAGE (V) -1.02 -1.00 -0.98 -55C 25C 125C 150C 0 25 -0.96 3093 G39 VIN = -3.6V VOUT = -3.3V IL = -1mA 15 10 5 0 50 75 100 125 150 175 200 VIOC SINK CURRENT (A) 0 -0.3 -0.6 -0.9 VIOC VOLTAGE (V) -1.2 Power Supply Ripple Rejection Power Supply Ripple Rejection Power Supply Ripple Rejection 120 COUT = 4.7F COUT = 22F 110 100 90 90 80 80 80 60 50 30 20 10 100 1k 10k 100k FREQUENCY (Hz) 70 60 50 VIN = -5V RSET = 33.2k COUT = 4.7F IL = -200mA 40 PSRR (dB) 100 90 70 30 1M 10M 20 10 100 70 60 50 VIN = -5V RSET = 33.2k CSET = 4.7F IL = -200mA 40 VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F 110 100 PSRR (dB) PSRR (dB) 120 CSET = 4.7F CSET = 0.47F 110 -1.5 3093 G41 3093 G40 120 0 25 50 75 100 125 150 TEMPERATURE (C) VIOC VIOC Source Source Current Current 20 -1.04 -0.90 -0.98 3093 G38 3093 G37 VIN = -4.3V -1.08 VOUT = -3.3V I = -1mA -1.06 L -0.92 -1.00 -0.90 -75 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) VIOC Voltage -0.94 -1.02 -0.92 -1.10 -0.96 VIN = -4.3V -1.08 VOUT = -3.3V I = -100A -1.06 IVIOC L = -1mA -1.04 -0.94 0.5 0 -75 -50 -25 -20 VIOC Voltage -1.10 VIOC VOLTAGE (V) VIN = -5V RSET = 33.2k 3.5 OUTPUT SOURCE CURRENT (mA) OUTPUT SOURCE CURRENT (mA) 4.0 TA = 25C, unless otherwise noted. IL = -200mA IL = -100mA IL = -50mA IL = -1mA 40 30 1k 10k 100k FREQUENCY (Hz) 1M 10M 3093 G43 3093 G42 20 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3093 G44 Rev. 0 For more information www.analog.com 11 LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Ripple Rejection as a Function of Error Amplifier Input Pair 100 90 80 70 80 PSRR (dB) PSRR (dB) 90 70 60 50 60 50 40 30 40 10 100 100kHz 500kHz 1MHz 2MHz 20 VOUT -1.5V -0.8V > VOUT > -1.5V VOUT -0.8V 30 20 2.0 100 VIN = VOUT - 2.3V IL = -200mA COUT = 4.7F CSET = 4.7F 110 Integrated RMS Output Noise (10Hz to 100kHz) Power Supply Ripple Rejection RMS OUTPUT NOISE (VRMS) 120 TA = 25C, unless otherwise noted. 10 1k 10k 100k FREQUENCY (Hz) 1M 0 10M 0 3093 G45 IL = -200mA RSET = 33.2k COUT = 4.7F CSET = 0.47F -1 -2 -3 -4 INPUT-TO-OUTPUT DIFFERENTIAL (V) 0.8 0.6 0.4 0.2 0 -5 0 -40 -80 -120 -160 LOAD CURRENT (mA) -200 3093 G47 8 6 4 2 2.0 VIN = VOUT - 2.3V COUT = 4.7F CSET = 4.7F ILOAD = -200mA 1.8 RMS OUTPUT NOISE (VRMS) RMS OUTPUT NOISE (VRMS) 1.0 Integrated RMS Output Noise (10Hz to 100kHz) VIN = -5V RSET = 33.2k COUT = 4.7F ILOAD = -200mA 10 1.2 3093 G46 Integrated RMS Output Noise (10Hz to 100kHz) 12 VIN = -5V 1.8 RSET = 33.2k C = 4.7F 1.6 COUT = 4.7F SET 1.4 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.01 0.1 1 10 SET PIN CAPACITANCE (F) 0 100 0 -2.5 -5 -7.5 -10 -12.5 OUTPUT VOLTAGE (V) 3093 G48 3093 G49 Noise Spectral Density Noise Spectral Density 1k 1k VIN = -5V RSET = 33.2k CSET = 4.7F ILOAD = -200mA CSET = 0.47F CSET = 1F CSET = 4.7F 10 CSET = 22F 1 0.1 OUTPUT NOISE (nV/Hz) OUTPUT NOISE (nV/Hz) CSET = 0.047F 100 VIN = -5V RSET = 33.2k 10 100 NOISE FLOOR COUT = 4.7F ILOAD = -200mA 1k 10k 100k FREQUENCY (Hz) 1M 10M 100 COUT = 4.7F 10 1 0.1 NOISE FLOOR 10 3093 G50 12 -15 100 COUT = 22F 1k 10k 100k FREQUENCY (Hz) 1M 10M 3093 G51 Rev. 0 For more information www.analog.com LT3093 TYPICAL PERFORMANCE CHARACTERISTICS Noise Spectral Density as a Function of Error Amplifier Input Pair ILOAD = -200mA 10 ILOAD = -100mA 1 ILOAD = -1mA NOISE FLOOR 0.1 10 100 ILOAD = -50mA 1k 10k 100k FREQUENCY (Hz) 1M 10M OUTPUT NOISE (nV/Hz) OUTPUT NOISE (nV/Hz) 100 1k VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F Noise Spectral Density (0.1Hz to 10Hz) VIN = VOUT - 2.3V COUT = 4.7F CSET = 4.7F ILOAD = -200mA 100 VOUT -0.5V -0.5V > VOUT > -1.5V 10 VOUT -1.5V 1 0.1 10k NOISE SPECTRAL DENSITY (V/Hz) Noise Spectral Density 1k TA = 25C, unless otherwise noted. NOISE FLOOR 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M VIN = -5V RSET = 33.2k COUT = 4.7F IL = -200mA 1k 100 10 1 0.1 0.01 0.1 CSET = 4.7F CSET = 22F 1 FREQUENCY (Hz) 3093 G54 3093 G53 3093 G52 10 Output Voltage Noise (0.1Hz to 10Hz) Output Noise (10Hz to 100kHz) 5V/DIV 5V/DIV VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F ILOAD = -200mA 1ms/DIV 3093 G55 VIN = - 5V RSET = 33.2k COUT = 4.7F CSET = 4.7F ILOAD = -200mA Output Voltage Noise (0.1Hz to 10Hz) 1s/DIV 3093 G56 Load Transient Response tr = tf = 50ns OUTPUT CURRENT 200mA/DIV 5V/DIV OUTPUT VOLTAGE 10mV/DIV VIN = - 5V RSET = 33.2k COUT = 4.7F CSET = 22F ILOAD = -200mA 1s/DIV 3093 G57 5s/DIV 3093 G58 VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F IL = -10mA TO -200mA Rev. 0 For more information www.analog.com 13 LT3093 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. Start-Up Time with and without Fast Start-Up Circuitry for Large CSET SET Line Transient Response Input Supply Ramp-Up and Ramp-Down tr = tf = 1s OUTPUT WITHOUT FAST START-UP OUTPUT VOLTAGE 1mV/DIV 1V/DIV PULSE EN/UV OUTPUT WITH FAST START-UP (SET TO 90%) INPUT VOLTAGE 1V/DIV OUTPUT VOLTAGE 2V/DIV INPUT VOLTAGE 500mV/DIV 5s/DIV RSET = 33.2k COUT = 4.7F CSET = 4.7F VIN = -4.5V TO -5.5V IL = -200mA 14 3093 G59 VIN = -5V RSET = 33.2k COUT = 4.7F CSET = 4.7F RL = 16.5 100ms/DIV 3093 G60 50ms/DIV 3093 G61 VIN = 0V TO -5V VEN/UV = VIN RSET = 33.2k COUT = 4.7F CSET = 4.7F RL = 16.5 Rev. 0 For more information www.analog.com LT3093 PIN FUNCTIONS IN (Pins 1, 2, Exposed Pad Pin 13): Input. These pins supply power to the regulator. The LT3093 requires a bypass capacitor at the IN pin. In general, a battery's output impedance rises with frequency, so include a bypass capacitor in battery-powered applications. While a 4.7F input bypass capacitor generally suffices, applications with large load transients may require higher input capacitance to prevent input supply droop. Consult the Applications Information section on the proper use of an input capacitor and its effect on circuit performance. EN/UV (Pin 3): Enable/UVLO. Pulling the LT3093's EN/UV pin low places the part in shutdown. Quiescent current in shutdown drops to 3A and the output voltage turns off. Alternatively, the EN/UV pin can set an input supply undervoltage lockout (UVLO) threshold using a resistor divider between IN, EN/UV and GND. The EN/UV pin is bidirectional and can be switched with either a positive or negative voltage. The LT3093 typically turns on when the EN/UV voltage exceeds 1.26V above ground (with a 200mV hysteresis on its falling edge) or 1.26V below ground (with a 215mV hysteresis). If unused, tie EN/UV to IN. Do not float the EN/UV pin. PG (Pin 4): Power Good. PG is an open-collector flag that indicates output voltage regulation. PG pulls low if PGFB is between 0V and -300mV. If the power good functionality is not needed, float the PG pin. The PG flag status is valid even if the LT3093 is in shutdown, with the PG pin being pulled low. PGFB (Pin 5): Power Good Feedback. The PG pin pulls high if PGFB is below -300mV on its rising edge, with 7mV hysteresis on its falling edge. Connecting an external resistor divider between OUT, PGFB, and GND sets the programmable power good threshold with the following transfer function: -0.3V * (1 + RPG1/RPG2) - IPGFB * RPG1. As discussed in the Applications Information section, PGFB also activates the fast start-up circuitry. If power good and fast start-up functionality are not needed, tie PGFB to IN. ILIM (Pin 6): Current Limit Programming Pin. Connecting a resistor between ILIM and GND programs the current limit. For best accuracy, Kelvin connect this resistor directly to the LT3093's GND pin. The programming scale factor is nominally 1.95A * k. If the programmable current limit functionality is not needed, tie ILIM to GND. Do not float the ILIM pin. VIOC (Pin 7): Voltage for Input-to-Output Control. The LT3093 incorporates a tracking feature to control a circuit supplying power to the LT3093 to maintain the differential voltage across the LT3093. This function maximizes efficiency and PSRR performance while minimizing power dissipation. See the Applications Information section for further information. If unused, float the VIOC pin. SET (Pin 8): Set. This pin is the inverting input of the error amplifier and the regulation setpoint for the LT3093. The SET pin sinks a precision 100A current that flows through an external resistor connected between SET and GND. The LT3093's output voltage is determined by VSET = ISET * RSET. Output voltage range is from zero to -19.5V. Adding a capacitor from SET to GND improves noise, PSRR, and transient response at the expense of increased start-up time unless the fast start-up capability is used via the PGFB pin. For optimum load regulation, Kelvin connect the ground side of the SET pin directly to the load. GND (Pin 9): Ground. OUTS (Pin 10): Output Sense. This pin is the noninverting input to the error amplifier. For optimal transient performance and load regulation, Kelvin connect OUTS directly to the output capacitor and the load. Also, tie the GND connections of the output capacitor and the SET pin capacitor directly together. Exercise care with regards to placement of input capacitors relative to output capacitors due to potential PSRR degradation from magnetic coupling effects; see the Applications Information section for further information on capacitor placement and board layout. A parasitic substrate diode exists between OUTS and IN pins of the LT3093; do not drive OUTS more than 0.3V below IN during normal operation or a fault condition. OUT (Pins 11, 12): Output. This pin supplies power to the load. For stability, use a minimum 4.7F output capacitor with an ESR below 30m and an ESL below 1.5nH. Large load transients require larger output capacitance to limit peak voltage transients. Refer to the Applications Information section for more information on output capacitance. A parasitic substrate diode exists between OUT and IN pins of the LT3093; do not drive OUT more than 0.3V below IN during normal operation or during a fault condition. Rev. 0 For more information www.analog.com 15 For more information www.analog.com RPG2 RPG1 RPG V+ 5 4 3 PGFB -300mV PG -1.26V EN/UV PROGRAMMABLE POWER GOOD + - 1.26V 9 IDEAL DIODE BIDIRECTIONAL ENABLE COMPARATOR GND VIOC AV = 1 BIAS IN -1.5V CURRENT REFERENCE INPUT UVLO CURRENT LIMIT THERMAL SHUTDOWN DROPOUT 1.8mA FAST START-UP - - + FAST START-UP DISABLE LOGIC INPUT-TO-OUTPUT CONTROL 7 8 90mV INPUT UVLO THERMAL SHUTDOWN SET-TO-OUTS PROTECTION CLAMP 100A SET 10 ERROR AMPLIFIER INTERNAL CURRENT LIMIT - + OUTS -300mV PROGRAMMABLE CURRENT LIMIT DRIVER + - + RSET + - + - + - 16 - CSET 6 1.5K ILIM RILIM CIN VIN 3093 BD IN 1, 2, 13 0.23 OUT 11, 12 COUT RL VOUT LT3093 BLOCK DIAGRAM Rev. 0 LT3093 APPLICATIONS INFORMATION The LT3093 is a high performance low dropout negative linear regulator featuring ADI's ultralow noise (2.2nV/Hz at 10kHz) and ultrahigh PSRR (73dB at 1MHz) architecture for powering noise sensitive applications. Designed as a precision current reference followed by a high performance rail-to-rail voltage buffer, the LT3093 can be easily paralleled to further reduce noise, increase output current and spread heat on the PCB. The device additionally features programmable current limit, fast start-up capability and programmable power good. The LT3093 is easy to use and incorporates all of the protection features expected in high performance regulators. Included are short-circuit protection, safe operating area protection, and thermal shutdown with hysteresis. Output Voltage The LT3093 incorporates a precision 100A current reference flowing into the SET pin, which also ties to the error amplifier's inverting input. Figure 1 illustrates that connecting a resistor from SET to ground generates a reference voltage for the error amplifier. This reference voltage is simply the product of the SET pin current and the SET pin resistor. The error amplifier's unity-gain configuration produces a low impedance version of this voltage on its noninverting input, i.e. the OUTS pin, which is externally tied to the OUT pin. The LT3093's output voltage is determined by VSET = ISET * RSET. 4.7F RSET 33.2k 4.7F LT3093 PGFB EN/UV SET GND + ILIM OUTS OUT - 100A VIN -5V IN 3093 F01 PINS NOT USED IN THIS CIRCUIT: PG, VIOC Figure 1. Basic Adjustable Regulator VOUT -3.3V IOUT(MAX) -200mA The LT3093's rail-to-rail error amplifier and current reference architecture allows for a wide output voltage range from 0V (using a 0 resistor) to VIN minus dropout. An NPN-based input pair is active for a 0V to -0.8V output and a PNP-based input pair is active for output voltages beyond -1.5V, with a smooth transition between the two input pairs from -0.8V to -1.5V output. The PNP-based input pair offers the best overall performance; refer to the Electrical Characteristics table for details on offset voltage, SET pin current, output noise and PSRR variation depending on the output voltage and corresponding active input pair(s). Table 1 lists common output voltages and their corresponding 1% RSET resistors. Table 1. 1% Resistor for Common Output Voltages VOUT (V) RSET (k) -2.5 24.9 -3.3 33.2 -5 49.9 -12 121 -15 150 The benefit of using a current reference compared with a voltage reference as used in conventional regulators is that the regulator always operates in a unity-gain configuration, independent of the programmed output voltage. This allows the LT3093 to have loop gain, frequency response and bandwidth independent of the output voltage. As a result, noise, PSRR and transient performance do not change with output voltage. Moreover, since error amplifier gain is not needed to amplify the SET pin voltage to a higher output voltage, output load regulation is more tightly specified in the hundreds of microvolts range and not as a fixed percentage of the output voltage. Since the zero TC current reference is highly accurate, the SET pin resistor can become the limiting factor in achieving high accuracy. Hence, it should be a precision resistor. Additionally, any leakage paths to or from the SET pin create errors in the output voltage. If necessary, use high quality insulation (e.g. Teflon, Kel-F); moreover, cleaning of all insulating surfaces to remove fluxes and other residues may be required. High humidity environments may require a surface coating at the SET pin to provide a moisture barrier. Rev. 0 For more information www.analog.com 17 LT3093 APPLICATIONS INFORMATION Minimize board leakage by encircling the SET pin with a guard ring operated at a similar potential--ideally tied to the OUT pin. Guarding both sides of the circuit board is recommended. Bulk leakage reduction depends on the guard ring width. Leakage of 100nA into or out of the SET pin creates a 0.1% error in the reference voltage. Leakages of this magnitude, coupled with other sources of leakage, can cause significant errors in the output voltage, especially over wide operating temperature ranges. Figure 2 illustrates a typical guard ring layout technique. 1 12 2 11 3 4 13 10 to avoid adding extra impedance (ESR and ESL) outside the feedback loop. To that end, minimize the effects of PCB trace and solder inductance by tying the OUTS pin directly to COUT and the GND side of CSET directly to the GND side of COUT, as well as keep the GND sides of CIN and COUT reasonably close, as shown in Figure 3. Refer to the LT3093 demo board manual for more information on the recommended layout that meets these requirements. While the LT3093 is robust and will not oscillate if the recommended layout is not followed, depending on the actual layout, phase/gain margin, noise and PSRR performance may degrade. OUT CSET 9 5 8 6 7 LT3093 3093 F02 Figure 2. DFN Guard Ring Layout PGFB Since the SET pin is a high impedance node, unwanted signals may couple into the SET pin and cause erratic behavior. This is most noticeable when operating with a minimum output capacitor at heavy load currents. Bypassing the SET pin with a small capacitance to ground resolves this issue--10nF is sufficient. EN/UV For applications requiring higher accuracy or an adjustable output voltage, the SET pin may be actively driven by an external voltage source capable of sourcing 100A. Connecting a precision voltage reference to the SET pin eliminates any errors present in the output voltage due to the reference current and SET pin resistor tolerances. Output Sensing and Stability The LT3093's OUTS pin provides a Kelvin sense connection to the output. The SET pin resistor's GND side provides a Kelvin sense connection to the load's GND side. Additionally, for ultrahigh PSRR, the LT3093 bandwidth is made quite high (~1MHz), making it very close to a typical 4.7F (1206 case size) ceramic output capacitor's self-resonance frequency (~2.3MHz). It is very important 18 RSET SET CIN SET GND + ILIM OUTS OUT VOUT IOUT(MAX) -200mA DEMO BOARD PCB LAYOUT ILLUSTRATES 4-TERMINAL CONNECTION TO COUT - 100A IN VIN COUT 3093 F03 PINS NOT USED IN THIS CIRCUIT: PG, VIOC Figure 3. COUT and CSET Connections for Best Performance Stability and Output Capacitance The LT3093 requires an output capacitor for stability. Given its high bandwidth, ADI recommends low ESR and ESL ceramic capacitors. A minimum 4.7F output capacitance with an ESR below 30m and an ESL below 1.5nH is required for stability. Given the high PSRR and low noise performance attained with using a single 4.7F ceramic output capacitor, larger values of output capacitor only marginally improve the performance because the regulator bandwidth decreases with increasing output capacitance--hence, there is little to be gained by using larger than the minimum 4.7F output capacitor. Nonetheless, larger values of output capacitance do decrease peak output deviations during a load Rev. 0 For more information www.analog.com LT3093 APPLICATIONS INFORMATION The X5R and X7R dielectrics result in more stable characteristics and are thus more suitable for use with the LT3093. The X7R dielectric has better stability across temperature, while the X5R is less expensive and is available in higher values. Nonetheless, care must still be exercised when using X5R and X7R capacitors. The X5R and X7R codes only specify operating temperature range and the maximum capacitance change over temperature. While capacitance change due to DC bias for X5R and X7R is better than Y5V and Z5U dielectrics, it can still be significant enough to drop capacitance below sufficient levels. As shown in Figure 6, capacitor DC bias characteristics tend to improve as component case size increases, but verification of expected capacitance at the operating voltage is highly recommended. High Vibration Environments Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress upon it, similar to how a piezoelectric microphone works. For a ceramic capacitor, this stress can be induced by mechanical vibrations within the system or due to thermal transients. LT3093 applications in high vibration environments have three distinct piezoelectric noise generators: ceramic BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 0 CHANGE IN VALUE (%) X5R -20 -40 -60 Y5V -80 -100 0 2 4 16 14 6 12 8 10 DC BIAS VOLTAGE (V) 3093 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F 20 CHANGE IN VALUE (%) Give extra consideration to the type of ceramic capacitors used. They are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitance in small packages, but they tend to have stronger voltage and temperature coefficients as shown in Figure 4 and Figure 5. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied over the operating temperature range. 20 X5R 0 -20 -40 Y5V -60 -80 -100 -50 -25 0 25 75 50 TEMPERATURE (C) 100 125 3093 F05 Figure 5. Ceramic Capacitor Temperature Characteristics 20 1210, 2.2mm THICK 1206, 1.8mm THICK 0805, 1.4mm THICK 0 CHANGE IN VALUE (%) transient. Note that bypass capacitors used to decouple individual components powered by the LT3093 increase the effective output capacitance. -20 -40 -60 -80 -100 MURATA: X7R, 25V,4.7F CERAMIC 1 5 10 15 DC BIAS (V) 20 25 3093 F06 Figure 6. Capacitor Voltage Coefficient for Different Case Sizes Rev. 0 For more information www.analog.com 19 LT3093 APPLICATIONS INFORMATION output, input, and SET pin capacitors. However, due to the LT3093's very low output impedance over a wide frequency range, negligible output noise is generated using a ceramic output capacitor. Similarly, due to the LT3093's ultrahigh PSRR, negligible output noise is generated using a ceramic input capacitor. Given the high SET pin impedance, any piezoelectric response from a ceramic SET pin capacitor generates significant output noise; peak-to-peak excursions of hundreds of Vs are possible. However, due to the SET pin capacitor's high ESR and ESL tolerance, any non-piezoelectrically responsive (tantalum, electrolytic, or film) capacitor can be used at the SET pin; do note that electrolytic capacitors tend to have high 1/f noise. In any case, use of surface mount capacitors is highly recommended. Stability and Input Capacitance The LT3093 is stable with a minimum 4.7F IN pin capacitor. ADI recommends using low ESR ceramic capacitors. Applications using long wires to connect the power supply to the LT3093's input and ground terminals together with low ESR ceramic input capacitors are prone to voltage spikes, reliability concerns and application-specific board oscillations. The wire inductance combined with the low ESR ceramic input capacitor forms a high Q resonant LC tank circuit. In some instances, this resonant frequency beats against the output current LDO bandwidth and interferes with stable operation. The resonant LC tank circuit formed by the wire inductance and input capacitor is the cause and not because of LT3093's instability. The self inductance, or isolated inductance, of a wire is directly proportional to its length. The wire diameter, however, has less influence on its self inductance. For example, the self inductance of a 2-AWG isolated wire with a diameter of 0.26" is about half the inductance of a 30-AWG wire with a diameter of 0.01". One foot of 30-AWG wire has 465nH of self inductance. Several methods exist to reduce a wire's self inductance. One method divides the current flowing towards the LT3093 between two parallel conductors. In this case, placing wire further apart reduces the inductance; up to a 50% reduction when placed only a few inches apart. Splitting the wires connects two equal inductors in parallel. However, when placed in close proximity to each other, their 20 mutual inductance adds to the overall self inductance of the wires--therefore a 50% reduction is not possible in such cases. The second and more effective technique to reduce the overall inductance is to place the forward and return current conductors (the input and ground wires) in close proximity. Two 30-AWG wires separated by 0.02" reduce the overall inductance to about one-fifth of a single wire. If a battery mounted in close proximity powers the LT3093, a 4.7F input capacitor suffices for stability. If a distantly located supply powers the LT3093, use a larger value input capacitor. Use a rough guideline of 1F (in addition to the 4.7F minimum) per 6" of wire length. The minimum input capacitance needed to stabilize the application also varies with the output capacitance as well as the load current. Placing additional capacitance on the LT3093's output helps. However, this requires significantly more capacitance compared to additional input bypassing. Series resistance between the supply and the LT3093 input also helps stabilize the application; as little as 0.1 to 0.5 suffices. This impedance dampens the LC tank circuit at the expense of dropout voltage. A better alternative is to use a higher ESR tantalum or electrolytic capacitor at the LT3093 input in parallel with a 4.7F ceramic capacitor. PSRR and Input Capacitance For applications utilizing the LT3093 for post-regulating switching converters, placing a capacitor directly at the LT3093 input results in AC current (at the switching frequency) to flow near the LT3093. This relatively high frequency switching current generates magnetic fields that couple to the LT3093 output, degrading the effective PSRR. While highly dependent on the PCB layout, the switching preregulator, the size of the input capacitor and other factors, the PSRR degradation can easily be over 30dB at 1MHz. This degradation is present even with the LT3093 desoldered from the board, it is a degradation in the PSRR of the PCB itself. While negligible for conventional low PSRR LDOs, the LT3093's ultrahigh PSRR requires careful attention to higher order parasitics in order to realize the full performance offered by the regulator. To mitigate the flow of high frequency switching current near the LT3093, the input capacitor can be entirely removed as long as the switching converter's output capacitor is located more than an inch away from Rev. 0 For more information www.analog.com LT3093 APPLICATIONS INFORMATION the LT3093. Magnetic coupling decreases rapidly with increasing distance. If the switching regulator is placed too far away (conservatively more than a couple inches) from the LT3093, the lack of an input capacitor presents a high impedance at the input of the LT3093 and oscillation may occur. It is generally a common (and preferred) practice to bypass regulator inputs with some capacitance, so this option is fairly limited in its scope and not the most palatable solution. To that end, ADI recommends referencing the LT3093 demo board layout for achieving the best possible PSRR performance. Two main factors contribute to higher PSRR with a poor layout. Parasitic trace inductance coupled with the low ESR ceramic input capacitor can lead to higher ripple at the input of the LDO than at the output of the driving supply. Also, physical loops create magnetic fields that couple from the input to the output. The LT3093 demo board utilizes layout techniques to minimize both parasitic inductance in traces and coupling of magnetic loops, preventing PSRR degradation while keeping the input capacitor. Filtering High Frequency Spikes For applications where the LT3093 is used to post-regulate a switching converter, its high PSRR effectively suppresses any harmonic content present at the switching frequency (typically 100kHz to 4MHz). However, there are very high frequency (hundreds of MHz) spikes associated with the switcher's power switch transition times that are beyond the LT3093's bandwidth and will almost directly pass through to the output. While the output capacitor is partly intended to absorb these spikes, its ESL will limit its ability at these frequencies. A ferrite bead or even the inductance associated with a short (e.g. 0.5") PCB trace coupled with a capacitor with a low impedance at the transition frequency can serve as an LC-filter to suppress these very high frequency spikes. Output Noise The LT3093 offers many advantages with respect to noise performance. Traditional linear regulators have several sources of noise. The most critical noise sources for a traditional regulator are its voltage reference, error amplifier, noise from the resistor divider network used for setting output voltage and the noise gain created by this resistor divider. Many low noise regulators pin out their voltage reference to allow for noise reduction by bypassing the reference voltage. Unlike most linear regulators, the LT3093 does not use a voltage reference; instead it uses a 100A current reference. The current reference operates with typical noise current level of 27pA/Hz (8nARMS over the 10Hz to 100kHz bandwidth). The resultant voltage noise equals the current noise multiplied by the resistor values, which is then RMS summed with the error amplifier's noise and the resistor's Johnson noise of 4kTR (k = Boltzmann's constant, 1.38 * 10-23 J/K, and T is absolute temperature) to give the net output noise. One problem faced by conventional linear regulators is that the resistor divider setting the output voltage gains up the reference noise. In contrast, the LT3093's unity-gain follower architecture presents no gain from the SET pin to the output. Therefore, using a capacitor to bypass the SET pin resistor allows output voltage noise to be independent of the programmed output voltage. The resultant output noise is then determined only by the error amplifier's noise, typically 2nV/Hz from 1kHz to 1MHz and 0.8VRMS in the 10Hz to 100kHz bandwidth when using a 4.7F SET pin capacitor. Paralleling multiple LT3093s further reduces noise by N for N parallel regulators. Refer to the Typical Performance Characteristics section for noise spectral density and RMS integrated noise performance over various load currents and SET pin capacitances. SET Pin (Bypass) Capacitance: Noise, PSRR, Transient Response and Soft-Start In addition to reducing output noise, using a SET pin bypass capacitor also improves PSRR and transient performance. Note that any bypass capacitor leakage deteriorates the LT3093's DC regulation. Capacitor leakage of as little as 100nA causes a 0.1% DC error. ADI recommends the use of a good quality low leakage ceramic capacitor. Using a SET pin bypass capacitor also soft starts the output and limits inrush current. The RC time constant formed by the SET pin resistor and capacitor determines Rev. 0 For more information www.analog.com 21 LT3093 APPLICATIONS INFORMATION soft-start time. Without the use of fast start-up, the rampup rate from 0 to 90% of nominal VOUT is: tSS 2.3 * RSET * CSET (Fast Start-Up Disabled) Fast Start-Up For ultralow noise applications that require low 1/f noise (i.e. at frequencies below 100Hz) a larger value SET pin capacitor is required; up to 22F may be used. While normally this would significantly increase the regulator's start-up time, the LT3093 incorporates fast start-up circuitry that increases the SET pin current to about 1.8mA during start-up. As shown in the Block Diagram, the 1.8mA current source remains engaged while PGFB is less than -300mV unless the regulator is in current limit, dropout, thermal shutdown, or input voltage is below the minimum VIN. If fast start-up capability is not used, tie PGFB to IN or to OUT (for output voltages more than -300mV). Note that doing so also disables power good functionality. ENABLE/UVLO The EN/UV pin is used to put the regulator into a micropower shutdown state. The LT3093 has an accurate -1.26V turn-on threshold on the EN/UV pin with 215mV of hysteresis. This threshold can be used in conjunction with a resistor divider from the input supply to define an accurate undervoltage lockout (UVLO) threshold for the regulator. The EN/UV pin current (IEN) at the threshold needs to be considered when calculating the resistor divider network. See the Electrical Characteristics table and Typical Performance curves for EN/UV pin characteristics. The EN/UV pin current can be ignored if REN1 is less than 100k. Use the following formula to determine resistor divider values (See Programming Undervoltage Lockout in the Typical Application section): VIN(UVLO) = -1.26V * (1 + REN2 / REN1) - IEN * REN2 Since the EN/UV pin is bidirectional, it can also be pulled above 1.26V to turn on the LT3093. In bipolar supply applications, the positive EN/UV threshold can be used to sequence the turn-on of the LT3093 after the positive regulator has turned on. If unused, tie the EN/UV pin to IN. 22 High Efficiency Linear Regulator--Input-to-Output Voltage Control The VIOC pin is used to control an upstream switching converter and facilitate a design solution that maximizes system efficiency while providing good transient response, low noise, and high power supply ripple rejection (PSRR) by maintaining a constant voltage across the LT3093 regardless of the device's output voltage. This works well in applications where the output voltage is varied for the application requirements. This regulation loop also minimizes total power dissipation in fault conditions; if the output is short-circuited and the LT3093 current limits, the VIOC amplifier lowers the switching regulator output voltage and limits the power dissipation in the LT3093. The VIOC pin is the output of a fast unity-gain amplifier that measures the voltage differential between IN and OUTS or -1.5V, whichever is lower. It typically connects to the feedback node or into the resistor divider of most LTC(R) switching regulators or LTM(R) power modules and sinks at least 100A of current. Targeting -1V differential from input-to-output provides an optimum tradeoff in terms of power dissipation and PSRR. The maximum output swing of the VIOC amplifier is limited only by the input voltage; it will provide an output all the way to maximum VIN. If paralleling multiple LT3093's, tie the VIOC pin of one of the devices to the upstream switching converter's feedback pin and float the remaining VIOC pins. The VIOC amplifier is designed to sink current, and only sources current through its internal impedance to ground. The VIOC pin has a typical impedance to ground of 120k 15%, this is important to consider if using a maximum input voltage configuration or if the LT3093 is disabled. As the VIOC buffer operates with high bandwidth, the switching converter's frequency compensation doesn't need to be adjusted while the VIOC buffer is inside the switching converter's feedback loop. Phase delay through the VIOC buffer is typically less than 4 for frequencies as high as 100kHz; within the switching converter's bandwidth (usually well below 100kHz) the VIOC buffer is transparent and acts like an ideal wire. For example, with a switching converter with less than 100kHz bandwidth and a phase margin of 50, using the VIOC buffer will Rev. 0 For more information www.analog.com LT3093 APPLICATIONS INFORMATION degrade the phase margin by at most 4. The net phase margin for the switching converter (using the VIOC pin) is at least 46. With the VIOC buffer inside the switching converter's feedback loop, keep the total capacitance on the VIOC pin to below 20pF. Typical VIOC Applications Figure 8 shows an application using the LT8330 configured as an inverting regulator powering the LT3093 to deliver a -3.3V output. The resistors shown drive the FBX pin of the LT8330 to -0.8V so that its output is -4.3V (with -1V on the VIOC pin) when the LT3093 is operating at -3.3V output and is -5V when the LT3093 is disabled. VIN V VIOC(NOM) 9.53k FBX LT3093 VIOC 3093 F08 38.3k Figure 8. VIOC Connection Using LT8330 Delivers -4.3V When Operating, -5V When LT3093 is Disabled In the event that the SET pin has an open-circuit fault condition, the LT3093's input voltage will increase to the switching converter's maximum output voltage and may violate the LT3093's absolute maximum rating for VIN. To prevent this, adding an optional resistor (R3) between the VIOC and IN pins of the regulator gives a maximum voltage configuration based on the following equation: V LDOIN(MAX ) = V FBSWITCHER 137k SW LT8330 V LDOIN - V LDOOUT = V VIOC(NOM) = R1+ R2 V FBSWITCHER * R1 IN * * For 0 VOUT -1.5V, VIN = VVIOC(NOM) - 1.5V. For VOUT -1.5V, VIN = VOUT + VVIOC(NOM). The VIOC pin voltage (and the input-to-output differential) is programmable to anywhere between -0.33V (the dropout voltage of the regulator) and the input voltage. As shown in Figure 7, the input-to-output differential is easily programmed using the following equation: R1+ R2 + R3 R1 IN * * Another inverting regulator configuration is shown in Figure 9, this time using the LT8580. The LT8580 FBX pin regulates at 3mV (typical) with 83.3A flowing out VIN 43.2k SW LT8580 LT3093 VIOC + 12.1k R3 3093 F09 FBX 120k Figure 9. VIOC Connection Using LT8580 LT3093 VIN IN VLDOIN SW UPSTREAM SWITCHING CONVERTER FB R3 (OPTIONAL) VFBSWITCHER R2 -1.5V OUT EN/UV + - - OUTS PGFB AV = 1 IN VLDOOUT: VARIABLE IOUT(MAX): -200mA 4.7F VIOC 120k R1 SET GND 3093 F07 4.7F Figure 7. Typical VIOC Application Rev. 0 For more information www.analog.com 23 LT3093 APPLICATIONS INFORMATION of the pin (IFBX). Because of this, only a single resistor is needed between the FBX pin and VIOC (from Figure 7, only R2 is necessary, R1 is not needed). In this case, the resistor is calculated as follows: VLDOIN - VLDOOUT = VVIOC(NOM) = VFBX - R2 * IFBX For the optional maximum voltage configuration, R3 is added and the maximum input voltage to the LT3093 is calculated as follows: V LDOIN(MAX ) = V VIOC(NOM) + R3 V VIOC(NOM) - R3 * IFBX 120k 0mA 200mA/DIV ILOAD VLDOIN 200mV/DIV VLDOOUT 50mV/DIV 3093 F11 200s/DIV RSET = 33.2k IL = -10mA TO -200mA Figure 11. Load Step Response Using the VIOC Buffer 0V Again, the resistors shown are configured to drive the output of the switcher to -4.3V when the LT3093 is operating at -3.3V output and -5V when disabled. Using the circuit from Figure 9, the LDO's input and output is shown in Figure 10 when pulsing the LT3093's EN/UV pin. As can be seen, when the LDO is disabled, the LDO input voltage goes to the maximum voltage set by the resistor divider on the VIOC pin. Figure 11 shows the load step response of the LT8580 using the VIOC buffer. Figure 12 shows the LDO's input and output voltage response to stepping the SET pin voltage from -3V to -4V. Figure 13 shows the LDO's input and output voltage while ramping the SET pin from 0V to -4.5V, and as can be seen, the LT8580's output voltage tracks the LT3093's output voltage when below -1.5V and limits at the maximum voltage set by the resistor divider set on the VIOC pin. Last, Figure 14 shows the noise spectral density at the LT3093's input and output. VSET AND VLDOOUT ARE OVERLAID 1V/DIV VLDOIN 3093 F12 500s/DIV VSET = -3V TO -4V IL = -200mA Figure 12. Stepping VSET from -3V to -4V (and Back to -3V) VSET AND VLDOOUT ARE OVERLAID 0V 1V/DIV VLDOIN 3093 F13 5ms/DIV IL = -200mA Figure 13. Ramping VSET from 0V to -4.5V (and Back to 0V) 10 0V 2V/DIV VLDOIN = -4.3V VLDOOUT = -3.3V IL = -200mA VLDOOUT NOISE (V/Hz) 1 VLDOIN 0V 2V/DIV VEN/UV RSET = 33.2k RL = 16.5 500ms/DIV LDOIN 0.1 0.01 3093 F10 LDOOUT NOISE FLOOR 0.001 Figure 10. LT3093 EN/UV Pulse 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 3093 F14 Figure 14. LT3093's Input and Output Noise Spectral Density 24 Rev. 0 For more information www.analog.com LT3093 APPLICATIONS INFORMATION Programmable Power Good As illustrated in the Block Diagram, power good threshold is user programmable using the ratio of two external resistors, RPG1 and RPG2: VOUT(PG_THRESH) = -0.3V(1 + RPG1/RPG2) - IPGFB * RPG1 If the PGFB pin becomes less than -300mV, the opencollector PG pin deasserts and becomes high impedance. The power good comparator typically has 7mV hysteresis and 5s of deglitching. The PGFB pin current (IPGFB) can be ignored if RPG2 is less than 30k, otherwise it must be considered when determining the resistor divider network. If power good functionality is not used, float the PG pin. Please note that programmable power good and fast start-up capabilities are disabled for output voltages between OV and -300mV. Take care when laying out traces for PG and PGFB on a PCB. If the PG and PGFB pins are run close to each other for a distance (typically greater than two inches), stray capacitance from trace-to-trace couples the PG signal into the high impedance PGFB signal. Since PG is out of phase relative to PGFB, this results in oscillation. To avoid this, minimize the distance the two traces run close to each other; lowering the impedance seen at the PGFB pin by using lower value resistors for the PGFB divider also helps. Externally Programmable Current Limit The ILIM pin internally regulates to -300mV. Connecting a resistor from ground to ILIM sets the current flowing into the ILIM pin, which in turn programs the LT3093's current limit. With the 1.95k * A programming scale factor, the current limit can be calculated as follows: Current Limit = 1.95k * A / RILIM For example, a 9.76k resistor programs the current limit to 200mA and a 15k resistor programs the current limit to 130mA. For good accuracy, Kelvin connect this resistor to the LT3093's GND pin. In cases where the IN-to-OUT differential is greater than 7V, the LT3093's foldback circuitry decreases the internal current limit. As a result, the internal current limit may override the externally programmed current limit to keep the LT3093 within its safe-operating-area (SOA). See the graph of Internal Current Limit vs Input-to-Output Differential in the Typical Performance Characteristics section. If not used, tie ILIM to GND. Output Overshoot Recovery During a load step from heavy load to very light or no load, the output voltage overshoots before the regulator responds to turn the power transistor off. With very light or no load, it takes a long time to discharge the output capacitor. The LT3093 incorporates an overshoot recovery circuit that turns on a current source to discharge the capacitor in the event that OUTS is higher than SET. This current is typically 1.8mA. If OUTS is externally held above SET, the current source turns on in an attempt to restore OUTS to its programmed voltage. The current source remains on until the external circuitry releases OUTS. Direct Paralleling for Higher Current Higher output current is obtained by paralleling multiple LT3093s. Tie all SET pins together and all IN pins together. Connect the OUT pins together using small pieces of PCB trace (used as a ballast resistor) to equalize currents in the LT3093s. PCB trace resistance in m/inch is shown in Table 2. Table 2. PC Board Trace Resistance WEIGHT (oz) 10mil WIDTH 20mil WIDTH 1 54.3 27.1 2 27.1 13.6 Trace resistance is measured in m/in. The small worst-case offset of 2mV for each paralleled LT3093 minimizes the required ballast resistor value. Figure 15 illustrates that two LT3093s, each using a 50m PCB trace ballast resistor, provide better than 20% accurate output current sharing at full load. The two 50m external resistors only add 10mV of output regulation drop with a 1A maximum current. With a -3.3V output, this only adds 0.3% to the regulation accuracy. As has been discussed previously, tie the OUTS pins directly to the output capacitors. Rev. 0 For more information www.analog.com 25 LT3093 APPLICATIONS INFORMATION 4.7F LT3093 16.5k SET PGFB 10F ILIM OUTS OUT + EN/UV VIN -5V 5% GND 4.7F 50m - 100A IN VOUT -3.3V IOUT(MAX) -400mA LT3093 SET PGFB GND ILIM OUT + EN/UV 4.7F OUTS 50m - 100A IN 3093 F15 PINS NOT USED IN THESE CIRCUITS: PG, VIOC Figure 15. Parallel Devices More than two LT3093s can also be paralleled for even higher output current and lower output noise. Paralleling multiple LT3093s is also useful for distributing heat on the PCB. For applications with high input-to-output voltage differential, an input series resistor or a resistor in parallel with the LT3093 can also be used to spread heat. PCB Layout Considerations Given the LT3093's high bandwidth and ultrahigh PSRR, careful PCB layout must be employed to achieve full device performance. Figure 16 shows a recommended layout that delivers full performance of the regulator. Refer to the LT3093's DC2952A demo board manual for further details. Thermal Considerations The LT3093 has internal power and thermal limiting circuits that protect the device under overload conditions. 26 The thermal shutdown temperature is nominally 167C with about 8C of hysteresis. For continuous normal load conditions, do not exceed the maximum junction temperature (125C for E- and I-grades, 150C for H-grade). It is important to consider all sources of thermal resistance from junction to ambient. This includes junction-to-case, case-to-heat sink interface, heat sink resistance or circuit board-to-ambient as the application dictates. Additionally, consider all heat sources in close proximity to the LT3093. The undersides of the DFN and MSOP packages have exposed metal from the lead frame to the die attachment. Both packages allow heat to directly transfer from the die junction to the PCB metal to limit maximum operating junction temperature. The dual-in-line pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of the PCB. Rev. 0 For more information www.analog.com LT3093 APPLICATIONS INFORMATION For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PCB and its copper traces. Copper board stiffeners and plated through-holes can also be used to spread the heat generated by the regulator. information on thermal resistance and high thermal conductivity test boards, refer to JEDEC standard JESD51, notably JESD51-7 and JESD51-12. Achieving low thermal resistance necessitates attention to detail and careful PCB layout. Table 3 and Table 4 list thermal resistance as a function of copper area on a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1oz solid internal planes and 2oz top/bottom planes with a total board thickness of 1.6mm. The four layers were electrically isolated with no thermal vias present. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. For more Table 3. Measured Thermal Resistance for DFN Package COPPER AREA TOP SIDE* BOTTOM SIDE BOARD AREA THERMAL RESISTANCE 2500mm2 2500mm2 2500mm2 34C/W 1000mm2 2500mm2 2500mm2 34C/W 225mm2 2500mm2 2500mm2 35C/W 100mm2 2500mm2 2500mm2 36C/W *Device is mounted on topside 3093 F16 Figure 16. Recommended DFN Layout Rev. 0 For more information www.analog.com 27 LT3093 APPLICATIONS INFORMATION Table 4. Measured Thermal Resistance for MSOP Package COPPER AREA TOP SIDE* BOTTOM SIDE BOARD AREA THERMAL RESISTANCE 2500mm2 2500mm2 2500mm2 33C/W 1000mm2 2500mm2 2500mm2 33C/W 225mm2 2500mm2 2500mm2 34C/W 100mm2 2500mm2 2500mm2 35C/W *Device is mounted on topside Calculating Junction Temperature Example: Given an output voltage of -3.3V and input voltage of -5V 5%, output current range from 1mA to 200mA, and a maximum ambient temperature of 85C, what is the maximum junction temperature? The LT3093's power dissipation is: IOUT(MAX) * (VIN(MAX) - VOUT) + IGND * VIN(MAX) where: IOUT(MAX) = -200mA VIN(MAX) = -5.25V IGND (at IOUT = 200mA and VIN = -5.25V) = -5.8mA thus: PDISS = -0.2A * (-5.25V + 3.3V) + 5.8mA * 5.25V = 0.42W Using a DFN package, the thermal resistance is in the range of 34C/W to 36C/W depending on the copper area. Therefore, the junction temperature rise above ambient approximately equals: 0.42W * 35C/W = 14.7C The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient: TJ(MAX) = 85C + 14.7C = 99.7C Overload Recovery Like many IC power regulators, the LT3093 incorporates safe-operating-area (SOA) protection. The SOA protection activates at input-to-output differential voltages greater than 7V. The SOA protection decreases the current limit 28 as the input-to-output differential increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltages up to the LT3093's absolute maximum ratings. The LT3093 provides some level of output current for all values of input-to-output differential voltage. Refer to the Current Limit curves in the Typical Performance Characteristics section. When power is first applied and input voltage rises, the output follows the input and keeps the input-to-output differential low to allow the regulator to supply large output current and start-up into high current loads. Due to current limit foldback, however, at high input voltages a problem can occur if the output voltage is low and the load current is high. Such situations occur after the removal of a short-circuit or if the EN/UV pin is pulled high after the input voltage has already turned on. The load line in such cases intersects the output current profile at two points. The regulator now has two stable operating points. With this double intersection, the input power supply may need to be cycled down to zero and brought back up again to make the output recover. Other linear regulators with foldback current limit protection (such as the LT3090, LT1964 and LT1175) also exhibit this phenomenon, so it is not unique to the LT3093. Protection Features The LT3093 incorporates several protection features for sensitive applications. Precision current limit and thermal overload protection safeguard the LT3093 against overload and fault conditions at the device's output. For normal operation, do not allow the junction temperature to exceed 125C (E- and I-grades) or 150C (H-grade). Pulling the LT3093's output above ground induces no damage to the part. If IN is left open circuit or grounded, OUT can be pulled 20V above GND. In this condition, a maximum current of 25mA flows into the OUT pin and out of the GND pin. If IN is powered by a voltage source, OUT sinks the LT3093's (foldback) short circuit current and protects itself by thermal limiting. In this case, however, grounding the EN/UV pin turns off the device and stops OUT from sinking the short-circuit current. Rev. 0 For more information www.analog.com LT3093 TYPICAL APPLICATION Programming Undervoltage Lookout 4.7F 110k V IN(UVLO)RISING = -1.26V * 1 49.9k | LT3093 33.2k 9.76k SET GND REN1 49.9k + EN/UV REN2 110k OUTS OUT 4.7F VOUT -3.3V IOUT(MAX) 200mA - PGFB 4.7F ILIM 100A VIN -4V TURN-ON -3.35V TURN-OFF IN 3093 TA02 PINS NOT USED IN THIS CIRCUIT: PG, VIOC Rev. 0 For more information www.analog.com 29 LT3093 PACKAGE DESCRIPTION DD Package 12-Lead Plastic DFN (3mm x 3mm) (Reference LTC DWG # 05-08-1725 Rev A) 0.70 0.05 3.50 0.05 2.10 0.05 2.38 0.05 1.65 0.05 PACKAGE OUTLINE 0.25 0.05 0.45 BSC 2.25 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3.00 0.10 (4 SIDES) R = 0.115 TYP 7 0.40 0.10 12 2.38 0.10 1.65 0.10 PIN 1 NOTCH R = 0.20 OR 0.25 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 6 0.200 REF 1 0.23 0.05 0.45 BSC 0.75 0.05 2.25 REF 0.00 - 0.05 (DD12) DFN 0106 REV A BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD AND TIE BARS SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 30 Rev. 0 For more information www.analog.com LT3093 PACKAGE DESCRIPTION MSE Package 12-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1666 Rev G) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 0.102 (.112 .004) 5.10 (.201) MIN 2.845 0.102 (.112 .004) 0.889 0.127 (.035 .005) 6 1 1.651 0.102 (.065 .004) 1.651 0.102 3.20 - 3.45 (.065 .004) (.126 - .136) 12 0.65 0.42 0.038 (.0256) (.0165 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 4.039 0.102 (.159 .004) (NOTE 3) 0.12 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 7 NO MEASUREMENT PURPOSE 0.406 0.076 (.016 .003) REF 12 11 10 9 8 7 DETAIL "A" 0 - 6 TYP 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 1 2 3 4 5 6 0.650 (.0256) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MSE12) 0213 REV G Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications moreby information www.analog.com subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. 31 LT3093 TYPICAL APPLICATION Parallel Devices 4.7F LT3093 16.5k SET GND ILIM + PGFB 10F VIN -5V 5% EN/UV OUTS 4.7F OUT 50m - 100A IN LT3093 VOUT -3.3V IOUT(MAX) -400mA SET GND + PGFB EN/UV ILIM OUTS 4.7F OUT 50m - 100A IN 3093 TA03 PINS NOT USED IN THIS CIRCUIT: PG, VIOC RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT3094 -20V, 500mA, Ultralow Noise Ultrahigh PSRR Negative Linear Regulator 0.8VRMS Noise and 74dB PSRR at 1MHz, VIN = -1.8V to -20V, 235mV Dropout Voltage, Programmable Current Limit and Power Good, 3mm x 3mm DFN and MSOP Packages LT3045 20V, 500mA, Ultralow Noise Ultrahigh PSRR Linear Regulator 0.8VRMS Noise and 75dB PSRR at 1MHz, VIN = 1.8V to 20V, 260mV Dropout Voltage, 3mm x 3mm DFN and MSOP Packages LT3042 20V, 200mA, Ultralow Noise Ultrahigh PSRR Linear Regulator 0.8VRMS Noise and 79dB PSRR at 1MHz, VIN = 1.8V to 20V, 350mV Dropout Voltage, Programmable Current Limit and Power Good, 3mm x 3mm DFN and MSOP Packages LT3090 -36V, 600mA Negative Linear Regulator with Programmable Current Limit 300mV Dropout Voltage, Low Noise: 18VRMS, VIN: -1.5V to -36V, Single Resistor Output, DFN and MSOP Packages LT3091 -36V, 1.5A Negative Linear Regulator 300mV Dropout Voltage, Low Noise: 18VRMS, VIN: -1.5V to -36V, Single Resistor Output, DFN, TSSOP, TO-220 and DD-Pak Packages LT1175 500mA, Negative Low Dropout Micropower Regulator 500mV Dropout Voltage, VIN = -4.5V to -20V, N8, S8, DD-PAK, TO-220 and SOT-223 Packages LT1964 200mA, Negative Low Noise Low Dropout Regulator 340mV Dropout Voltage, Low Noise: 30VRMS, VIN = -1.9V to -20V, DFN and SOT-23 Packages LT3015 1.5A, Fast Transient Response, Negative LDO Regulator 310mV Dropout Voltage, Low Noise: 60VRMS, VIN = -2.3V to -30V, DFN, MSOP, TO-220 and DD-PAK Packages LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 350mV Dropout Voltage (2-Supply Operation), Low Noise: 40VRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN, MSOP, TO-220, DD and SOT-223 Packages LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40VRMS, VIN: 1.2V to 36V, Single Resistor Output, DFN and MSOP Packages 32 Rev. 0 05/19 For more information www.analog.com www.analog.com ANALOG DEVICES, INC. 2019