X1228S14IZ-4.5AT1 - Intersil Corporation

FN8100.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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All other trademarks mentioned are the property of their respective owners.

X1228

4K (512 x 8), 2-Wire™ RTC

Real Time Clock/Calendar/CPU

Supervisor with EEPROM

FEATURES

• Real Time Clock/Calendar

—Tracks time in Hours, Minutes, and Seconds

—Day of the Week, Day, Month, and Year

• 2 Polled Alarms (Non-volatile)

—Settable on the Second, Minute, Hour, Day of the

Week, Day, or Month

—Repeat Mode (periodic interrupts)

• Oscillator Compensation on chip

—Internal feedback resistor and compensation

capacitors

—64 position Digitally Controlled Trim Capacitor

—6 digital frequency adjustment settings to

±30ppm

• CPU Supervisor Functions

—Power-on Reset, Low Voltage Sense

—Watchdog Timer (SW Selectable: 0.25s, 0.75s,

1.75s, off)

• Battery Switch or Super Cap Input

• 512 x 8 Bits of EEPROM

—64-Byte Page Write Mode

—8 modes of Block Lock™ Protection

—Single Byte Write Capability

• High Reliability

—Data Retention: 100 years

—Endurance: 100,000 cycles per byte

• 2-Wire™ Interface interoperable with I2C*

—400kHz data transfer rate

• Frequency Output (SW Selectable: Off, 1Hz,

4096Hz, or 32.768kHz)

•Low Power CMOS

—1.25µA Operating Current (Typical)

• Small Package Options

—14 Ld SOIC and 14 Ld TSSOP

• Repetitive Alarms

• Temperature Compensation

• Pb-Free Plus Anneal Available (RoHS Compliant)

APPLICATIONS

• Utility Meters

• HVAC Equipmen t

• Audio/Video Components

• Set Top Box/Television

•Modems

• Network Routers, Hubs, Switches, Bridges

• Cellular Infrastructure Equipment

• Fixed Broadband Wireless Equipment

• Pagers/PDA

• POS Equipment

• Test Meters/Fixtures

• Offic e Automation (Copiers, Fax)

• Home Appliances

• Computer Products

• Other Industrial/Medical/Automotive

BLOCK DIAGRAM

X2 Oscillator Frequency Timer

Logic

Divider Calendar

Control/

Registers

1Hz Time

Keeping

Registers

Alarm Regs

Compare

Mask

RESET

Control

Decode

Logic Alarm

(EEPROM)

SCL

SDA

Serial

Interface

Decoder

EEPROM

ARRAY

Watchdog

Timer Low Voltage

Reset

Registers

Status

(SRAM)

Select

PHZ/IRQ

BACK

32.768kHz

(SRAM)

Battery

Circuitry

Switch

OSC Compensation

Data Sheet October 17, 2005

2FN8100.2

October 17, 2005

Ordering Information

PART NUMBER PART MARKING

VCC RANGE

(V) VTRIP

TEMP RANGE

(°C) PACKAGE

X1228S14-4.5A X1228S AL 2.7 to 5.5 4.63V ± 112mV 0 to 70 14 Ld SOIC

X1228S14Z-4.5A (Note) X1228S Z AL 0 to 70 14 Ld SOIC (Pb-free)

X1228S14I-4.5A X1228S AM -40 to 85 14 Ld SOIC

X1228S14IZ-4.5A (Note) X1228S Z AM -40 to 85 14 Ld SOIC (Pb-free)

X1228V14-4.5A X1228V AL 0 to 70 14 Ld TSSOP

X1228V14Z-4.5A (Note) X1228V Z AL 0 to 70 14 Ld TSSOP (Pb-free)

X1228V14I-4.5A X1228V AM -40 to 85 14 Ld TSSOP

X1228V14IZ-4.5A (Note) X1228V Z AM -40 to 85 14 Ld TSSOP (Pb-free)

X1228S14 X1228S 4.38V ± 112mV 0 to 70 14 Ld SOIC

X1228S14Z (Note) X1228S Z 0 to 70 14 Ld SOIC (Pb-free)

X1228S14I X1228S I -40 to 85 14 Ld SOIC

X1228S14IZ (Note) X1228S Z I -40 to 85 14 Ld SOIC (Pb-free)

X1228V14 X1228V 0 to 70 14 Ld TSSOP

X1228V14Z (Note) X1228V Z 0 to 70 14 Ld TSSOP (Pb-free)

X1228V14I X1228V I -40 to 85 14 Ld TSSOP

X1228V14IZ (Note) X1228V Z I -40 to 85 14 Ld TSSOP (Pb-free)

X1228S14-2.7A X1228S AN 2.85V ± 100mV 0 to 70 14 Ld SOIC

X1228S14Z-2.7A (Note) X1228S Z AN 0 to 70 14 Ld SOIC (Pb-free)

X1228S14I-2.7A X1228S AP -40 to 85 14 Ld SOIC

X1228S14IZ-2.7A (Note) X1228S Z AP -40 to 85 14 Ld SOIC (Pb_free)

X1228V14-2.7A X1228V AN 0 to 70 14 Ld TSSOP

X1228V14Z-2.7A (Note) X1228V Z AN 0 to 70 14 Ld TSSOP (Pb-free)

X1228V14I-2.7A X1228V AP -40 to 85 14 Ld TSSOP

X1228V14IZ-2.7A (Note) X1228V Z AP -40 to 85 14 Ld TSSOP (Pb-free)

X1228S14-2.7* X1228S F 2.65V ± 100mV 0 to 70 14 Ld SOIC

X1228S14Z-2.7* (Note) X1228S Z F 0 to 70 14 Ld SOIC (Pb-free)

X1228S14I-2.7 X1228S G -40 to 85 14 Ld SOIC

X1228S14IZ-2.7 (Note) X1228S Z G -40 to 85 14 Ld SOIC (Pb-free)

X1228V14-2.7 X1228V F 0 to 70 14 Ld TSSOP

X1228V14Z-2.7 (Note) X1228V Z F 0 to 70 14 Ld TSSOP (Pb-free)

X1228V14I-2.7 X1228V G -40 to 85 14 Ld TSSOP

X1228V14IZ-2.7 (Note) X1228V Z G -40 to 85 14 Ld TSSOP (Pb-free)

*Add "T1" suffix for tape and reel.

Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

X1228

3FN8100.2

October 17, 2005

PIN DESCRIPTIONS

PIN ASSIGNMENTS

Pin Number

SOIC/TSSOP Symbol Brief Description

1X1X1. The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal

is used with the X1228 to supply a timebase for the real time clock. The reco mmended crystal

is a Citizen CFS206-32.768KDZF. Internal compensatio n circuitry is included to fo rm a

complete oscillator circuit. Care should be taken in the placement of the crystal and the layout

of the circuit. Plenty of grou nd plane aroun d the device and short traces to X1 are highly

recommended. See Application se ction for more recommenda tions.

2X2X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal

is used with the X1228 to supply a timebase for the real time clock. The reco mmended crystal

is a Citizen CFS206-32.768KDZF. Internal compensatio n circuitry is included to fo rm a

complete oscillator circuit. Care should be taken in the placement of the crystal and the layout

of the circuit. Plenty of grou nd plane aroun d the device and short traces to X2 are highly

recommended. See Application se ction for more recommenda tions.

6 RESET RESET Output – RESET. This is a reset signal output. This signal notifies a host

processor that the watchdog time period has expired or that the voltage has dropped below

a fixed VTRIP threshold. It is an open drain active LOW output. Recommended value for the

pullup resistor is 5kΩ. If unused, tie to ground.

SS VSS.

8SDASerial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the

device. It has an open drain output and may be wire ORed with other open drain or open

collector outputs. The input buffer is always active (not gated).

An open drain output requires the use of a pull-up resistor. The output circuitry controls the

fall time of the output signal with the use of a slope controlled pull-down. The circuit is

designed for 400kHz 2-wire interface speeds.

9SCLSerial Clock (SCL). The SCL input is used to clock all data into and out of the device. The

input buffer on this pin is always active (not gated).

12 PHZ/IRQ Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from the

internal oscillator or an interrupt signal output. It is a CMOS output.

When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz

or inactive.

When used as interrupt output, this signal notifies a host processor that an alarm has

occurred and an action is required. It is an active LOW output.

The control bits for this function are FO1 and FO0 and are found in address 0011h of the

Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on

page 14.

13 VBACK VBACK. This input provides a backup supply voltage to the device. VBACK supplies power

to the device in the event the VCC supply fails. This pin can be connected to a battery, a

Supercap or tied to ground if not used.

14 VCC VCC.

NC = No internal connection

X2 1

14 Ld TSSOP/SOIC

RESET

BACK

PHZ/IRQ

SCL

SDA

X1228

4FN8100.2

October 17, 2005

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias...................-65°C to +135°C

Storage Temperature........................-65°C to +150°C

Voltage on VCC, VBACK and PHZ/IRQ

pin (respect to ground) ............................-0.5V to 7.0V

Voltage on SCL, SDA, X1 and X2

pin (respect to ground) ...............-0.5V to 7.0V or 0.5V

above VCC or VBACK (whi chever is higher)

DC Output Current ..............................................5 mA

Lead Temperature (Soldering, 10 sec).............. 300°C

Stresses above those listed under “Absolute Maximu m

Ratings” may cause permanent damage to the device.

This is a stress rating only and the functio nal operation

of the device at these or any other conditions above

those indicated in the operational sections of this

specification is not implied. Exposure to absolute ma x-

imum rating conditions for extended periods may

affect device reliability.

DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)

OPERATING CHARACTERISTICS

Symbol Parameter Conditions Min Typ Max Unit Notes

VCC Main Power Supply 2.7 5.5 V

VBACK Backup Power Supply 1.8 5.5 V

VCB Switch to Backup Supply VBACK -0.2 VBACK -0.1 V

VBC Switch to Main Supply VBACK VBACK +0.2 V

Symbol Parameter Conditions Min Typ Max Unit Notes

ICC1 Read Active Supply

Current VCC = 2.7V 400 µA 1, 5, 7, 14

VCC = 5.0V 800 µA

ICC2 Program Supply Current

(nonvolatile) VCC = 2.7V 2.5 mA 2, 5, 7, 14

VCC = 5.0V 3.0 mA

ICC3 Main Timekeeping

Current VCC = 2.7V 10 µA 3, 7, 8, 14, 15

VCC = 5.0V 20 µA

IBACK

Timekeeping Current –

(Low Voltage Sense and

Watchdog Timer

disabled

VBACK = 1.8V 1.25 µA 3, 6, 9, 14, 15

“See Perfor-

mance Data”

VBACK = 3.3V 1.5 µA

ILI Input Leakage Current 10 µA 10

ILO Output Leakage Current 10 µA 10

VIL Input LOW Voltage -0.5 VCC x 0.2 or

VBACK x 0.2 V13

VIH Input HIGH Voltage VCC x 0.7 or

VBACK x 0.7 VCC + 0.5 or

VBACK + 0.5 V13

VHYS Schmitt Trigger Input

Hysteresis VCC related level .05 x VCC or

.05 x VBACK V13

VOL1 Output LOW Voltage for

SDA and RESET VCC = 2.7V 0.4 V11

VCC = 5.5V 0.4

VOL2 Output LOW Voltage for

PHZ/IRQ VCC = 2.7V VCC x 0.3 V11

VCC = 5.5V VCC x 0.3

VOH2 Output HIGH Voltage for

PHZ/IRQ VCC = 2.7V VCC x 0.7 V12

VCC = 5.5V VCC x 0.7

X1228

5FN8100.2

October 17, 2005

Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address

Byte are incorrect or until 200nS after a stop ending a read or write operation.

(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.

(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiat e a nonvolatile write cycle; tWC a fter a stop

that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave

Address Byte.

(4) For reference only and not tested.

(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz

(6) VCC = 0V

(7) VBACK = 0V

(8) VSDA = VSCL=VCC, Others = GND or VCC

(9) VSDA =VSCL=VBACK, Others = GND or VBACK

(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = VCC or GND

(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V

(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V

(13) Threshold voltages based on the higher of Vcc or Vback.

(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).

(15) Typical values are for TA = 25°C

Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V

Notes: (1) This parameter is not 100% tested.

(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers

AC CHARACTERISTICS

AC Test Conditions

Figure 18. Standard Output Load for testing the device with VCC = 5.0V

Symbol Parameter Max. Units Test Conditions

COUT(1) Output Capacitance (SDA, PHZ/IRQ, RESET)10pF V

OUT = 0V

CIN(1) Input Capacitance (SCL) 10 pF VIN = 0V

Input Pulse Levels VCC x 0.1 to VCC x 0.9

Input Rise and Fall Times 10ns

Input and Output Timing

Levels VCC x 0.5

Output Load Standard Output Load

SDA

1533Ω

100pF

5.0V

For VOL= 0.4V

and IOL = 3 mA

Equivalent AC Output Load Circuit for VCC = 5V

1316Ω

5.0V

PHZ/IRQ

100pF

806Ω

X1228

6FN8100.2

October 17, 2005

AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)

Notes: (1) This parameter is not 100% tested.

(2) Cb = total capacitance of one bus line in pF.

TIMING DIAGRAMS

Bus Timing

Symbol Parameter Min. Max. Units

fSCL SCL Clock Frequency 400 kHz

tIN Pulse width Suppression Time at inputs 50(1) ns

tAA SCL LOW to SDA Data Out Valid 0.1 0.9 µs

tBUF Time the bus must be free before a new transmission can start 1.3 µs

tLOW Clock LOW Time 1.3 µs

tHIGH Clock HIGH Time 0.6 µs

tSU:STA Start Condition Setup Time 0.6 µs

tHD:STA Start Condition Hold Time 0.6 µs

tSU:DAT Data In Setup Time 100 ns

tHD:DAT Data In Hold Time 0 µs

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Output Hold Time 50 ns

tRSDA and SCL Rise Time 20 +.1Cb(2) 300 ns

tFSDA and SCL Fall Time 20 +.1Cb(2) 300 ns

Cb Capacitive load for each bus line 400 pF

tSU:STO

tDH

tHIGH

tSU:STA tHD:STA tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tFtLOW

tBUF

tAA

X1228

7FN8100.2

October 17, 2005

Write Cycle Timing

Power-up Timing

Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.

VCC slew rate should be between 0.2mV/µsec and 50mV/µsec.

(2) Typical values are for TA = 25°C and VCC = 5.0V

Nonvolatile Write Cycle Timing

Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is

the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.

WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS

Watchdog/Low Voltage Reset Parameters (Se eFigures 3 and 4)

SCL

SDA

tWC

8th Bit of Last Byte ACK

Stop

Condition Start

Condition

Symbol Parameter Min. Typ.(2) Max. Units

tPUR(1) Time from Power-up to Read 1 ms

tPUW(1) Time from Power-up to Write 5 ms

Symbol Parameter Min. Typ.(1) Max. Units

tWC(1) Write Cycle Time 5 10 ms

Symbols Parameters Min. Typ. Max. Unit

VPTRIP

Programmed Reset Trip Voltage

X1228-4.5A

X1228

X1228-2.7A

X1228-2.7

4.50

4.25

2.75

2.55

4.63

4.38

2.85

2.65

4.75

4.50

2.95

2.75

tRPD VCC Detect to RESET LOW 500 ns

tPURST Power-up Reset Time-out Delay 100 250 400 ms

tFVCC Fall Time 10 µs

tRVCC Rise Time 10 µs

tWDO Watchdog Timer Period (Crystal = 32.768kHz):

WD1 = 0, WD0 = 0

WD1 = 0, WD0 = 1

WD1 = 1, WD0 = 0

1.7

725

225

1.75

750

250

1.8

775

275

tRST Watchdog Reset Time-out Delay (Crystal=32.768 kHz) 225 250 275 ms

tRSP 2-Wire interface 1 µs

VRVALID Reset Valid VCC 1.0 V

X1228

8FN8100.2

October 17, 2005

VTRIP Programming Timing Diagram

VTRIP Programming Parameters

Parameter Description Min. Max. Units

tVPS VTRIP Program Enable Voltage Setup time 1 µs

tVPH VTRIP Program Enable Voltage Hold time 1 µs

tTSU VTRIP Setup time 1 µs

tTHD VTRIP Hold (stable) time 10 ms

tVPO VTRIP Program Enable Voltage Off time

(Between successive adjustments) 0µs

tRP VTRIP Program Recovery Period

(Between successive adjustments) 10 ms

VPProgramming Voltage 14 16 V

VTRAN VTRIP Programmed Voltage Range 1.7 5.0 V

Vtv VTRIP Program variation after programming

(Programmed at 25°C) -25 +25 mV

VTRIP programming parameters are not 100% Tested.

01234567 01234567 01234567 01234567

VCC

(VTRIP)

tVPH

tVPS tVPO

tRP

SCL

SDA

AEh 03h/01h

RESET VP = 15V

00h00h

VCC

tTSU tTHD

VTRIP

X1228

9FN8100.2

October 17, 2005

DESCRIPTION

The X1228 device is a Real Time Clock with

clock/calendar, two polled alarms with integrated 512x8

EEPROM, oscillator compensation, CPU Supervisor

(POR/LVS and WDT) and battery backup switch.

The oscillator uses an external, low-cost 32.768kHz

crystal. All compensation and trim components are

integrated on the chip. This eli minates several external

discrete components and a trim capacitor, saving

board area and component cost.

The Real-Time Clock keeps track of time with

separate registers for Hours, Minutes, Seconds. The

Calendar has separa te reg iste rs for Date , Mo nth, Year

and Day-of-week. The calendar is correct through

2099, with au tomatic leap year corr ection.

The powerful Dual Alarms can be set to any

Clock/Calendar value for a match. For instance, every

minute, ever y Tuesday, or 5:23 AM on March 21. The

alarms can be polled in the Status Register or provide

a hardware interrupt (IRQ Pin). There is a repeat

mode for the alarms allowing a periodic interru pt.

The PHZ/IRQ pin may be s of twa re s ele cte d t o pr ov ide

a frequency ou tput of 1 Hz, 4096 Hz, o r 32,768 Hz.

The X1228 device integrates CPU Supervisor func-

tions and a Battery Switch. Ther e is a Power-On Reset

(RESET output) with typically 250 ms delay from

power-on. It will also assert RESET when Vcc goes

below the specified threshold. The Vtrip threshold is

user repro-grammable. There is a WatchDog Timer

(WDT) with 3 selectable time-out periods (0.25s,

0.75s, 1.75s) and a disabled setting. The watchdog

activates the RESET pin when it expires.

The device offers a backup power input pin. This

VBACK pin allows the device to be backed up by

battery or SuperCap. The entire X1228 device is fully

operational from 2.7 to 5.5 volts and the

clock/calendar portion of the X1228 device remains

fully operational down to 1.8 volts (Standby M ode).

The X1228 device provides 4K bits of EEPROM with 8

modes of BlockLock™ control. The BlockLock allows a

safe, secure memor y for critical user and con figuration

data, while allowing a large user storage area.

PIN DESCRIPTIONS

Serial Clock (SCL)

The SCL input is used to clock all data into and out of

the device. The input b uffer on this p in is always active

(not gated).

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into

and out of the device. It has an open drain output and

may be wire ORed with other open drain or open col-

lector outputs. The input buffer is always active (not

gated).

An open drain output requires the use of a pull-up

resistor. The output circuitry controls the fall time of

the output signal with the use of a slope controlled

pull-down. The circuit is designed for 400kHz 2-wire

interface speeds.

VBACK

This input provides a backup supply voltage to the

device. VBACK supplies power to the device in the

event the VCC supply fails. This pin can be connected

to a battery, a Supe rcap or tied to ground if not used.

RESET Output – RESET

This is a reset signal output. This signal notifies a host

processor that the watchdog time period has expired or

that the voltage has dropped below a fixed VTRIP thresh-

old. It is an open drain active LOW output. Recom-

mended value for the pullup resistor is 5kΩ. If unused, tie

to ground.

Programmable Frequ ency/Interrupt Out put – PHZ/IRQ

This is either an output from the internal oscillator or an

interrupt signal output. It is a CMOS output.

When used as frequency output, this signal has a fre-

quency of 32.768kHz, 4096Hz, 1Hz or inactive.

When used as interrupt output, this signal notifies a

host processor that an alarm has occurred and an

action is required. It is an active LOW output.

The control bits for this function are FO1 and FO0 and

are found in address 00 11h of the Clo ck Contro l Mem-

ory map. See “Programmable Frequency Output

Bits—FO1, FO0” on page 14.

NC = No internal connection

X1228

X2 1

14-Pin TSSOP/SOIC

RESET

VSS

VCC

VBACK

PHZ/IRQ

SCL

SDA

X1228

10 FN8100.2

October 17, 2005

X1, X2

The X1 and X2 pins are the input and output,

respectively, of an inverting amplifier. An external

32.768kHz quartz crystal is used with the X1228 to

supply a timebase for the real time clock. The

recommended crystal is a Citizen CFS206-32.768KDZF.

Internal compensation circuitry is included to form a

complete oscillator circuit. Care should be taken in the

placement of the crystal and the layout of the circuit.

Plenty of ground plane around the device and short

traces to X1 and X2 are highly recommended. See

Application section for more recommendations.

Figure 1. Recommended Crystal connection

POWER CONTROL OPERATION

The power control circuit accepts a VCC and a VBACK

input. The power control circuit power the clock from

VBACK when VCC < VBACK - 0.2V. It will switch back to

power the device from VCC when VCC exceeds VBACK.

Figure 2. Power Control

REAL TIME CLOCK OPERATION

The Real Time Clock (RTC) uses an external

32.768kHz quartz crystal to maintain an accurate inter-

nal representation of the second, minute, hour, day,

date, month, and year. The RTC has leap-year correc-

tion. The clock also corrects for months having fewer

than 31 days and has a bit that controls 24 hour or

AM/PM format. When the X1228 powers up after the

loss of both VCC and VBACK, the clock will not operate

until at least one byte is written to the clock register.

Reading the Real T ime Cloc k

The RTC is read by initiating a Read command and

specifying the address corresponding to the register of

the Real Time Clock. The RTC Registers can then be

read in a Sequential Read Mode. Since the clock runs

continuously and a read takes a finite amount of time,

there is the possibility that the clock could change during

the course of a read op eration. In th is device, the time is

latched by the read command (falling edge of the clock

on the ACK bit prior to RTC data output) into a separate

latch to avoid time changes during the read operation.

The clock continues to run. Alarms occurring during a

read are unaffected by the read operation.

Writing to the Real Time Clock

The time and date may be set by writing to the RTC

registers. To avoid changing the current time by an

uncompleted write operation, the current time value is

loaded into a separate buffer at the falling ed ge of the

clock on the ACK bit before the RTC data input bytes,

the clock continues to run. The new serial input data

replaces the values in the buffer. This new RTC value

is loaded back into the RTC Register by a stop bit at

the end of a valid write sequence. An invalid write

operation aborts the time update procedure and the

contents o f the buffer ar e dis car d ed . After a valid write

operation the RTC will reflect the newly loaded data

beginning w ith the next “o ne second” clock cy cle after

the stop bit is written. The RTC continues to update

the time while an RTC register write is in progress and

the RTC continues to run during any nonvolatile write

sequences. A single byte may be written to the RTC

without affecting the othe r bytes.

Accuracy of the Real Time Clock

The accuracy of the Real Time Clock depends on the

frequency of the quartz crystal that is used as the time

base for the RTC. Since the resonant frequency of a

crystal is temperature dependent, the RTC perfor-

mance will also be dependent upon temperature. The

frequency deviation of the crystal is a fuction of the

turnover temperature of the crystal from the crystal’s

nominal frequency. For example, a >20ppm frequency

deviation translates into an accuracy of >1 minute per

month. These parameters are available from the

crystal manufacturer. Intersil’s RTC family provides

on-chip crystal compensation networks to adjust load-

capacitance to tune oscillator frequency from +116

ppm to -37 ppm when u sing a 12.5 pF loa d crystal.

For

more detail information see the App lication section.

VBACK In

Voltage

VCC

Off

X1228

11 FN8100.2

October 17, 2005

CLOCK/CONTROL REGISTERS (CCR)

The Control/Clock Registers are located in an area

separate from the EEPROM array and are only

accessible following a slave byte of “1101111x” and

reads or writes to addresses [0000h:003Fh]. The

clock/control memory map has memory addresses

from 0000h to 003Fh. The defined addresses are

described in the Table 1. Writing to and reading from

the undefined addresses are not recommended.

CCR access

The contents of the CCR can be modified by perform-

ing a byte or a page write operation directly to any

address in the CCR. Prior to writing to the CCR

(except the status register), however, the WEL and

RWEL bits must be set using a two step process (See

section “Writing to the Clock/Control Registers.”)

The CCR is divided into 5 sections. Th ese are:

1. Alarm 0 (8 bytes; non-volatile)

2. Alarm 1 (8 bytes; non-volatile)

3. Control (4 bytes; non-volatile)

4. Real Time Clock (8 bytes; volatile)

5. Status (1 byte; volatile)

Each register is read and written through buffers. The

non-volatile portion (or the counter portion of the RTC) is

updated only if RWEL is set and only after a valid write

operation and stop bit. A sequential read or page write

operation provides access to the contents of only one

section of the CCR per operation. Access to another sec-

tion requires a new operation. Continued reads or writes,

once reaching the end of a section, will wrap around to

the start of the section. A read or write can begin at any

address in the CCR.

It is not necessary to set the RWEL bit prior to writing

the status register. Section 5 supports a single byte

read or write only. Continued reads or writes from this

section terminates the oper ation.

The state of the CCR can be read by performing a ran-

dom read at any address in the CCR at any time. This

returns the contents of that re gister location. Additiona l

registers are read by performing a sequential read.

The read instruction latches all Clock registers into a

buffer, so an update of the clock does not change the

time being read. A sequential read of the CCR will not

result in the output of data from the memory array. At

the end of a read, the master supplies a stop condition

to end the operation and free the bus. After a read of

the CCR, the address remains at the previous address

+1 so the user can execute a current address read of

the CCR and continu e reading the next Re gister.

ALARM REGISTERS

There are two alarm registers whose contents mimic

the contents of the RTC register, but add enable bits

and exclude the 24 hour time selection bit. The enable

bits specify which registers to use in the comparison

between the Alarm and Real Time Registers. For

example:

– Setting the Enable Month bit (EMOn*) bit in combi-

nation with other ena ble bits and a specific alarm

time, the user can establish an alarm that triggers at

the same time once a year.

*n = 0 for Al arm 0: N = 1 for Alarm 1

Table 1. Clock/Control Memory Map

Addr. Type Reg

Name

Bit

Range

Default

76543210 (optional)

003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h

0037 RTC

(SRAM)

Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 19/20 20h

0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h

0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h

0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h

0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h

0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h

0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h

0013 Control

(EEPROM)

DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h

0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h

0011 INT IM AL1E AL0E FO1 FO0 x x x 00h

0010 BL BP2 BP1 BP0 WD1 WD0 0 0 0 18h

X1228

12 FN8100.2

October 17, 2005

When there is a match, an alar m flag is set. The occur-

rence of an alarm can be determined by polling the

AL0 and AL1 bits or by enabling the IRQ output, using

it as hardware flag.

The alarm enable bits are located in the MSB of the

particular register. When all enable bits are set to ‘0’,

there are no alarms.

– The user can set the X1 228 to alar m ever y We dnes-

day at 8:00 AM by setting the EDWn *, the EH Rn*

and EMNn* enab le bits to ‘1’ and setting the DWAn*,

HRAn* and MNAn* Alarm registers to 8:00 AM

Wednesday.

– A daily ala rm for 9:30PM results when the EHRn*

and EMNn* enable bits are set to ‘1’ and the HRAn*

and MNAn* registers are set to 9:30 PM.

*n = 0 for Alarm 0 : N = 1 for Ala rm 1

REAL TIME CLOCK REGISTERS

Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)

These registers depict BCD representations of the

time. As such, SC (Seconds) and MN (Minutes) range

from 00 to 59, HR (Hour) is 1 to 12 with a n AM or PM

indicator (H21 b it) or 0 to 23 (with M IL=1), DT (D ate) is

1 to 31, MO (Month) i s 1 to 12, YR (Yea r) is 0 to 99.

Date of the Week Register (DW)

This register provides a Day of the Week status and

uses three bits DY2 to DY0 to represent the seven

days of the week. The counter advances in the cycle

0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical

value to a specific day of the week is arbitrar y and may

be decided by the system software designer. The

default value is defined as ‘0’.

24 Hour Time

If the MIL bit of the HR register is 1, the RTC uses a

24-hour format. If the MIL bit is 0, the RTC uses a 12-

hour format and H21 bit functions as an AM/PM indi-

cator with a ‘1’ representing PM. The clock defaults to

standard time with H21 = 0.

Leap Years

Leap years add the day February 29 and are defined

as those years that are divisible by 4. Years divisible

by 100 are not le ap years, unless they are a lso divisi-

ble by 400. This means that the year 2000 is a leap

year, the year 2100 is not. The X1228 does not correct

for the leap year in the year 2100.

000F Alarm1

(EEPROM)

Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 19/20 20h

000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h

000D YRA1 Unused - Default = RTC Year value (No EEPROM) - Future expansion

000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h

000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h

000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h

0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h

0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h

0007 Alarm0

(EEPROM)

Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h

0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h

0005 YRA0 Unused - Default = RTC Year value (No EEPROM) - Future expansion

0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h

0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h

0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h

0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h

0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h

Table 1. Clock/Control Memory Map (Continued)

Addr. Type Reg

Name

Bit

Range

Default

76543210 (optional)

X1228

13 FN8100.2

October 17, 2005

STATUS REGISTER (SR)

The Status Register is located in the CCR memory

map area at address 003Fh. This is a volatile register

only and is used to control the WEL and RWEL write

enable latches, read two power status and two alarm

bits. This register is separate from both the array and

the Clock/Control Registers (CCR).

Table 2. Status Register (SR)

BAT: Battery Supply—Volatile

This bit set to “1” indicates that the device is operating

from VBACK, not VCC. It is a read-only bit and is set/reset

by hardware (X1228 internally). Once the device begins

operating from VCC, the device sets this bit to “0”.

AL1, AL0: Alarm bits—Volatile

These bits announce if either al arm 0 or ala rm 1 match

the real time clock. If there is a match, the respective

bit is set to ‘1’. The falling edge of the last data bit in a

SR Read operation resets the flags. Note: Only the AL

bits that are set when an SR read starts will be reset.

An alarm bit that is set by an alarm occur ring during an

SR read operation will remain set after the read opera-

tion is complete.

RWEL: Register Write Enable Latch—Volatile

This bit is a volatile latch that powers up in the LOW

(disabled) state. The RWEL bit must be set to “1” prior

to any writes to the Clock/Control Registers. Writes to

RWEL bit do not cause a nonvolatile write cycle, so the

device is ready for the next operation immediately after

the stop condition. A write to the CCR requires both the

RWEL and WEL bits to be set in a specific sequence.

WEL: Write Enable Latch—Volatile

The WEL bit controls the access to the CCR and mem-

ory array during a write operation. This bit is a volatile

latch that powers up in the LOW (disabled) state. While

the WEL bit is LOW, writes to the CCR or any array

address will be ignored (no acknowledge will be issued

after the Data Byte). The WEL bit is set by writing a “1”

to the WEL bit and zeroes to the other bits of the Status

to 0 (by writing a “0” to the WEL bit and zeroes to the

other bits of the Status Register) or until the part powers

up again. Writes to WEL bit do not cause a nonvolatile

write cycle, so the device is ready for the next operation

immediately after the stop condition.

RTCF: Real Time Clock Fail Bit—Volatile

This bit is set to a ‘1’ after a total power failure. This is

a read only bit that is set by hardware (X1228 inter-

nally) when the device powers up after having lost all

power to the device. The bit is set regardless of

whether VCC or VBACK is applied first. The loss of only

one of the supplies does n ot result in setting the RTCF

bit. The first valid write to the RTC after a complete

power failure (writing one byte is sufficient) resets the

RTCF bit to ‘0’.

Unused Bits:

This device does not use bits 3 o r 4 in the SR, but must

have a zero in these b it positions. The Data Byte ou tput

during a SR read will contain zeros in these bit locations.

CONTROL REGISTERS

The Control Bits and Registers, described under this

section, are nonvolatile.

Block Protect Bits—BP2, BP1, BP0

The Block Protect Bits, BP2, BP1 and BP0, determine

which blocks of the array are write protected. A write to a

protected block of memory is igno red. The block protect

bits will prevent write operations to one of eight segments

of the array. The partitions are described in Table 3 .

Table 3. Block Protect Bits

Watchdog Timer Control Bits—WD1, WD0

The bits WD1 and WD0 control the period of the

Watchdog Timer. See Table 4 for options.

Addr 7 6 5 4 3 2 1 0

003Fh BAT AL1 AL0 0 0 RWEL WEL RTCF

Default 0 0 0 0 0 0 0 1

BP2

BP1

BP0

Protected Addres ses

X1228 Array Lock

0 0 0 None None (Default)

0 0 1 180h - 1FFh Upper 1/4

0 1 0 100h - 1FFh Upper 1/2

0 1 1 000h - 1FFh Full Array

1 0 0 000h - 03Fh First Page

1 0 1 000h - 07Fh First 2 pgs

1 1 0 000h - 0FFh First 4 pgs

1 1 1 000h - 1FFh First 8 pgs

X1228

14 FN8100.2

October 17, 2005

Table 4. Watchdog Timer Time-Out Options

INTERRUPT CONTROL AND FREQUENCY

OUTPUT REGISTER (INT)

Interrupt Control and Status Bits (IM, AL1E, AL0E)

There are two Interrupt Control bits, Alarm 1 Interrupt

Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to

specifically enable or disable the alarm interrupt signal

output (IRQ). The interrupts are enabled when either the

AL1E and AL0E bits are set to ‘1’, respectively.

Two volatile bits (AL1 and AL0), associated with the

two alarms respectively, indicate if an alarm has hap-

pened. These bits are set on an alarm condition

regardless of whether the IRQ interrupt is enabled.

The AL1 and AL0 bits in the status reg ister are reset

by the falling edge of the eighth clock of a read o f the

Pulse Interrupt Mode

The pulsed interrrupt mode allows for repetitive or

recurring alarm functionality. Hence an repetitive or

recurring alarm can be set for every nth second, or nth

minute, or nth hour, or nth date, or for the same day of

the week. The pulsed interrupt mode can be consid-

ered a repetitive interrupt mode, with the repetition

rate set by the time setting of the a larm.

The Pulse Interrupt Mode is enabled when the IM bit is

set.

The Alarm IRQ output will output a single pulse of

short duration (approximately 10-40ms) once the

alarm condition is met. If the interrupt mode bit (IM bit)

is set, then this pulse will be periodic.

Programmable Frequency Output Bits—FO1, FO0

These are two output control bits. They select one of

three divisions of the internal oscillator, that is applied

to the PHZ outp ut pin. Ta bl e 5 shows the selection bits

for this output. When using the PHZ output function,

the Alarm IRQ output function is disabled.

Table 5. Programmable Frequency Output Bits

ON-CHIP OSCILLATOR COMPENSATION

Digital Trimming Register (DTR) — DTR2, DTR1

and DTR0 (Non-Volatile)

The digital trimming Bits DTR2, DTR1 and DTR0

adjust the number of counts per second and average

the ppm error to achieve better accuracy.

DTR2 is a sign bit. DTR2 = 0 means frequency

compensation is > 0. DTR2 = 1 means frequency

compensation is < 0.

DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm

adjustment and DTR0 gives 20 ppm adjustment.

A range from -30ppm to +30ppm can be represented

by using three bits above.

Table 6. Digital Trimming Registers

WD1 WD0 Watchdog Time-Out Period

0 0 1.75 seconds

0 1 750 milliseconds

1 0 250 milliseconds

1 1 Disabled (default)

IM Bit Interrupt / Alarm Frequency

0 Single Time Event Set By Alarm

1Repetitive / Recurring Time Event Set By

Alarm

FO1 FO0 Output Frequency

(average of 100 samples)

0 0 Alarm IRQ output

0 1 32.768kHz

1 0 4096Hz

11 1Hz

DTR Register Estima te d fre que n cy

PPMDTR2 DTR1 DTR0

0 0 0 0 (Default)

010 +10

001 +20

011 +30

100 0

110 -10

101 -20

111 -30

X1228

15 FN8100.2

October 17, 2005

Analog Trimming Register (ATR) (Non-volatile)

Six analog trimming Bits from ATR5 to ATR0 are pro-

vided to adjust the on-chip loading capacitance

range. The on-chip load capacitance ranges from

3.25pF to 18.75pF. Each bit has a different weight for

capacitance adjustment. In addition, using a Citizen

CFS-206 crystal with different ATR bit combinations

provides an estimated ppm range from +116ppm to

-37ppm to the nominal frequency compensation . The

combination of digital and analog trimming can give

up to +146ppm adjustment.

The on-chip ca pacitance can be calcula ted as follows:

CATR = [(ATR value, decimal) x 0.25 pF] + 11.0pF

Note that the ATR values are in two’s complement,

with ATR(000000) = 11.0pF, so the entire range runs

from 3.25pF to 18.75pF in 0.25pF steps.

The values calculated above are typical, an d total load

capacitance seen by the crystal will include approxi-

mately 2pF of package and board capacitance in addi-

tion to the ATR value.

See Application section and Intersil’s Application Note

AN154 for more informa tion.

WRITING TO THE CLOCK/CONTROL REGISTERS

Changing any of the nonvolatile bits of the

clock/control register requir es the following steps:

– Write a 02h to the Status Register to set the Write

Enable Latch (WEL). This is a volatile opera tion, so

there is no delay after the write. (Operation pre-

ceeded by a start and ended with a stop).

– Write a 06h to the Status Register to set both the

bit. This is also a volatile cycle. The zeros in the data

byte are required. (Operation preceeded by a start

and ended with a stop).

– Wri te one to 8 bytes to the Clock/C on tr ol Reg ist er s

with the desired clock, alarm, or control data. This

sequence starts with a start bit, require s a slave byte

of “11011110” and an address within the CCR and is

terminated by a stop bit. A write to the CCR changes

EEPROM values so these initiate a nonvolatile write

cycle and will take up to 10ms to complete. Writes to

undefined ar ea s ha ve no effe ct. T he RW EL bit is

reset by the completion of a nonvolatile write cycle,

so the sequence must be repeated to again initiate

another change to the CCR contents. If the

sequence is not completed for any reason (by send-

ing an incorrect number of bits or sending a start

instead of a stop, for example) the RWEL bit is not

reset and the device remains in an active mode.

– Writing all zeros to the status register re sets both the

WEL and RWEL bits.

– A read operation occurring between any of the previ-

ous operations will not interrupt the register write

operation.

POWER-ON RESET

Application of power to the X1228 activates a Power-

on Reset Circuit that pulls the RESET pin active. This

signal provides several benefits.

– It prevents the system microprocessor from starting

to operate with insufficient voltage.

– It prevents the processor from operating prior to sta-

bilization of the oscillator.

– It a llows time for a n FPGA to download its configura-

tion prior to initialization of the circuit.

– It prevents communication to the EEPROM, greatly

reducing the likelihood of data corruption on power-up.

When VCC exceeds the device VTRIP threshold value

for typically 250ms th e circuit releases RESET, allow-

ing the system to begin operation. Recommended

slew rate is between 0.2V/ms a nd 50V/ms.

WATCHDOG TIMER OPERATION

The watchdog timer is selectable. By writing a value to

WD1 and WD0, the watchdog timer can be set to 3 dif-

ferent time out periods or off. When the Watchdog

timer is set to off, the watchdog circuit is configured for

low power operation.

Watchdog Timer Restart

The Watchdog Timer is started by a falling edge of

SDA when the SCL line is high and followed by a stop

bit. The start signal restarts the watchdog timer

counter, resetting the period of the counter back to the

maximum. If another start fails to be detected prior to

the watchdog timer expiration, then the RESET pin

becomes active. In the event that the start signal

occurs during a reset time out period, the start will

have no effect. When using a single START to refresh

watchdog timer, a STOP bit should be followed to

reset the device back to stand-by mode.

X1228

16 FN8100.2

October 17, 2005

LOW VOLTAGE RESET OPERATION

When a power failure occurs, and the voltage to the

part drops below a fixed vTRIP voltage, a reset pulse is

issued to the host microcontroller. The circuitry moni-

tors the VCC line with a voltage comparator which

senses a preset threshold voltage. Power-up and

power-down waveforms are shown in Figure 4. The

Low Voltage Reset circuit is to be designed so the

RESET signal is valid down to 1.0V.

When the low voltage reset signal is active, the operation

of any in progress nonvolatile write cycle is unaffected,

allowing a nonvolatile write to continue as long as possi-

ble (down to the power-on reset voltage). The low volt-

age reset signal, when active, terminates in progress

communications to the device and prevents new com-

mands, to reduce the likelihood of data corruption.

Figure 3. Watchdog Restart/Time Out

Figure 4. Power-on Reset and Low Voltage Reset

VCC THRESHOLD RESET PROCEDURE

[OPTIONAL]

The X1228 is shipped with a standard VCC threshold

(VTRIP) voltage. This value will not change over normal

operating and storage conditions. However, in applica-

tions where the standard VTRIP is not exactly right, or if

higher precision is needed in the VTRIP value, the

X1228 threshold may be adjusted. The procedure is

described below, a nd u ses the app lica t ion of a n onvo l-

atile write control signal.

Setting the VTRIP Voltage

It is necessary to reset the trip point before setting the

new value.

To set the new VTRIP voltage, apply the desired VTRIP

threshold voltage to the VCC pin and tie the RESET pin

to the programming voltage VP. Then write data 00h to

address 01h. The stop bit followin g a valid write opera-

tion initiates the VTRIP programming sequence. Bring

RESET to VCC to complete the operation. Note: this

operation may take up to 10 milliseconds to complete

and also writes 00h to address 01h of the EEPROM

array.

tRSP<tWDO tRST

RESET

SDA

tRSP

Note: All inputs are ignored during the active reset period (tRST).

tRST

SCL

tRSP>tWDO

Start Stop Start

TRIP

RESET

PURST

RPD

RVALID

X1228

17 FN8100.2

October 17, 2005

Figure 5. Set VTRIP Level Sequence (VCC = desired VTRIP value)

Resetting the VTRIP Voltage

This procedure is used to set the VTRIP to a “native”

voltage level. For example, if the current VTRIP is 4.4V

and the new VTRIP must be 4.0V, then the VTRIP must

be reset. When V TRIP is res et, the new VTRIP is some-

thing less than 1.7V. This procedure must be used to

set the voltage to a lower value.

To reset the new VTRIP voltage, apply more than 5.5V

to the VCC pin and tie the RESET pin to the

programming voltage VP. Then write 00h to address

03h. The stop bit of a valid write operation initiates the

VTRIP programming sequence. Bring RESET to VCC to

complete the operation. Note: this operation takes up

to 10 milliseconds to complete and also writes 00h to

address 03h of the EEPROM array.

For best accuracy in setting VTRIP, it is advised that

the following sequence be used.

1.Program VTRIP as above.

2.Measure resulting VTRIP by measuring the VCC

value where a RESET occurs. Calculate Delta =

(Desired – Measured) VTRIP value.

3.Perform a VTRIP program using the following formula

to set the voltage of the RESET pin:

VRESET = (Desired Value – Delta) + 0.025V

Figure 6. Reset VTRIP Level Sequence

SCL

SDA

01h

RESET VP = 15V

00h

01234567 01234567 01234567 01234567

AEh 00h

VCC

Note: BP0, BP1, BP2 must be disabled.

01234567

SCL

SDA

AEh

01234567

03h

RESET VP = 15V

00h

01234567 01234567

00h

VCC

Note: BP0, BP1, BP2 must be disabled.

X1228

18 FN8100.2

October 17, 2005

SERIAL COMMUNICATION

Interface Conventions

The device supports a bi directional bu s oriente d proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter, and the receiving device

as the receiver. The device controlling the transfer is

called the master and the device being controlled is

called the slave. The master always initiates data

transfers, and provides the clock for both transmit and

receive operations. Therefore, the devices in this fam-

ily operate as slaves in all ap plications.

Clock and Data

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 7.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL

is HIGH. The device continuously monitors the SDA

and SCL lines for the start condition and will not

respond to any command until this condition has been

met. See Figure 8.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

when SCL is HIG H. The stop condition is also used to

place the device into the Standby power mode after a

read sequence. A stop condition can only be issued

after the transm itting device has released th e bus. See

Figure 8.

Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bi ts of data. Refer to Figure 9.

The device will respond with an acknowledge after

recognition of a start condition and if the correct

Device Identifier and Select bits are contained in the

Slave Address Byte. If a write operation is selected,

the device will respond with an acknowledge after the

receipt of e ach subsequent e ight bit word. Th e device

will acknowledge all incoming data and address bytes,

except for:

– The Slave Address Byte when the Device Identifier

and/or Select bits are incorrect

– All Data Bytes of a write when the WEL in the Write

Protect Register is LOW

– The 2nd Data Byte of a Status Register Write Oper-

ation (only 1 data byte is allowed)

In the read mode, the device will transmit eight bits of

data, release the SDA line, th en monitor the line for an

acknowledge. If an acknowledge is detected and no

stop condition is generated by the master, the device

will continue to transmit data. The device will terminate

further data transmissions if an acknowledge is not

detected. The master must then issu e a stop condition

to return the device to Standby mode and place the

device into a known state.

Figure 7. Valid Data Changes on the SDA Bus

SCL

SDA

Data Stable Data Change Data Stable

X1228

19 FN8100.2

October 17, 2005

Figure 8. Valid Start and Stop Conditions

Figure 9. Acknowledge Response From Receiver

DEVICE ADDRESSING

Following a start condition, the master must output a

Slave Address Byte. The first four bits of the Slave

Address Byte specify access to either the EEPROM

array or to the CCR. Slave bits ‘1010’ access the

EEPROM array. Slave bits ‘1101’ access the CCR.

When shipped from the factory, EEPROM array is

UNDEFINED, and should be programmed by the cus-

tomer to a known state.

Bit 3 through Bit 1 of the slave byte specify the device

select bits. These are set to ‘111’.

The last bit of the Slave Address Byte defines the

operation to be perfor me d. Whe n th is R/W bit is a one,

then a read operation is selected. A zero selects a

write operation. Refer to Figure 10.

After loading the entire Slave Address Byte from the

SDA bus, the X1228 compares the device identifier

and device select bits with ‘1010111’ or ‘1101111’.

Upon a correct compare, the device outputs an

acknowledge on the SDA line.

Following the Slave Byte is a two byte word address.

The word address is either supplied by the master

device or obtained fr om an internal counter. On power-

up the internal address counter is set to address 0h,

so a current address read of the EEPROM array starts

at address 0. When required, as part of a random

read, the master must supply the 2 Word Address

Bytes as shown in Figu re 10.

In a random read operation, the slave byte in the

“dummy write” portion must match the slave byte in

the “read” section. That is if the random read is from

the array the slave byte must be 1010111x in both

instances. Similarly, for a random read of the

Clock/Control Registers, the slave byte must be

1101111x in both places.

SCL

SDA

Start Stop

SCL from

Master

Data Output

from Transmitter

Data Output

from Receiver

81 9

Start Acknowledge

X1228

20 FN8100.2

October 17, 2005

Figure 10. Slave Address, Word Address, and Data Bytes (64 Byte pages)

Write Operations

Byte Write

For a write operation, the device requires the Slave

Address Byte and the Word Address Bytes. This gives

the master access to any one of the words in the array

or CCR. (Note: Prior to writing to the CCR, the master

must write a 02h, then 06h to th e status register in two

preceding operations to enable the write operation.

See “Writing to the Clock/Control Registers.” Upon

receipt of each address byte , the X1228 r esponds with

an acknowledge. After receiving both address bytes

the X1228 await s the eigh t bit s of data . Afte r re ceivin g

the 8 data bits, the X1228 again responds with an

acknowledge. The master then terminates the transfer

by generating a stop condition. The X1228 then

begins an internal write cycle of th e data to the nonvol-

atile memory. During the internal write cycle, the

device inputs are disabled, so the device will not

respond to any requests from the master. The SDA out-

put is at high impedance. See Figure 11.

Figure 11. Byte Write Sequence

Figure 12. Writing 30 bytes to a 64-byte memory page starting at address 40.

Slave Address Byte

Byte 0

D7 D6 D5 D2D4 D3 D1 D0

A0A7 A2A4 A3 A1

Data Byte

Byte 3

A6 A5

00 0 0 0A80

11R/W

Device Identifier

Array

CCR

0Word Address 1

Byte 1

Word Address 0

Byte 2

Slave

Address Word

Address 1

Data

SDA Bus

Signals From

The Slave

Signals from

the Master

Word

Address 0

1111 0000000

Address

23 Bytes

7 Bytes

Address

= 6

Address Pointer

Ends Here

Addr = 7

X1228

21 FN8100.2

October 17, 2005

A write to a protected block of memory is ignored, but

will still receive an acknowledge. At the end of the

write command, the X1228 will not initiate an internal

write cycle, and will continue to ACK commands.

Page Write

The X1228 has a page write operation. It is initiated in

the same manner as the byte write operation; but

instead of terminating th e write cycle after the first data

byte is transferred, the master can transmit up to 63

more bytes to the memory array and up to 7 more

bytes to the clock/control registers. (Note: Prior to writ-

ing to the CCR, the master must write a 02h, then 06h

to the status register in two preceding operations to

enable the write operation. See “Writing to the

Clock/Control Registers.”

After the receipt of each byte, the X1228 responds with

an acknowledge, and the address is internally incre-

mented by one. When the counter reaches the end of

the page, it “rolls over” and goes back to the first

address on the same page. This means that the master

can write 64 bytes to a memory array page or 8 bytes to

a CCR section starting at any location on that page. For

example, if the master begins writing at location 40 of

the memory and loads 30 bytes, then the first 23 bytes

are written to addresses 40 through 63, and the last 7

bytes are written to columns 0 through 6. Afterwards,

the address counter would point to location 7 on the

page that was just written. If the master supplies more

than the maximum bytes in a page, then the previously

loaded data is over written by the new data, one byte at

a time. Refer to Figure 12.

The master terminates the Data Byte loading by issu-

ing a stop condition, which causes the X1228 to begin

the nonvolatile write cycle. As with the byte write oper-

ation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 13 for the address,

acknowledge, and data transfer seq uence.

Stops and Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and it’s associated ACK signal. If a stop is issued in the

middle of a data byte, or before 1 full data byte + ACK is

sent, then the X1228 resets itself without performing the

write. The contents of the array are not affected.

Figure 13. Page Write Sequence

Word

Address 0

Slave

Address Word

Address 1 Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(1)

1 ≤ n ≤ 64 for EEPROM array

1 ≤ n ≤ 8 for CCR

11110000000

X1228

22 FN8100.2

October 17, 2005

Acknowledge Polling

Disabling of the inputs during nonvolatile write cycles

can be used to ta ke advantag e of the typical 5mS write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

X1228 initiates the internal nonvolatile write cycle.

Acknowledge polling can begin immediately. To do

this, the master issues a start condition followed by the

Memory Array Slave Address Byte for a write or read

operation (AEh or AFh). If the X1228 is still busy with

the nonvolatile write cycle then no ACK will be

returned. When the X1228 has completed the write

operation, an ACK is returned and the host can pro-

ceed with the read or wr ite operation. Refer to the flow

chart in Figure 15. Note: Do not use the CCR Salve

byte (DEh or DFh) for Acknowledge Polling.

Read Operations

There are three basic read operations: Current

Address Read, Rando m Read, and Sequ ential Read.

Current Address Read

Internally the X1228 contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power-up, the sixteen bit

address is initialized to 0h. In this way, a current

address read immediately after the power-on reset

can download the entire contents of memory starting

at the first location.Upon receipt of the Slave Address

Byte with the R/W bit set to one, the X1228 issues an

acknowledge, then transmits eight data bits. The mas-

ter terminates the read operation by not responding

with an acknowledge during the ninth clock and issu-

ing a stop condition. Refer to Figure 14 for the

address, acknowledge, and data transfer sequence.

Figure 15. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read

operation, the master must either issue a stop condi-

tion during the ninth cycle or hold SDA HIGH during

the ninth clock cycle and then issue a stop condition.

Figure 14. Current Address Read Sequence

ACK

returned?

Byte load completed

by issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

Issue STOP

Continue normal

Read or Write

command

sequence

PROCEED

YES

nonvolatile write

Cycle complete. Continue

command sequence?

Issue Memory Array Slave

Address Byte

AFh (Read) or AEh (Write)

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

11111

X1228

23 FN8100.2

October 17, 2005

Random Read

Random read operations allows the master to access

any location in the X1228. Prior to issuing the Slave

Address Byte with the R/W bit set to zero, the master

must first perform a “dummy” write operation.

The master issues the start condition and the slave

address byte, receives an acknowledge, then issues

the word address bytes. After acknowledging receipt

of each word address byte, the master immediately

issues another start condition and the slave address

byte with the R/W bit set to one. This is followed by an

acknowledge from the devic e and then by the eight bit

data word. The master terminates the read operation

by not responding with an acknowledg e and the n issu -

ing a stop condition. Refer to Figure 16 for the

address, acknowledge , and data transfer sequence.

In a similar operation called “Set Current Address,” the

device sets the address if a stop is issued instead of

the second start shown in Figure 16. The X1228 then

goes into standby mode after the stop and all bus

activity will be ignored until a start is detected. This

operation loads the new address into the address

counter. The next Current Address Read operation will

read from the newly loaded address. This operation

could be useful if the master knows the next address it

needs to read , but is not ready for the data.

Sequential Read

Sequential reads can be initiated as either a current

address read or random address read. The first data

byte is transmitted as with the other modes; however,

the master now responds with an acknowledge, indi-

cating it requires add itional da ta. The device continues

to output data for each acknowledge received. The

master terminates the read operation by not responding

with an acknowledge and then issuing a stop condition.

The data output is sequential, with the data from

address n followed by the data from address n + 1.

The address counter for read operations increments

through all page and column addresses, allowing the

entire memory contents to be serially read during one

operation. At the end of the addre ss space the counter

“rolls over” to the start of the address space and the

X1228 continues to output data for each acknowledge

received. Refer to Figure 17 for the acknowledge and

data transfer sequence.

Figure 16. Random Address Read Sequence

Figure 17. Sequential Read Sequence

Slave

Address Word

Address 1

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Word

Address 0

1111 1111

0000000

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

X1228

24 FN8100.2

October 17, 2005

APPLICATION SECTION

CRYSTAL OSCILLATOR AND TEMPERATURE

COMPENSATION

Intersil has now integrated the oscillator compensation

circuity on-chip, to eliminate the need for external

components and adjust for crystal drift over tempera-

ture and enable very high accuracy time keeping

(<5ppm drift).

The Intersil RTC family uses an oscillator circuit with

on-chip crystal compensation network, including

adjustable load-capacitance. The only external com-

ponent required is the crystal. The compensation net-

work is optimized for operation with certain crystal

parameters which are common in many of the surface

mount or tuning-fork crystals available today. Table 6

summarizes these par ameters.

Table 7 contains some crystal manufacturers and part

numbers that meet the requirements for the Intersil

RTC products.

The turnover temperature in Table 6 describes the

temperature where the apex of the of the drift vs. tem-

perature curv e occurs. This curv e is parabolic with the

drift increasing as (T-T0)2. For an Epson MC-405

device, for example, the turnover temperature is typi-

cally 25 deg C, and a peak drift of >110ppm occurs at

the temperature extremes of -40 and +85 deg C. It is

possible to address this variable drift by adjusting the

load capacitance of the crystal, which will result in pre-

dictable change to the crystal frequency. The Intersil

RTC family allows this adjustment over temperature

since the devices include on-chip load capacitor trim-

ming. This control is handled by the Analog Trimming

capacitance range covered by the ATR circuit is

approximately 3.25pF to 18.75pF, in 0.25pf incre-

ments. Note that actual capacitance would also

include about 2pF of package related capacitance. In-

circuit tests with commercially available crystals dem-

onstrate that this range of capacitance allows fre-

quency control from +116ppm to -37ppm, using a

12.5pF load crystal.

In addition to the analog compen sation af forded b y the

adjustable load capacitance, a digital compensation

feature is available for the Intersil RTC family. There

are three bits known as the Digital Trimming Register

or DTR, and they ope rate by addin g or skippi ng pulses

in the clock signal. The range provided is ±30ppm in

increments of 10ppm. T he default se tting is 0ppm. The

DTR control can be used for coarse adjustments of

frequency drift over temperature or for crystal initial

accuracy correction.

Table 6. Crystal Parameters Required for Intersil RTC’s

Table 7. Crystal Manufactur ers

Parameter Min Typ Max Units Notes

Frequency 32.768 kHz

Freq. Tolerance ±100 ppm Down to 20ppm if desired

Turnover Temperature 20 25 30 °C Typically the value used for most

crystals

Operating Temperature Range -40 85 °C

Parallel Load Capacitance 12.5 pF

Equivalent Series Resistance 50 kΩFor best oscillator performance

Manufacturer Part Number Temp Range +25°C Freq Toler.

Citizen CM201, CM202, CM200S -40 to +85°C ±20ppm

Epson MC-405, MC-406 -40 to +85°C ±20ppm

Raltron RSM-200S-A or B -40 to +85°C ±20ppm

SaRonix 32S12A or B -40 to +85°C ±20ppm

Ecliptek ECPSM29T-32.768K -10 to +60°C ±20ppm

ECS ECX-306/ECX-306I -10 to +60°C ±20ppm

Fox FSM-327 -40 to +85°C ±20ppm

X1228

25 FN8100.2

October 17, 2005

A final application for the ATR control is in-circuit cali-

bration for high accuracy applications, along with a

temperature sensor chip. Once the RTC circuit is pow-

ered up with battery backup, the PHZ output is set at

32.768kHz and frequency drift is measured. The ATR

control is then adjusted to a setting which minimizes

drift. Once adjusted at a particular temperature, it is

possible to adjust at other discrete temperatures for

minimal overall drift, and store the resulting settings in

the EEPROM. Extremely low overall temperature drift

is possible with this method. The Intersil evaluation

board contains the circuitry necessary to implement

this control.

For more detailed operation see Intersil’s application

note AN154 on Intersil’s website at www.intersil.com.

Layout Considerations

The crystal input at X1 has a very high impedance an d

will pick up high frequency signals from other circuits

on the board. Since the X2 pin is tied to the other side

of the crystal, it is also a sensitive node. These signals

can couple into the oscillator circuit and produc e dou-

ble clocking or mis-clocking, seriously affecting the

accuracy of the RTC. Care needs to be taken in layout

of the RTC circu it to avoid noise p ickup. Below in Fig-

ure 15 is a sugg ested layout for the X1228 device.

Figure 15. Suggested Layout for Intersil RTC in SO-14

The X1 and X2 connections to the crystal are to be

kept as short as possible. A thick ground trace around

the crystal is advised to minimize noise intrusion, but

ground near the X1 and X2 pins should be avoided as

it will add to the load capacitance at those pins. Keep

in mind these guidelines for other PCB layers in the

vicinity of the RTC device. A small decoupling capaci-

tor at the Vcc pin of the chip is mandatory, with a solid

connection to ground.

Assembly

Most electronic circuits do not have to deal with

assembly issues, but with the RTC devices assembly

includes insertion or soldering of a live battery into an

unpowered circuit. If a socket is soldered to the board,

and a battery is inserted in final assembly, then there

are no issues with operation of the RTC. If the battery

is soldered to the board directly, then the RTC device

Vback pin will see some transient upset from either

soldering tools or intermittent battery connections

which can stop the circuit from oscillating. Once the

battery is soldered to the board, the only way to assure

the circuit will start up is to momentarily (very short

period of time !) short the Vback pin to ground and the

circuit will begin to oscillate.

Oscillator Measurements

When a proper crystal is selected and the layout guide-

lines above are observed, the oscillator should start up

in most circuits in less than one second. Some circuits

may take slightly longer, but startup should definitely

occur in less than 5 seconds. When testing RTC cir-

cuits, the most common impulse is to apply a scope

probe to the circuit at the X2 pin (oscillator output) and

observe the waveform. DO NOT DO THIS! Although in

some cases you may see a useable waveform, due to

the parasitics (usually 10pF to ground) applied with the

scope probe, there will be no useful information in that

waveform other than the fact that the circuit is oscillat-

ing. The X2 output is sensitive to capacitive impedance

so the voltage levels and the frequency will be affected

by the parasitic elements in the scope probe. Applying a

scope probe can possibly cause a faulty oscillator to

start up, hiding other issues (although in the Intersil

RTC’s, the internal circuitry assures startup when using

the proper crystal and layout).

The best way to analyze the RTC circuit is to power it

up and read the real time clock as time advances, or if

the chip has the PHZ output, look at the output of that

pin on an oscilloscope (after enabling it with the con-

trol register, and using a pullup resistor for an open-

drain output). Alternatively, the X1226/1286/1288

devices have an IRQ- output which ca n be checked by

setting an alarm for each minute. Using the pulse

interrupt mode setting, the once-per-minute interrupt

functions as an indication of proper oscillation.

0.1µF

XTAL1 U1R1 10k

X1228

32.768kGz

X1228

26 FN8100.2

October 17, 2005

Backup Battery Oper at io n

Many types of batteries can be used with the Intersil

RTC products. 3.0V or 3.6V Lithium batteries are

appropriate, and sizes are available that can power a

Intersil RTC device for up to 10 years. Another option

is to use a supercapacitor for applications where Vcc

may disappear intermittently for short periods of time.

Depending on the value of supercapacitor used,

backup time can last from a few days to two weeks

(with >1F). A simple silicon or Schottky barrier diode

can be used in series with Vcc to charge the superca-

pacitor, which is connected to the Vback pin. Do not

use the diode to charge a battery (especially lithium

batteries!).

Figure 16. Supercapactor charging circuit

Since the battery switchover occurs at Vcc=Vback-

0.1V (see F igure 16), the ba ttery voltage m ust always

be lower than the Vcc voltage during normal operation

or the battery will be drained. A second consideration

is the trip point setting for the system RESET- func-

tion, known as Vtr ip. Vtr ip is set at the factory at levels

for systems with either Vcc = 5V or 3.3V operation,

with the following standard o ptions:

VTRIP = 4.63V ± 3%

VTRIP = 4.38V ± 3%

VTRIP = 2.85V ± 3%

VTRIP = 2.65V ± 3%

The summary of conditions for backup battery opera-

tion is given in Table 8:

Table 8. Battery Backup Operation

*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device

2.7-5.5V

Supercapacitor

back

1. Example Application, Vcc = 5V, Vback = 3.0V

Condition Vcc Vback Vtrip Iback Reset Notes

a. Normal Operation 5.00 3.00 4.38 <<1µA H

b. Vcc on with no battery 5.00 0 4.38 0 H

c. Backup Mode 0-1.8 1.8-3.0 4.38 <2µA L Timekeeping

only

2. Example Application, Vcc = 3.3V,Vback = 3.0V

Condition Vcc Vback Vtrip Iback Reset

a. Normal Operation 3.30 3.00 2.65 <<1µA H

b. Vcc on with no battery 3.30 0 2.65 0 H

c. Backup Mode 0-1.8 1.8-3.0* 2.65 <2µA* L Timekeeping

only

d. UNWANTED - Vcc ON, Vback

powering 2.65 - 3.30 > Vcc 2.65 up to 3mA H Internal

Vcc=Vback

X1228

27 FN8100.2

October 17, 2005

Referring to Figure 16, Vtrip applies to the “Internal

Vcc” node which powers the entire device. This means

that if Vcc is powered down and the battery voltage at

Vback is higher than the Vtrip voltage, then the entire

chip will be running from the battery. If Vback falls to

lower than Vtrip, then the chip shuts down and all out-

puts are disabled except for the oscillator and time-

keeping circuitry. The fact that the chip can be

powered from Vback is not necessarily an issue since

standby current for the RTC devices is <2µA for this

mode (called “main timekeeping current” in the data

sheet). Only when the serial interface is active is there

an increase in supply current, and with Vcc powered

down, the serial interface will most likely be inactive.

One way to prevent operation in battery backup mode

above the Vtrip level is to add a diode drop (silicon

diode preferred) to the battery to insure it is below

Vtrip. This will also provide reverse leakage protection

which may be needed to get safety agency approval.

One mode that should always be avoided is the opera-

tion of the RTC device with Vback gre ater than bo th Vcc

and Vtrip (Condition 2d in Table 8). This will cause the

battery to drain quickly as serial bus commu nication and

non-volatile writes will require higher supplier current.

PERFORMANCE DATA

IBACK Performance

1.4

1.2

1.0

0.8

0.6

0.4

0.2

IBACK vs. Temperature

Multi-Lot Process Variation Data

Temperature °C

-40 25 60 85

IBACK (µA)

3.3V

1.8V

X1228

28 FN8100.2

October 17, 2005

PACKAGING INFORMATION

0.150 (3.80)

0.158 (4.00) 0.228 (5.80)

0.244 (6.20)

0.014 (0.35)

0.020 (0.51)

Pin 1

Pin 1 Index

0.050 (1.27)

0.336 (8.55)

0.345 (8.75)

0.004 (0.10)

0.010 (0.25)

0.053 (1.35)

0.069 (1.75)

(4X) 7°

14-Lead Plastic, SOIC, Package Code S14

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

0.250"

0.050"Typical

0.030"Typical

14 Places

FOOTPRINT

0.010 (0.25)

0.020 (0.50)

0.016 (0.410)

0.037 (0.937)

0.0075 (0.19)

0.010 (0.25)

0° - 8°

X 45°

X1228

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8100.2

October 17, 2005

PACKAGING INFORMATION

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

14-Lead Plastic, TSSOP, Package Code V14

See Detail “A”

.031 (.80)

.041 (1.05)

.169 (4.3)

.177 (4.5) .252 (6.4) BSC

.025 (.65) BSC

.193 (4.9)

.200 (5.1)

.002 (.05)

.006 (.15)

.047 (1.20)

.0075 (.19)

.0118 (.30)

0° - 8°

.010 (.25)

.019 (.50)

.029 (.75)

Gage Plane

Seating Plane

Detail A (20X)

X1228