DIN
SCLK
VA
GND
VOUT 1
2
3
6
5
4
SYNC
1
2
3
4
8
7
6
5
GND
DIN
SCLK
VA
NC
NC
VOUT SYNC
DAC101S101, DAC101S101-Q1
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SNAS321F –JUNE 2005–REVISED MARCH 2013
DAC101S101/DAC101S101Q 10-Bit Micro Power, RRO Digital-to-Analog Converter
Check for Samples: DAC101S101,DAC101S101-Q1
1FEATURES DESCRIPTION
The DAC101S101 is a full-featured, general purpose
2• DAC101S101Q is AEC-Q100 Grade 1 Qualified 10-bit voltage-output digital-to-analog converter
and is Manufactured on an Automotive Grade (DAC) that can operate from a single +2.7V to 5.5V
Flow. supply and consumes just 175 µA of current at 3.6
• Ensured Monotonicity Volts. The on-chip output amplifier allows rail-to-rail
output swing and the three wire serial interface
• Low Power Operation operates at clock rates up to 30 MHz over the
• Rail-to-Rail Voltage Output specified supply voltage range and is compatible with
• Power-on Reset to Zero Volts Output standard SPI, QSPI, MICROWIRE and DSP
• Wide Temperature Range of −40°C to +125°C interfaces. Competitive devices are limited to 20 MHz
clock rates at supply voltages in the 2.7V to 3.6V
• Wide Power Supply Range of +2.7V to +5.5V range.
• Small Packages The supply voltage for the DAC101S101 serves as its
• Power Down Feature voltage reference, providing the widest possible
output dynamic range. A power-on reset circuit
APPLICATIONS ensures that the DAC output powers up to zero volts
and remains there until there is a valid write to the
• Battery-Powered Instruments device. A power-down feature reduces power
• Digital Gain and Offset Adjustment consumption to less than a microWatt.
• Programmable Voltage & Current Sources The low power consumption and small packages of
• Programmable Attenuators the DAC101S101 make it an excellent choice for use
• Automotive in battery operated equipment.
The DAC101S101 is a direct replacement for the
KEY SPECIFICATIONS AD5310 and is one of a family of pin compatible
• Resolution 10 bits DACs, including the 8-bit DAC081S101 and the 12-bit
DAC121S101. The DAC101S101 operates over the
• DNL +0.15, -0.05 LSB (typ) extended industrial temperature range of −40°C to
• Output Settling Time 8 μs (typ) +105°C while the DAC101S101Q operates over the
• Zero Code Error 3.3 mV (typ) Grade 1 automotive temperature range of −40°C to
+125°C. The DAC101S101 is available in a 6-lead
• Full-Scale Error −0.06 %FS (typ) SOT and an 8-lead VSSOP and the DAC101S101Q
• Power Consumption is availabe in the 6-lead SOT only.
– Normal Mode, 0.63 mW (3.6V) / 1.41 mW
(5.5V) typ
– Pwr Down Mode, 0.14 μW (3.6V) / 0.33 μW
(5.5V) typ
Pin Configuration
Figure 1. Package Number DDC0006A Figure 2. Package Number DGK0008A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
POWER-ON
RESET
DAC
REGISTER
INPUT
CONTROL
LOGIC
10-BIT DAC
10
10
POWER-DOWN
CONTROL
LOGIC
BUFFER
1k 100k
SCLK DIN
SYNC
REF(+) REF(-)
VAGND
DAC101S101
VOUT
DAC101S101, DAC101S101-Q1
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Block Diagram
PIN DESCRIPTIONS
SOT VSSOP
(SOT-23) Symbol Description
Pin No.
Pin No.
1 4 VOUT DAC Analog Output Voltage.
2 8 GND Ground reference for all on-chip circuitry.
3 1 VAPower supply and Reference input. Should be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling
4 7 DIN edges of SCLK after the fall of SYNC.
Serial Clock Input. Data is clocked into the input shift register on the falling
5 6 SCLK edges of this pin.
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling edges
6 5 SYNC of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is
brought high before the 16th clock, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
2, 3 NC No Connect. There is no internal connection to these pins.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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CIRCUITRY
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Absolute Maximum Ratings (1)(2)(3)
Supply Voltage, VA6.5V
Voltage on any Input Pin −0.3V to (VA+ 0.3V)
Input Current at Any Pin (4) 10 mA
Package Input Current (4) 20 mA
Power Consumption at TA= 25°C See (5)
ESD Susceptibility (6)
Human Body Model 2500V
Machine Model 250V
Soldering Temperature, Infrared,
10 Seconds (7) 235°C
Storage Temperature −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) All voltages are measured with respect to GND = 0V, unless otherwise specified
(4) When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO
Ohms.
(7) See the section entitled "Surface Mount" found in any post 1986 Texas Instruments Linear Data Book for methods of soldering surface
mount devices.
Operating Ratings (1) (2)
Operating Temperature Range
DAC101S101 −40°C ≤TA≤+105°C
DAC101S101Q −40°C ≤TA≤+125°C
Supply Voltage, VA(3) +2.7V to 5.5V
Any Input Voltage (4) −0.1 V to (VA+ 0.1 V)
Output Load 0 to 1500 pF
SCLK Frequency Up to 30 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified
(3) To ensure accuracy, it is required that VAbe well bypassed.
(4) The analog inputs are protected as shown below. Input voltage magnitudes up to VA+ 300 mV or to 300 mV below GND will not
damage this device. However, errors in the conversion result can occur if any input goes above VAor below GND by more than 100 mV.
For example, if VAis 2.7VDC, ensure that −100mV ≤input voltages ≤2.8VDC to ensure accurate conversions.
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Package Thermal Resistances
Package θJA
8-Lead VSSOP 240°C/W
6-Lead SOT 250°C/W
Electrical Characteristics
The following specifications apply for VA= +2.7V to +5.5V, RL= 2kΩto GND, CL= 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified.
Typical Limits Units
Symbol Parameter Conditions (1) (1) (Limits)
STATIC PERFORMANCE
Resolution 10 Bits (min)
Monotonicity 10 Bits (min)
INL Integral Non-Linearity Over Decimal codes 12 to 1011 ±0.6 ±2.8 LSB (max)
VA= 2.7V to 5.5V +0.15 +0.35 LSB (max)
DNL Differential Non-Linearity −0.05 −0.2 LSB (min)
ZE Zero Code Error IOUT = 0 +3.3 +15 mV (max)
FSE Full-Scale Error IOUT = 0 −0.06 −1.0 %FSR (max)
GE Gain Error All ones Loaded to DAC register −0.10 ±1.0 %FSR (max)
ZCED Zero Code Error Drift −20 µV/°C
VA= 3V −0.7 ppm/°C
TC GE Gain Error Tempco VA= 5V −1.0 ppm/°C
OUTPUT CHARACTERISTICS
0V (min)
Output Voltage Range (2) VAV (max)
VA= 3V, IOUT = 10 µA 1.8 mV
VA= 3V, IOUT = 100 µA 5.0 mV
ZCO Zero Code Output VA= 5V, IOUT = 10 µA 3.7 mV
VA= 5V, IOUT = 100 µA 5.4 mV
VA= 3V, IOUT = 10 µA 2.997 V
VA= 3V, IOUT = 100 µA 2.990 V
FSO Full Scale Output VA= 5V, IOUT = 10 µA 4.995 V
VA= 5V, IOUT = 100 µA 4.992 V
RL=∞1500 pF
Maximum Load Capacitance RL= 2kΩ1500 pF
DC Output Impedance 1.3 Ohm
VA= 5V, VOUT = 0V, −63 mA
Input code = 3FFh
VA= 3V, VOUT = 0V, −50 mA
Input code = 3FFh
IOS Output Short Circuit Current VA= 5V, VOUT = 5V, 74 mA
Input code = 000h
VA= 3V, VOUT = 3V, 53 mA
Input code = 000h
LOGIC INPUT
IIN Input Current (2) ±1 µA (max)
VA= 5V 0.8 V (max)
VIL Input Low Voltage (2) VA= 3V 0.5 V (max)
(1) Typical figures are at TJ= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)
The following specifications apply for VA= +2.7V to +5.5V, RL= 2kΩto GND, CL= 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified.
Typical Limits Units
Symbol Parameter Conditions (1) (1) (Limits)
VA= 5V 2.4 V (min)
VIH Input High Voltage (2) VA= 3V 2.1 V (min)
CIN Input Capacitance (2) 3pF (max)
POWER REQUIREMENTS
VA= 5.5V 256 332 µA (max)
Normal Mode
fSCLK = 30 MHz VA= 3.6V 174 226 µA (max)
VA= 5.5V 221 297 µA (max)
Normal Mode
fSCLK = 20 MHz VA= 3.6V 154 207 µA (max)
VA= 5.5V 145 µA (max)
Normal Mode
fSCLK = 0 VA= 3.6V 113 µA (max)
IASupply Current (output unloaded) VA= 5.0V 83 µA (max)
All PD Modes,
fSCLK = 30 MHz VA= 3.0V 42 µA (max)
VA= 5.0V 56 µA (max)
All PD Modes,
fSCLK = 20 MHz VA= 3.0V 28 µA (max)
VA= 5.5V 0.06 1.0 µA (max)
All PD Modes,
fSCLK = 0 (2) VA= 3.6V 0.04 1.0 µA (max)
VA= 5.5V 1.41 1.83 mW (max)
Normal Mode
fSCLK = 30 MHz VA= 3.6V 0.63 0.81 mW (max)
VA= 5.5V 1.22 1.63 mW (max)
Normal Mode
fSCLK = 20 MHz VA= 3.6V 0.55 0.74 mW (max)
VA= 5.5V 0.80 µW (max)
Normal Mode
fSCLK = 0 VA= 3.6V 0.41 µW (max)
Power Consumption (output
PCunloaded) VA= 5.0V 0.42 µW (max)
All PD Modes,
fSCLK = 30 MHz VA= 3.0V 0.13 µW (max)
VA= 5.0V 0.28 µW (max)
All PD Modes,
fSCLK = 20 MHz VA= 3.0V 0.08 µW (max)
VA= 5.5V 0.33 5.5 µW (max)
All PD Modes,
fSCLK = 0 (3) VA= 3.6V 0.14 3.6 µW (max)
VA= 5V 91 %
IOUT / IAPower Efficiency ILOAD = 2mA VA= 3V 94 %
(3) This parameter is ensured by design and/or characterization and is not tested in production.
A.C. and Timing Characteristics
The following specifications apply for VA= +2.7V to +5.5V, RL= 2kΩto GND, CL= 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified.
Units
Symbol Parameter Conductions Typical Limits (Limits)
fSCLK SCLK Frequency 30 MHz (max)
Output Voltage Settling Time 100h to 300h code
tsCL≤200 pF 5 7.5 µs (max)
(1) change, RL= 2kΩ
SR Output Slew Rate 1 V/µs
Glitch Impulse Code change from 200h to 1FFh 12 nV-sec
Digital Feedthrough 0.5 nV-sec
(1) This parameter is ensured by design and/or characterization and is not tested in production.
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A.C. and Timing Characteristics (continued)
The following specifications apply for VA= +2.7V to +5.5V, RL= 2kΩto GND, CL= 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011. Boldface limits apply for TMIN ≤TA≤TMAX: all other limits TA= 25°C, unless otherwise specified.
Units
Symbol Parameter Conductions Typical Limits (Limits)
VA= 5V 6 µs
tWU Wake-Up Time VA= 3V 39 µs
1/fSCLK SCLK Cycle Time 33 ns (min)
tHSCLK High time 5 13 ns (min)
tLSCLK Low Time 5 13 ns (min)
Set-up Time SYNC to SCLK Rising
tSUCL −15 0ns (min)
Edge
tSUD Data Set-Up Time 2.5 5ns (min)
tDHD Data Hold Time 2.5 4.5 ns (min)
VA= 5V 0 3ns (min)
tCS SCLK fall to rise of SYNC VA= 3V −21ns (min)
2.7 ≤VA≤3.6 9 20 ns (min)
tSYNC SYNC High Time 3.6 ≤VA≤5.5 5 10 ns (min)
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 1024 = VA/ 1024.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data
bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded
into the DAC and the value of VAx 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is
measured from the center of that code value. The end point method is used. INL for this product is
specified over a limited range, per the Electrical Characteristics Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value
is
LSB = VREF / 2n
where
• VREF is the supply voltage for this product
• "n" is the DAC resolution in bits, which is 10 for the DAC101S101 (1)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the output code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VREF.
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DB15 DB0
SCLK
DIN
SYNC
tSYNC tSUCL
tSUD
tDHD
tLtHtCS
|||
|
|
||
1 2 13 14 15 16
fCLK
1
OUTPUT
VOLTAGE
DIGITAL INPUT CODE
00 1023
ZE
FSE
GE = FSE - ZE
FSE = GE + ZE
1023 x VA
1024
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SNAS321F –JUNE 2005–REVISED MARCH 2013
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents, is the power consumed by the
device without a load.
SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value.
WAKE-UP TIME is the time for the output to settle within 1/2 LSB of the final value after the device is
commanded to the active mode from any of the power down modes.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
Transfer Characteristic
Figure 3. Input / Output Transfer Characteristic
Timing Diagram
Figure 4. DAC101S101 Timing
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Typical Performance Characteristics
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
DNL at VA= 3.0V DNL at VA= 5.0V
Figure 5. Figure 6.
INL at VA= 3.0V INL at VA= 5.0V
Figure 7. Figure 8.
TUE at VA= 3.0V TUE at VA= 5.0V
Figure 9. Figure 10.
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Typical Performance Characteristics (continued)
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
DNL INL
vs. vs.
VAVA
Figure 11. Figure 12.
3V DNL 5V DNL
vs. vs.
fSCLK fSCLK
Figure 13. Figure 14.
3V DNL 5V DNL
vs. vs.
Clock Duty Cycle Clock Duty Cycle
Figure 15. Figure 16.
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Typical Performance Characteristics (continued)
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
3V DNL 5V DNL
vs. vs.
Temperature Temperature
Figure 17. Figure 18.
3V INL 5V INL
vs. vs.
fSCLK fSCLK
Figure 19. Figure 20.
3V INL 5V INL
vs. vs.
Clock Duty Cycle Clock Duty Cycle
Figure 21. Figure 22.
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Typical Performance Characteristics (continued)
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
3V INL 5V INL
vs. vs.
Temperature Temperature
Figure 23. Figure 24.
Zero Code Error Zero Code Error
vs. vs.
fSCLK Clock Duty Cycle
Figure 25. Figure 26.
Zero Code Error Full-Scale Error
vs. vs.
Temperature fSCLK
Figure 27. Figure 28.
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Typical Performance Characteristics (continued)
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
Full-Scale Error Full-Scale Error
vs. vs.
Clock Duty Cycle Temperature
Figure 29. Figure 30.
Supply Current Supply Current
vs. vs.
VATemperature
Figure 31. Figure 32.
5V Glitch Response Power-On Reset
Figure 33. Figure 34.
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Typical Performance Characteristics (continued)
fSCLK = 30 MHz, TA= 25C, Input Code Range 12 to 1011, unless otherwise stated
3V Wake-Up Time 5V Wake-Up Time
Figure 35. Figure 36.
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VA
R
R
R
R
To Output Amplifier
R
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FUNCTIONAL DESCRIPTION
DAC Section
The DAC101S101 is fabricated on a CMOS process with an architecture that consists of a resistor string and
switches that are followed by an output buffer. The power supply serves as the reference voltage. The input
coding is straight binary with an ideal output voltage of:
VOUT = VAx (D / 1024)
where
•Dis the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value
between 0 and 1023 (2)
Resistor String
The resistor string is shown in Figure 37. This string consists of 1024 equal valued resistors in series with a
switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that
the DAC is monotonic.
Figure 37. DAC Resistor String
Output Amplifier
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the
amplifier are described in the Electrical Characteristics Tables.
Serial Interface
The three-wire interface is compatible with SPI, QSPI and MICROWIRE as well as most DSPs. See the Timing
Diagram for information on a write sequence.
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A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be
brought high for the minimum specified time before the next write sequence so that a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write
sequences to minimize power consumption.
Input Shift Register
The input shift register, Figure 38, has sixteen bits. The first two bits are "don't cares" and are followed by two
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing
Diagram, Figure 4.
Figure 38. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation.
Power-On Reset
The power-on reset circuit controls the output voltage during power-up. The DAC register is filled with zeros and
the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC.
Power-Down Modes
The DAC101S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the
control register.
Table 1. Modes of Operation
DB13 DB12 Operating Mode
0 0 Normal Operation
0 1 Power-Down with 1kΩto GND
1 0 Power-Down with 100kΩto GND
1 1 Power-Down with Hi-Z
When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of
these bits the supply current drops to its power-down level and the output is pulled down with either a 1kΩor a
100KΩresistor, or is in a high impedance state, as described in Table 1.
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC register are unaffected when in power-down. Minimum
power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The
time to exit power-down (Wake-Up Time) is typically tWU µsec as stated in the A.C. and Timing Characteristics
Table.
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68HC11 DAC101S101
PC7
SCK
MOSI
SCLK
DIN
SYNC
80C51/80L51 DAC101S101
P3.3
TXD
RXD
SCLK
DIN
SYNC
ADSP-2101/
ADSP2103 DAC101S101
TFS
DT
SCLK
DIN
SCLK
SYNC
DAC101S101, DAC101S101-Q1
SNAS321F –JUNE 2005–REVISED MARCH 2013
www.ti.com
Applications Information
The simplicity of the DAC101S101 implies ease of use. However, it is important to recognize that any data
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
DSP/Microprocessor Interfacing
Interfacing the DAC101S101 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
ADSP-2101/ADSP2103 Interfacing
Figure 39 shows a serial interface between the DAC101S101 and the ADSP-2101/ADSP2103. The DSP should
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
Figure 39. ADSP-2101/2103 Interface
80C51/80L51 Interface
A serial interface between the DAC101S101 and the 80C51/80L51 microcontroller is shown in Figure 40. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is to transmitted to the DAC101S101. Since the 80C51/80L51 transmits 8-
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC101S101 requires data with the MSB first.
Figure 40. 80C51/80L51 Interface
68HC11 Interface
A serial interface between the DAC101S101 and the 68HC11 microcontroller is shown in Figure 41. The SYNC
line of the DAC101S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
Figure 41. 68HC11 Interface
16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DAC101S101 DAC101S101-Q1
LM4050-4.1
or
LM4050-5.0
DAC101S101
DIN
SCLK
SYNC VOUT = 0V to 5V
0.47 PF
Input
Voltage
R
VZ
LM4130-4.1
DAC101S101
DIN
SCLK
SYNC VOUT = 0V to 4.092V
C1
0.1 PFC2
2.2 PF
Input
Voltage
MICROWIRE
DEVICE
DAC101S101
CS
SK
SO
SCLK
DIN
SYNC
DAC101S101, DAC101S101-Q1
www.ti.com
SNAS321F –JUNE 2005–REVISED MARCH 2013
Microwire Interface
Figure 42 shows an interface between a Microwire compatible device and the DAC101S101. Data is clocked out
on the rising edges of the SCLK signal.
Figure 42. Microwire Interface
USING References as Power Supplies
Recall the need for a quiet supply source for devices that use their power supply voltage as a reference voltage.
Since the DAC101S101 consumes very little power, a reference source may be used as the supply voltage. The
advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise
regulators can also be used for the power supply of the DAC101S101. Listed below are a few power supply
options for the DAC101S101.
LM4130
The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the
DAC101S101. Its primary disadvantage is the lack of a 3V and 5V versions. However, the 4.096V version is
useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the VIN pin with a 0.1µF capacitor and
the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a
space-saving 5-pin SOT-23.
Figure 43. The LM4130 as a power supply
LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the
DAC101S101. It does not come in a 3 Volt version, but 4.096V and 5V versions are available. It comes in a
space-saving 3-pin SOT-23.
Figure 44. The LM4050 as a power supply
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DAC101S101 DAC101S101-Q1
LP3985
DAC101S101
DIN
SCLK
SYNC VOUT = 0V to 5V
1 PF0.1 PF
Input
Voltage
0.01 PF
DAC101S101, DAC101S101-Q1
SNAS321F –JUNE 2005–REVISED MARCH 2013
www.ti.com
The minimum resistor value in the circuit of Figure 44 should be chosen such that the maximum current through
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the
DAC101S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its
minimum current for regulation plus the maximum DAC101S101 current in full operation. The conditions for
minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value
at its maximum due to tolerance, and the DAC101S101 draws its maximum current. These conditions can be
summarized as
R(min) = ( VIN(max) −VZ(min) / (IA(min) + IZ(max))
where
• VZ(min) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
• IZ(max) is the maximum allowable current through the LM4050
• IA(min) is the minimum DAC101S101 supply current (3)
and R(max) = ( VIN(min) −VZ(max) / (IA(max) + IZ(min) )
where
• VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
• IZ(min) is the minimum current required by the LM4050 for proper regulation
• IA(max) is the maximum DAC101S101 supply current (4)
LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC101S101. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes
in a space-saving 5-pin SOT-23 and 5-bump micro SMD packages.
Figure 45. Using the LP3985 regulator
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF
ceramic capacitor with an ESR requirement of 5mΩto 500mΩis required at the output. Careful interpretation
and understanding of the capacitor specification is required to ensure correct device operation.
LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3.0V, 3.3V and 5V versions, among others.
18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DAC101S101 DAC101S101-Q1
DAC101S101
DIN
SCLK
SYNC VOUT
0.1 PF
+
10 PF
+
-
+5V
R1
R2
-5V
+5V
±5V
10 pF
LP2980
DAC101S101
DIN
SCLK
SYNC VOUT = 0V to 5V
1 PF
Input
Voltage ON / OFF
VIN VOUT
DAC101S101, DAC101S101-Q1
www.ti.com
SNAS321F –JUNE 2005–REVISED MARCH 2013
Figure 46. Using the LP2980 regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
Bipolar Operation
The DAC101S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 47. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
Figure 47. Bipolar Operation
The output voltage of this circuit for any code is found to be
VO= (VAx (D / 1024) x ((R1 + R2) / R1) - VAx R2 / R1)
where
• D is the input code in decimal form
• With VA= 5V and R1 = R2 (5)
VO= (10 x D / 1024) - 5V (6)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-to-Rail Amplifiers
AMP PKGS Typ VOS Typ ISUPPLY
LMC7111 SOT-23-5 0.9 mV 25 µA
SOIC-8
LM7301 0.03 mV 620 µA
SOT-23-5
LM8261 SOT-23-5 0.7 mV 1 mA
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: DAC101S101 DAC101S101-Q1
DAC101S101, DAC101S101-Q1
SNAS321F –JUNE 2005–REVISED MARCH 2013
www.ti.com
Layout, Grounding, and Bypassing
For best accuracy and minimum noise, the printed circuit board containing the DAC101S101 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There should be a single ground plane. A single
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC101S101. Special care is required to
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC101S101 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to
the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC101S101 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines should have controlled impedances.
20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: DAC101S101 DAC101S101-Q1
DAC101S101, DAC101S101-Q1
www.ti.com
SNAS321F –JUNE 2005–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 20
Copyright © 2005–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: DAC101S101 DAC101S101-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DAC101S101CIMK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X63C
DAC101S101CIMKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X63C
DAC101S101CIMM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 105 X62C
DAC101S101CIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X62C
DAC101S101CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 105 X62C
DAC101S101QCMK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X63Q
DAC101S101QCMKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 X63Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC101S101, DAC101S101-Q1 :
•Catalog: DAC101S101
•Automotive: DAC101S101-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC101S101CIMK/NOPB SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
DAC101S101CIMKX/NOP
BSOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
DAC101S101CIMM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC101S101CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC101S101CIMMX/NOP
BVSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC101S101QCMK/NOP
BSOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
DAC101S101QCMKX/NO
PB SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC101S101CIMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0
DAC101S101CIMKX/NOP
BSOT DDC 6 3000 210.0 185.0 35.0
DAC101S101CIMM VSSOP DGK 8 1000 210.0 185.0 35.0
DAC101S101CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
DAC101S101CIMMX/NOP
BVSSOP DGK 8 3500 367.0 367.0 35.0
DAC101S101QCMK/NOPB SOT DDC 6 1000 210.0 185.0 35.0
DAC101S101QCMKX/NOP
BSOT DDC 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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