This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004 1
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
Document Title
4Bank x 2M x 16bits Synchronous DRAM
Revision History
Revision No. History Draft Date Remark
0.1 Initial Draft February 2004 Preliminary
0.2 Correcte Erratum of IDD5 Current Spec. APRIL 2004 Preliminary
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.2 / Apr. 2004 2
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
DESCRIPTION
The Hynix HY5W26D(L)F(P)-H is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5W26D(L)F(P)-H is organized as 4banks of 2,097,152x16.
HY5W26D(L)F(P)-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
ORDERING INFORMATION
Part No. Clock
Frequency
CAS
Latency Power Organization Package
HY5W26DF-H
133MHz 3
Normal
4Banks x 2Mbits
x16
54Ball FBGA, Lead
HY5W26DFP-H 54Ball FBGA, Lead Free
HY5W26DLF-H Low
power
54Ball FBGA, Lead
HY5W26DLFP-H 54Ball FBGA, Lead Free
• Voltage : VDD, VDDQ 2.5V supply voltage
• All device pins are compatible with LVTTL interface
• 54Ball FBGA
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation
• Auto refresh and self refresh
• 4096 Refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Burst Read Single Write operation
Rev. 0.2 / Apr. 2004 3
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
Ball CONFIGURATION
54 Ball
FBGA
0.8mm
Ball Pitch
<Bottom View>
987321
A
B
C
D
E
F
G
H
J
54 Ball
FBGA
0.8mm
Ball Pitch
<Bottom View>
987321
A
B
C
D
E
F
G
H
J
H
J
B
C
D
A
G
F
E
VSS
DQ14
DQ12
DQ10
DQ8
UDQM
NC
A8
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BA1
A1
A2
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
1 2 3 7 8 9
< Top View >
Rev. 0.2 / Apr. 2004 4
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
Ball FUNCTION DESCRIPTIONS
Ball Out SYMBOL TYPE DESCRIPTION
F2 CLK INPUT Clock : The system clock input. All other inputs are registered to the SDRAM
on the rising edge of CLK
F3 CKE INPUT Clock Enable : Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend or self refresh
G9 CS INPUT Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM
G7,G8 BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
H7, H8, J8,
J7, J3, J2,
H3, H2, H1,
G3, H9, G2
A0 ~ A11 INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
F8, F7, F9 RAS, CAS,
WE INPUT Command Inputs : RAS, CAS and WE define the operation
Refer function truth table for details
F1, E8 UDQM,
LDQM INPUT Data Mask:Controls output buffers in read mode and masks input data in
write mode
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1,
A2
DQ0 ~
DQ15 I/O Data Input/Output:Multiplexed data input/output pin
A9, E7, J9,
A1, E3, J1 VDD/VSS SUPPLY Power supply for internal circuits
A7, B3, C7,
D3, A3, B7,
C3, D7
VDDQ/VSSQ SUPPLY Power supply for output buffers
E2, G1 NC - No connection : These pads should be left unconnected
Rev. 0.2 / Apr. 2004 5
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM
Internal Row
Counter
Column
Pre
Decoder
Column Add
Counter
Self Refresh
Logic & Timer
Sense AMP & I/O Gate
I/O Buffer & Logic
Address
Register Burst
Counter
Mode Register
State Machine Address Buffers
Bank Select
Column Active
Row Active
CAS Latency
CLK
CKE
CS
RAS
CAS
WE
U/LDQM
A0
A1
BA1
BA0
A11
Row
Pre
Decoder
Refresh
DQ0
DQ15
X-Decoder
X-Decoder
X-Decoder
X-Decoder
Y-Decoder
2Mx16 BANK 0
2Mx16 BANK 1
2Mx16 BANK 2
2Mx16 BANK 3
Memory
Cell
Array
Data Out Control
Pipe Line
Control
Rev. 0.2 / Apr. 2004 6
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
BASIC FUNCTIONAL DESCRIPTION
Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0000 OP Code 00 CAS Latency BT Burst Length
OP Code
A9 Write Mode
0Burst Read and Burst Write
1 Burst Read and Single Write
Burst Type
A3 Burst Type
0Sequential
1Interleave
Burst Length
A2 A1 A0 Burst Length
A3 = 0 A3=1
00 0 1 1
00 1 2 2
01 0 4 4
01 1 8 8
1 0 0 Reserved Reserved
1 0 1 Reserved Reserved
1 1 0 Reserved Reserved
1 1 1 Full Page Reserved
CAS Latency
A6 A5 A4 CAS Latency
0 0 0 R e s e r v e d
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 Reserved
1 0 1 R e s e r v e d
1 1 0 R e s e r v e d
1 1 1 Reserved
Rev. 0.2 / Apr. 2004 7
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
ABSOLUTE MAXIMUM RATING
DC OPERATING CONDITION (TA= 0 to 70oC )
Note : 1. All voltages are referenced to VSS = 0V
2. VDDQ must not exceed the level of VDD
3. Internal VREF = 0.9V
AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=2.5V, VSS=0V)
CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=2.5V)
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 oC
Storage Temperature TSTG -55 ~ 125 oC
Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 3.6 V
Voltage on VDD relative to VSS VDD -1.0 ~ 3.6 V
Voltage on VDDQ relative to VSS VDDQ -1.0 ~ 3.6 V
Short Circuit Output Current IOS 50 mA
Power Dissipation PD 1 W
Soldering Temperature . Time TSOLDER 260 . 10 oC . Sec
Parameter Symbol Min Typ Max Unit Note
Power Supply Voltage VDD 2.3 2.5 2.7 V 1
VDDQ 1.65 - 2.7 V 1, 2
Input High Voltage VIH 0.8*VDDQ -VDDQ+0.3 V 1, 2, 3
Input Low Voltage VIL -0.3 -0.2*VDDQ V1, 2, 3
Parameter Symbol Value Unit Note
AC Input High/Low Level Voltage VIH / VIL 2.4/0.4 V
Input Timing Measurement Reference Level Voltage Vtrip 1.4 V
Input Rise/Fall Time tR / tF1ns
Output Timing Measurement Reference Level Voltage Voutref 1.4 V
Output Load Capacitance for Access Time Measurement CL pF 1
Parameter Pin Symbol
H
Unit
Min Max
Input capacitance
CLK CI1 2.5 3.5 pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, LDQM, UDQM CI2 2.5 3.8 pF
Data input /
output capacitance DQ0 ~ DQ15 CI/O 4.0 6.5 pF
Rev. 0.2 / Apr. 2004 8
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
Note 1.
DC CHARACTERRISTICS I (TA= 0 to 70oC)
Note :
1. VIN = 0 to 2.5V, All other balls are not tested under VIN =0V
2. DOUT is disabled, VOUT=0 to 2.7V
Parameter Symbol Min Max Unit Note
Input Leakage Current ILI -1 1 uA 1
Output Leakage Current ILO -1 1 uA 2
Output High Voltage VOH VDDQ-0.2 - V IOUT = -0.1mA
Output Low Voltage VOL -0.2 V
IOUT = +0.1mA
Vtt=1.4V
RT=500 Ω
30pF
Output
DC Output Load Circuit AC Output Load Circuit
Vtt=1.4V
RT=50 Ω
30pF
Output Z0 = 50Ω
Rev. 0.2 / Apr. 2004 9
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
DC CHARACTERISTICS II (TA= 0 to 70oC)
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. HY5W26DF(P)-H
4. HY5W26DLF(P)-H
Parameter Symbol Test Condition
Speed
Unit Note
H
Operating Current IDD1 Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA 90 mA 1
Precharge Standby Current
in Power Down Mode
IDD2P CKE ≤ VIL(max), tCK = 15ns 2.0 mA
IDD2PS CKE ≤ VIL(max), tCK = ∞ 1.0 mA
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
10
mA
IDD2NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 9
Active Standby Current
in Power Down Mode
IDD3P CKE ≤ VIL(max), tCK = 15ns 5
mA
IDD3PS CKE ≤ VIL(max), tCK = ∞ 5
Active Standby Current
in Non Power Down Mode
IDD3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
2clks.
All other pins ≥ VDD-0.2V or ≤ 0.2V
20
mA
IDD3NS CKE ≥ VIH(min), tCK = ∞
Input signals are stable. 20
Burst Mode Operating Current IDD4 tCK ≥ tCK(min), IOL=0mA All banks active 120 mA 1
Auto Refresh Current IDD5 tRC ≥ tRC(min), All banks active 180 mA 2
Self Refresh Current IDD6 CKE ≤ 0.2V
Normal 2.0
mA
3
Low power 0.8 4
Rev. 0.2 / Apr. 2004 10
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter.
2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns,
then (tR/2-0.5)ns should be added to the parameter.
Parameter Symbol HUnit Note
Min Max
System Clock
Cycle Time
CAS Latency=3 tCK3 7.5 1000 ns
CAS Latency=2 tCK2 9.5 ns
Clock High Pulse Width tCHW 2.5 - ns 1
Clock Low Pulse Width tCLW 2.5 - ns 1
Access Time
From Clock
CAS Latency=3 tAC3 -5.4ns 2
CAS Latency=2 tAC2 -7.0ns
Data-out Hold Time tOH 2.5 - ns
Data-Input Setup Time tDS 2.0 - ns 1
Data-Input Hold Time tDH 1.0 - ns 1
Address Setup Time tAS 2.0 - ns 1
Address Hold Time tAH 1.0 - ns 1
CKE Setup Time tCKS 2.0 - ns 1
CKE Hold Time tCKH 1.0 - ns 1
Command Setup Time tCS 2.0 - ns 1
Command Hold Time tCH 1.0 - ns 1
CLK to Data Output in Low-Z Time tOLZ 1.0 - ns
CLK to Data Output
in High-Z Time
CAS Latency=3 tOHZ3 -5.4ns
CAS Latency=2 tOHZ2 -7.0ns
Rev. 0.2 / Apr. 2004 11
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Note : 1. A new command can be given tRC after self refresh exit.
Parameter Symbol HUnit Note
Min Max
RAS Cycle Time Operation tRC 65 - ns
RAS Cycle Time Auto Refresh tRRC 65 - ns
RAS to CAS Delay tRCD 19 - ns
RAS Active Time tRAS 45 100K ns
RAS Precharge Time tRP 19 - ns
RAS to RAS Bank Active Delay tRRD 15 - ns
CAS to CAS Delay tCCD 1-CLK
Write Command to Data-In Delay tWTL 0 - CLK
Data-in to Precharge Command tDPL 2-CLK
Data-In to Active Command tDAL tDPL + tRP
DQM to Data-Out Hi-Z tDQZ 2-CLK
DQM to Data-In Mask tDQM 0-CLK
MRS to New Command tMRD 2-CLK
Precharge to Data Output High-Z CAS Latency=3 tPROZ3 3-CLK
CAS Latency=2 tPROZ2 2-CLK
Power Down Exit Time tDPE 1-CLK
Self Refresh Exit Time tSRE 1-CLK1
Refresh Time tREF -64ms
Rev. 0.2 / Apr. 2004 12
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
COMMAND TRUTH TABLE
Note
NOTICE : Do not use to forced
Extended Mode Register Mode Set
.
- Standard SDRAMs do not Operate when entering the
Extended Mode Register Mode
.
Command CKEn-1 CKEn CS RAS CAS WE DQM ADDR A10/AP BA Note
Mode Register Set H X L L L L X OP code
No Operation H X
HX XX
XX
LHHH
Bank Active H X L L H H X RA V
Read
HXLHLHXCA
L
V
Read with Autoprecharge H
Write
HXLHLLXCA
L
V
Write with Autoprecharge H
Precharge All Banks
HXLLHLXX
HX
Precharge selected Bank LV
Burst Stop H X L H H L X X
DQM H X V X
Auto Refresh H H L L L H X X
Burst-Read-Single-WRITE H X L L L L X A9 ball High
(Other balls OP code)
MRS
Mode
Self Refresh1
Entry H L L L L H X
X
Exit L H
HX XX
X
LHHH
Precharge
power down
Entry H L
HX XX
X
X
LHHH
Exit L H
HX XX
X
LHHH
Clock
Suspend
Entry H L
HX XX
X
XLVVV
Exit L H X X
Rev. 0.2 / Apr. 2004 13
Preliminary
HY5W26D(L)F(P)-H
4Banks x 2M x 16bits Synchronous DRAM
PACKAGE INFORMATION
54 Ball 0.8mm pitch 8mm FBGA
Unit [mm]
1.20max
0.340
±
0.05
0.450
±
0.05
8.0
6.40 BSC
0.80(Typ) A1 INDEX MARK
8.00
0.80(Typ)
6.40
4.00
±
0.05
Bottom
View
0.8
3.20
±
0.05
