Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 History Initial Draft Correcte Erratum of IDD5 Current Spec. Draft Date Remark February 2004 Preliminary APRIL 2004 Preliminary This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 1 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY5W26D(L)F(P)-H is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5W26D(L)F(P)-H is organized as 4banks of 2,097,152x16. HY5W26D(L)F(P)-H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES * Voltage : VDD, VDDQ 2.5V supply voltage * Auto refresh and self refresh * All device pins are compatible with LVTTL interface * 4096 Refresh cycles / 64ms * 54Ball FBGA * Programmable Burst Length and Burst Type * All inputs and outputs referenced to positive edge of system clock * Data mask function by UDQM, LDQM * Internal four banks operation - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst * Programmable CAS Latency ; 2, 3 Clocks * Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency CAS Latency HY5W26DF-H HY5W26DFP-H HY5W26DLF-H HY5W26DLFP-H Power Organization 54Ball FBGA, Lead Normal 133MHz 3 Low power Package 4Banks x 2Mbits x16 54Ball FBGA, Lead Free 54Ball FBGA, Lead 54Ball FBGA, Lead Free This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / Apr. 2004 2 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM Ball CONFIGURATION 9 8 3 7 2 1 A B C 54 Ball D FBGA E 0.8mm Ball Pitch F G H J <Bottom View> 1 2 3 7 8 9 VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 NC VSS E VDD LDQM DQ7 UDQM CLK CKE F /CAS /RAS /WE NC A11 A9 G BA0 BA1 /CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD < Top View > Rev. 0.2 / Apr. 2004 3 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM Ball FUNCTION DESCRIPTIONS Ball Out SYMBOL TYPE DESCRIPTION F2 CLK INPUT Clock : The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK F3 CKE INPUT Clock Enable : Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh G9 CS INPUT Chip Select : Enables or disables all inputs except CLK, CKE, UDQM and LDQM G7,G8 BA0, BA1 INPUT Bank Address : Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2 A0 ~ A11 INPUT Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8 Auto-precharge flag : A10 F8, F7, F9 RAS, CAS, WE INPUT Command Inputs : RAS, CAS and WE define the operation Refer function truth table for details F1, E8 UDQM, LDQM INPUT Data Mask:Controls output buffers in read mode and masks input data in write mode A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 DQ0 ~ DQ15 I/O A9, E7, J9, A1, E3, J1 VDD/VSS SUPPLY Power supply for internal circuits A7, B3, C7, D3, A3, B7, C3, D7 VDDQ/VSSQ SUPPLY Power supply for output buffers NC - E2, G1 Rev. 0.2 / Apr. 2004 Data Input/Output:Multiplexed data input/output pin No connection : These pads should be left unconnected 4 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Low Power Synchronous DRAM Internal Row Counter Self Refresh Logic & Timer 2Mx16 BANK 3 CLK CAS Column Active U/LDQM A0 Address Buffers BA1 DQ0 DQ15 Y-Decoder Column Add Counter Bank Select A11 Memory Cell Array Column Pre Decoder WE A1 2Mx16 BANK 0 I/O Buffer & Logic Refresh 2Mx16 BANK 1 Sense AMP & I/O Gate State Machine RAS 2Mx16 BANK 2 X-Decoder X-Decoder X-Decoder X-Decoder CKE CS Row Pre Decoder Row Active Address Register Mode Register Burst Counter CAS Latency Data Out Control Pipe Line Control BA0 Rev. 0.2 / Apr. 2004 5 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length OP Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 0 1 0 1 1 0 1 0 A2 A1 A0 1 0 0 0 2 0 1 3 0 Reserved 1 Burst Length A3 = 0 A3=1 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 Reserved 1 0 0 Reserved Reserved Reserved 1 1 0 Reserved 1 0 1 Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Rev. 0.2 / Apr. 2004 6 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM ABSOLUTE MAXIMUM RATING Symbol Rating Unit Ambient Temperature Parameter TA 0 ~ 70 oC Storage Temperature TSTG -55 ~ 125 oC VIN, VOUT VDD VDDQ IOS PD -1.0 ~ 3.6 -1.0 ~ 3.6 -1.0 ~ 3.6 50 1 V V V mA W TSOLDER 260 . 10 Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature . Time oC . Sec DC OPERATING CONDITION (TA= 0 to 70oC ) Parameter Symbol VDD VDDQ VIH VIL Power Supply Voltage Input High Voltage Input Low Voltage Min 2.3 1.65 0.8*VDDQ -0.3 Typ 2.5 - Max 2.7 2.7 VDDQ+0.3 0.2*VDDQ - Unit V V V V Note 1 1, 2 1, 2, 3 1, 2, 3 Note : 1. All voltages are referenced to VSS = 0V 2. VDDQ must not exceed the level of VDD 3. Internal VREF = 0.9V AC OPERATING TEST CONDITION (TA= 0 to 70 oC, VDD=2.5V, VSS=0V) Parameter AC Input High/Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise/Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Symbol VIH / VIL Vtrip tR / tF Voutref CL Value 2.4/0.4 1.4 1 1.4 Unit V V ns V pF Note 1 CAPACITANCE (TA= 0 to 70 oC, f=1MHz, VDD=2.5V) H Parameter Input capacitance Data input / output capacitance Rev. 0.2 / Apr. 2004 Pin Symbol Unit Min Max CLK CI1 2.5 3.5 pF A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM CI2 2.5 3.8 pF DQ0 ~ DQ15 CI/O 4.0 6.5 pF 7 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM Note 1. Vtt=1.4V Vtt=1.4V RT=500 Output RT=50 Output Z0 = 50 30pF 30pF DC Output Load Circuit AC Output Load Circuit DC CHARACTERRISTICS I (TA= 0 to 70oC) Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH VDDQ-0.2 - V IOUT = -0.1mA Output Low Voltage VOL - 0.2 V IOUT = +0.1mA Note : 1. VIN = 0 to 2.5V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 2.7V Rev. 0.2 / Apr. 2004 8 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM DC CHARACTERISTICS II (TA= 0 to 70oC) Parameter Symbol Speed Test Condition H Unit Note 1 Operating Current IDD1 Burst length=1, One bank active tRC tRC(min), IOL=0mA 90 mA Precharge Standby Current in Power Down Mode IDD2P CKE VIL(max), tCK = 15ns 2.0 mA IDD2PS CKE VIL(max), tCK = 1.0 mA IDD2N CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V 10 IDD2NS CKE VIH(min), tCK = Input signals are stable. 9 IDD3P CKE VIL(max), tCK = 15ns 5 IDD3PS CKE VIL(max), tCK = 5 IDD3N CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V 20 IDD3NS CKE VIH(min), tCK = Input signals are stable. 20 Burst Mode Operating Current IDD4 tCK tCK(min), IOL=0mA All banks active 120 mA 1 Auto Refresh Current IDD5 tRC tRC(min), All banks active 180 mA 2 Self Refresh Current IDD6 CKE 0.2V Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Normal mA mA mA 2.0 3 mA Low power 0.8 4 Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY5W26DF(P)-H 4. HY5W26DLF(P)-H Rev. 0.2 / Apr. 2004 9 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Parameter Symbol H Min Max Unit Note CAS Latency=3 tCK3 7.5 CAS Latency=2 tCK2 9.5 Clock High Pulse Width tCHW 2.5 - ns 1 Clock Low Pulse Width tCLW 2.5 - ns 1 CAS Latency=3 tAC3 - 5.4 ns CAS Latency=2 tAC2 - 7.0 ns Data-out Hold Time tOH 2.5 - ns Data-Input Setup Time tDS 2.0 - ns 1 Data-Input Hold Time tDH 1.0 - ns 1 Address Setup Time tAS 2.0 - ns 1 Address Hold Time tAH 1.0 - ns 1 CKE Setup Time tCKS 2.0 - ns 1 CKE Hold Time tCKH 1.0 - ns 1 Command Setup Time tCS 2.0 - ns 1 Command Hold Time tCH 1.0 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - ns System Clock Cycle Time Access Time From Clock CLK to Data Output in High-Z Time 1000 ns ns CAS Latency=3 tOHZ3 - 5.4 ns CAS Latency=2 tOHZ2 - 7.0 ns 2 Note : 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 0.2 / Apr. 2004 10 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol H Min Max Unit RAS Cycle Time Operation tRC 65 - ns RAS Cycle Time Auto Refresh tRRC 65 - ns RAS to CAS Delay tRCD 19 - ns RAS Active Time tRAS 45 100K ns RAS Precharge Time tRP 19 - ns RAS to RAS Bank Active Delay tRRD 15 - ns CAS to CAS Delay tCCD 1 - CLK Write Command to Data-In Delay tWTL 0 - CLK Data-in to Precharge Command tDPL 2 - CLK Data-In to Active Command tDAL tDPL + tRP DQM to Data-Out Hi-Z tDQZ 2 - CLK DQM to Data-In Mask tDQM 0 - CLK MRS to New Command tMRD 2 - CLK Precharge to Data Output High-Z CAS Latency=3 tPROZ3 3 - CLK CAS Latency=2 tPROZ2 2 - CLK Power Down Exit Time tDPE 1 - CLK Self Refresh Exit Time tSRE 1 - CLK Refresh Time tREF - 64 ms Note 1 Note : 1. A new command can be given tRC after self refresh exit. Rev. 0.2 / Apr. 2004 11 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 ball High (Other balls OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh1 X Precharge power down Clock Suspend Exit L H Entry H L Exit L H X ADDR A10/AP BA RA X Note V L H L H V V H X L V MRS Mode X X X X X X X Note NOTICE : Do not use to forced Extended Mode Register Mode Set. - Standard SDRAMs do not Operate when entering the Extended Mode Register Mode. Rev. 0.2 / Apr. 2004 12 Preliminary HY5W26D(L)F(P)-H 4Banks x 2M x 16bits Synchronous DRAM PACKAGE INFORMATION 54 Ball 0.8mm pitch 8mm FBGA Unit [mm] 8.0 6.40 BSC 0.80(Typ) 0.8 A1 INDEX MARK 0.80(Typ) 0.450 0.05 View 3.20 0.05 4.00 0.05 8.00 6.40 Bottom 0.3400.05 1.20 max Rev. 0.2 / Apr. 2004 13