Document Number: MMA16xxKW
Rev. 4, 03/2012
Freescale Semiconductor
Data Sheet: Technical Data
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
DSI Inertial Sensor
The MMA16xxKW family , a SafeAssure solution, includes the DSI2.5 compatible
overdamped Z-axis satellite accelerometers.
Features
• ±50g to ±312.5g Nominal Full-Scale Range
• Selectable 180 Hz, 2-pole, 400 Hz, 4-pole, or 800 Hz, 4-pole LPF
• DSI2.5 Compatible with full support of Mandatory Commands
• Internal High Side Bus Switch for DSI2.5 Daisy Chain Applicati ons
• 16 μs internal sample rate, with interpolation to 1 ms
• -40°C to 125°C Operating Temperature Range
• Pb-Free 16-Pin QFN, 6 by 6 Package
• Qualified AECQ100, Revision G, Grade 1 (-40°C to +125°C)
(http://www.aecouncil.com/)
Typical Applications
• Airbag Front and Side Crash Detection
For user register array programming, please consult your Freescale representative.
ORDERING INFORMATION
Device Axis Range Package Shipping
MMA1605KW Z 50g 2086-01 Tubes
MMA1606KW Z 62.5g 2086-01 Tubes
MMA1612KW Z 125g 2086-01 Tubes
MMA1618KW Z 187g 2086-01 Tubes
MMA1631KW Z 312g 2086-01 Tubes
MMA1605KWR2 Z 50g 2086-01 Tape & Reel
MMA1606KWR2 Z 62.5g 2086-01 Tape & Reel
MMA1612KWR2 Z 125g 2086-01 Tape & Reel
MMA1618KWR2 Z 187g 2086-01 Tape & Reel
MMA1631KWR2 Z 312g 2086-01 Tape & Reel
MMA16xxKW
16-PIN QFN
CASE 2086-01
PIN CONNECTIONS
Bottom View
Top View
TEST2
BUSRTN
TEST7
V
SS
TEST6
TEST5
BUSIN
HCAP
C
REGA
TEST4
C
REG
TEST3
TEST1
BUSOUT
V
SSA
PCM
1
2
3
4
5 6 7 8
12
11
10
9
16 15 14 13
17
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Application Diagram
Figure 1. Applicatio n Diag ram
Device Orientation
Figure 2. Device Orientation Diagram
External Component Recommendatio ns
Ref Des Type Description Purpose
C1 Ceramic 100 pF ≤ C1 ≤ 1000 pF 10%, 50V, X7R BUSIN Power Supply Decoupling, ESD
C2 Ceramic 100 pF ≤ C2 ≤ 1000 pF, 10%, 50V, X7R BUSOUT Power Supply Decoupling, ESD
C3 Ceramic, Tantalum 1 μF ≤ C3 ≤ 100 μF, 10%, 50V, X7R Reservoir Capacitor for Keep Alive during Signaling
C4 Ceramic 1 μF, 10%, 10V, X7R Voltage Regulator Output Capacitor (CREG)
C5 Ceramic 1 μF, 10%, 10V, X7R Voltage Regulator Output Capacitor (CREGA)
VSS
VCC BUSIN
BUSRTN
TEST1
TEST3
TEST4
TEST5
MMA16xx
BUSOUT
BUSIN
BUSRTN
BUSOUT
TEST6
HCAP
VSSA
CREG
CREGA
C1
C2
C3
C4 C5
TEST7
PCM
VSS
TEST2
Z: 0 g
EARTH GROUND
Z: 0 g Z: 0 g Z: 0 g Z: +1 g Z: -1 g
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
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Internal Block Diagram
Figure 3. Block Diagram
SELF-TEST
INTERFACE
CONTROL
LOGIC
OTP
ARRAY
FUSE
ΣΔ
CONVERTER
CONTROL
IN STATUS
OUT
OSCILLATOR
g-CELL
LOW-VOLTAGE
RESET
SERIAL
ENCODER
HCAP
PCM
HCAP
DIGITAL
REGULATOR
VOLTAGE
ANALOG
REGULATOR
VOLTAGE
CREG
CREGA
VREGA
VREG
VREG
VREGA VREG
REFERENCE
VOLTAGE
VREF VSSA
TEST5
TEST
TEST6
TEST3
TEST4
BUSIN
BUSOUT VDSI_REF
VDSI_REF
BUSRTN
VSS
1z
D–
–
D1z
1–
–()×
--------------------------------- 3
SINC Filter Compensation
Low-Pass Filter
IIR PCM Encoder
DSP
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1 Pin Connections
Figure 4. Block Diagram
Table 1. Pin Description
Pin Pin
Name Formal Name Definition
1TEST2 Test Pin This pin must be left unconnected in the applicat ion.
2TEST3 Test Pin This pin must be grounded in the application.
3TEST1 Test Pin This pin must be grounded in the application.
4BUSRTN Ground This pin is the common return for power and signalling.
5PCM PCM
Output This pin provides a 4 MHz PCM signal proportional to the accel eration data for test purposes. The output can be enabled or
disabled via OTP. If unused, this pin must be left unconnected in the application. Reference Section 3.5.3. 6.
6BUSOUT BUS output This pin is internally connect ed to BUSIN thro ugh a switch. For da isy chain configur ations, this pi n is connected to the BUSIN
pin of the next slave on the DSI bus. The in ternal bus switch is open f ollowing r eset, and is closed when an Initi alization com-
mand is received.
7BUSIN Supply /
Comm This pin is connected to the DSI positive bus node and provides th e power suppl y and communica tio n to the syst em master.
An external capacitor must be conn ected to between this pin and the BUSRTN pin. Refere nce Figure 1.
8HCAP Hold Capacitor This pin rectifies the supply voltage on the BUSIN pin to create the supply voltage for the de vice. An external capacitor must
be connected between this pin and the BUSRTN pin to store ener gy for operation during master communication signalling.
Reference Figure 1.
9 CREG Digital
Supply This pin is connected to the power supply for the internal digital circuitry. An external capacitor must be connected between
this pin and VSS. Reference Figure 1.
10 TEST4 Test Pin This pin must be grounded in the application.
11 CREGA Analog
Supply This pin is connected to the power supply for the internal ana log circuitry. An external capacitor must be connected between
this pin and VSSA. Reference Figure 1.
12 VSSA Analog GND This pin is the power supply return node for analog circuitry.
13 TEST5 Test Pin This pin enables test mode, and pro vid es the SPI programming voltage in test mode. This pin is must be grounded in the
application.
14 TEST6 Test Pin This pin must be grounded in the application.
15 TEST7 Test Pin This pin must be grounded in the application.
16 VSS Digital GND This pin is the power supply return node for the digital circuitry.
17 PAD Die Attach Pa d This pin is the die attach flag, and should be connected to VSS i n the application. Reference Section 5.
Corner
Pads Corner Pads The corner pads are internally connect ed to VSS.
TEST2
BUSRTN
TEST7
V
SS
TEST6
TEST5
BUSIN
H
CAP
C
REGA
TEST4
C
REG
TEST3
TEST1
BUSOUT
V
SSA
PCM
1
2
3
4
5678
12
11
10
9
16 15 14 13
17
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2 Electrical Characteristics
2.1 Maximum Rati ngs
Maximum ratings are the extreme limits to which the device ca n be exposed without permanently damaging it. Do not apply
voltages higher than those shown in the table below.
2.2 Operating Range
The operating ratings are the limits normally expected in the application.
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#Rating Symbol Value Unit
1
2Supply Voltage (continuous) (BUSIN,BUSOUT, HCAP)
Supply Voltage (pulsed < 400 ms, repet ition rate 60s) (BUSIN,BUSOUT, HCAP) VCC
VCC -0.3 to +30.0
-0.3 to +34.0 V
V(3)
(3)
3C
REG, CREGA, PCM, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 -0.3 to +3.0 V (3)
4
5
BUSIN,BUSOUT, BUSRTN and HCAP Current
Maximum duration 1s
Continuous IIN
IIN 400
75 mA
mA (3)
(3)
6 Powered Shock (six sides, 0.5 ms duration) gpms ±2000 g (5)
7 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (5)
8 Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation) hDROP 1.2 m (5)
9
10
11
Electrostatic Discharge (per AEC100)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0Ω)
MM (200 pF, 0Ω)
VESD
VESD
VESD
±2000
±500
±200
V
V
V
(5)
(5)
(5)
12
13
Temperature Range
Storage
Junction Tstg
TJ-40 to +125
-40 to +150 °C
°C (3)
(3)
14 Thermal Resistance θJC 2.5 °C/W (11)
#Characteristic Symbol Min Typ Max Units
15
16
Supply Voltage
VHCAP
BUSIN VHCAP
VBUS
VL
6.3
-0.3 ⎯
⎯
VH
30
30 V
V(1,12)
(1,12)
17 Programming Voltage
Applied to BUSIN (DSI) VPP 14.0 ⎯30.0 V (3)
18 Programming Current
BUSIN IPP 85 ⎯⎯mA (3)
19
20
Operating Temperature Rang e TA
TA
TL
-40
-40 ⎯
⎯
TH
+105
+125 °C
°C (1)
(3)
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2.3 E lectrical Characteristics - Supply and I/O
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
2.4 E lectrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#Characteristic Symbol Min Typ Max Units
21 Quiescent Supply Current * IDD ⎯⎯8.0 mA (1)
22 Inrush Current (excluding HCAP Capacitor charge current)
Power On until VREG Stable IINRUSH ⎯⎯20 mA (3)
23
24
Internally Regulated Voltages
VREG
VREGA VREG
VREGA 2.425
2.425 2.50
2.50 2.575
2.575 V
V(1)
(1)
25
26
27
VHCAP Under-Voltage Detection (See Figure 5)
Under-Voltage Detection Threshold
VHCAP Recovery Threshold
Hysteresis (VPORHCAP_r - VPORHCAP_f)
VPORHCAP_f
VPORHCAP_r
VHYST_HCAP
5.8
⎯
70
6.0
⎯
100
6.2
6.3
140
V
V
mV
(3,6)
(3,6)
(3)
28
29
30
31
Internal Regulator Low Voltage Detection Thr eshold
VREG Falling
VREGA Falling
Hysteresis
VREG
VREGA
VPORVREG_f
VPORVREGA_f
VHYST_VREG
VHYST_VREGA
2.15
2.15
0.05
0.05
2.25
2.25
0.10
0.10
2.40
2.40
0.15
0.15
V
V
V
V
(3.6)
(3.6)
(3)
(3)
32
33
External Capacitor (CREG, CREGA)
Capacitance
ESR (including interconnect resistance)
CREG, CREGA
RCREGESR,
RCREGAESR
500
⎯1000
⎯1500
200 nF
mΩ(9)
(9)
34 Output High Voltage (PCM)
ILoad = 100 μAV
OH VREG - 0.1 ⎯⎯V(9)
35 Output Low Voltage (PCM)
ILoad = 100 μAV
OL ⎯⎯0.1 V (9)
36
37
Temperature Monitoring
Under-Temperature Monitor Threshold
Over-Temperature Monitor Threshold TUNDER
TOVER
⎯
155 ⎯
⎯-55
⎯°C
°C (9)
(9)
#Characteristic Symbol Min Typ Max Units
38 BUSOUT Bus Switch Resistance
0V ≤ VBUSIN ≤ 30 V, ISW = 160 mA *R
SW ⎯4.0 8.0 Ω(1)
39 HCAP Rectifier Leakage Current
VBUSIN = 0 V, VHCAP = 9.0V * IRLKG ⎯⎯100 μA(1)
40
41
BUSIN to HCAP Rectifier Voltage Drop (VBUSIN = 7 V)
IHCAP = -15 mA
IHCAP = -100 mA *
*VRECT
VRECT
⎯
⎯0.75
0.9 1.0
1.2 V
V(1)
(1)
42
43
BUSIN Bias Current
VBUSIN = 8.0V, VHCAP = 9.0V
VBUSIN = 4.5V, VHCAP = 24V, No Response Current *I
BUSIN_BIAS
IBUSIN_BIAS -100
-100 ⎯
⎯100
100 μA
μA(1)
(1)
44
45
BUSOUT Bias Current
VBUSOUT = 8.0V, VHCAP = 9.0V
VBUSOUT = 4.5V, VHCAP = 24 V, No Response Current *I
BUSOUT_BIAS
IBUSOUT_BIAS -100
-100 ⎯
⎯100
100 μA
μA(1)
(1)
46 BUSOUT Discharge Resistance RBUSOUT_Discharge 3500 ⎯8000 Ω(3)
47 BUSIN Response Current
VBUSIN = 4.0 V *IRESP 9.9 11 12.1 mA (1)
48
49
BUSIN to BUSOUT Leakage Current (BUS SWITCH open)
VBUSIN = 24.0V, VBUSOUT = 0V
VBUSIN = 0V, VBUSOUT = 16V *I
SW_Leak
IRSW_Leak -20
-20 ⎯
⎯20
20 μA
μA(1)
(1)
50
51
BUSIN Logic Thresholds
Signal Threshold
Frame Threshold *
*VTHS
VTHF 2.8
5.5 3.0
6.0 3.2
6.5 V
V(1)
(1)
52
53
BUSIN Logic Hysteresis
Signal
Frame *
*VHYSS
VHYSF 30
100 ⎯
⎯90
300 mV
mV (3)
(3)
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2.5 Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#Characteristic Symbol Min Typ Max Units
54
55
56
57
58
59
60
Sensitivity (10-bit @ 100Hz referenced to 0 Hz)
50g Range
62.5g Range
125g Range
187g Range
312g Range
Total Sensitivity Error (including non-linearity)
TA = 25°C
TL ≤ TA ≤ TH
*
*
*
*
*
*
*
SENS
SENS
SENS
SENS
SENS
ΔSENS_25
ΔSENS
⎯
⎯
⎯
⎯
⎯
-5
-7
10.24
8.192
4.096
2.731
1.638
⎯
⎯
⎯
⎯
⎯
⎯
⎯
+5
+7
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
%
%
(1,14)
(1,14)
(1,14)
(1,14)
(1,14)
(1)
(1)
61 Digital Offset
10-bit output * OFF10Bit 460 512 564 LSB (1)
62
63
Range of Output (10-Bit Mode)
Acceleration
Internal Error RANGEACC
RANGEERR 1
⎯
⎯
01023
⎯LSB
LSB (3)
(3)
64
65
Cross-Axis Sensitivity
X-axis to Z-axis
Y-axis to Z-axis VXZ
VYZ -5
-5 —
—+5
+5 %
%(3)
(3)
66 ADC Output Noise Peak (1 Hz - 1 kHz, 10-Bit) nSD -4 — +4 LSB (3)
67 System Output Noise (10-Bit, RMS, All Ranges) nRMS ⎯⎯+1.2 LSB (3)
68 Non-linearity (all ranges) NLOUT -2 ⎯+2 % (3)
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2.6 E lectrical Characteristics - Self-Test and Overload
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified.
#Characteristic Symbol Min Typ Max Units
69
70
Acceleration (without hitting internal g-cell stop s)
±50g, ±62.5g, ±125g Positi ve
±50g, ±62.5g, ±125g Negative gg-cell_Clip60ZP
gg-cell_Clip60ZN 425
-1205 642
-720 980
-512 g
g(9)
(9)
71
72
Acceleration (without hitting internal g-cell stop s)
±187g, ±312g Positive
±187g, ±312g Negative gg-cell_Clip240ZP
gg-cell_Clip240ZN 1450
-3100 2180
-2210 2800
-1800 g
g(9)
(9)
73
74
ΣΔ and Sinc Filter Clipping Limit
±50g Range Positive
±50g Range Negative gADC_Clip60ZP
gADC_Clip60ZN 160
-333 238
-274 335
-216 g
g(9)
(9)
75
76
ΣΔ and Sinc Filter Clipping Limit
±62.5g Range Positive
±62.5g Range Negative gADC_Clip60ZP
gADC_Clip60ZN 160
-333 238
-274 335
-216 g
g(9)
(9)
77
78
ΣΔ and Sinc Filter Clipping Limit
±125g Range Positive
±125g Range Negative gADC_Clip120ZP
gADC_Clip120ZN 306
-693 433
-544 577
-415 g
g(9)
(9)
79
80
ΣΔ and Sinc Filter Clipping Limit
±187g Range Positive
±187g Range Negative gADC_Clip240ZP
gADC_Clip240ZN 836
-1909 1178
-1566 1599
-1245 g
g(9)
(9)
81
82
ΣΔ and Sinc Filter Clipping Limit
±312g Range Positive
±312g Range Negative gADC_Clip480ZP
gADC_Clip480ZN 836
-1909 1178
-1566 1599
-1245 g
g(9)
(9)
83
84
85
86
87
Deflection, 10-Bit, Self-Test - Offset, 30 sample ave, TA = 25°C)
±50g Range
±62.5g Range
±125g Range
±187g Range
±312g Range
*
*
*
*
*
ΔDFLCT_Z50
ΔDFLCT_Z62
ΔDFLCT_Z125
ΔDFLCT_Z187
ΔDFLCT_Z312
⎯
⎯
⎯
⎯
⎯
307
245
299
205
123
⎯
⎯
⎯
⎯
⎯
LSB
LSB
LSB
LSB
LSB
(1)
(1)
(1)
(1)
(1)
88 Self-Test deflection range, TA = 25 °CΔDFLCT -10 ⎯+10 % (1)
89 Self-Test deflection range, TL ≤ TA ≤ THΔDFLCT -20 ⎯+20 % (1)
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2.7 Dynamic Electrical Characteristics - DSI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
# Characteristic Symbol Min Typ Max Units
90
91
92
93
Reset Recovery (See Figure 20)
POR negated to 1st DSI Command (Initialization Command)
POR negated to Acceleration Data Valid (Including LPF Init)
DSI Clear Command to 1st DSI Command (Initialization Command)
DSI Clear Command to Acceleration Data Valid (Including LPF In it)
tDSI_INIT
tDSP_INIT
tDSI_INIT
tDSP_INIT
⎯
⎯
⎯
⎯
400 / fOSC
⎯
400 / fOSC
⎯
⎯
10000 / fOSC
⎯
10000 / fOSC
s
s
s
s
(7)
(7)
(7)
(7)
94 HCAP Under-Voltage Reset Delay (See Figure 5)
VHCAP < VPORHCAP_f to POR assertion tHCAP_POR ⎯880 / fOSC ⎯s(7)
95 VREG Under-Voltage Reset Delay (See Figure 6)
VREG < VPORVREG_f to POR assertion tVREG_POR ⎯⎯ 5μs(3)
96 VREGA Under-Voltage Reset Delay (See Figure 7)
VREGA < VPORVREGA_f to POR assertion tVREGA_POR ⎯⎯ 5μs(3)
97
98
99
VREG, VREGA Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Time ()
Disconnect Rate ()
tPOR_CAPTEST
tCAPTEST_TIME
tCAPTEST_RATE
⎯
⎯
⎯
12000 / fOSC
6 / fOSC
256 / fOSC
⎯
⎯
⎯
s
s
s
(7)
(7)
(7)
100 Initialization to Bus Switch Closing tBS 89 ⎯138 μs(7)
101 BUSOUT Discharge Resistance
Activation Time tBUSOUT_Discharge 9.5 10 10.5 μs(3)
102 Communication Data Rate DRATE 100 ⎯200 kbps (7)
103 Loss of Signal Reset Time
Maximum time below frame threshold tTO 2.00 ⎯4.00 ms (7)
104 BUSIN Response Current Slew Rate
1.0 mA to 9.0 mA, 9.0 to 1.0 mA tITR 0.33 ⎯10.0 mA/μs(3)
105
106
BUSIN Timing to Response Current
BUSIN Negative Voltage Transition = 3.0V to IRSP = 7.0 mA rise
BUSIN Negative Voltage Transition = 3.0V to IRSP = 5.0 mA fall tRSP_R
tRSP_F
⎯
⎯
⎯
⎯2.50
2.50 μs
μs(7)
(7)
107
108
DSI BUSIN Signal Duty Cycle
Logic ‘0’
Logic ‘1’ *
*DCL
DCH 10
60 33
67 40
90 %
%(7)
(7)
109
110
111
112
Inter-frame Separ ation Time (See Figure 8)
Following Read Write NVM Command
Following Initialization, BS = 1
Following Initialization, BS = 0
Following other DSI bus co mmands
tIFS
tIFS
tIFS
tIFS
2
200
20
20
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
ms
μs
μs
μs
(7)
(7)
(7)
(7)
113 DSI Data Latency tLAT_DSI 4 / fOSC ⎯5 / fOSC s(7)
114 Bus Switch Open Time
Reset Asserted to ISW_LEAK ≤ 20 μAtBSOPEN ⎯⎯500 μs(3)
115 OTP Program Timing
Time to program one OTP bit tPROG_BIT 64 ⎯256 μs(7)
116
117
118
119
120
121
Self-Test Response Time
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 180 Hz LPF)
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 400 Hz LPF)
Self-Test Activation time (EOFSlave to 90% ΔDFLCT_xxx, 800 Hz LPF)
Self-Test Deactivation time (EOFSlave to 10% ΔDFLCT_xxx, 800 Hz LPF)
tST_ACT_180
tST_DEACT_180
tST_ACT_400
tST_DEACT_400
tST_ACT_800
tST_DEACT_800
2.00
2.00
1.00
1.00
0.50
0.50
⎯
⎯
⎯
⎯
⎯
⎯
5.00
5.00
2.50
2.50
1.75
1.75
ms
ms
ms
ms
ms
ms
(7)
(7)
(7)
(7)
(7)
(7)
122 Error Detection Response Time
Mirror Register CRC Error to Status Flag (S) set (Factory or User Array) tCRC_Err ⎯75 / fOSC ⎯s(7)
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2.8 Dynamic Electrical Characteristics - Signal Chain
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
Notes:
1.Parameters tested 100% at final test at -40°C, 25°C, and 105°C.
2.Parameters tested 100% at probe.
3.Verified by characterization.
4.* Indicates critical characteristic.
5.Verified by qualification testing, not tested in production.
6.Parameters verified by pass/fail testing in production.
7.Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8.Verified by user system level characterization, not tested in production, or at component level.
9.Verified by Simulation.
10.Measured at final test. Self-Test activation occurs under control of the test program.
11.Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
12.Maximum voltage characterized. Minimum voltage tested 100% at final test. Maximum voltage tested 100% to 24V at final test.
13.N/A.
14.Sensitivity, and overload capability specifications w ill be reduced when 800 Hz filter is selected.
15.Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
16.Target values. Actual values to be determined during device characterization.
#Characteristic Symbol Min Typ Max Units
123 Internal Oscillator Frequen cy * fOSC 3.80 4 4.20 MHz (1)
124 Data Interpolation Latency tLAT_INTERP 64 / fOSC ⎯65 / fOSC s(7)
125
126
127
128
129
130
DSP Low-Pass Filter
Cutoff frequency LPF0 (referenced to 0 Hz)
Filter Order LPF0
Cutoff frequency LPF1 (referenced to 0 Hz)
Filter Order LPF1
Cutoff frequency LPF2 (referenced to 0 Hz)
Filter Order LPF2
fC_LPF0
OLPF0
fC_LPF1
OLPF1
fC_LPF2
OLPF2
171
⎯
380
⎯
760
⎯
180
2
400
4
800
4
189
⎯
420
⎯
840
⎯
Hz
1
Hz
1
Hz
1
(7)
(7)
(7)
(7)
(7)
(7)
131
132
Sensing Element Rolloff Frequency (-3 db)
±50g, ±62.5g, ±125g
±187g, ±312g fgcell_3dB_zlo
fgcell_3dB_zhi 798
1437 ⎯
⎯2211
2425 Hz
Hz (9)
(9)
133
134
Sensing Element Natura l Frequency
±50g, ±62.5g, ±125g
±187g, ±312g fgcell_zlo
fgcell_zhi 7000
13600 ⎯
⎯8000
15100 Hz
Hz (9)
(9)
135
136
Sensing Element Dampi ng Ratio
±50g, ±62.5g, ±125g
±187g, ±312g ζgcell_zlo
ζgcell_zhi 1.870
2.040 ⎯
⎯4.610
7.580 ⎯
⎯(9)
(9)
137
138
Sensing Element Delay (@100 Hz)
±50g, ±62.5g, ±125g
±187g, ±312g fgcell_delay100_zlo
fgcell_delay100_zhi 77
47 ⎯
⎯200
160 μs
μs(9)
(9)
139 Package Resonance Frequency fPackage 100 ⎯⎯kHz (9)
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Figure 5. VHCAP Under-Voltage Detection
Figure 6. VREG Under-Vo ltage Detection
Figure 7. VREGA Under-Voltage Detection
VPORHCAP_r
VHCAP
VPORHCAP_f
VHYST_HCAP
tHCAP_POR
UV
UV: UNDER-VOLTAGE CONDITION
EXISTS
UV
POR
VPORVREG_r
VREG
VPORVREG_f
VHYST_VREG
POR
tVREG_POR
VPORVREGA_r
VREGA
VPORVREGA_f
VHYST_VREGA
POR
tVREGA_POR
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Figure 8. DSI Bus Inter-frame Timing
tIFS_slave
tIFS_master
LOGIC ‘1’ LOGIC ‘0’
tSTART_master
tSTART_slave
BUSIN’
IRESPONSE
1mA
9mA
tRSP_R
tITR
tITR
tRSP_F
VTHS
VTHF
DSP_OUT
tLAT_DSI
tLAT_INTERP
EOFslave
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3 Functional Description
3.1 User Accessible Data Array
A user accessible data array allows for each device to be customized. The array consists of an OTP factory programmable
array , an OTP user programmable array , and read-only registers for device status. The OTP arrays incorporate independent CRC
circuitry for fault detection (reference Section 3.2). Portions of the factory programmable array are reserved for factory-pro-
grammed trim values. The user accessible data is shown in the table below.
Type codes
F: Freescale programmed OTP locationU/F:User and/or Freescale programmed OTP location.
R: Read-only registerU:User Programmed OTP locati on.
Note: Unused and Unprogrammed Spare bits always read ‘0’.
3.1.1 Device Serial Number Registers
A unique serial number is programmed into the serial number registers of each device during manufacturing. The serial num-
ber is composed of the following information:
Serial numbers begin at 1 for all produced devices in each lot, and are sequentially assigned. Lot numbers begin at 1 and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number . Depending on
lot size and quantities, all possible lot numbers and seri al numbers may not be assigned.
The serial number registers are included in the factory programmed OTP CRC verification. Reference Section 3.2.1 for details
regarding the CRC verification. Beyond this, the contents of the serial number registers have no impact on device operation or
performance, and are only used for traceability purposes.
Table 2. User Accessible Data
Byte
Addr
RA[3:0] Register Nibble Addr
WA[3:0]
Bit Function Nibble Addr
(WA[3:0])
Bit Function Type
7654 3210
$00 SN0 SN[7] SN[6] SN[5] SN[4] SN[3] SN[2] SN[1] SN[0]
F
$01 SN1 SN[15] SN[14] SN[13] SN[12] SN[11] SN[10] SN[9] SN[8]
$02 SN2 SN[23] SN[22] SN[21] SN[20] SN[19] SN[18] SN[17] SN[16]
$03 SN3 SN[31] SN[30] SN[29] SN[28] SN[27] SN[26] SN[25] SN[24]
$04 TYPE
Reference
Table 39
LPF[1] LPF[0] 0 0
Reference
Table 39
RNG[3] RNG[2] RNG[1] RNG[0]
U/F
$05 DEVCFG DEVID UNUSED UNUSED UNUSED UNUSED CRC_U[2] CRC_U[1] CRC_U[0]
$06 DEVCFG1 UD00[5] UD00[4] UD00[3] UD00[2] UD00[1] UD00[0] AT_OTP[1] AT_OTP[0]
$07 DEVCFG2 LOCK_U UNUSED PCM RESERVED ADDR[3] ADDR[2] ADDR[1] ADDR[0]
$08 UD01 UD01[7] UD01[6] UD01[5] UD01[4] UD01[3] UD01[2] UD01[1] UD01[0]
$09 UD02 UD02[7] UD02[6] UD02[5] UD02[4] UD02[3] UD02[2] UD02[1] UD02[0]
$0A UD03 UD03[7] UD03[6] UD03[5] UD03[4] UD03[3] UD03[2] UD03[1] UD03[0]
$0B UD04 UD04[7] UD04[6] UD04[5] UD04[4] UD04[3] UD04[2] UD04[1] UD04[0]
$0C UD05 UD05[7] UD05[6] UD05[5] UD05[4] UD05[3] UD05[2] UD05[1] UD05[0]
$0D UD06 UD06[7] UD06[6] UD06[5] UD06[4] UD06[3] UD06[2] UD06[1] UD06[0]
$0E UD07 UD07[7] UD07[6] UD07[5] UD07[4] UD07[3] UD07[2] UD07[1] UD07[0]
$0F UD08 UD08[7] UD08[6] UD08[5] UD08[4] UD08[3] UD08[2] UD08[1] UD08[0]
Bit Range Content
SN[12:0] Serial Number
SN[31:13 ] Lot Number
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3.1.2 Device Type Register (TYPE)
The Device Type Register is an OTP configuration register which contains device configur ation information. Bit 5 - Bit 0 are
factory programmed and are included in the factory programmed OTP CRC verification. These bits are read only to the user . Bit
7 - Bit 6 are user programmable OTP bits and are included in the user programmable OTP CRC verification.
3.1.2.1 Low-Pass Filter Selection Bits (LPF[1:0]) (TYPE[7:6])
The Low-Pass Filter selection bit selects between one of three low-pass filter options. These bits can be factory or user pro-
grammed.
This filter option is not implemented. LPF[ 1:0] must not be set to this value to guarantee proper operation and performance.
3.1.2.2 Range Selection Bits (RNG[3:0]) (TYPE[3:0])
The Range Selection Bits indicate the full-scale range of the device, as shown below. These bits are factory programmed.
Table 3. Factory Configuration Register
Location Bit
RA[3:0] Register WA[3:0] 7654WA[3:0] 3 2 1 0
$04 TYPE Bnk0 $08 LPF[1] LPF[0] 0 0 RNG[3] RNG[2] RNG[1] RNG[0]
Factory Default 0000 0000
LPF[1] LPF[0] Low-Pass Filter Selected
0 0 400 Hz, 4-Pole
0 1 Not Enabled1
1 0 180 Hz, 2-Pole
1 1 800 Hz, 4-Pole
RNG[3] RNG[2] RNG[1] RNG[0] Full-Scale Range g-Cell Design
0000 N/A N/A
0001 N/A N/A
0010 50g Medium-g
0011 62g Medium-g
0100 125g Medium-g
0101 187g High-g
0110 312g High-g
0111 N/A N/A
1000
Reserved N/A
1001
1010
1011
1100
1101
1110
1111
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3.1.3 Device Configuration Register (DEVCFG)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programma-
ble OTP array.
3.1.3.1 Device ID Bit (DEVCFG[7])
The Device ID Bit is a user programmable bit which allows the user to select between 2 device IDs. The Device ID is trans-
mitted in response to the Request ID DSI command. Reference Section 4.2.1.5 for more information regarding the Request ID
DSI command. This bit can be factory or user programmed.
3.1.3.2 User Configuration CRC (CRC_U[2:0], DEVCFG[2:0])
The User Configuration CRC bits contain the 3-bit CRC used for verification of the user programmable OTP array. Reference
Section 3.2.2 for details regarding the CRC for the user programmable OTP array . These bits can be factory or user programmed.
3.1.4 Device Configuration Register 1 (DEVCFG1)
The Device configuration register is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details.
3.1.4.1 User Specific Data 00 Bits (UD00[5:0], DEVCFG1[7:2])
The User Specific Data bit s have no imp act on the device function or performance. The bits can be programmed with user or
assembly specific information. These bits can be factory or user programmed.
3.1.4.2 Attribute Bits (AT_OTP[1:0], DEVCFG1[1:0])
The Attribute Bits are user defined bits which are transmitted in response to the Request St atus, Disable Self-Test Stimulus or
Enable Self-Test Stimulus DSI commands. The transmitted values are qualified by the LOCK_U bit as shown in the table below .
These bits can be factory or us er programmed.
Table 4. Device Cont rol Register
Location Bit
RA[3:0] Register WA[3:0] 7654WA[3:0] 3 2 1 0
$05 DEVCFG Bnk0 $0ADEVID000Bnk0 $ 09 0 CRC_U[2] CRC_U[1] CRC_U[0]
Factory Default 1000 0000
DEVID Device ID
0 ‘00110’
1 ‘00100’
Table 5. Device Control Register 1
Location Bit
RA[3:0] Register WA[3:0] 7654WA[3:0] 3 2 1 0
$06 DEVCFG1 Bnk2 $06 UD00[5] UD00[4] UD00[3] UD00[2] Bnk1 $06 UD00[1] UD00[0] AT_OTP[1] AT_OTP[0]
Factory Default 0000 0000
LOCK_U DEVCFG1 Values DSI Transmitted Values
AT_OTP[1] AT_OTP[0] AT[1] AT[0]
0XX10
1
0000
0101
1010
1111
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3.1.5 Device Configuration 2 Register (DEVCFG2)
Device configuration register 2 is a user programmable OTP register which contains device configuration information. This
register is included in the user register CRC check. Refer to Section 3.2.2 for details regarding the CRC for the user programma-
ble OTP array.
3.1.5.1 User Configuration Lock Bit (LOCK_U, DEVCFG2[7])
The LOCK_U bit is a factory or user programmed OTP bit which inhibits writes to the user configuration array when active.
Reference Section 3.2.2 for details regarding the LOCK_U bit and CRC verification.
3.1.5.2 PCM Bit (DEVCFG2[5])
The PCM Bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a Pulse Code
Modulated signal proportional to the acceleration response. Reference Section 3.5.3.6 for more information regarding the PCM
output. When the PCM output is cleared, the PCM output pin is actively pulled low. This bit can be factory or user programmed.
3.1.5.3 Device Addre s s (AD DR[ 3: 0] , DEVCF G 2[ 3: 0] )
The Device Address bits define the preprogrammed DSI Bus device address. If th e Device Addres s bits are programmed to
‘0000’, there is not preprogrammed address, and the address must be assigned via the Initialization DSI command. Reference
Section 4.2.1.1 for more details regarding the Initialization DSI co mmand. These bits can be factory or user programmed.
3.1.6 User Data Registers (UDx)
The User Dat a Re gi st ers a r e user programmab le OTP register which can be programmed with user or assembly specific in-
formation. These registers have no impact on the device performance, but are included in the user register CRC check. Refer to
Section 3.2.2 for details regarding the user register CRC check. These registers can be factory or user programmed.
Table 6. Device Cont rol Register
Location Bit
RA[3:0] Register WA[3:0] 7654WA[3:0] 3210
$07 DEVCFG2
Bnk0 $07
Bnk2 $07
Bnk3 $07
Bnk3 $0F
LOCK_U UNUSED PCM RESERVED Bnk1 $07 ADDR[3] ADDR[2] ADDR[1] ADDR[0]
Factory Default 0000 0000
Location Bit
RA[3:0] Register WA[3:0] 7654WA[3:0] 3 2 1 0
$08 UD01 Bnk2 $08 UD01[7] UD01[6] UD01[5] UD01[4] Bnk1 $08 UD01[3] UD01[2] UD01[1] UD01[0]
$09 UD02 Bnk2 $09 UD02[7] UD02[6] UD02[5] UD02[4] Bnk1 $09 UD02[3] UD02[2] UD02[1] UD02[0]
$0A UD03 Bnk2 $0A UD03[7] UD03[6] UD03[5] UD03[4] Bnk1 $0A UD03[3] UD03[2] UD03[1] UD03[0]
$0B UD04 Bnk2 $0B UD04[7] UD04[6] UD04[5] UD04[4] Bnk1 $0B UD04[3] UD04[2] UD04[1] UD04[0]
$0C UD05 Bnk2 $0C UD05[7] UD05[6] UD05[5] UD05[4] Bnk1 $0C UD05[3] UD05[2] UD05[1] UD05[0]
$0D UD06 Bnk2 $0D UD06[7] UD06[6] UD06[5] UD06[4] Bnk1 $0D UD06[3] UD06[2] UD06[1] UD06[0]
$0E UD07 Bnk2 $0E UD07[7] UD07[6] UD07[5] UD07[4] Bnk1 $0E UD07[3] UD07[2] UD07[1] UD07[0]
$0F UD08 Bnk2 $0F UD08[7] UD08[6] UD08[5] UD08[4] Bnk1 $0F UD08[3] UD08[2] UD08[1] UD08[0]
Factory Default 0000 0000
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3.2 O TP Array Lock and CRC Verification
3.2.1 Factory Programmed OTP Array Lock and CRC Verification
The Factory programmed OTP array is verified for errors with a 3-bit CRC. The CRC veri fication is enabled only when the
Factory programmed OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout in which
the internal lock bit is read as ‘1’. Automatic OTP readou ts occur only after POR or a DSI Clear Command is received.
The Factory programmed OTP array is locked by Freesca le and will always be active after POR. The CRC is continuously
calculated on the factory programmed OTP array, which incl udes the registers listed below:
Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification
uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. The calculated CRC is compared against the
CRC_F[2:0] bits. If a CRC mismatch is detected, an internal data error is set and the device responds to DSI messages as spec-
ified in Section 4.3. The CRC verification is completed on the memory registers which hold a copy of the fuse array values, not
the fuse array values.
3.2.2 User Programmable OTP Array Lock and CRC Verification
The User Programmable OTP array is independently verified for errors with a 3-bit CRC. The CRC verification is enabled only
when the User Programmable OTP array is locked and the lock is active. The lock is active only after an automatic OTP readout
in which the LOCK_U bit is read as ‘1’. Automatic OTP readouts occur only after POR or a DSI Clear Command is received.
Once the LOCK_U bit is active, the CRC is continuously calculated on the user programmable OTP Array, which includes the
registers listed below:
Bits are fed in from right to left (LSB first), and top to bottom (lower addresses first) in the register map. The CRC verification
uses a generator polynomial of g(x) = X3 + X + 1, with a seed value = ‘111’. The calculated CRC is compared against the user
programmed CRC, CRC_U[2:0 ], which is also included in the user programmable array. If a CRC mismatch is detected, an in-
ternal data error is set, and the device responds to DSI messages as specified in Section 4.3. The CRC verification is completed
on the memory registers which hold a copy of the fuse array values, not the fuse array values. Writes to the User Programmable
OTP array using the Write NVM Command will update the mirror registers and result in a change to the CRC calculation regard-
less of the state of the LOCK_U bit. A CRC mismatch will only be detected if the LOCK_U bit is active.
Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register
After Automatic Readout Lock Bit Active? CRC Verification
Enabled?
0N/A NO NO
10NONO
11 YES YES
Register Name Register Addresses Included in Factory CRC?
Serial Number Registers SN0, SN1, SN2, SN3 Yes
Type Register TYPE[5:0] Yes
Factory Programmable Device Con figuration
Bits Internal Registe r M a p Yes
Factory OTP Array CRC CRC_F[2:0] No
Factory OTP Array Lock Bit LOCK_F No
Factory Lock Bit Value in Fuse Array Lock Bit Value in Mirror Register
After Automatic Readout Lock Bit Active? CRC Verification
Enabled?
0N/A NO NO
10NONO
11 YES YES
Register Name Register Addresses Included in User CRC?
Type Register TYPE[7:6] Yes
Device ID Bit DEVCFG[7]: DEVID Yes
User Data Register 0 DEVCFG1[7:2]: UD00[5:0] Yes
Attribute Bits DEVCFG1[1:0]: AT_OTP[1:0] Yes
PCM Bit DEVCFG2[5]: PCM Yes
RESERVED Bit DEVCFG2[4] Yes
Device Address DEVCFG2[3:0]: ADDR[3:0] Yes
User Data Registers 1 - 8 UD01 - UD08 Yes
User Programmable OTP Array CRC DEVCFG[2:0]: CRC_U[2:0] No
User Programmable OTP Array Lock Bit DEVCFG2[7]: LOCK_U No
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3.3 Voltage Regulators
The device derives its internal supply voltage from the HCAP supply voltage. The device includes separate internal voltage
regulator s for th e an a l og (VREGA) and digital circuitry (VREG). External filter capacitors are required, as shown in Figure 1.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
HCAP and internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the
HCAP supply or internally regulate d voltages fall be low predetermined levels. A reference generator provides a stable voltage
which is used by the ΣΔ converter.
Figure 9. Voltage Regulation and Monitoring
3.3.1 CREG and CREGA Regulator Capacitor
The internal regulator requires an external capacitor between the CREG pin and VSS pin, and the CREGA pin and VSSA pin for
stability. Figure 1 shows the recommended types and values for each of these capacitors.
3.3.2 VHCAP Voltage Monitor
The device includes a circuit to monitor the voltage on the HCAP pin. If the voltage falls below the specified threshold in
Section 2, the device will be reset within the reset delay time (tHCAP_POR) specified in Section 2.7.
CREGA
CREG
HCAP
VOLTAGE
REGULATOR
REFERENCE
GENERATOR
VREGA = 2.50 V
DIGITAL
LOGIC
DSP
OTP
ARRAY
OSCILLATOR
ΣΔ
CONVERTER
BIAS
GENERATOR
TRIM TRIM
VREF_MOD = 1.250 V
VREG = 2.50 V
BANDGAP
REFERENCE
VBUF
V
REF
VREGA
POR
V
REF
COMPARATOR
COMPARATOR
HCAP
COMPARATOR
V
REGA
V
REG
VOLTAGE
REGULATOR
Analog Filter Delay
t
VREG_POR
Analog Filter Delay
t
VREG_POR
Digital De la y
t
HCAP_POR
VOLTAGE
REGULATOR VBUF
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3.3.3 VREG, and VREGA Under-Voltage Monitor
The device includes a circuit to monitor the internally regulated voltages (VREG and VREGA). If either of the internal regulator
voltages fall below the specified thresholds in Section 2, the device will be reset within the reset delay time (tVREG_POR,
tVREGA_POR) specified in Se cti o n 2. 7.
3.3.4 VREG and VREGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the conne ction to the external CREG or CREGA capacitor
becomes open. At a continuous rate specified in Section 2.7 (tCAPTEST_RATE), both regulators are simultaneously disabled for a
short duration (tCAPTEST_TIME). If either of the external capacitors are not present, the associated regulator voltage will fall below
the internal reset threshold, forcing a device reset.
Figure 10. VREG Capacitor Monitor
Figure 11. VREGA Capacitor Monitor
3.4 I nternal Oscillator
The device includes a factory trimmed oscillator as specified in Section 2.8.
CAP_Test
V
REG
Time
Capacitor Present
V
PORVREG_f
POR
Capacitor Open
tCAPTEST_TIME
tCAPTEST_RATE
CAP_Test
V
REGA
Time
Capacitor Present
V
PORREGA_f
POR
Capacitor Open
tCAPTEST_TIME
tCAPTEST_RATE
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3.5 Acceleration Signal Path
3.5.1 Transducer
The device transducer is an overdamped mass-spring-damper system described by the following transfer function:
where:
ζ = Damping Ratio
ωn = Natural Frequency = 2∗Π∗fn
Reference Section 2.8 for transducer parameters.
3.5.2 ΣΔ Converter
The sigma delta converter provides the interface between the g-cell and the DSP block. The output of the ΣΔ converter is a
data stream at a nominal frequency of 1 MHz.
Figure 12. ΣΔ Converter Block Diagram
3.5.3 Digital Signal Processing Block
A digital signal processing (DSP) block is used to perform signal filtering and compensation operations. A diagram illustrating
the signal processing flow within the DSP block is shown in Figure 13.
Figure 13. Signal Chain Di agram
Hs()
ωn
2
s22ξω
ns⋅⋅ ⋅ ω
n
2
++
------------------------------------------------------=
1-BIT
QUANTIZER
z-1
1 - z-1
z-1
1 - z-1
FIRST
INTEGRATOR SECOND
INTEGRATOR
α1=
β1
α2
β2
VX
CINT1
g-cell
CBOT
CTOP
ΔC = CTOP - CBOT
ΣΔ_OUT
V = ±2 × VREF
ADC
DAC
V = ΔC x VX / CINT1
ΣΔ
_OUT
Sinc Filter
1z
D–
–
D1z
1–
–()×
--------------------------------- 3
a0
n11 n12 z1–
⋅()n13 z2–
⋅()++
d11 d12 z1–
⋅()d13 z2–
⋅()++
----------------------------------------------------------------------------- n21 n22 z1–
⋅()n23 z2–
⋅()++
d21 d22 z1–
⋅()d23 z2–
⋅()++
-----------------------------------------------------------------------------
⋅⋅
Low-Pass Filter Output
OUTPUT
Compensation
ABE
CDF
Interpolation
Scaling
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3.5.3.1 Decimation Sinc Filter
The serial data stream produced by the ΣΔ converters is decimated and converted to parallel values by a 3rd order 16:1 sinc
filter with a decimation factor of 16.
Figure 14. Sinc Filter Response, tS = 16 μs
Table 7. Signal Chain Characteristics
Description Sample Time
(μs) Data Width
(Bits) Over Range
(Bits) Signal Width
(Bits) Signal Noise
(Bits) Signal Margin
(Bits) Typical Block
Latency Reference
AΣΔ 11 1 112/fosc Section 3.5.2
BSINC Filter 16 20 12 4 Section 3.5.3.1
CLow-Pass Filter 16 26 1 12 4 9 Reference
Section
3.5.3.2 Section 3.5.3.2
DCompensation 16 26 4 10 3 9 24/fosc Section 3.5.3.3
EDSP Sampling 16 10 4/fosc Section 3.5.3.5
10-Bit Output Scaling
FInterpolation 1 10 64/fosc Section 3.5.3. 5
Hz() 1z
16–
–
16 1 z 1–
–()×
-----------------------------------3
=
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3.5.3.2 Low-Pass Filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
The device provides the option for one of three low-pass filters. The filter is selected with the LPF[1:0] bits in the TYPE register.
The filter selection options are listed in Section 3.1.2.1, Table 8. Response parameters for the low-pass filter are specified in
Section 2.8. Filter characteristics are illustrated in the figures below.
Note: Low-Pass Filter Figures do not include g-cell frequency response.
Table 8. Low-Pass Filter Coefficients
Description Filter Coefficients Group Delay
180 Hz LPF
a00.000534069200512
4608/fosc
n11 0.25 d11 1
n12 0.499999985098839 d12 -1.959839582443237
n13 0.25 d13 0.960373640060425
n21 1d
21 1
n22 0d
22 0
n23 0d
23 0
400 Hz LPF
a00.003135988372378
3392/fosc
n11 0.000999420881271 d11 1.0
n12 0.001998946070671 d12 -1.892452478408814
n13 0.000999405980110 d13 0.89558845758438
n21 0.250004753470421 d21 1.0
n22 0.499986037611961 d22 -1.919075012207031
n23 0.250009194016457 d23 0.923072755336761
800 Hz LPF
a00.011904109735042
1728/fosc
n11 0.003841564059258 d11 1.0
n12 0.007683292031288 d12 -1.790004611015320
n13 0.003841534256935 d13 0.801908731460571
n21 0.250001862645149 d21 1.0
n22 0.499994158744812 d22 -1.836849451065064
n23 0.250003993511200 d23 0.852215826511383
Hz() a0
n11 z0
⋅()n12 z1–
⋅()n13 z2–
⋅()++
d11 z0
⋅()d12 z1–
⋅()d13 z2–
⋅()++
-------------------------------------------------------------------------------------------- n21 z0
⋅()n22 z1–
⋅()n23 z2–
⋅()++
d11 z0
⋅()d22 z1–
⋅()d23 z2–
⋅()++
--------------------------------------------------------------------------------------------
⋅⋅=
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Figure 15. Low-Pass Filter Characteristic s: fC = 180 Hz, 2-Pole, tS = 16 μs
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Figure 16. Low-Pass Filter Characteristic s: fC = 400 Hz, 4-Pole, tS = 16 μs
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Figure 17. Low-Pass Filter Characteristic s: fC = 800 Hz, 4-Pole, tS = 16 μs
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3.5.3.3 Compensation
The device includes internal compensation circuitry to compensate for sensor offset, sensitivity and non-lineari ty.
3.5.3.4 Data Interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is delayed one sample time. On reception of an accel eration data request, the transmitted data is inter-
polated from the two previous samples, resulting in a latency of one sample time, and a maximum signal jitter of ±1/16 of a sample
time. Reference Figure 8 for more information regarding interpolation and data latency.
3.5.3.5 Output Scaling
The 26 bit digital output from the DSP is clipped and scaled to a 10-bit or 8-Bit word which covers the acceleration range of
the device. Figure 18 shows the method used to establish the acceleration data word from the 26-bit DSP output.
Figure 18. Output Scaling Diagram
3.5.3.6 PCM Output Function
The device provides the option for a PCM output function. The PCM output is activated if the PCM bit is set in the DEVCFG2
register. When the PCM function is enabled, a 4 MHz Pulse Code Modulated signal proportional to the upper 9 bits of the accel-
eration response is output onto the PCM pin. The PCM output is intended for test use only. A block diagram of the PCM output
is shown in Figure 19.
Figure 19. PCM Output Function Block Diagra m
Over Range Signal Noise Margin
D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 ... D2 D1 D0
10-Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 Using Truncation
9-Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 D13 Using Truncation
8-Bit Data Word D21 D20 D19 D18 D17 D16 D15 D14 Using Truncation
Output Scaling
D_x[9:1]
A
9 Bit ADDER
PCM
B
CARRY
SUM
fCLK = 4 MHz
Sample updated every 16μS9
9
9
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
D
FF
CLK
Q
Q
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3.6 Device Initialization
Following powerup, unde r-voltage reset or reception of a DSI Clear Command, the device proceeds through an initialization
process as described in the following tables:
Figure 20. Initiali zation Ti ming
Table 9. Power-up or Under-Voltage Reset Initialization Process
#Description Time S Flag ST Flag DSI Response
1 Power up to a Known State 0 N/A N/A No Re sponse
3 Read Fuse Array and Copy to Memory Array (Mirror Registers) 1 0 No Response
4 Initialize DSI State Machine (the device is ready f or DSI Messages) tDSI_INIT 10DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
5 Initialize the DSP (Acceleration Data is Valid) tDSP_INIT 0 0 Normal
Table 10. DSI Clear Command Initialization Process
#Description Time S Flag ST Flag DSI Response
1 the device logic comes out of reset 0 1 0 No Response
3 Read Fuse Array and Copy to Memory Array (Mirror Registers) 1 0 No Response
4 Initialize DSI State Machine (the device is ready f or DSI Messages) tDSI_INIT 10DSI Read Acceleration Data Short response = zero.
DSI Read Acceleration Data Long response = invalid data.
5 Initialize the DSP (Acceleration Data is Valid) tDSP_INIT 0 0 Normal
tINT_INIT
BUSIN’
DSP_OUT
VPORHCAP_r
VHCAP
DSI Ready
POR
VREG
VREGA
VPORVREG_r
VPORVREGA_r
Internal Delay
tDSP_INIT
tDSI_INIT
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3.7 O verload Response
3.7.1 Overload Performance
The device is designed to operate within a specified range. However, acceleration beyond that range (overload) impacts the
operating range outp ut of the sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the
device that is dependent upon the overload frequency and amplitude. The device g-cell is overdamped, providing the optimal
design for overload performance. However , the performance of the device during an overload condition is affected by many other
parameters, including:
• g-cell damp ing
• Non-linearity
• Clipping limits
• Symmetry
Figure 21 shows the g-cell, Sigma Delta, and output clipping of the device over frequency. The relevant parameters are spec-
ified in Section 2.
Figure 21. Output Clipping Vs. Frequency
3.7.2 Sigma Delta Overrange Response
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. Th e ΣΔ converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates predict-
ably under all cases of overrange, altho ugh the signal may include residual high frequency components for some time after re-
turning to the normal range of operation due to non-linear effects of the sensor.
5kHz fg-Cell fLPF
gADC_Clip
gg-cell_Clip
Determined by g-cell
10kHz
g-cellRolloff
Acceleration (g)
Frequency (kHz)
LPFRolloff
Region Clipped by g-cell
Region Clipped by ADC
Region of Signal Distortion due to
Asymmetry and Non-Linearity
Region of No Signal Distortion Beyond
Specification
Region of Interest
roll-off and ADC clipping
gRange_Norm
Determined by g-c e ll
roll-off and full-scale range
Region Clipped
by Output
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4 DSI Protocol Layer
4.1 Communication Interface Overview
The device is compatible with the DSI Bus St andard V2.5.
4.1.1 DSI Physical Layer
Reference DSI Bus Standard V2.5, Section 3 for information regarding the physical layer.
4.1.2 DSI Data Link Layer
Reference DSI Bus Standard,V2.5, Section 4 for information regarding the DSI data link layer. The sections below describe
the DSI data link layer features supported.
4.2 DSI Protocol
4.2.1 DSI Bus Commands
DSI Bus Commands are summarized in Table 11. The device supports only the command formats specified in Section 4.2.1.
The device will ignore commands of any other format. If a CRC error is detected, or a reserved or un-implemented command is
received, the device will not respond.
Following all messages, the device requires a minimum inter-frame separation (tIFS). As long as the minimum inter-frame sep-
aration times defined in Section 4.2.1 are met, all supported commands are guaranteed to be executed, and the device will be
ready for the next message. The device will respond as appropriate during the subsequent DSI transfe r. Exactly one response
is attempted.
Table 11 . DSI Bus Command Summary
Command Command Format Data
C3 C2 C1 C0 Hex Description D7 D6 D5 D4 D3 D2 D1 D0
0000$0Initialization Standard Long Only NV BSBnk[1]Bnk[0]PA[3]PA[2]PA[1]PA[0]
0001$1Request Status Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0010$2Read Acceleration DataStandard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0011$3Not Implemented Not Implemented Not Implemented
0100$4Request ID InformationStandard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
0101$5Not Implemented Not Implemented Not Implemented
0110$6Not Implemented Not Implemented Not Implemented
0111$7Clear Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1000$8Not Implemented Not Implemented Not Implemented
1001$9Read Write NVM Standard/Enhanced LWA[3]WA[2]WA[1]WA[0]RD[3]RD[2]RD[1]RD[0]
1010$AFormat Control Standard/Enhanced LR/WFA[2]FA[1]FA[0]FD[3]FD[2]FD[1]FD[0]
1011$BRead Register Data Standard/Enhanced L 0 0 0 0 RA[3]RA[2]RA[1]RA[0]
1100$CDisable Self-Test Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1101$DActivate Self-Test Standard/Enhanced L/S⎯⎯⎯⎯⎯⎯⎯⎯
1110$ENot Implemented Not Implemented Not Implemented
1111$FReverse Initialization Not Implemented Not Implemented
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4.2.1.1 Initialization Command
The initialization command conforms to the description provided in Section 6.1.1 of the DSI Bus S tandard V2.5. The initializa-
tion command is only supporte d as a standard long comma nd. No other commands are recognized by the device until a valid
standard long initialization command is received.
Figure 22 illustrates the sequence of operations performed following negation of internal power-on reset (POR) and execution
of a DSI Initialization command. The BUSOUT node is tested for a bus short to high voltage condition, and the bus fault (BF) flag
is set if an error condition is detected. If no bus fault condition is detected and the BS bit is set in the Initialization command mes-
sage, the bus switch will be closed. The device implements a blanking time (tDSI_BLANK_INIT) to allow for the bus voltage to re-
cover following closure of the bus switch .
If the device has been preprogrammed, PA[3:0] and A[3:0] must match the preprogrammed address.
If no device address has been previously programmed into the OTP array, PA[3:0] contains the device address, and A[3:0]
must be zero. If either addressing condition is not met, the device address is not assigned, the bus switch will remain open and
the device will not respond to the Initialization comma nd. If the addressing conditions are met, the new device address is as-
signed to A[3:0]. Once the device address is assigned, the new address (A[3:0]) is not protected by the User Programmable OTP
Array CRC Verification. The User Programmable OTP array CRC is calculated and verified using the OTP programmed values
of A[3:0] = ‘0000’.
Once initialized, the device will no longer recognize or respond to Initialization commands.
Table 12. Initialization Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
NV BS Bnk[1]Bnk[0]PA[3]PA[2]PA[1]PA[0]A[3]A[2]A[1]A[0]00004 bits
Table 13. Initialization Command Bit Definitions
Bit Field Definition
C[3:0] Initialization Command = ‘0000’
A[3:0] DSI device address. This address is set to the preprogrammed device address following reset, or to ‘0000’ if no preprogrammed address
has been assigned.
PA[3:0] DSI Address to be programmed.
Bnk[1:0] These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details regarding register programming and bank selection.
BS Bus Switch state. This bit controls the state of the DSI bus switch.
1 - Close the bus switch.
0 - Do not close the bus switch.
NV
NVM Program Enable. Thi s bit enables p rogramming of the user-prog rammed OTP locat ions. Data to b e programmed is tran sferred to the
device during subsequent Read Write NVM commands.
1 - Enable OTP programming
0 - Disable OTP programming
Table 14. Initialization Command Response
Response CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
PA[3] PA[2] PA[1] PA[0] 0 0 0 BF NV BS Bnk[1] Bnk[0] PA[3] PA[2] PA[1] PA[0] 4 bits
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Figure 22. Initialization Sequence
Table 15. Init ialization Response Bit De finitions
Bit Field Definition
PA[3:0] DSI device address. Th is field contains the device address. If the device is unprogrammed when the initialization command is issued, the
device address is assigned. This field contains the programmed address. An Initialization command which attempts to assign a device
address of zero is ignored.
Bnk[1:0] These bits select the bank address for the user writable data registers. Bank selection affects the Read/Write NVM command operation.
Invalid combinations of B1 and B0 result in no response from the device to the associated initialization. Refer to Section 4.2.1.10 for fur-
ther details rega rding register programming and bank selection.
BS Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
NV NVM Program Enable. This bit indicates if programming of the user-accessible OTP is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
BF This bit indicates the success or failure of the bus test performed as part of t he Initialization command.
1 - Bus fault detected
0 - Bus test passed
INITIALIZATION
COMMAND?
ENABLE IRESP CURRENT
BS == 1?
WAIT FOR NEXT DSI
BUS COMMAND
Y
N
Y
N
Delay tBUSOUT_DISCHARGE
MEASURE VBUSOUT
Y
N
V
BUSOUT
< V
THH
?
SET BF FLAG
CLOSE BUS SWITCH DELAY
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4.2.1.2 Request Status Command
The Request Status command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request St atus command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
Table 16. Request Status Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]00010 to 8 bits
Table 17. Request Status Command Bit Definitions
Bit Field Definition
C[3:0] Request Status Command = ‘0001’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 18. Shor t Response - Reques t Status C om m a nd
Response CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0000000NVUST
BS AT[1] AT[0] S 0 0 to 8 bits
Table 19. Long Response - Request Status Command
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0000NVUST
BS AT[1] AT[0] S 0 0 to 8 bits
Table 20. Request Status Response Bit Definitions
Bit Field Definition
SThis bit indicates whether the device has detected an internal device error.
1 - Internal Error detected .
0 - No Internal Error detect ed
Reference Table 59 for conditi ons that set the S bit.
AT[1:0] Attribute bits locat ed in Register DEVCFG1 (Reference Section 3.1.4.2)
BS Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST This bit indicates whether internal self-test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U T his bi t is set if the voltage at HCAP is below the thresho l d specified in Section 2. Refer to Section 3.3.2 for details.
NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP locations is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0] DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the respon se message length of the received message
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4.2.1.3 Read Acceleration Data Command
The Read Acceleration Data command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Form at Control Command (Reference Section 4.2.1.11)
The device ignores the Request St atus command if the DSI device address is set to the DSI Global Device Address of ‘0000’.
The data bits D[7:0] in the command are only used in the CRC calculation.
The device truncates the LSBs for Acceleration Data Responses of length less than 10. If the result of the truncation is 0, the
minimum acceleration value is trans mi tt ed as defined in Table 26.
Table 21. Read Acceleration Data Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]00100 to 8 bits
Table 22. Read Acceleration Data Command Bit Definitions
Bit Field Definition
C[3:0] Read Acceleration Data Command = ‘0010’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 23. Short Response - Read Acceleration Data Command
Response
Length Response CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
8AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2]
0 to 8 bits
9AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1]
10
AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0]
11
S
12
0
13 ST14 AT_OTP[0]
15 AT_OTP[1]
Table 24. Long Response - Read Acceleration Data Command
Response CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3] A[2] A[1] A[0] 0 S AD[9] AD[8] AD[7] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] 0 to 8 bits
Table 25. Read Acceleration Response Bit Definitions
Bit Field Definition
AD[9:0] Ten-bit acceleration result produced by the device.
SThis bit indicates whether the device has detected an internal device error.
1 - Internal Error detected .
0 - No Internal Error detected
Reference Table 59 for conditi ons that set the S bit.
ST This bit indicates whether internal self -test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
A[3:0] DSI device address. This field contains the device address.
AT_OTP[1:0] Attribute bits located in Register DEVCFG1 (Reference Section 3.1.4.2)
Shaded bits are transmitted to meet the res ponse message length of the received message
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4.2.1.4 DSI Command #3
DSI Command ‘0011’ is not implemented. The device ignores all command formats with a command ID of ‘00 11’.
Table 26. Acceleration Data Values
8-Bit Data Value 9-Bit Data Value 10-Bit Data Value Description
Decimal Hex Decimal Hex Decimal Hex
255 0xFF 511 0x1FF 1023 0x3FF Maximum positive acceleration value
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•Positive acceleration values
131 0x83 259 0x103 515 0x203
130 0x82 258 0x102 514 0x202
129 0x81 257 0x101 513 0x201
128 0x80 256 0x100 512 0x200 Typical 0 g level
127 0x7F 127 0x0FF 511 0x1FF Negative acceleration values126 0x7E 126 0x0FE 510 0x1FE
125 0x7D 125 0x0FD 509 0x1FD
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
111111Maximum negative acceleration value
000000Sensor Error
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4.2.1.5 Request ID Information Command
The Request ID Information command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Request ID Information command if the DSI device address is set to the DSI Global Device Address
of ‘0000’. The data bits D[7:0] in the command are only used in the CRC calculation .
4.2.1.6 DSI Command #5
DSI Command ‘0101’ is not implemented. The device ignores all command forma ts with a command ID of ‘0101’.
4.2.1.7 DSI Command #6
DSI Command ‘0110’ is not implemented. The device ignores all command formats with a command ID of ‘0110’.
Table 27. Request ID Information Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]01000 to 8 bits
Table 28. Request ID Information Command Bit Definitions
Bit Field Definition
C[3:0] Request ID Information Dat a Command = ‘ 0100’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 29. Short Response - Request ID Information Command
Response CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0000000 V2 V1 V0 0 DEVID 1 0 0 0 to 8 bits
Table 30. Long Response - Request ID Information Command
Response CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0000V[2]V[1]V[0]0DEVID1000 to 8 bits
Table 31. Request ID Response Bit Definitions
Bit Field Definition
D[4:0] = {1’b0,DEVID, 3’b100} Device Identifier:‘00100’, or ‘01100’
DEVID: Bit 7 of the DEVCFG regIster
V[2:0] Version ID. This field indicates the device / silicon revision of the device.
A[3:0] DSI device address. This field contains the device address.
Shaded bits are transmitted to meet the response message length of the received message
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4.2.1.8 Clear Command
The Clear command is supporte d in th e following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
When the device successfully decodes a Clear Command, and the address field matches either the assigned device address
(PA[3:0]) or the DSI Global address of ‘0000’, the bus switch is opened within TBSOPEN, and the device logic is reset. Reference
Section 3.6 for the initialization sequence following a Clear Command. The data bits D[7:0] in the command are only used in the
CRC calculation. There is no response to th e Clear Command.
4.2.1.9 DSI Command #8
DSI Command ‘1000’ is not implemented. The device ignores all command forma ts with a command ID of ‘1000’.
Table 32. Clear Comm and
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]01110 to 8 bits
Table 33. Clear Comm and Bit Definitions
Bit Field Definition
C[3:0]
Clear Command = ‘0111’.
When a Clear Command is successfully decoded and the address field matches either t he assigned device address or the DSI Global
Device Address of ‘0000’, the bus switch is opened within tBSOPEN, and the device logic is reset. Reference Section 3.6 for the initialization
sequence following a Clear Command.
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field or the Global
Device Address of ‘0000’. Ot herwise, the command is ignored.
D[7:0] Used for CRC calculation only
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4.2.1.10 Write NVM Command
The Write NVM command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Write NVM command if the command is in any other format, or if the DSI device address is set to the
DSI Global Device Address of ‘0000’.
The Write NVM command uses the nibble address definitions in Table 2 and summarized in Table 39.
Writes to OTP occur only if the NV bit is set. The NV bit is set by the Initialization Command (reference Section 4.2.1.1). If the
NV bit is cleared when the command is executed, the mirror registers addressed by WA[3:0] are updated with the contents of
RD[3:0] and the DSI Device Address is returned regardless of the WA[3:0] value. If the Write NVM command is a request to
change the Device Address, the new Device Address is returned.
The DSI Bus idle voltage must exceed the minimum VPP voltage when programming the OTP array . No internal verification of
the VPP voltage is completed while writing is in process. To verify proper writes, it is recommend that the registers be read back
after writes to verify proper content s. The total Execution time for the Write NVM command is tPROG_BIT times the number of bits
being programmed (1 - 4 bits). Inter-frame spacing between the Write NVM command and the subsequent DSI command must
accommodate this timing.
Writes to the User Programmable OTP array using the Write NVM Command will update the mirror registers and result in a
change to the CRC calculation regardless of the state of the NV bit and the LOCK_U bit. A CRC mismatch will only be detected
if the LOCK_U bit is active (reference Section 3.2.2).
Table 34. Write NVM Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
WA[3]WA[2]WA[1]WA[0]RD[3]RD[2]RD[1]RD[0]A[3]A[2]A[1]A[0]10010 to 8 bits
Table 35. Write NVM Command Bit Definitions
Bit Field Definition
C[3:0] Write NVM Command = ‘1001’
A[3:0] DSI device address. Th is field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0] RD[3:0] contains the data to be wri tten to the OTP location addressed by WA[3:0] when the NV bit is set.
WA[3:0] WA[3:0] contai ns the nibble address of the OTP register to be written to when the NV bit is set.
Table 36. Long Response - Write NVM Command (NV = 1)
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3] A[2] A[1] A[0] WA[3] WA[2] WA[1] WA[0] 1 1 Bnk[1] Bnk[0] RD[3] RD[2] RD[1] RD[0] 0 to 8 bits
Table 37. Long Response - Write NVM Command (NV = 0)
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]00001111A[3]A[2]A[1]A[0]0 to 8 bits
Table 38. Write NVM Response Bit Definitions
Bit Field Definition
Bnk[1:0] These bit s provide the bank address selected in the Initialization command.
A[3:0] DSI device address. Th is field contains the device address. This field must match the internal programmed address field. Otherwise, the command is
ignored.
RD[3:0] RD[3:0] contains the contents of the registers addressed by WA[3:0] after the execution of the NVM write.
WA[3:0] WA[3:0] contai ns the nibble address of the OTP register to be written to when the NV bit is set.
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Table 39. OTP Register Nib ble Address Assign ments
Bank Address Register Address (Nibble) Register Description
Bnk[1] Bnk[0] WA[3] WA[2] WA[1] WA[0]
xx0000 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
xx0001
UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address AD DR[3:0]
xx0010
xx0011
xx0100
xx0101
000110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
000111 DEVCFG2[7] Only RD[3] is written to the LOCK_U bit
001000 TYPE[7:6] Only RD[3:2] is written to LPF[1:0]
001001 DEVCFG[3:0] RD[3] is written to DEVCFG[3] - UNUSED, RD[2:0] is written to CRC_U[2:0]
001010 DEVCFG[7:4] RD[3] is written to the DEVID bit, RD[2:0] is written to DEVCFG[6:4] - UNUSED
001011 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
001100 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
001101 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
001110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
001111 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
010110 DEVCFG1[3:0] RD[3:2] is written to UD00[1:0], RD[1:0] is written to AT[1:0]
010111 DEVCFG2[3:0] RD[3:0] is written to ADDR[3:0]
011000 UD01[3:0] RD[3:0] is written to UD01[3:0]
011001 UD02[3:0] RD[3:0] is written to UD02[3:0]
011010 UD03[3:0] RD[3:0] is written to UD03[3:0]
011011 UD04[3:0] RD[3:0] is written to UD04[3:0]
011100 UD05[3:0] RD[3:0] is written to UD05[3:0]
011101 UD06[3:0] RD[3:0] is written to UD06[3:0]
011110 UD07[3:0] RD[3:0] is written to UD07[3:0]
011111 UD08[3:0] RD[3:0] is written to UD08[3:0]
100110 DEVCFG1[7:4] RD[3:0] is written to UD00[5:2]
100111 DEVCFG2[5] Only RD[1] is written to the PCM bit
101000 UD01[7:4] RD[3:0] is written to UD01[7:4]
101001 UD02[7:4] RD[3:0] is written to UD02[7:4]
101010 UD03[7:4] RD[3:0] is written to UD03[7:4]
101011 UD04[7:4] RD[3:0] is written to UD04[7:4]
101100 UD05[7:4] RD[3:0] is written to UD05[7:4]
101101 UD06[7:4] RD[3:0] is written to UD06[7:4]
101110 UD07[7:4] RD[3:0] is written to UD07[7:4]
101111 UD08[7:4] RD[3:0] is written to UD08[7:4]
110110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
110111 DEVCFG2[6] Only RD[2] is written to the DEVCFG2[6] bit (UNUSED)
111000 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111001 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111010 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111011 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111100 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111101 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111110 UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
111111 DEVCFG2[4] Only RD[0] is written to DEVCFG2[4]
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4.2.1.11 Format Control Command
The Format Control command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Format Control command if the command is in any other format. The device supports the Format Con-
trol command with the DSI Global Address of ‘00 00’, but does not provide a response.
The format control registers defined in the DSI Bus S tandard V2.5 are shown in Table 44. The reset values assigned to each
register are also indicated.
Table 40. Forma t Control Comman d
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
R/WFA[2]FA[1]FA[0]FD[3]FD[2]FD[1]FD[0]A[3]A[2]A[1]A[0]10100 to 8 bits
Table 41. Format Control Command Bit Definitions
Bit Field Definition
C[3:0] Format Control Command = ‘1010’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
FD[3:0] Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to ‘1’.
FA[2:0] The Address of the Format Control Register to read or written.
R/W Read/Wri te determines if the register at address FA[2:0] is to be read or written.
1 - Write FD[3:0] to the Format Control Register addressed by FA[2:0]
0 - Read the Format Control Register addressed by FA[2:0]
Table 42. Long Respon s e - Format Con tro l Command
Response CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0110R/WFA[2]FA[1]FA[0]FD[3]FD[2]FD[1]FD[0]0 to 8 bits
Table 43. Format Control Response Bit Definitions
Bit Field Definition
FD[3:0] The contents of the Format Cont rol Register addressed by FA[2:0] .
FA[2:0] The Address of the Format Control Register that was read or written.
R/W Read/Wri te indicates if the register at add ress FA[2:0] was read or written.
1 - FD[3:0] contains th e data written to the Format Control Register addressed by FA[2:0]
0 - FD[3:0] contains th e contents for the Format Control Register addressed by FA[2:0]
A[3:0] DSI device address. This field contains the device address.
Table 44. Format Control Register Values
Format Control Register Register Address Reset Values DSI Standard Values Definition
FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] FD[3] FD[2] FD[1] FD[0]
CRC Polynomial - Low Nibble 00000010001CRC Polynomial = X4+1
CRC Polynomial - High Nibble 00100010001
Seed - Low Nibble 01010101010 Se ed = ‘1010’
Seed - High Nibble 01100000000
CRC Length (0 to 8) 10001000100 CRC Length = 4
Short Word Data Length (8 to 15)10110001000Short Command Length = 8
Reserved 11000000000 N/A
Format Selection 11100000000 N/A
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The following restrictions apply to format control register operations:
• Writes to the CRC Length Register of values greater than 8 are ignored. The cont ents of the register are
unchanged.
• Writes to the Short W ord Data Length register of values less than 8 are ignored. The contents of the register are
unchanged.
The contents of the Format Selection register determine whether the standard DSI values or the values in the format control
registers are used. If the Format Selection register contains ‘1111’, the Format Control register values are active. Any write to the
Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Com-
mand will maintain the format of the previous command resulting in an invalid response.
A write of ‘0000’ to the Format Selection register activates the standard DSI values.
A write to the Format Selection register of any other value is ignored.
4.2.1.12 Read Register Data Command
The Read Register Data command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to
the DSI Global Device Address of ‘0000’.
The read register command uses the byte address definitions shown in Table 2. Readable registers along with th eir Byte ad-
dresses are shown in Table 2.
Table 45. Read Register Data Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
0000RA[3]RA[2]RA[1]RA[0]A[3]A[2]A[1]A[0]10110 to 8 bits
Table 46. Read Register Data Command Bit Definitions
Bit Field Definition
C[3:0] Read Register Data Command = ‘1011’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
RA[3:0] RA[3:0] contains the byte address of the register to be read.
Table 47. Long Response - Read Register Data Command
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3] A[2] A[1] A[0] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 0 to 8 bits
Table 48. Read Register Data Response Bit Definitions
Bit Field Definition
RD7:0] RD[7:0] contains the data of the register addressed by RA[3:0].
RA[3:0] RA[3:0] contains the byte address of the register to be read.
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
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4.2.1.13 Disable Self-Test Command
The Disable Self-Test co mmand is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device supports the Disable Self-T est command
with the DSI Global Address of ‘0000’, but does not provide a respon se.
The Disable Self-T est Command removes the voltage from the self-test plate of the transducer which results in the acceleration
output value returning to the 0g offset value within tST_DEACT_xxx, as specified in Section 2.
A self-test lockout is activated when the device receives two consecutive Disable Self-Test commands Once self-test lockout
is activated, the internal self-test circuitry is disabled until one of the following conditions occurs:
• HCAP under-voltage
• A Clear command is received
• Internal regulator under-voltage resulting in a reset.
• A Frame Timeout resultin g in a reset.
Table 49. Disable Self-Test Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]11000 to 8 bits
Table 50. Disable Self-Test Command Bit Definitions
Bit Field Definition
C[3:0] Disable Self-Test Command = ‘1100’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 51. Short Response - Disable Self-Test Command
Response CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0000000NVUSTBS AT[1] AT[0] S 0 0 to 8 bits
Table 52. Long Resp on s e - Disa bl e Sel f-Test Command
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0000NVUSTBS AT[1] AT[0] S 0 0 to 8 bits
Table 53. Disable Self-Test Response Bit Definitions
Bit Field Definition
SThis bit indicates whether the device has detected an internal device error.
1 - Internal Error detected .
0 - No Internal Error detected
Reference Table 59 for conditi ons that set the S bit.
AT[1:0] Attribute bits located in Register DEVCFG1 (Reference Sect ion 3.1.4.2)
BS Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST This bit indicates whether internal self -test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP loca tions is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0] DSI device address. This field contains the device address.
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4.2.1.14 Enable Self-Test Command
The Enable Self-Test command is supported in the following command formats:
• Standard Long Command
• Standard Short Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
• Enhanced Short Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The data bits D[7:0] in the command are only used in the CRC calculation. The device ignores the Enable Self-Test command
when it is sent to the DSI Global Address of ‘0000’.
The Enable Self-Test Command applie s a voltage to the self-test plate of the transduce r which results in a delta in the accel-
eration output value of ΔDFLCT_xxx within tST_ACT_xxx, as specified in Section 2. This remains present until the Disable Self-T est
command is received.
Activation of the self-test circuit is inhibited if the self-test locking has been activated. If self-test locking is activated, the internal
self-test circuitry remains disabled, and the ST bit is cleared in the response. Self-Test locking is described in Section 4.2.1.13.
Table 54. Enable Self-Test Command
Data Address Command CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
⎯⎯⎯⎯⎯⎯⎯⎯A[3]A[2]A[1]A[0]11014 bits
Table 55. Enable Self-Test Command Bit Definitions
Bit Field Definition
C[3:0] Enable Self-Test Command = ‘1101’
A[3:0] DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
D[7:0] Used for CRC calculation only
Table 56. Short Response - Enable Self-Test Command
Response CRC
D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
0000000NVUSTBS AT[1] AT[0] S 0 4 bits
Table 57. Long Response - Enable Self-Test Command
Data CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0000NVUSTBS AT[1] AT [0] S 0 4 bit s
Table 58. Enable Self-Test Response Bit Definitions
Bit Field Definition
SThis bit indicates whether the device has detected an internal device error.
1 - Internal Error detected .
0 - No Internal Error detected
Reference Table 59 for conditi ons that set the S bit.
AT[1:0] Attribute bits located in Register DEVCFG1 (Reference Sect ion 3.1.4.2)
BS Bus Switch state. This bit controls the state of the bus switch:
1 - Close the bus switch
0 - Do not close the bus switch
ST This bit indicates whether internal self -test circuitry is active
1 - Self-Test active
0 - Self-Test disabled
U This bit is set if the voltage at HCAP is below the threshold specified in Section 2. Refer to Section 3.3.2 for details.
NV NVM Program Enable. This bit indicates whether programming of the user-programmable OTP loca tions is enabled.
1 - OTP programming Enabled
0 - OTP programming Disabled
A[3:0] DSI device address. This field contains the device address.
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4.2.1.15 DSI Command #14
DSI Command ‘1110’ is not implemented. Th e device ignores all command formats with a command ID of ‘1110’.
4.2.1.16 Reverse Initialization Command
The Reverse Initialization Command is not implemented. The device ignores all command formats with a command ID of
‘1111’. The device ignores all command received on the BUSOUT pin.
4.3 Exception Handling
Table 59 summarizes the exception conditions detected by the device and the response for each exception.
Table 59. Exception Handling
Condition Description SST UResponse
Exception Self-Test
Request
Power On
Reset N/A Power Applied
Clear Command 1 1 0 – Reference Section 3.6
VREG
Under-Voltage N/A VREG < VPORCREG_f
– Device held in Reset.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VREG returns above VPORCREG_r
VREGA
Under-Voltage N/A VREGA < VPORCREG_f
– Device held in Reset.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VREGA returns above VPORCREGA_r
VHCAP
Under-Voltage
Transient
Disabled VHCAP < VPORCREG_f for less
than tHCAP_POR, ST Disabled 001– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
– Device does not need to be re-initialized if VHCAP returns above
VPORHCAP_r before tHCAP_POR
Enabled VHCAP < VPORCREG_f for less
than tHCAP_POR, ST Enabled 011 – DSI Read Acceleration Data Short response = self-test data.
– DSI Read Acceleration Data Long response = self-test data.
– Device does not need to be re-initialized if VHCAP returns above
VPORHCAP_r before tHCAP_POR
VHCAP
Under-Voltage N/A VHCAP < VPORCREG_f for longer
than tHCAP_POR
– Device is Reset and will continue to Reset every tHCAP_POR until VHCAP
returns above VPORHCAP_r, or an internal supply under-voltage condition
occurs.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VHCAP returns above VPORHCAP_r
Capacitor Test
Failure N/A
– Device is Reset and will continue to be reset every tPOR_CAPTEST until the
capacitor failure is removed.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when capacit or failure is removed.
DSI Frame
Timeout N/A VBUSIN < VTHF for longer than tTO
– Device is Reset and will continue to be reset every tTO until the BUSIN
voltage returns above VTHF or a supply under-voltage condit i on occurs.
– No response to DSI commands.
– Bus switch open within tBSOPEN.
– Device must be re-initialized when VBUSIN returns above VTHF
Fuse CRC
Fault
(Factory Array)
Disabled CRC failure detected in factory
programmed OTP array and the
LOCK_F bit is set. ST Disabled 100 – DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
Enabled CRC failure detected in factory
programmed OTP array and the
LOCK_F bit is set. ST Enabled 110 – DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = self-test data.
Fuse CRC
Fault
(User Ar r a y )
Disabled CRC failure detected in User pro-
grammed OTP array and the
LOCK_U bit is set. ST Disabled 100 – DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
Enabled CRC failure detected in User pro-
grammed OTP array and the
LOCK_U bit is set. ST Enabled 110– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = self-test data.
Temperature
Out of Range
Disabled Temperature out of range, ST
Disabled. 100– DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = normal.
Enabled Temperature out of range, ST
Enabled. 110 – DSI Read Acceleration Data Short response = zero.
– DSI Read Acceleration Data Long response = self-test data.
Self-Test
Enabled Enabled ST Enabled 1 1 0 – Internal self-test circuitry enabled.
– DSI Read Acceleration Data Short response = self-test data.
– DSI Read Acceleration Data Long response = self-test data.
Self-Test
Lockout Disabled Two consecut i v e Disable Self-
Test DSI commands received. 000– Internal self-test circuitry disabled.
– Enable Self-Test DSI command does not enable Self-Test. Normal
response to Enable Self-Test DSI command except the ST bit is not set.
– DSI Clear command or Reset disables lockout.
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5 Package
5.1 Case Outline Drawing
Reference Freescale Case Outli ne Drawing # 98ASA00090D
http://www.freescale.com/files/shared/doc/package_info/98ASA00090D.pdf
5.2 Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Table 60. Revision History
Revision
number Revision
date Description of changes
4 03/2012 • Added SafeAssure logo, changed first paragraph and disclaimer to include trademark
information.
MMA16xxKW
Rev. 4
03/2012
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