PS1
PS2
IN GATE OUT
IN GATE OUT
RLOAD
CLOAD
LM5050-1
LM5050-1
GND
GND VS
VS
VIN VOUT
GND
OFF
OUT
IN GATE
LM5050-1
Shutdown
GND GND
VS
Low= FET On, High= FET Off
100:
0.1 PF
+5.0V to +75V
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LM5050-1
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LM5050-1/-Q1 High-Side OR-ing FET Controller
1 Features 3 Description
The LM5050-1/-Q1 High Side OR-ing FET Controller
1• Available in Standard and AEC-Q100 Qualified operates in conjunction with an external MOSFET as
Versions LM5050Q0MK-1 (up to 150°C TJ) and an ideal diode rectifier when connected in series with
LM5050Q1MK-1 (up to 125°C TJ)a power source. This ORing controller allows
• Wide Operating Input Voltage Range, VIN:1Vto MOSFETs to replace diode rectifiers in power
75 V (VBIAS required for VIN < 5 V) distribution networks thus reducing both power loss
and voltage drops.
• 100-V Transient Capability
• Charge Pump Gate Driver for External N-Channel The LM5050-1/-Q1 controller provides charge pump
MOSFET gate drive for an external N-Channel MOSFET and a
fast response comparator to turn off the FET when
• Fast 50-ns Response to Current Reversal current flows in the reverse direction. The LM5050-1/-
• 2-A Peak Gate Turnoff Current Q1 can connect power supplies ranging from 5 V to
• Minimum VDS Clamp for Faster Turnoff 75 V and can withstand transients up to 100 V.
• Package: SOT-6 (Thin SOT-23-6) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
2 Applications LM5050-1
Active OR-ing of Redundant (N+1) Power SOT (6) 2.90 mm × 1.60 mm
LM5050-1-Q1
Supplies
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Full Application
Typical Redundant Supply Configuration
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
7.4 Device Functional Modes........................................ 13
1 Features.................................................................. 18 Application and Implementation ........................ 14
2 Applications ........................................................... 18.1 Application Information............................................ 14
3 Description............................................................. 18.2 Typical Applications ................................................ 16
4 Revision History..................................................... 29 Power Supply Recommendations...................... 21
5 Pin Configuration and Functions......................... 310 Layout................................................................... 21
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 21
6.1 Absolute Maximum Ratings ...................................... 410.2 Layout Example .................................................... 21
6.2 ESD Ratings: LM5050-1 .......................................... 411 Device and Documentation Support................. 22
6.3 ESD Ratings: LM5050-1-Q1 ..................................... 411.1 Documentation Support ........................................ 22
6.4 Recommended Operating Conditions....................... 411.2 Related Links ........................................................ 22
6.5 Thermal Information.................................................. 411.3 Community Resources.......................................... 22
6.6 Electrical Characteristics........................................... 511.4 Trademarks........................................................... 22
6.7 Typical Characteristics.............................................. 811.5 Electrostatic Discharge Caution............................ 22
7 Detailed Description............................................ 11 11.6 Glossary................................................................ 22
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 12 Information ........................................................... 22
7.3 Feature Description................................................. 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (June 2013) to Revision E Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
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IN
1
2
3
6
5
4
VS
GND
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5 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NAME
The main supply pin for all internal biasing and an auxiliary supply for the internal gate drive
1 VS I charge pump. Typically connected to either VOUT or VIN; a separate supply can also be used.
2 GND PWR Ground return for the controller
A logic high state at the OFF pin will pull the GATE pin low and turn off the external MOSFET.
3 OFF I Note that when the MOSFET is off, current will still conduct through the FET's body diode. This
pin should may be left open or connected to GND if unused.
4 IN I Voltage sense connection to the external MOSFET Source pin.
Connect to the Gate of the external MOSFET. Controls the MOSFET to emulate a low forward-
5 GATE O voltage diode.
6 OUT O Voltage sense connection to the external MOSFET Drain pin.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
IN, OUT Pins to Ground(2) –0.3 100 V
GATE Pin to Ground(2) –0.3 100 V
VS Pin to Ground –0.3 100 V
OFF Pin to Ground –0.3 7 V
Storage Temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The GATE pin voltage is typically 12 V above the IN pin voltage when the LM5050-1 is enabled (that is, OFF Pin is Open or Low, and
VIN > VOUT). Therefore, the absolute maximum rating for the IN pin voltage applies only when the LM5050-1 is disabled (that is, OFF
Pin is logic high), or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V
6.2 ESD Ratings: LM5050-1 VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Machine model (MM)(2) ±150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) The MM is a 200-pF capacitor discharged through a 0-Ωresistor (that is, directly) into each pin. Applicable test standard is JESD-A115-
A.
6.3 ESD Ratings: LM5050-1-Q1 VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±2000
V(ESD) Electrostatic discharge V
Machine model (MM)(2) ±150
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) The MM is a 200-pF capacitor discharged through a 0-Ωresistor (that is, directly) into each pin. Applicable test standard is JESD-A115-
A.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
IN, OUT, VS Pins 5 75 V
OFF Pin 0 5.5 V
Standard Grade −40 125 °C
Junction Temperature (TJ) LM5050Q0MK-1 −40 150 °C
LM5050Q1MK-1 −40 125 °C
6.5 Thermal Information LM5050-1/-Q1
THERMAL METRIC(1) DDC (SOT) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 180.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 41.3 °C/W
RθJB Junction-to-board thermal resistance 28.2 °C/W
ψJT Junction-to-top characterization parameter 0.7 °C/W
ψJB Junction-to-board characterization parameter 27.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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Thermal Information (continued)
LM5050-1/-Q1
THERMAL METRIC(1) DDC (SOT) UNIT
6 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
6.6 Electrical Characteristics
Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VS PIN
Operating
VVS Supply Voltage TJ= –40°C to 125°C 5 75 V
Range TJ= 25°C 75
VVS= 5 V, VIN = 5 V
VOUT = VIN - 100 mV TJ= –40°C to 125°C 105
TJ= 25°C 100
Operating VVS= 12 V, VIN = 12 V
IVS μA
Supply Current VOUT = VIN - 100 mV TJ= –40°C to 125°C 147
TJ= 25°C 130
VVS= 75 V, VIN = 75 V
VOUT = VIN - 100 mV TJ= –40°C to 125°C 288
IN PIN
Operating Input
VIN TJ= –40°C to 125°C 5 75 V
Voltage Range VIN = 5 V TJ= 25°C 190
VVS= VIN
VOUT = VIN - 100 mV TJ= –40°C to 125°C 32 305
GATE = Open
IIN IN Pin current μA
TJ= 25°C 320
VIN = 12 V to 75 V
VVS= VIN LM5050MK-1,
TJ= –40°C to 125°C 233 400
VOUT = VIN - 100 mV LM5050Q1MK-1
GATE = Open TJ= –40°C to 125°C LM5050Q0MK-1 233 475
OUT PIN
Operating
VOUT Output Voltage TJ= –40°C to 125°C 5 75 V
Range VIN = 5 V to 75 V TJ= 25°C 3.2
IOUT OUT Pin Current VVS= VIN µA
TJ= –40°C to 125°C 8
VOUT = VIN - 100 mV
GATE PIN
VIN = 5 V TJ= 25°C 30
VVS = VIN
VGATE = VIN TJ= –40°C to 125°C 12 41
VOUT = VIN - 175 mV
Gate Pin Source
IGATE(ON) µA
Current VIN = 12 V to 75 V TJ= 25°C 32
VVS = VIN
VGATE = VIN TJ= –40°C to 125°C 20 41
VOUT = VIN - 175 mV
VIN = 5 V TJ= 25°C 7
VVS = VIN
VGATE - VIN in TJ= –40°C to 125°C 4 9
VOUT = VIN - 175 mV
VGS Forward V
VIN = 12 V to 75 V TJ= 25°C 12
Operation(1) VVS = VIN TJ= –40°C to 125°C 9 14
VOUT = VIN - 175 mV
(1) Measurement of VGS voltage (that is. VGATE - VIN) includes 1 MΩin parallel with CGATE.
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Electrical Characteristics (continued)
Typical values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 12 V, VVS = VIN, VOUT = VIN, VOFF = 0 V, CGATE= 47 nF, and TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Gate TJ= 25°C 25
CGATE = 0(2)
Capacitance TJ= –40°C to 125°C 85
Discharge Time CGATE = 10 nF(2) TJ= 25°C 60
tGATE(REV) at Forward to ns
Reverse TJ= 25°C 180
Transition CGATE = 47 nF(2) TJ= –40°C to 125°C 350
See Figure 1
Gate
Capacitance
DischargeTime
tGATE(OFF) at OFF pin Low CGATE = 47 nF(3) TJ= 25°C 486 ns
to High
Transition
See Figure 2 TJ= 25°C 2.8
VGATE = VIN + 3 V
Gate Pin Sink LM5050MK-1,
IGATE(OFF) VOUT > VIN + 100 mV TJ= –40°C to 125°C 1.8 A
Current LM5050Q1MK-1
t≤10 ms TJ= –40°C to 125°C LM5050Q0MK-1 1.4
Reverse VSD TJ= 25°C –28
VSD(REV) Threshold VIN - VOUT mV
TJ= –40°C to 125°C –41 –16
VIN < VOUT
Reverse VSD
ΔVSD(REV) TJ= 25°C 10 mV
Hysteresis TJ= 25°C 19
LM5050MK-1,
VIN = 5 V TJ= –40°C to 125°C 1 37
LM5050Q1MK-1
VVS = VIN
Regulated VIN - VOUT TJ= –40°C to 125°C LM5050Q0MK-1 1 60
Forward VSD
VSD(REG) mV
Threshold TJ= 25°C 22
VIN > VOUT LM5050MK-1,
VIN = 12 V TJ= –40°C to 125°C 4.4 37
LM5050Q1MK-1
VVS = VIN
VIN - VOUT TJ= –40°C to 125°C LM5050Q0MK-1 4.4 60
OFF PIN
OFF Input High TJ= 25°C 1.56
VOUT = VIN-500 mV
VOFF(IH) Threshold VOFF Rising TJ= –40°C to 125°C 1.75
Voltage V
OFF Input Low TJ= 25°C 1.4
VOUT = VIN - 500 mV
VOFF(IL) Threshold VOFF Falling TJ= –40°C to 125°C 1.1
Voltage
OFF Threshold
ΔVOFF Voltage VOFF(IH) - VOFF(IL) TJ= 25°C 155 mV
Hysteresis TJ= 25°C 5
VOFF = 4.5 V
OFF Pin Internal
IOFF TJ= –40°C to 125°C 3 7 µA
Pulldown VOFF = 5 V TJ= 25°C 8
(2) Time from VIN-VOUT voltage transition from 200 mV to -500 mV until GATE pin voltage falls to VIN + 1 V. See Figure 1.
(3) Time from VOFF voltage transition from 0 V to 5 V until GATE pin voltage falls to VIN + 1 V. See Figure 2
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VOFF
VGATE - VIN
0.0V
1.0V
VOFF(IL)
0.0V
VOFF(IH)
5.0V
VGATE
tGATE(OFF)
VIN - VOUT
VGATE - VIN
0.0V
1.0V
0 mV
VSD(REV)
-500 mV
VSD(REG)
200 mV
VGATE
VIN > VOUT
VIN < VOUT
tGATE(OFF)
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Figure 1. Gate OFF Timing for Forward to Reverse Transition
Figure 2. Gate OFF Timing for OFF Pin Low to High Transition
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6.7 Typical Characteristics
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ= 25°C
Figure 3. IIN vs VIN Figure 4. IIN vs VIN
Figure 5. IOUT vs VOUT Figure 6. IOUT vs VOUT
Figure 7. IVS vs VVS Figure 8. IVS vs VVS
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-5 0 5 10 15 20 25 30
10
12
14
16
18
20
22
24
26
VOLTS (V)
TIME (5ms / DIV)
Vin
Vout
Vgate
-50 0 50 100 150 200 250
10
12
14
16
18
20
22
24
26
VOLTS (V)
TIME (50ns / DIV)
Vin
Vout
Vgate
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Typical Characteristics (continued)
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ= 25°C
Figure 9. (VGATE - VIN) vs VIN, VVS = VOUT Figure 10. (VGATE - VIN) vs VIN, VVS = VOUT
Figure 11. Forward CGATE Charge Time, CGATE = 47 nF Figure 12. Reverse CGATE Discharge, CGATE = 47 nF
Figure 13. VGATE - VIN vs Temperature Figure 14. tGATE(REV) vs Temperature
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Typical Characteristics (continued)
Unless otherwise stated: VVS = 12 V, VIN = 12 V, VOFF = 0 V, and TJ= 25°C
Figure 15. OFF Pin Thresholds vs Temperature Figure 16. OFF Pin Pulldown vs Temperature
Figure 18. OFF Pin, ON to OFF Transition
Figure 17. CGATE Charge and Discharge vs OFF Pin
Figure 20. GATE Pin vs (RDS(ON) × IDS)
Figure 19. OFF Pin, OFF to ON Transition
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7 Detailed Description
7.1 Overview
Blocking diodes are commonly placed in series with supply inputs for the purpose of ORing redundant power
sources and protecting against supply reversal. The LM5050 replaces diodes in these applications with an N-
MOSFET to reduce both the voltage drop and power loss associated with a passive solution. At low input
voltages, the improvement in forward voltage loss is readily appreciated where headroom is tight, as shown in
Figure 2. The LM5050 operates from 5 V to 75 V and it can withstand an absolute maximum of 100 V without
damage. A 12-V or 15-A ideal diode application is shown in Figure 24. Several external components are included
in addition to the MOSFET, Q1. Ideal diodes, like their non-ideal counterparts, exhibit a behavior known as
reverse recovery. In combination with parasitic or intentionally introduced inductances, reverse recovery spikes
may be generated by an ideal diode during an reverse current shutdown. D1, D2 and R1 protect against these
spikes which might otherwise exceed the LM5050 100-V survival rating. COUT also plays a role in absorbing
reverse recovery energy. Spikes and protection schemes are discussed in detail in the Short Circuit Failure of an
Input Supply section.
NOTE
The OFF pin may be used to active the GATE pull down circuit and turn off the pass
MOSFET, but it does not disconnect the load from the input because Q1’s body diode is
still present.
If Vs is powered while IN is floating or grounded, then about 0.5mA will leak from the Vs
pin into the IC and about 3mA will leak from the OUT pin into the IC. From this leakage,
about 50 uA will flow out of the IN pin and the rest will flow to ground. This does not affect
long term reliability of the IC, but may influence circuit design. See Reverse Input Voltage
Protection With IQ Reduction for details on how to avoid this leakage current.
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IN OUTGATE
1.5V
OFF
VS
GND
LM5050- 1
Reverse
Comparator
LOAD
INPUT
35 µA
14V
30 mV
30 µA
30 mV
5 µA
- +
-+
Bias
Circuitry
-+
2A
MOSFET Off
+12V Charge
Pump
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7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 IN, GATE, and OUT Pins
When power is initially applied, the load current will flow from source to drain through the body diode of the
MOSFET. Once the voltage across the body diode exceeds VSD(REG) then the LM5050-1 begins charging the
MOSFET gate through a 32 µA (typical) charge pump current source . In forward operation, the gate of the
MOSFET is charged until it reaches the clamping voltage of the 12-V GATE to IN pin Zener diode internal to the
LM5050-1.
The LM5050-1 is designed to regulate the MOSFET gate-to-source voltage. If the MOSFET current decreases to
the point that the voltage across the MOSFET falls below the VSD(REG) voltage regulation point of 22 mV (typical),
the GATE pin voltage will be decreased until the voltage across the MOSFET is regulated at 22 mV. If the
source-to-drain voltage is greater than the VSD(REG) voltage, the gate-to-source voltage will increase and
eventually reach the 12-V GATE to IN pin Zener clamp level.
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Feature Description (continued)
If the MOSFET current reverses, possibly due to failure of the input supply, such that the voltage across the
LM5050-1 IN and OUT pins is more negative than the VSD(REV) voltage of -28 mV (typical), the LM5050-1 will
quickly discharge the MOSFET gate through a strong GATE to IN pin discharge transistor.
If the input supply fails abruptly, as would occur if the supply was shorted directly to ground, a reverse current
will temporarily flow through the MOSFET until the gate can be fully discharged. This reverse current is sourced
from the load capacitance and from the parallel connected supplies. The LM5050-1 responds to a voltage
reversal condition typically within 25 ns. The actual time required to turn off the MOSFET will depend on the
charge held by the gate capacitance of the MOSFET being used. A MOSFET with 47 nF of effective gate
capacitance can be turned off in typically 180 ns. This fast turnoff time minimizes voltage disturbances at the
output, as well as the current transients from the redundant supplies.
7.3.2 VS Pin
The LM5050-1 VS pin is the main supply pin for all internal biasing and an auxiliary supply for the internal gate
drive charge pump.
For typical LM5050-1 applications, where the input voltage is above 5 V, the VS pin can be connected directly to
the OUT pin. In situations where the input voltage is close to, but not less than, the 5 V minimum, it may be
helpful to connect the VS pin to the OUT pin through an RC Low-Pass filter to reduce the possibility of erratic
behavior due to spurious voltage spikes that may appear on the OUT and IN pins. The series resistor value
should be low enough to keep the VS voltage drop at a minimum. A typical series resistor value is 100 Ω. The
capacitor value should be the lowest value that produces acceptable filtering of the voltage noise.
If Vs is powered while IN is floating or grounded, then about 0.5 mA will leak from the Vs pin into the IC and
about 3mA will leak from the OUT pin into the IC. From this leakage, about 50 uA will flow out of the IN pin and
the rest will flow to ground. This does not affect long term reliability of the IC, but may influence circuit design.
See Reverse Input Voltage Protection With IQ Reduction for details on how to avoid this leakage current.
Alternately, it is possible to operate the LM5050-1 with VIN value as low as 1 V if the VS pin is powered from a
separate supply. This separate VS supply must be from 5 V and 75 V. See Figure 27.
7.3.3 OFF Pin
The OFF pin is a logic level input pin that is used to control the gate drive to the external MOSFET. The
maximum operating voltage on this pin is 5.5 V.
When the OFF pin is high, the MOSFET is turned off (independent of the sensed IN and OUT voltages). In this
mode, load current will flow through the body diode of the MOSFET. The voltage difference between the IN pin
and OUT pins will be approximately 700 mV if the MOSFET is operating normally through the body diode.
The OFF pin has an internal pulldown of 5 µA (typical). If the OFF function is not required the pin may be left
open or connected to ground.
7.4 Device Functional Modes
7.4.1 ON/OFF Control Mode
The MOSFET can be turned off by asserting the OFF pin high. This mode only disables the MOSFET, but VOUT
is still available through the body diode of the MOSFET.
7.4.2 External Power Supply Mode
The Vs pin of the LM5050 can be operated from 5 V to 75 V as the bias input supply. In this mode VIN voltage
can be as low as 1 V, as shown in Figure 27.
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IN GATE OUT
IN GATE OUT
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Systems that require high availability often use multiple, parallel-connected redundant power supplies to improve
reliability. Schottky OR-ing diodes are typically used to connect these redundant power supplies to a common
point at the load. The disadvantage of using OR-ing diodes is the forward voltage drop, which reduces the
available voltage and the associated power losses as load currents increase. Using an N-channel MOSFET to
replace the OR-ing diode requires a small increase in the level of complexity, but reduces, or eliminates, the
need for diode heat sinks or large thermal copper area in circuit board layouts for high power applications.
Figure 21. OR-ing with Diodes
The LM5050-1/-Q1 is a positive voltage (that is, high-side) OR-ing controller that will drive an external N-channel
MOSFET to replace an OR-ing diode. The voltage across the MOSFET source and drain pins is monitored by
the LM5050-1 at the IN and OUT pins, while the GATE pin drives the MOSFET to control its operation based on
the monitored source-drain voltage. The resulting behavior is that of an ideal rectifier with source and drain pins
of the MOSFET acting as the anode and cathode pins of a diode respectively.
Figure 22. OR-ing With MOSFETs
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Application Information (continued)
8.1.1 MOSFET Selection
The important MOSFET electrical parameters are the maximum continuous Drain current ID, the maximum
Source current (that is, body diode) IS, the maximum drain-to-source voltage VDS(MAX), the gate-to-source
threshold voltage VGS(TH), the drain-to-source reverse breakdown voltage V(BR)DSS, and the drain-to-source On
resistance RDS(ON).
The maximum continuous drain current, ID, rating must exceed the maximum continuous load current. The rating
for the maximum current through the body diode, IS, is typically rated the same as, or slightly higher than the
drain current, but body diode current only flows while the MOSFET gate is being charged to VGS(TH).
Gate Charge Time = Qg/ IGATE(ON)
1. The maximum drain-to-source voltage, VDS(MAX), must be high enough to withstand the highest differential
voltage seen in the application. This would include any anticipated fault conditions.
2. The drain-to-source reverse breakdown voltage, V(BR)DSS, may provide some transient protection to the OUT
pin in low voltage applications by allowing conduction back to the IN pin during positive transients at the OUT
pin.
3. The gate-to-source threshold voltage, VGS(TH), should be compatible with the LM5050-1 gate drive
capabilities. Logic level MOSFETs, with RDS(ON) rated at VGS(TH) at 5 V, are recommended, but sub-Logic
level MOSFETs having RDS(ON) rated at VGS(TH) at 2.5 V, can also be used.
4. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-
drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by
using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a
MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
(a) Reverse transition detection. Higher RDS(ON) will provide increased voltage information to the LM5050-1
Reverse Comparator at a lower reverse current level. This will give an earlier MOSFET turnoff condition
should the input voltage become shorted to ground. This will minimize any disturbance of the redundant
bus.
(b) Reverse current leakage. In cases where multiple input supplies are closely matched it may be possible
for some small current to flow continuously through the MOSFET drain to source (that is, reverse)
without activating the LM5050-1 Reverse Comparator. Higher RDS(ON) will reduce this reverse current
level.
(c) Cost. Generally, as the RDS(ON) rating goes lower, the cost of the MOSFET goes higher.
5. The dominate MOSFET loss for the LM5050-1 active OR-ing controller is conduction loss due to source-to-
drain current to the output load, and the RDS(ON) of the MOSFET. This conduction loss could be reduced by
using a MOSFET with the lowest possible RDS(ON). However, contrary to popular belief, arbitrarily selecting a
MOSFET based solely on having low RDS(ON) may not always give desirable results for several reasons:
(a) Selecting a MOSFET with an RDS(ON) that is too large will result in excessive power dissipation.
Additionally, the MOSFET gate will be charged to the full value that the LM5050-1 can provide as it
attempts to drive the Drain to Source voltage down to the VSD(REG) of 22 mV typical. This increased Gate
charge will require some finite amount of additional discharge time when the MOSFET needs to be
turned off.
(b) As a guideline, it is suggest that RDS(ON) be selected to provide at least 22 mV, and no more than 100
mV, at the nominal load current.
(c) (22 mV / ID)≤RDS(ON) ≤(100 mV / ID)
(d) The thermal resistance of the MOSFET package should also be considered against the anticipated
dissipation in the MOSFET to ensure that the junction temperature (TJ) is reasonably well controlled,
because the RDS(ON) of the MOSFET increases as the junction temperature increases.
6. PDISS = ID2× (RDS(ON))
7. Operating with a maximum ambient temperature (TA(MAX)) of 35°C, a load current of 10 A, and an RDS(ON) of
10 mΩ, and desiring to keep the junction temperature under 100°C, the maximum junction-to-ambient
thermal resistance rating (θJA) must be:
(a) RθJA ≤(TJ(MAX) - TA(MAX))/(ID2× RDS(ON))
(b) RθJA ≤(100°C - 35°C)/(10 A × 10 A × 0.01 Ω)
(c) RθJA ≤65°C/W
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5050-1 LM5050-1-Q1
VIN
48V VOUT
GND
OFF
OUT
IN GATE
LM5050-1
OFF/ON
GND GND
Q1
SUM40N10-30
+
R1
100:
CIN
1 PF
75V
D1
SS16T3
COUT
22 PF
63V
D2
SMBJ60A
VS
C1
0.1 PF
100V
S D
G
IN GATE OUT CLOAD
LM5050-1
GND
COUT
Parasitic
Inductance
Parasitic
Inductance
Shorted
Input
Reverse Recovery Current
VS
LM5050-1
,
LM5050-1-Q1
SNVS629E –MAY 2011–REVISED DECEMBER 2015
www.ti.com
Application Information (continued)
8.1.2 Short Circuit Failure of an Input Supply
An abrupt 0-Ωshort circuit across the input supply will cause the highest possible reverse current to flow while
the internal LM5050-1 control circuitry discharges the gate of the MOSFET. During this time, the reverse current
is limited only by the RDS(ON) of the MOSFET, along with parasitic wiring resistances and inductances. Worst
case instantaneous reverse current would be limited to:
ID(REV) = (VOUT - VIN) / RDS(ON) (1)
The internal Reverse Comparator will react, and will start the process of discharging the Gate, when the reverse
current reaches:
ID(REV) = VSD(REV) / RDS(ON) (2)
When the MOSFET is finally switched off, the energy stored in the parasitic wiring inductances will be transferred
to the rest of the circuit. As a result, the LM5050-1 IN pin will see a negative voltage spike while the OUT pin will
see a positive voltage spike. The IN pin can be protected by diode clamping the pin to GND in the negative
direction. The OUT pin can be protected with a TVS protection diode, a local bypass capacitor, or both. In low
voltage applications, the MOSFET drainto- source breakdown voltage rating may be adequate to protect the
OUT pin (that is, VIN + V(BR)DSS(MAX) < 75 V ), but most MOSFET data sheets do not ensure the maximum
breakdown rating, so this method should be used with caution.
Figure 23. Reverse Recovery Current Generates Inductive Spikes at VIN and VOUT pins.
8.2 Typical Applications
8.2.1 Typical Application With Input and Output Transient Protection
Figure 24. Typical Application With Input and Output Transient Protection Schematic
16 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM5050-1 LM5050-1-Q1
LM5050-1
,
LM5050-1-Q1
www.ti.com
SNVS629E –MAY 2011–REVISED DECEMBER 2015
Typical Applications (continued)
8.2.1.1 Design Requirements
Table 1 shows the parameters for Figure 24
Table 1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Minimum Input Voltage, VINMIN 6 V
Maximum Input Voltage, VINMax 50 V
Output Current Range, IOUT 0 to 15 A
Ambient Temperature Range, TA0°C to 50°C
8.2.1.2 Detailed Design Procedure
The following design procedure can be used to select component values for the LM5050-1.
8.2.1.2.1 Power Supply Components (R1 C1,) Selection
The LM5050-1 VS pin is the main supply pin for all internal biasing and an auxiliary supply for the internal gate
drive charge pump. The series resistor (R1) value should be low enough to keep the VS voltage drop at a
minimum. A typical series resistor value is 100 Ω. The capacitor value (0.1 uF typical) should be the lowest value
that produces acceptable filtering of the voltage noise.
8.2.1.2.2 MOSFET (Q1) Selection
The MOSFET (Q1) selection procedure is explained in detail in MOSFET Selection. The MOSFET used in the
design example is SUM40N10-30-E3.
8.2.1.2.3 D1 and D2 Selection for Inductive Kick-Back Protection
Diode D1 and capacitor C1 and diode D2 and capacitor C2 in the Figure 27 serve as inductive kick-back
protection to limit negative transient voltage spikes generated on the input when the input supply voltage is
abruptly shorted to zero volts. As a result, the LM5050-1 IN pin will see a negative voltage spike while the OUT
pin will see a positive voltage spike. The IN pin can be protected by schottky diode (D1) clamping the pin to GND
in the negative direction, similarly the OUT pin should be protected with a TVS protection diode (D1), or with a
local bypass capacitor, or both. D1 is selected as 1-A, 60-V Schottky Barrier Rectifier (SS16T3G) and D2 is the
60 V, TVS (SMBJ60A-13-F).
8.2.1.3 Application Curves
Figure 25. Forward voltage (VIN-VOUT) Drop Reduces Figure 26. Forward Voltage (VIN-VOUT) Drop Increases
When Gate is Enabled (VIN = 12 V) When Gate is Disabled (VIN = 12 V)
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM5050-1 LM5050-1-Q1
PS1
PS2
IN GATE OUT
IN GATE OUT
RLOAD
CLOAD
LM5050-1
LM5050-1
GND
GND
COUT
VS
VS
VIN
1V to 75V VOUT
GND
OFF
OUT
IN GATE
LM5050-1
Off/On
GND GND
VBIAS
5.0V to 75V
Q1
+
C1
1.0 PF
100V D1
C2
22 PF
100V
D2
TVS
82V
VS
GND
R1
100
C3
0.1 PF
100V
LM5050-1
,
LM5050-1-Q1
SNVS629E –MAY 2011–REVISED DECEMBER 2015
www.ti.com
8.2.2 Using a Separate VS Supply for Low Vin Operation
In some applications, it is desired to operate LM5050-1 from low supply voltage. The LM5050-1 can operate with
a 1-V rail voltage, provided its VS pin is biased from 5 V to 75 V. The detail of such application is depicted in
Figure 27.
Figure 27. Using a Separate vs Supply for Low Vin Operation Schematic
8.2.3 ORing of Two Power Sources
Figure 28. ORing of Two Power Sources
18 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM5050-1 LM5050-1-Q1
VIN
5.0V to 75V VOUT
GND
OFF
OUT
IN GATE
LM5050-1
OFF/ON
GND GND
Q1
SUM40N10-30
CIN
1 PF
100V
D1
B180-13-F
VS
S D
G
ON/OFF
Control
Q1
VOUT
GND
CIN Cout
D1
D2
D3
D4
C1
R1
VIN
GND
Q2
100»
0.1µF
100V
LM5050-1
IN GATE OUT VS
GND SMBJ60A
22uF
63V
1uF
75V
SS16T3
BAS40-7-F
SS16T3
NTR5198NLT3G
SUM40N10-30
48V
LM5050-1
,
LM5050-1-Q1
www.ti.com
SNVS629E –MAY 2011–REVISED DECEMBER 2015
8.2.4 Reverse Input Voltage Protection With IQ Reduction
If Vs is powered while IN is floating or grounded, then about 0.5 mA will leak from the Vs pin into the IC and
about 3 mA will leak from the OUT pin into the IC. From this leakage, about 50 uA will flow out of the IN pin and
the rest will flow to ground. This does not affect long term reliability of the IC, but may influence circuit design.
In battery powered applications, whenever LM5050-1 functionality is not needed, the supply to the LM5050-1 can
be disconnected by turning “OFF” Q2, as shown in Figure 29. This disconnects the ground path of the LM5050-1
and eliminates the current leakage from the battery.
The quiescent current of LM5050-1 can be also reduced by disconnecting the supply to VS pin, whenever
LM5050-1 function is not need.
Figure 29. Reverse Input Voltage Protection With IQ Reduction Schematic
8.2.5 Basic Application With Input Transient Protection
Figure 30. Basic Application With Input Transient Protection Schematic
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM5050-1 LM5050-1-Q1
VIN
48V VOUT
GND
OFF
OUT
IN GATE
LM5050-1
GND GND
Q1
SUM40N10-30
+
R1
100:
CIN
1 PF
75V
D1
SS16T3
COUT
22 PF
63V
D2
SMBJ60A
VS
C1
0.1 PF
100V
S D
G
D3
SS16T3
LM5050-1
,
LM5050-1-Q1
SNVS629E –MAY 2011–REVISED DECEMBER 2015
www.ti.com
8.2.6 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection
Figure 31. 48-V Application With Reverse Input Voltage (VIN = –48 V) Protection Schematic
8.2.6.1 Application Curves
Figure 32. Operation With Positive Polarity Input With Figure 33. Operation With Negative polarity Input With
(VIN = 25 V) (VIN = –25 V)
20 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM5050-1 LM5050-1-Q1
VOUT
LM5050-1
D
GS
Gate
IN
OUT
OFF
VS
GND
VIN
C1
R1
GND
D1
D4
COUT
CIN
LM5050-1
,
LM5050-1-Q1
www.ti.com
SNVS629E –MAY 2011–REVISED DECEMBER 2015
9 Power Supply Recommendations
When the LM5050-1/-Q1 shuts off the external MOSFET, transient voltages will appear on the input and output
due to reverse recovery, as discussed in Short Circuit Failure of an Input Supply.To prevent LM5050-1 and
surrounding components from damage under the conditions of a direct input short circuit, it is necessary to clamp
the negative transient at IN, and OUT pins with TVS.
10 Layout
10.1 Layout Guidelines
The typical PCB layout for LM5050-1/-Q1 is shown in Figure 34. TI recommends connecting the IN, Gate and
OUT pins close to the source and drain pins of the MOSFET. Keep the traces of the MOSFET drain wide and
short to minimize resistive losses. Place surge suppressors (D1 and D4) components as shown in the example
layout of LM5050-1 in Layout Example.
10.2 Layout Example
Figure 34. Typical Layout Example With D2PAK N-MOSFET
Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM5050-1 LM5050-1-Q1
LM5050-1
,
LM5050-1-Q1
SNVS629E –MAY 2011–REVISED DECEMBER 2015
www.ti.com
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
Achieving Stable VGS Using LM5050-1 with Low Current and Noisy Input Supply, SLVA684
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LM5050-1 Click here Click here Click here Click here Click here
LM5050-1-Q1 Click here Click here Click here Click here Click here
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated
Product Folder Links: LM5050-1 LM5050-1-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5050MK-1/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SZHB
LM5050MKX-1/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 SZHB
LM5050Q0MK-1/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 150 SL5B
LM5050Q0MKX-1/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 150 SL5B
LM5050Q1MK-1/NOPB ACTIVE SOT-23-THIN DDC 6 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 SP3B
LM5050Q1MKX-1/NOPB ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 SP3B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2017
Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5050-1, LM5050-1-Q1 :
•Catalog: LM5050-1
•Automotive: LM5050-1-Q1
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5050MK-1/NOPB SOT-
23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050MKX-1/NOPB SOT-
23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050Q0MK-1/NOPB SOT-
23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050Q0MKX-1/NOPB SOT-
23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050Q1MK-1/NOPB SOT-
23-THIN DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LM5050Q1MKX-1/NOPB SOT-
23-THIN DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5050MK-1/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM5050MKX-1/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
LM5050Q0MK-1/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM5050Q0MKX-1/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
LM5050Q1MK-1/NOPB SOT-23-THIN DDC 6 1000 210.0 185.0 35.0
LM5050Q1MKX-1/NOPB SOT-23-THIN DDC 6 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Mar-2017
Pack Materials-Page 2
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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