NCP2823BFCT1G - ON SEMICONDUCTOR

January, 2011 − Rev. 2

1Publication Order Number:

NCP2823/D

NCP2823 Series

High Efficiency 3W

Filterless Class D Audio

Amplifier

The NCP2823A/B are cost effective mono audio power amplifiers

designed for portable electronic devices. NCP2823A is optimized for

8 W operation and NCP2823B can operate with speaker impedance

down to 4.0 W. For Instance, NCP2823B is capable of delivering 3 W

of continuous average power to a 4.0 W from a 5.0 V supply in a

Bridge Tied Load (BTL) configuration. Under the same conditions,

NCP2823A can provide 1.5 W to an 8.0 W BTL load with less than

10% THD+N. For cellular handsets or PDAs it offers space and cost

savings because no output filter is required when using inductive

transducers. With more than 90% efficiency and very low shutdown

current, it increases the lifetime of your battery and drastically lowers

the junction temperature.

NCP2823 processes analog inputs with a pulse width modulation

technique that lowers output noise and THD. The device allows

independent gain while summing signals from various audio sources.

Thus, in cellular handsets, the earpiece, the loudspeaker and even

melody ringer can be driven with a single NCP2823. Due to its low

26 mV noise floor, A−weighted, clean listening is guaranteed no matter

the load sensitivity.

Features

•Optimized PWM Output Stage: Filterless Capability

•Externally gain setting

•Low consumption: 1.8 mA for NCP2823A

•High efficiency: up to 92%

•Large Output Power Capability:

3 W @ VP = 5.0 V, RL = 4 W, THD+N < 10%

3 W @ VP = 5.5 V, RL = 4 W, THD+N < 1%

•High PSRR: up to −77 dB

•Fully Differential Capability: RF immunity

•Thermal and Auto recovery Short−Circuit Protection

•CMRR (−80 dB) Eliminates Two Input Coupling Capacitors

•Pin to Pin compatible with NCP2820 Flip−Chip

•These Devices are Pb−Free and are RoHS Compliant

Typical Applications

•Audio Amplifier for

♦Cellular Phones

♦Digital Cameras

♦Personal Digital Assistant and Portable Media Player

♦GPS

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9−PIN FLIP−CHIP CSP

FC SUFFIX

CASE 499AL

MARKING

DIAGRAM

XXX = QTA for NCP2823A

= PMA for NCP2823B

= TPG for NCP2823A

with backside laminate

A = Assembly Location

Y = Year

WW = Work Week

G= Pb−Free Package

XXXG

AYWW

See detailed ordering and shipping information on page 10 of

this data sheet.

ORDERING INFORMATION

1.45 mm

3.7 mm

NCP2823 Series

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Figure 1. Pin Description

AGNDINP VOUTN

PVDD

EN VOUTP

PGND

INN

AVDD

(Top View)

Figure 2. Simplified Block Diagram

Data

Processor

GND

VOUTP

VOUTN

Positive

Differential

Input

INP

Negative

Differential

Input

INN

RL = 8 W

Shutdown

Control

VDD

RAMP

GENERATOR

BATTERY

300 kW

Vih

Vil

CMOS

Output

Stage

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PIN FUNCTION DESCRIPTION

Name Type Description

A1 INP INPUT Positive Differential Input

C1 INN INPUT Negative Differential Input

B2 PVDD POWER Power Supply: This pin is the power supply of the device. A 4.7 mF ceramic capacitor or larger must

bypass this input to the ground. This capacitor should be placed as close a possible to this input.

B1 AVDD POWER Analog Power Supply: This pin must be connected to PVDD.

C3 VOUTP OUTPUT Positive output Special care must be observed at layout level. See the Layout recommendations.

A3 VOUTN OUTPUT Negative output: Special care must be observed at layout level. See the Layout recommendations.

C2 EN INPUT Enable: When a High logic is applied to this pin, the device is activated

B3 PGND POWER Power Ground: This pin is the power ground and carries the high switching current. A high quality

ground must be provided to avoid any noise spikes/uncontrolled operation. Care must be observed to

avoid high−density current flow in a limited PCB copper track.

A2 AGND POWER Analog Ground: This pin is the analog ground of the device and must be connected to GND plane.

MAXIMUM RATINGS

Rating Symbol Value Unit

AVDD, PVDD Pins: Power Supply Voltage (Note 2) VP−0.3 to +6.0 V

INP/N ,Pins: Input (Note 2) VINP/N −0.3 to +VDD V

Digital Input/Output: EN Pin:

Input Voltage

Input Current

VDG

IDG

−0.3 to VDD +0.3

Human Body Model (HBM) ESD Rating are (Note 3) ESD HBM 2000 V

Machine Model (MM) ESD Rating are (Note 3) ESD MM 200 V

WCSP 1.5 x 1.5 mm package (Notes 6 and 7)

Thermal Resistance Junction−to−Case RqJC 90 °C/W

Operating Ambient Temperature Range TA−40 to +85 °C

Operating Junction Temperature Range TJ−40 to +125 °C

Maximum Junction Temperature (Note 6) TJMAX +150 °C

Storage Temperature Range TSTG −65 to +150 °C

Moisture Sensitivity (Note 5) MSL Level 1

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.

2. According to JEDEC standard JESD22−A108B.

3. This device series contains ESD protection and passes the following tests:

Human Body Model (HBM) +/−2.0 kV per JEDEC standard: JESD22−A114 for all pins.

Machine Model (MM) +/−200 V per JEDEC standard: JESD22−A115 for all pins.

4. Latch up Current Maximum Rating: $100 mA per JEDEC standard: JESD78 class II.

5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

6. The thermal shutdown set to 150°C (typical) avoids irreversible damage on the device due to power dissipation.

7. The RqCA is dependent on the PCB heat dissipation. The maximum power dissipation (PD) is dependent on the min input voltage, the max

output current and external components selected.

RqCA +

125 *TA

*RqJC

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ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V to 5.5 V

(Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VDD = 3.6 V. (see Note 8)

Symbol Parameter Conditions Min Typ Max Unit

GENERAL PERFORMANCES

VPOperational Power Supply 2.5 5.5 V

FOSC Oscillator Frequency 250 300 350 kHz

IDD Supply current NCP2823A

VP = 3.6 V, No Load

NCP2823B

VP = 3.6 V, No Load

1.8

2.6

2.4

4.6

Isd Shutdown current VENL = VENR = 0 V 0.01 1 mA

TON Turn ON Time EN rising edge 7.4 ms

TOFF Turn Off Time EN falling edge 4 ms

Zsd Class D Output impedance in

shutdown mode

VENL = 0 V 20 kW

RDS(ON) Static drain−source on−state

resistance of power Mosfets

300 mW

hEfficiency NCP2823A, VP = 3.6 V, Po = 600 mW, RL =

8 W, F = 1 kHz

92 %

NCP2823B, VP = 3.6 V, Po = 1 W, RL = 4 W,

F = 1 kHz

Av Voltage gain 285 kW

300 kW

315 kW

V/V

FLP −3 dB Cut off Frequency of

the Built in Low Pass Filter 30

kHz

TSD Thermal Shut Down

Protection

150 °C

TSDH Thermal Shut Down

Hysteresis

10 °C

VIH Rising Voltage Input Logic

High

1.2 −VDD V

VIL Falling Voltage Input Logic

Low

−0.4 V

RPLD Pull Down Resistor 250 kW

AUDIO PERFORMANCES

voo Output offset 0.3 mV

PSRR Power supply rejection ratio F = 217 Hz, Input ac grounded −77 dB

F = 1 kHz, Input ac grounded −63

SNR Signal to noise ratio VP = 5 V, Pout = 600 mW (A. Weighted) 97 dB

CMRR Common mode rejection ratio Input shorted together

VIC = 1 Vpp, f = 217 Hz

−80 dB

Vn Output Voltage noise Input ac grounded, Av =

0 dB

weighting

35 mV

A. Weighted 26

8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ

= TA = 25°C.

NCP2823 Series

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ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and for VDD between 2.5 V to 5.5 V

(Unless otherwise noted). Typical values are referenced to TA = + 25 °C and VDD = 3.6 V. (see Note 8)

Symbol UnitMaxTypMinConditionsParameter

AUDIO PERFORMANCES

Po Output Power NCP2823A

RL = 8 W

F = 1 kHz

THD+N

< 1%

VP = 5 V 1.5 W

VP = 3.6 V 0.7

VP = 2.5 V 0.22

THD+N

< 10%

VP = 5 V 1.8

VP = 3.6 V 0.87

VP = 2.5 V 0.4

NCP2823B

RL = 4 W

F = 1 kHz

THD+N

< 1%

VP = 5 V 1.72

VP = 3.6 V 1.2

VP = 2.5 V 0.58

THD+N

< 10%

VP = 5 V 3

VP = 3.6 V 1.57

VP = 2.5 V 0.71

THD+N Total harmonic distortion plus

noise

VP = 3.6 V, Av = 6 dB, Po = 0.5 W 0.1 %

VP = 5 V, Av = 6 dB, Po = 1 W 0.08

8. Performances guaranteed over the indicated operating temperature range by design and/or characterization, production tested at TJ

= TA = 25°C.

NCP2823 Series

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TYPICAL OPERATING CHARACTERISTICS

Pout (mW)

(%)

Figure 3. Efficiency vs Pout

100

0 500 1000 1500 2000

VP = 5.5 V

5 V

4.2 V

3.6 V 3 V to 2.5 V

Pout (W)

THD+N (%)

0.01 0.1 110

0.01

0.1

Figure 4. NCP2823A/B, THD+N vs Pout,

RL = 8 W

VP = 5.5 V

4.2 V

3.6 V

3 V

2.5 V

0.01

0.1

0.01 0.1 1 10

Pout (W)

THD+N (%)

Figure 5. NCP2823B, THD+N vs Pout, RL = 4 W

VP = 5.5 V

4.2 V

3.6 V

3 V

FREQUENCY (Hz)

THD(%)

0.001

0.01

0.1

10 100 1000 10000 100000

VP = 2.7 V

Figure 6. THD+N vs Frequency Pout = 150 mW,

RL = 8 W

0.001

0.01

0.1

10 100 1000 10000 100000

FREQUENCY (Hz)

THD(%)

0.001

0.01

0.1

10 100 1000 10000 100000

THD(%)

FREQUENCY (Hz)

VP = 3.6 V

VP = 5 V

Figure 7. THD+N vs Frequency Pout = 250 mW,

RL = 8 W

Figure 8. THD+N vs Frequency Pout = 500 mW,

RL = 8 W

3.6 V

VP = 5 V

2.5 V

5 V

2.5 V

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TYPICAL OPERATING CHARACTERISTICS

0.001

0.01

0.1

10 100 1000 10000 100000

FREQUENCY (Hz)

THD(%)

VP = 5 V

Figure 9. THD+N vs Frequency Pout = 1 W,

RL = 8 W

0.001

0.01

0.1

10 100 1000 10000 10000

THD(%)

FREQUENCY (Hz)

VP = 2.7 V

Figure 10. THD+N vs Frequency

Pout = 300 mW, RL = 4 W

0.001

0.01

0.1

10 100 1000 10000 100000

THD(%)

FREQUENCY (Hz)

Figure 11. THD+N vs Frequency

Pout = 500 mW, RL = 4 W

4.2 V

VP = 5 V

2.5 V

0.001

0.01

0.1

10 100 1000 10000 10000

THD(%)

FREQUENCY (Hz)

VP = 5 V

VP = 3.6 V

Figure 12. THD+N vs Frequency

Pout = 1 W, RL = 4 W

0.001

0.01

0.1

10 100 1000 10000 100000

THD(

)

FREQUENCY (Hz)

Figure 13. THD+N vs Frequency Pout = 2 W,

RL = 4 W

VP = 5 V

−90

−80

−70

−60

−50

−40

−30

−20

−10

10 100 1000 10000 100000

CMRR(dB)

FREQUENCY (Hz)

VP = 2.5 V

to 5.5 V

Figure 14. CMRR vs Frequency, Vipp = 1 Vpp,

RL = 8 W

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TYPICAL OPERATING CHARACTERISTICS

−120

−100

−80

−60

−40

−20

10 100 1000 10000 100000

FREQUENCY (Hz)

CMRR (dB)

Figure 15. CMRR vs Frequency vs VP

Vrip = 1 Vpp

Vrip = 200 mVpp

−90

−80

−70

−60

−50

−40

−30

−20

−10

10 100 1000 10000 100000

PSRR (dB)

FREQUENCY (Hz)

Figure 16. PSRR vs Frequency

VP = 4.2 V

3.6 V

2.5 V

−90

−80

−70

−60

−50

−40

−30

−20

−10

10 100 1000 10000 100000

PSRR (dB)

VP = 4.2 V 3.6 V

2.5 V

Figure 17. PSRR vs Frequency

FREQUENCY (Hz)

Input Grounded

Input Floating

NCP2823 Series

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DETAIL OPERATING DESCRIPTION

General Description

The basic structure of the NCP2823A/B is composed of

one analog pre−amplifier, a pulse width modulator and an

H−bridge CMOS power stage. The first stage is externally

configurable with gain−setting resistor Ri and the internal

fixed feedback resistor Rf (the closed−loop gain is fixed by

the ratios of these resistors). The load is driven differentially

through two output stages. The differential PWM output

signal is a digital image of the analog audio input signal. The

human ear is a band pass filter regarding acoustic

waveforms, which the typical cut off values are 20 Hz and

20 kHz. Thus, the user will hear only the amplified audio

input signal within the frequency range. The switching

frequency and its harmonics are fully filtered. The inductive

parasitic element of the loudspeaker helps to guarantee a

superior distortion value.

Power Amplifier

The output PMOS and NMOS transistors of the amplifier

have been designed to deliver a maximum output power

before clipping. The channel resistance (Ron) of the NMOS

and PMOS transistors is typically 0.3 W.

Gain Selection

The preamplifier stage amplifies the input signal. The

gain is fully configurable by external resistors.

The gain setting is given by the following equation:

Av +

300 kW

(eq. 1)

Turn On and Turn Off Transitions

In order to reduce “pop and click” noises during transition,

the output power in the load must not be established or cutoff

suddenly. When logic high is applied to the Enable pin, the

internal biasing voltage rises quickly and, 4 ms later, once

the output DC level is around the common mode voltage, the

gain is established slowly (5.0 ms). Thus, the total turn on

time to get full power to the load is 7.4 ms (typical). The

device has the same behavior when it is turned−off by a logic

low on the Enable pin. No power is delivered to the load 4 ms

after a falling edge on the shutdown pin. Due to the fast turn

on and off times, the shutdown signal can be used as a mute

signal as well.

Shutdown Function

The device enters shutdown mode when the Enable signal

is low. During the shutdown mode, the DC Shutdown

current of the circuit does not exceed 1 mA.

The NCP2823A/B has an internal resistor (RPLD =

250 kW) connected between GND and Enable. The purpose

of this resistor is to eliminate any unwanted state changes

when the Enable pin is floating.

30 kHz Built−in Low Pass Filter

This filter allows connecting directly a DAC or a CODEC

to the NCP2823 input without increasing the output noise by

mixing frequency with the DAC/CODEC output frequency.

Consequently, optimized operation with DACs or CODECs

is guaranteed without additional external components.

Power Supply Bypassing

The NCP2823 requires a correct decoupling of the power

supply in order to guarantee the best operation in terms of

audio performances. To achieve these performances, it is

necessary to place a 4.7 mF low ESR ceramic capacitor as

close as possible to the PVDD pin in order to reduce high

frequency transient spikes due to parasitic inductance (see

Layout considerations).

Input Capacitors Cin

Thanks to its fully differential architecture the NCP2823

does not require input capacitors. However, it is possible to

use input capacitors when the differential source is not

biased or in single ended configuration. In this case it is

necessary to take into account the corner frequency which

can influence the low frequency response of the NCP2823.

The following equation will help choose the adequate input

capacitor.

fC+1

2@p@Ri @Cin

(eq. 2)

Over Current Protection

This protection allows detecting an over current in the

H−Bridge. When the current is higher than 2A for the

NCP2823B or 1A for the NCP2823A, the H−Bridge is

positioned in high impedance. When the short circuit is

removed or the current is lower, the NCP2823 goes back to

normal operation. This protection avoids over current due to

a bad assembly (Output shorted together, to VDD or to

ground).

Layout Recommendations

For Efficiency and EMI standpoints, it is strongly

recommended to use Power and ground plane in order to

reduce parasitic resistance and inductance.

For the same reason, it is recommended to keep the output

traces short and well shielded in order to avoid them to act

as antenna.

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The EMI Level is strongly dependent upon the

application. However, ferrite beads placed close to the

NCP2823 will reduce EMI radiation when it is needed.

Ferrite value is strongly dependent upon the application.

Figure 18. PCB Layout example

ORDERING INFORMATION

Device Package Shipping†

NCP2823AFCT2G WLCSP9

(Pb−Free)

3000 / Tape & Reel

NCP2823AFCCT2G WLCSP9

(Backside Laminate Coating)

(Pb−Free)

3000 / Tape & Reel

NCP2823BFCT1G WLCSP9

(Pb−Free)

3000 / Tape & Reel

NCP2823BFCT2G WLCSP9

(Pb−Free)

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Demo Board Available:

NCP2823AGEVB/D and NCP2823BGEVB/D evaluation board configure the device in typical application.

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PACKAGE DIMENSIONS

9−PIN FLIP−CHIP CSP

FC SUFFIX

CASE 499AL−01

ISSUE O

DIM MIN MAX

MILLIMETERS

A0.540 0.660

A1 0.210 0.270

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO SPHERICAL

CROWNS OF SOLDER BALLS.

−A−

−B−

0.10 C

−C−

0.05 C

0.10 C

4 X

SEATING

PLANE

0.05 C

0.03 C

A B

9 X b

12 3

D1.450 BSC

0.330 0.390

b0.290 0.340

e0.500 BSC

D1 1.000 BSC

E1 1.000 BSC

1.450 BSC

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TOP VIEW

BOTTOM VIEW

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

NCP2823/D

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