ISG2000 5 V CATV MODEM RF TRANSCEIVER FEATURES DESCRIPTION AND APPLICATIONS * TWO WAY DOCSIS BASED DESIGN: 91-860 MHz Downstream 5-42 MHz Upstream The ISG2000 is a complete RF transceiver designed for use in cable modem applications. The transceiver integrates a diplex filter, triple conversion receiver and transmit AGC amplifier (see Figure 1). The diplex filter provides over 40 dB of isolation between the TX band and the RX band. The receiver section provides channel selectivity and converts QAM carriers to low IF sampling frequency for digital signal processing. The transmitter section provides 50 dB of gain control while maintaining excellent linearity performance. * INTERFACES DIRECTLY WITH QAM DEMOD/MOD ICs * BUILT IN RF TRANSMITTER: 50 dB AGC Driver * LOW PHASE NOISE: -83 dBc/Hz @ 10 KHz * BUSINESS CARD SIZE: 3.4" x 2.0" x 0.5" * RUGGED DESIGN/NO MICROPHONICS: All SMD Components "Coiless" * LOW POWER CONSUMPTION: RX: 1.2 Watts, TX: 0.6 Watts * EUROPEAN AND JAPANESE VERSIONS AVAILABLE ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25C) PART NUMBER SYMBOLS PARAMETERS RF Performance (RX) fOP Operating Frequency Range Input Signal Level Gain Range VAGC Automatic Gain Control Voltage RF VAGC Automatic Gain Control Voltage IF Noise Figure (Max Gain) NFMAX Phase Noise at 10 kHz Offset LO Radiation at RF Input Resolution Lock Time (end to end channel) Input Impedance (Nominal) RLIN Input Return Loss Channel Bandwidth USA Output Frequency1 Passband Ripple Image Rejection Inband Group Delay CSO2 CTB2 Frequency Offset ISG2000 UNITS MIN MHz dBmV dB 91 -20 25 0 0 dB dBc/Hz dBm KHz msec. ohms dB MHz MHz dB dB ns dBc dBc KHz TYP 8 -83 -40 62.5 18 75 MAX 860 15 75 3.3 3.3 10 -80 5 5.70 6 5.75 1 5.80 2 50 -50 100 45 45 +50 Notes: 1. Optional Output Frequency of 43.75 MHz Available 2. 110 Channels at +15 dBmV/tone 05/10/2000 ISG2000 ELECTRICAL CHARACTERISTICS (VCC = 5 V, VCC2 = 24 V, TA = 25C) PART NUMBER SYMBOLS ISG2000 PARAMETERS RF Performance (TX) Operating Frequency Range fOP Gain (VAGC = 0 V) Gain (VAGC = 3.3 V) VAGC Automatic Gain Control Voltage 2nd Harmonic Level (Single Tone, POUT = +58 dBmV) 3rd Harmonic Level (Single Tone, POUT = +58 dBmV) RLOUT Output Return Loss TX ON On/Off Setting Time (See Figure 1) On/Off Setting Time (See Figure 1) TX OFF Power Requirements Supply Voltage V1 RX ( 5 V) Supply Voltage V2 RX ( 30 V) mA Supply Voltage V1 TX ( 5 V) Supply Current Supply Current 1 (RX) ICC1 (RX) ICC2 (RX) Supply Current 2 (RX) Supply Current 1 (TX) ICC1 (TX) Physical Interface To the CATV Network To the Motherboard Physical Dimensions LxWxH Environmental Specs TOP Operating Temperature1 Storage Temperature TSTG UNITS MIN MHz dB dB V dBc dBc dB S S 5 0 -53 -53 V V V 4.75 22 4.75 TYP MAX 42 35 -30 3.3 mA mA mA -56 -56 10 12 5 6 5 24 5 5.25 31.5 9 240 1.5 120 320 2 160 Female F-Connector 16 Pin Header 3.4 x 2.0 x 0.5" C C -5 -40 60 75 Note: 1. Temperature performance parameters will vary slightly. ABSOLUTE MAXIMUM RATINGS TX ENABLE APPLICATION CIRCUIT (Figure 1) (TC = 25 C unless otherwise noted) SYMBOLS VIN PARAMETERS RF Input Voltage UNITS dBmV RATINGS 5 Volt 60 VCC1 (RX) Supply Voltage 1 (RX) V 6 VCC2 (RX) Supply Voltage 2 (RX) V 35 VCC (TX) Supply Voltage (TX) V 6 TOP Operating Temperature C -10 to 60 TSTG Storage Temperature C -40 to 75 TSOL Soldering Temperature C 260 tSOL Soldering Time sec. 4 Note: 1. Operation in excess of any one of these parameters may result in permanent damage. 1 2 2 R1 4.7 K ohm Square Wave (1) 0-3.3 Volts 3 3.0 K ohm 2 2 R2 C1 1000 pF 0 ISG2000 PSAVE pin 3 2 2 ISG2000 PIN FUNCTIONS Pin No. Pin Name 1 RFAGC Description The RFAGC pin is used to adjust gain in the dual conversion tuner. This pin has a positive gain vs. AGC slope. 20 dB of gain control is available by varying the voltage from 0.5 V to 3.3 V. 2 VCC (TX) The VCC (TX) pin powers the TX amplifier. A 5 V bias is required and nominal current is 125 mA. 3 TXEN The TXEN pin is used to enable/disable the TX amplifier. When TXEN is set LOW, the TX amplifier is disabled. In this state, a standby current of 3 mA is required from VCC (TX). When TXEN is set HIGH, the TX amplifier is enabled. In this state, a nomimal current of 125 mA is required from VCC (TX). TXIN- is the inverting input to the TX amplifier. The input frequency range spans 5-42 MHz. 4 TXIN- 5 TXIN+ TXIN+ is the non-inverting input to the TX amplifier. The input frequency range spans 5-42 MHz. 6 TXAGC The TXAGC pin is used to adjust gain in the TX amplifier. The pin has a positive gain vs. AGC slope. 50 dB of gain control is available by varying the voltage from 0.5 V to 3.0 V. 7 VCC2 (RX) 8 VCC1 (RX) 9 IFAGC 10 GND Equivalent Circuit 1 1K 1K 0.1 F 3 10 K 4 5 4 5 6 10 K 1000 p The VCC2 (RX) pin powers the loop filter for the first LO. A bias of 24 V - 30 V is required and maximum current draw is 2 mA. The VCC1 (RX) pin powers the entire RX section. A bias of 5 V is required and nominal current draw is 250 mA. The IFAGC pin is used to adjust gain in the final downconverter stage of the RX section. The pin has a positive gain vs. AGC slope. 30 dB of gain control is available by varying the voltage from 0.5 to 2.0 V. Ground. 9 1K 1000 p ISG2000 PIN FUNCTIONS Pin No. Pin Name Description 11 CLK Clock pin for the dual PLL. High impedance CMOS input. Data for the various latches is clocked in on the rising edge into a 20-bit shift register. 12 DATA Serial data pin for the dual PLL. High impedance CMOS input. MSB entered first. The last two bits are the control bits. 13 LDEN Latch enable pin for the dual PLL. High impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 latches determined by the 2 control bits. 14 GND Ground. 15 IFOUT+ Non-Inverting final IF output. Equivalent Circuit 240 5.6 H 39 p 16 IFOUT- Inverting final IF output. 240 5.6 H 39 p Note: 1. For programming information, refer to National LMX2336 data sheet (http://www.national.com) FIGURE 1 43.75 MHz 91-860 MHz DUAL PLL CABLE IN/OUT CLK DATA LD EN TX IN 5-65 MHz RX OUT 15 68 p 68 p 16 ISG2000 OUTLINE DIMENSIONS (Units in mm) Pin Connections 1. RF AGC 2. VCC (TX) 3. TXEN 4. TX IN - 5. TX IN + 6. TXAGC 7. VCC2 Rx) 8. VCC1 (Rx) 9. IF AGC 10. GND 11. CLK 12. DATA 13. LDEN 14. GND 15. IF OUT+ 16. IF OUT- 54.0 52.4 13.2 17.3 DATUM LINE 1.6 2.2 3.5 2.5 1.7 4.0 4.1 2.9 24.5-0.2 43.3 3.0 PIN 1 MODEL 7.7 14.0 SERIAL NUMBER ISGXXX 98017 00056 DATE CODE DATUM LINE 2.0 MAX 0.4-0.1 26.7-0.2 19.9 0.6-0.1 2.54 x 15 = 38.1-0.2 88.2 89.3 0.4-0.1 Note: All tolerances 0.15 mm unless otherwise specified. RECOMMENDED PAD LAYOUT (Units in mm [inches]) 87.5 [3.445] 3.2 [0.125] 4 PLS 50.2 [1.976] 56.8 [2.236] 3.0 [0.118] 2.54 [0.100] 15 PLS PIN 1 26.8 [1.055] 92.5 [3.642] 0.9 [0.035] 16 PLS ISG2000 Table 1. Programmable Modes C1 C2 R16 0 0 RF2 Phase Detector Polarity 0 1 RF1 Phase Detector Polarity C1 1 1 C2 0 1 R17 RF2 ICPO R18 R19 R20 RF2 DO RF2 LD RF2 FO TRI-STATE RF1 ICPO RF1DO RF1 LD RF1 FO TRI-STATE N19 RF2 Prescaler RF1 Prescaler N20 Pwdn RF2 Pwdn RF1 Table 2. Mode Select Truth Table Phase DO TRI-STATE ICPO1 RF1 RF2 Pwdn2 Detector Prescaler Prescaler Polarity3 0 Negative Normal LOW 64/65 64/65 pwrd up Operation 1 Positive TRI-STATE HIGH 128/129 128/129 pwrd dn VCO CHARACTERISTICS Notes: 1. The ICPO LOW Current State = 1/4 x ICPO HIGH Current. 2. Activitation of the RF2 PLL or RF1 PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality does not become disabled until both RF2 and RF1 powerdown bits are activated. The OSCIN is connected to VCC through a 100 k resistor and the OSCOUT goes HIGH when this condition exists. The MICROWAVETM control register remains active and capable of loading and latching data during all the powerdown modes. 3. Phase Detector Polarity Depending upon VCO characteristics, the R16 bits should be set accordingly: When VCO characteristics are positive like (1), R16 should be set HIGH, when VCO characteristics are negative like (2), R16 should be set LOW. VCO Output Frequency (1) (2) VCO Input Voltage Table 3. The FOLD Output Truth Table RF1 R (19) RF2 R (19) RF1 R (20) (RF1 LD) (RF2 LD) (RF1 FO) 0 0 0 0 1 0 1 0 0 1 1 0 X 0 0 X 0 1 X 1 0 X 1 1 0 0 0 1 1 1 1 0 1 1 1 1 X - Don't care condition RF2 R (20) FOLD (RF2 FO) Output State 0 Disabled1 0 RF2 Lock Detect2 0 RF1 Lock Detect2 0 RF1/RF2 Lock Detect2 1 RF2 Reference Divider Output 0 RF1 Reference Divider Output 1 RF2 Programmable Divider Output 0 RF1 Programmable Divider Output 1 Fastlock3 1 For internal use only 1 For internal use only 1 Counter Reset4 Notes: 1. When the FOLD output is disabled, it is actively pulled to a low logic state. 2. Lock detect output provided to indicate when the VCO frequency is in "lock". When the loop is locked and a lock detect mode is selected, the pin's output is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked. 3. The Fastlock mode utilized the FOLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop's Icpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). 4. The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in "close" alignment with R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth acquisition upon powering up. ISG2000 Serial Data Input Timing DATA N20: WSB (R20: WSB) N19 (R19) N10 (R10) N9 (R9) C2 (R8) (C2) C1: LSB (C1: LSB) CLOCK tCWL LE tCS OR tCH tCWH tES tEW LE Notes: 1. Parenthesis data indicates programmable reference divider data. 2. Data shifted into register on clock rising edge. 3. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2 V @ VCC = 2.7 V and 2.6 V @ VCC = 5.5 V. Phase Comparator and Internal Charge Pump Characteristics. fr fp LD Do H f >f r p Z f =f r p L f <f r p f <f r p f <f r p Notes: 1. Phase difference detection range: -2 to +2 2. The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked. ISG BROADBAND, Inc. 4701 Patrick Henry Drive * SUITE #701 * Santa Clara, CA 95054-1863 * (408) 330-6660 FAX (408) 330-6688 * www.isgbroadband.com DATA SUBJECT TO CHANGE WITHOUT NOTICE 05/10/2000