LTC3838
1
3838fb
For more information www.linear.com/LTC3838
Typical applicaTion
FeaTures DescripTion
Dual, Fast, Accurate Step-
Down DC/DC Controller with
Differential Output Sensing
The LTC
®
3838 is a dual, PolyPhase
®
synchronous step-down
DC/DC switching regulator controller. Two independent
channels drive all N-channel power MOSFETs. The controlled
on-time, valley current mode control architecture allows for
fast transient response and constant frequency switching
in steady-state operation, independent of VIN, VOUT and
load current. Its load-release transient detection feature
significantly reduces overshoot at low output voltages.
Differential output voltage sensing, along with a preci-
sion internal reference, offers an accurate ±0.67% output
regulation on Channel 1, even if the remote output ground
deviates from local ground by ±500mV. The second channel
can either provide an independent ±1% output, or together
with the first channel of this controller, serve as one of the
PolyPhase channels for a single-output voltage.
The switching frequency can be programmed from 200kHz
to 2MHz with an external resistor, and can be synchronized to
an external clock. Very low tON and tOFF times allow for near
0% and near 100% duty cycles, respectively. Voltage track-
ing soft start-up and multiple safety features are provided.
1.2V/1.5V, 15A, 350kHz, DCR Sense, Step-Down Converter (Refer to Figure 16 for Full Design)
applicaTions
n Wide VIN Range: 4.5V to 38V, VOUT: 0.6V to 5.5V
n ±0.67% Output Voltage Accuracy Over Temperature,
Differential Output Voltage Sensing, Allowing Up to
±500mV Line Loss at Remote Ground on Channel 1
n ±1% Output on the Independent 2nd Channel
n Controlled On-Time, Valley Current Mode Control
n Fast Load Transient Response
n Detect Transient (DTR) Reduces VOUT Overshoot
n Frequency Programmable from 200kHz to 2MHz,
Synchronizable to External Clock
n tON(MIN) = 30ns, tOFF(MIN) = 90ns
n RSENSE or Inductor DCR Current Sensing
n Overvoltage Protection and Current Limit Foldback
n Power Good Output Voltage Monitor
n Output Voltage Tracking and Adjustable Soft Start-Up
n Thermally Enhanced 38-Pin (5mm × 7mm) QFN and
TSSOP packages
n Distributed Power Systems
n Point-of-Load Converters
n Computing Systems
n Data Communication Systems
L, LT, LTC, LTM, PolyPhase, OPTI-LOOP, µModule, Linear Technology and the Linear logo
are registered trademarks and No RSENSE and UltraFast are trademarks of Linear Technology
Corporation. All other trademarks are the property of their respective owners. Protected by U.S.
Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611.
115k
SENSE1–
SENSE1+
SENSE2–
SENSE2+
VIN
BOOST1
DRVCC1
TG1
BG1
PGND
BG2
DRVCC2
VOUTSENSE1+
VOUTSENSE1–
TRACK/SS1
ITH1
VFB2
TRACK/SS2
ITH2
4.7µF
V
OUT2
1.5V
15A
V
IN
4.5V TO 38V
VOUT1
1.2V
15A 0.1µF 0.1µF
330µF
×2330µF
×2
10k
10k
15k
10k
0.56µH 0.56µH
3838 TA01a
RT
SGND
SW1
BOOST2
LTC3838 TG2
INTVCC
SW2
++
Efficiency/Power Loss
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
1
EFFICIENCY
10
3838 F16b
70
60
50
0
1.5
2.0
2.5
1.0
0.5
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
POWER
LOSS
LTC3838
2
3838fb
For more information www.linear.com/LTC3838
absoluTe MaxiMuM raTings
VIN Voltage ................................................. –0.3V to 40V
BOOST1, BOOST2 Voltages ....................... –0.3V to 46V
SW1, SW2 Voltages ...................................... –5V to 40V
INTVCC, DRVCC1, DRVCC2, EXTVCC, PGOOD1,
PGOOD2, RUN1, RUN2, (BOOST1-SW1),
(BOOST2-SW2), MODE/PLLIN Voltages ...... –0.3V to 6V
VOUTSENSE1+, VOUTSENSE1–, SENSE1+, SENSE2+,
SENSE1–, SENSE2– Voltages ....................... –0.6V to 6V
(Note 1)
13 14 15 16
TOP VIEW
39
PGND
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1TRACK/SS2
ITH2
VRNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
RT
VRNG1
ITH1
TRACK/SS1
V
OUTSENSE1+
TG2
SW2
BG2
DRV
CC2
EXTV
CC
INTVCC
PGND
VIN
DRV
CC1
BG1
SW1
TG1
VFB2
SENSE2+
SENSE2–
DTR2
RUN2
PGOOD2
BOOST2
VOUTSENSE1–
SENSE1+
SENSE1–
DTR1
RUN1
PGOOD1
BOOST1
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TOP VIEW
FE PACKAGE
38-LEAD PLASTIC TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DTR2
SENSE2–
SENSE2+
VFB2
TRACK/SS2
ITH2
VRNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
RT
VRNG1
ITH1
TRACK/SS1
V
OUTSENSE1+
V
OUTSENSE1–
SENSE1+
SENSE1–
RUN2
PGOOD2
BOOST2
TG2
SW2
BG2
DRVCC2
EXTVCC
INTVCC
PGND
VIN
DRVCC1
BG1
SW1
TG1
BOOST1
PGOOD1
RUN1
DTR1
39
PGND
TJMAX = 125°C, θJA = 28°C/W
EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB
pin conFiguraTion
TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 5V
DTR1, DTR2, PHASMD, RT, VRNG1, VRNG2, VFB2,
ITH1, ITH2 Voltages ................ –0.3V to (INTVCC + 0.3V)
Operating Junction Temperature Range
(Note 2, 3, 4) .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
FE Package .......................................................300°C
Table 1. Comparison of LTC3838 Options
PART NUMBER DESCRIPTION
LTC3838 ±0.67% Differential Output Regulation on Channel 1
±1% Output Regulation on Channel 2
Separate-Per-Channel Continuous 30mV to 100mV Current Sense Range Controls
LTC3838-1 ±0.67% and ±0.75%, Both Differential Output Regulation on Channel 1 and 2
Single-Pin 30mV/60mV Current Sense Range Control, Improved Current Limit Accuracy Than LTC3838
LTC3838-2 ±0.67% Differential Output Regulation with Internal Reference on Channel 1
±4mV Differential Output Regulation with External Reference Voltage on Channel 2
Fixed 30mV Current Sense Range, Improved Current Limit Accuracy Than LTC3838
LTC3838
3
3838fb
For more information www.linear.com/LTC3838
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3838EUHF#PBF LTC3838EUHF#TRPBF 3838 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3838IUHF#PBF LTC3838IUHF#TRPBF 3838 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
LTC3838EFE#PBF LTC3838EFE#TRPBF LTC3838FE 38-Lead Plastic TSSOP –40°C to 125°C
LTC3838IFE#PBF LTC3838IFE#TRPBF LTC3838FE 38-Lead Plastic TSSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VIN Input Voltage Operating Range 4.5 38 V
VOUT1,2(REG) Regulated Output Voltage Operating Range VOUT1 Regulated Differentially with Respect to
VOUTSENSE1–, VOUT2 Regulated with Respect to
SGND
0.6 5.5 V
IQInput DC Supply Current
Both Channels Enabled
Only One Channel Enabled
Shutdown Supply Current
MODE/PLLIN = 0V, No Load
RUN1 or RUN2 (But Not Both) = 0V
RUN1 = RUN2 = 0V
3
2
15
mA
mA
µA
VOUTSENSE1(REG) Regulated Differential Feedback Voltage on
Channel 1 (VOUTSENSE1+ – VOUTSENSE1–)ITH1 = 1.2V (Note 5)
TA = 25°C
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.5985
0.596
0.594
0.6
0.6
0.6
0.6015
0.604
0.606
V
V
V
Regulated Differential Feedback Voltage on
Channel 1 Over Line, Load and Common
Mode
VIN = 4.5V to 38V, ITH1 = 0.5V to 1.9V (Note 5),
–0.5V < VOUTSENSE1– < 0.5V
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.594
0.591
0.6
0.6
0.606
0.609
V
V
VFB2(REG) Regulated Feedback Voltage on Channel 2 ITH2 = 1.2V (Note 5)
TA = 25°C
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.597
0.594
0.592
0.6
0.6
0.6
0.603
0.606
0.608
V
V
V
Regulated Feedback Voltage on Channel 2
Over Line, Load VIN = 4.5V to 38V, ITH2 = 0.5V to 1.9V (Note 5)
TA = 0°C to 85°C
TA = –40°C to 125°C
l
l
0.592
0.588
0.6
0.6
0.608
0.612
V
V
IVOUTSENSE1+VOUTSENSE1+ Input Bias Current VOUTSENSE1+ – VOUTSENSE1– = 0.6V ±5 ±25 nA
IVOUTSENSE1–VOUTSENSE1– Input Bias Current VOUTSENSE1+ – VOUTSENSE1– = 0.6V –25 –50 µA
IVFB2 VFB2 Input Bias Current VFB2 = 0.6V –5 ±50 nA
gm(EA)1,2 Error Amplifier Transconductance ITH = 1.2V (Note 5) 1.7 mS
tON(MIN)1,2 Minimum Top Gate On-Time VIN = 38V, VOUT = 0.6V, RT = 20k (Note 6) 30 ns
tOFF(MIN)1,2 Minimum Top Gate Off-Time (Note 6) 90 ns
orDer inForMaTion
(http://www.linear.com/product/LTC3838#orderinfo)
LTC3838
4
3838fb
For more information www.linear.com/LTC3838
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Current Sensing
VSENSE(MAX)1,2 Maximum Valley Current Sense Threshold
(VSENSE1,2+ – VSENSE1,2–)VRNG = 2V, VFB = 0.57V, VSENSE– = 2.5V
VRNG = 0V, VFB = 0.57V, VSENSE– = 2.5V
VRNG = INTVCC, VFB = 0.57V, VSENSE– = 2.5V
l
l
l
80
21
39
100
30
50
120
40
61
mV
mV
mV
VSENSE(MIN)1,2 Minimum Valley Current Sense Threshold
(VSENSE1,2+ – VSENSE1,2–)
(Forced Continuous Mode)
VRNG = 2V, VFB = 0.63V, VSENSE– = 2.5V
VRNG = 0V, VFB = 0.63V, VSENSE– = 2.5V
VRNG = INTVCC, VFB = 0.63V, VSENSE– = 2.5V
–50
–15
–25
mV
mV
mV
ISENSE1,2+SENSE1,2+ Pins Input Bias Current VSENSE+ = 0.6V
VSENSE+ = 5V ±5
1±50
±2 nA
µA
ISENSE1,2–SENSE1,2– Pins Input Bias Current
(Internal 500k Resistor to SGND) VSENSE– = 0.6V
VSENSE– = 5V 1.2
10 µA
µA
Start-Up and Shutdown
VRUN1,2 RUN Pin On Threshold VRUN1,2 Rising l1.1 1.2 1.3 V
RUN Pin On Hysteresis VRUN1,2 Falling from On Threshold 100 mV
IRUN1,2 RUN Pin Pull-Up Current when Off RUN1,2 = SGND 1.2 µA
RUN Pin Pull-Up Current Hysteresis IRUN1,2(HYS) = IRUN1,2(ON) – IRUN1,2(OFF) 5 µA
UVLO INTVCC Undervoltage Lockout INTVCC Falling
INTVCC Rising
l
l
3.3 3.7
4.2
4.5 V
V
ITRACK/SS1,2 Soft-Start Pull-Up Current 0V < TRACK/SS1,2 < 0.6V 1 µA
Frequency and Clock Synchronization
fClock Output Frequency
(Steady-State Switching Frequency) RT = 205k
RT = 80.6k
RT = 18.2k
450 200
500
2000
550 kHz
kHz
kHz
Channel 2 Phase (Relative to Channel 1) PHASMD = SGND
PHASMD = Floating
PHASMD = INTVCC
180
180
240
Deg
Deg
Deg
CLKOUT Phase (Relative to Channel 1) PHASMD = SGND
PHASMD = Floating
PHASMD = INTVCC
60
90
120
Deg
Deg
Deg
VPLLIN(H) Clock Input High Level Into MODE/PLLIN 2 V
VPLLIN(L) Clock Input Low Level Into MODE/PLLIN 0.5 V
RMODE/PLLIN MODE/PLLIN Input DC Resistance With Respect to SGND 600 kΩ
Gate Drivers
RTG(UP)1,2 TG Driver Pull-Up On Resistance TG High 2.5 Ω
RTG(DOWN)1,2 TG Driver Pull-Down On Resistance TG Low 1.2 Ω
RBG(UP)1,2 BG Driver Pull-Up On Resistance BG High 2.5 Ω
RBG(DOWN)1,2 BG Driver Pull-Down On Resistance BG Low 0.8 Ω
tD(TG/BG)1,2 Top Gate Off to Bottom Gate On Delay Time (Note 6) 20 ns
tD(BG/TG)1,2 Bottom Gate Off to Top Gate On Delay Time (Note 6) 15 ns
LTC3838
5
3838fb
For more information www.linear.com/LTC3838
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The junction temperature (TJ, in °C) is calculated from the ambient
temperature (TA, in °C) and power dissipation (PD, in Watts) according to
the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: The LTC3838 is tested under pulsed loading conditions such that
TJ ≈ TA. The LTC3838E is guaranteed to meet specifications over the 0°C
to 85°C operating junction temperature range. Specifications over the
–40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LTC3838I is guaranteed to meet specifications over the –40°C to
125°C operating junction temperature range . Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors.
elecTrical characTerisTics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3).
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Internal VCC Regulator
VDRVCC1 Internally Regulated DRVCC1 Voltage 6V < VIN < 38V 5.0 5.3 5.6 V
DRVCC1 Load Regulation IDRVCC1 = 0mA to –100mA –1.5 –3 %
VEXTVCC EXTVCC Switchover Voltage EXTVCC Rising 4.4 4.6 4.8 V
EXTVCC Switchover Hysteresis 200 mV
EXTVCC to DRVCC2 Voltage Drop VEXTVCC = 5V, IDRVCC2 = –100mA 200 mV
PGood Output
OV PGOOD Overvoltage Threshold VFB1,2 Rising, with Respect to Regulated Voltage 5 7.5 10 %
UV PGOOD Undervoltage Threshold VFB1,2 Falling, with Respect to Regulated Voltage –5 –7.5 –10 %
PGOOD Threshold Hysteresis VFB1,2 Returning to Reference Voltage 2 %
VPGOOD(L)1,2 PGOOD Low Voltage IPGOOD = 2mA 0.1 0.3 V
tD(PGOOD)1,2 Delay from VFB Fault (OV/UV) to PGOOD
Falling
Delay from VFB Good to PGOOD Rising
50
20
µs
µs
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. The maximum
rated junction temperature will be exceeded when this protection is active.
Continuous operation above the specified absolute maximum operating
junction temperature may impair device reliability or permanently damage
the device.
Note 5: The LTC3838 is tested in a feedback loop that adjusts
(VOUTSENSE1+ – VOUTSENSE1–) or VFB2 to achieve specified error amplifier
output voltages (ITH1,2).
Note 6: Delay times are measured with top gate (TG) and bottom gate
(BG) driving minimum load, and using 50% levels.
LTC3838
6
3838fb
For more information www.linear.com/LTC3838
Typical perForMance characTerisTics
Transient Response
(Discontinuous Mode)
Load Release with Detect Transient (DTR)
Feature Enabled
Load Release with Detect Transient (DTR)
Feature Disabled
Load Step
(Discontinuous Mode)
Load Release
(Discontinuous Mode)
Transient Response
(Forced Continuous Mode)
Load Step
(Forced Continuous Mode)
Load Release
(Forced Continuous Mode)
ILOAD
10A/DIV
IL
10A/DIV
50µs/DIV 3838 G01
LOAD TRANSIENT = 0A TO 15A TO 0A
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
VOUT
50mV/DIV
AC-COUPLED
ILOAD
10A/DIV
IL
10A/DIV
5µs/DIV 3838 G02
LOAD STEP = 0A TO 15A
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, VRNG1
= SGND
VOUT
50mV/DIV
AC-COUPLED
ILOAD
10A/DIV
IL
10A/DIV
5µs/DIV 3838 G03
LOAD RELEASE = 15A TO 0A
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
VOUT
50mV/DIV
AC-COUPLED
ILOAD
10A/DIV
IL
10A/DIV
50µs/DIV 3838 G04
LOAD TRANSIENT = 500mA TO 15A TO 500mA
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, VRNG1
= SGND
VOUT
50mV/DIV
AC-COUPLED
ILOAD
10A/DIV
IL
10A/DIV
5µs/DIV 3838 G05
LOAD STEP = 500mA TO 15A
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, VRNG1
= SGND
VOUT
50mV/DIV
AC-COUPLED
ILOAD
10A/DIV
IL
10A/DIV
5µs/DIV 3838 G06
LOAD RELEASE = 15A TO 500mA
VIN = 12V
VOUT = 1.2V
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
VOUT
50mV/DIV
AC-COUPLED
SW
3V/DIV
VOUT
50mV/DIV
AC-COUPLED
ITH
1V/DIV
IL
10A/DIV
5µs/DIV 3838 G08
LOAD RELEASE = 15A TO 5A
VIN = 5V
VOUT = 0.6V
FIGURE 17 CIRCUIT, CHANNEL 1 MODIFIED:
RFB2 = 0Ω, VRNG2 = SGND, CITH1 = 120pF, CITH2 = 0pF,
RITH1/2 = 46.4k TO SGND//42.2k TO INTVCC,
CONNECTION FROM RITH1/2 AND CITH1 TO DTR1 PIN REMOVED.
DTR1 PIN TIED TO INTVCC
SW
3V/DIV
VOUT
50mV/DIV
AC-COUPLED
ITH
1V/DIV
IL
10A/DIV
5µs/DIV 3838 G07
LOAD RELEASE = 15A TO 5A
VIN = 5V
VOUT = 0.6V
FIGURE 17 CIRCUIT, CHANNEL 1 MODIFIED:
RFB2 = 0Ω, VRNG2 = SGND, CITH1 = 120pF, CITH2 = 0pF,
FROM DTR1 PIN: RITH1 = 46.4k TO SGND, RITH2 = 42.2k TO INTVCC
LTC3838
7
3838fb
For more information www.linear.com/LTC3838
Typical perForMance characTerisTics
Phase Relationship:
PHASMD = Ground
Phase Relationship:
PHASMD = Float
Phase Relationship:
PHASMD = INTVCC
Overcurrent Protection
Regular Soft Start-Up
Short-Circuit Protection
Soft Start-Up Into
Pre-Biased Output
Overvoltage Protection
Output Tracking
RUN1
5V/DIV
VOUT
500mV/DIV
1ms/DIV 3838 G09
CSS = 10nF
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
TRACK/SS1
200mV/DIV
RUN1
5V/DIV
VOUT
500mV/DIV
1ms/DIV 3838 G10
CSS = 10nF
VIN = 12V
VOUT = 1.2V
VOUT PRE-BIASED TO 0.75V
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
TRACK/SS1
200mV/DIV
VOUT
500mV/DIV
10ms/DIV 3838 G11
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
TRACK/SS1
200mV/DIV
VOUT
100mV/DIV
5ms/DIV 3838 G12
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
CURRENT LIMIT = 17A
OVERLOAD = 7.5A TO 17.5A
FIGURE 17 CIRCUIT, CHANNEL 1, V
IL
5A/DIV
FULL CURRENT LIMIT
WHEN VOUT HIGHER
THAN HALF OF REGULATED
VOUT
1V/DIV
SHORT-
CIRCUIT
TRIGGER
500µs/DIV 3838 G13
VIN = 12V
VOUT = 1.2V
ILOAD = 0A
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1 = SGND
IL
10A/DIV COUT
RECHARGE
CURRENT LIMIT STARTS TO FOLD BACK AS
VOUT DROPS BELOW HALF OF REGULATED
VOUT
100mV/DIV
AC-COUPLED
20µs/DIV 3838 G14
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS
MODE
ILOAD = 0A
FIGURE 17 CIRCUIT, CHANNEL 1, V
RNG1
= SGND
BG STAYS ON UNTIL
VOUT IS PULLED
BELOW OVERVOLTAGE
THRESHOLD
IL
10A/DIV
BG1
5V/DIV
OVERVOLTAGE CREATED BY APPLYING
A CHARGED CAPACITOR TO VOUT
500ns/DIV
60°
0°
3838 G15
FIGURE 19 CIRCUIT
VIN = 12V
VOUT1 = 5V, VOUT2 = 3.3V
LOAD = 0A
MODE/PLLIN = 333kHz EXTERNAL CLOCK
CLKOUT
5V/DIV
SW2
10V/DIV
SW1
10V/DIV
PLLIN
5V/DIV
180°
500ns/DIV
0°
3838 G15
FIGURE 19 CIRCUIT
VIN = 12V
VOUT1 = 5V, VOUT2 = 3.3V
LOAD = 0A
MODE/PLLIN = 333kHz EXTERNAL CLOCK
CLKOUT
5V/DIV
SW2
10V/DIV
SW1
10V/DIV
PLLIN
5V/DIV
90°
180°
500ns/DIV
0°
3838 G17
FIGURE 19 CIRCUIT
VIN = 12V
VOUT1 = 5V, VOUT2 = 3.3V
LOAD = 0A
MODE/PLLIN = 333kHz EXTERNAL CLOCK
CLKOUT
5V/DIV
SW2
10V/DIV
SW1
10V/DIV
PLLIN
5V/DIV
120°
240°
LTC3838
8
3838fb
For more information www.linear.com/LTC3838
Typical perForMance characTerisTics
CLKOUT/Switching Frequency
vs Input Voltage
CLKOUT/Switching Frequency
vs Temperature
tON(MIN) and tOFF(MIN)
vs VOUT (Voltage on SENSE– Pin)
tON(MIN) and tOFF(MIN)
vs Voltage on VIN Pin
tON(MIN) and tOFF(MIN)
vs Switching Frequency
Output Regulation
vs Input Voltage
Error Amplifier Transconductance
vs Temperature
Output Regulation
vs Load Current
Output Regulation
vs Temperature
VIN (V)
0
–0.2
NORMALIZED ∆V
OUT
(%)
–0.1
0
0.1
0.2
5 10 15 20
3838 G18
25 30 35 40
CHANNEL 1
CHANNEL 2
VOUT = 0.6V
ILOAD = 5A
VOUT NORMALIZED AT VIN = 15V
ILOAD (A)
0
NORMALIZED ∆V
OUT
(%)
0
0.1
8
3838 G19
–0.1
–0.2 24610
0.2
CHANNEL 1
CHANNEL 2
VIN = 15V
VOUT = 0.6V
VOUT NORMALIZED AT ILOAD = 4A
TEMPERATURE (°C)
–50
–0.6
NORMALIZED ∆V
OUT
(%)
–0.4
–0.2
0
0.2
0 50 100
150
3838 G20
0.4
0.6
–25 25 75 125
CHANNEL 1
CHANNEL 2
VIN = 15V
VOUT = 0.6V
ILOAD = 0A
VOUT NORMALIZED AT TA = 25°C
VIN (V)
0
–2
NORMALIZED ∆f
(%)
–1
0
1
2
5 10 15 20
3838 G21
25 30 35 40
VOUT = 0.6V
ILOAD = 5A
f = 500kHz
FREQUENCY NORMALIZED AT VIN = 15V
TEMPERATURE (°C)
–50
–2
NORMALIZED ∆f
(%)
–1
0
1
2
–25 0 25 50
3838 G23
75 100 125
150
VIN = 15V, VOUT = 0.6V
ILOAD = 0A
f = 500kHz
FREQUENCY NORMALIZED AT TA = 25°C
VSENSE– (V)
0
0
TIME (ns)
20
40
60
123 4
3838 G24
5
80
100
10
30
50
70
90
6
VIN = 38V
RT ADJUSTED FOR fCLKOUT = 2MHz
tOFF(MIN)
tON(MIN)
VIN (V)
0
0
TIME (ns)
20
40
60
510 15 20
3838 G25
353025
80
100
10
30
50
70
90
40
VOUT = 0.6V
RT ADJUSTED FOR fCLKOUT = 2MHz
tOFF(MIN)
tON(MIN)
CLKOUT/SWITCHING FREQUENCY (kHz)
200
0
TIME (ns)
20
40
60
500 800 1100 1400
3838 G26
1700
80
100
10
30
50
70
90
2000
VIN = 38V
VOUT = 0.6V
tOFF(MIN)
tON(MIN)
TEMPERATURE (°C)
–50
1.50
TRANSCONDUCTANCE (mS)
1.55
1.60
1.65
1.70
0 50 100 150
3838 G27
1.75
1.80
–25 25 75 125
LTC3838
9
3838fb
For more information www.linear.com/LTC3838
Typical perForMance characTerisTics
RUN Pin Thresholds
vs Temperature
RUN Pull-Up Currents
vs Temperature
TRACK/SS Pull-Up Currents
vs Temperature
INTVCC Undervoltage Lockout
Thresholds vs Temperature
Shutdown Current Into VIN Pin
vs Voltage on VIN Pin
Quiescent Current Into VIN Pin
vs Temperature
Current Sense Voltage
vs ITH Voltage
Maximum Current Sense Voltage
vs Temperature
Maximum Current Sense Voltage
vs Voltage on SENSE– Pin
ITH VOLTAGE (V)
0
–60
CURRENT SENSE VOLTAGE (mV)
–40
0
20
40
1.6
120
3838 G28
–20
0.8
0.4 2
1.2
2.4
60
80
100
VRNG = 2V
VRNG = 1V
VRNG = 0.6V
FORCED CONTINUOUS MODE
TEMPERATURE (°C)
–50
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
20
40
60
80
0 50 100
150
3838 G29
100
120
–25 25 75 125
VRNG = 2V
VRNG = 1V
VRNG = 0.6V
TEMPERATURE (°C)
–50
RUN PIN THRESHOLDS (V)
0.8
1.2
150
3838 G30
0.4
0050 100
–25 25 75 125
1.6
0.6
1.0
0.2
1.4 SWITCHING REGION
SHUTDOWN REGION
STAND-BY REGION
TEMPERATURE (°C)
–50
CURRENT (µA)
4
6
150
3838 G31
2
0050 100
–25 25 75 125
8
3
5
1
7
RUN PIN ABOVE 1.2V
SWITCHING THRESHOLD
RUN PIN BELOW 1.2V
SWITCHING THRESHOLD
TEMPERATURE (°C)
–50
CURRENT (µA)
1.00
1.10
150
3838 G32
0.90
0.80 050 100
–25 25 75 125
1.20
0.95
1.05
0.85
1.15
TEMPERATURE (°C)
–50
3.3
UVLO THRESHOLDS (V)
3.5
3.7
3.9
4.1
0 50 100 150
3838 G33
4.3
4.5
–25 25 75 125
UVLO RELEASE
(INTVCC RISING)
UVLO LOCK
(INTVCC FALLING)
VIN (V)
0
CURRENT (µA)
20
30
40
3838 G34
10
010 20 30
515 25 35
40
15
25
5
35
130°C
25°C
–45°C
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (mA)
2.5
3.0
3.5
25 75 150
3838 G35
2.0
1.5
1.0 –25 0 50 100 125
BOTH CHANNELS ON
CHANNEL 1 ON ONLY
CHANNEL 2 ON ONLY
SENSE PIN VOLTAGE (V)
–0.5
0
MAXIMUM CURRENT SENSE
–
VOLTAGE (mV)
20
40
60
80
120
0.5 1.5 2.5 3.5
3838 G22
4.5 5.5
100 VRNG = 2V
VRNG = 1V
VRNG = 0.6V
LTC3838
10
3838fb
For more information www.linear.com/LTC3838
pin FuncTions
(QFN/TSSOP)
PHASMD (Pin 4/Pin 8): Phase Selector Input. This pin
determines the relative phases of channels and the
CLKOUT signal. With zero phase being defined as the
rising edge of TG1: Pulling this pin to SGND locks TG2 to
180°, and CLKOUT to 60°. Connecting this pin to INTVCC
locks TG2 to 240° and CLKOUT to 120°. Floating this pin
locks TG2 to 180° and CLKOUT to 90°.
MODE/PLLIN (Pin 5/Pin 9): Operation Mode Selection
or External Clock Synchronization Input. When this pin
is tied to INTVCC, forced continuous mode operation is
selected. Tying this pin to SGND allows discontinuous
mode operation. When an external clock is applied at this
pin, both channels operate in forced continuous mode and
synchronize to the external clock.
CLKOUT (Pin 6/Pin 10): Clock Output of Internal Clock
Generator. Its output level swings between INTVCC and
SGND. If clock input is present at the MODE/PLLIN pin, it
will be synchronized to the input clock, with phase set by
the PHASMD pin. If no clock is present at MODE/PLLIN, its
frequency will be set by the RT pin. To synchronize other
controllers, it can be connected to their MODE/PLLIN pins.
SGND (Pin 7/Pin 11): Signal Ground. All small-signal analog
and compensation components should be connected to
this ground. Connect SGND to the exposed pad and PGND
pin using a single PCB trace.
RT (Pin 8/Pin 12): Clock Generator Frequency Program-
ming Pin. Connect an external resistor from RT to SGND
to program the switching frequency between 200kHz and
2MHz. An external clock applied to MODE/PLLIN should
be within ±30% of this programmed frequency to ensure
frequency lock. When the RT pin is floating, the frequency
is internally set to be slightly under 200kHz.
VRNG1, VRNG2 (Pins 9, 3/Pins 13, 7): Current Sense Volt-
age Range Inputs. When programmed between 0.6V and
2V, the voltage applied to VRNG1,2 is twenty times (20×)
the maximum sense voltage between SENSE1,2+ and
SENSE1,2–, i.e., for either channel, (VSENSE+ – VSENSE–) =
0.05 • VRNG. If a VRNG is tied to SGND, the channel oper-
ates with a maximum sense voltage of 30mV, equivalent
to a VRNG of 0.6V; If tied to INTVCC, a maximum sense
voltage of 50mV, equivalent to a VRNG of 1V.
ITH1, ITH2 (Pins 10, 2/Pins 14, 6): Current Control
Threshold. This pin is the output of the error amplifier and
the switching regulator’s compensation point. The current
comparator threshold increases with this control voltage.
The voltage ranges from 0V to 2.4V, with 0.8V correspond-
ing to zero sense voltage (zero inductor valley current).
TRACK/SS1, TRACK/SS2 (Pins 11, 1/Pins 15, 5): External
Tracking and Soft-Start Input. The LTC3838 regulates the
feedback voltages (VOUTSENSE1+ – VOUTSENSE1–) and VFB2
to the smaller of 0.6V or the voltage on the TRACK/SS1,2
pins respectively. An internal 1µA temperature-independent
pull-up current source is connected to each TRACK/SS
pin. A capacitor to ground at this pin sets the ramp time
to the final regulated output voltage. Alternatively, another
voltage supply connected to this pin allows the output to
track the other supply during start-up.
VOUTSENSE1+ (Pin 12/Pin 16): Differential Output Sense
Amplifier (+) Input of Channel 1. Connect this pin to a
feedback resistor divider between the positive and negative
output capacitor terminals of VOUT1. In nominal operation
the LTC3838 will attempt to regulate the differential output
voltage VOUT1 to 0.6V divided by the feedback resistor
divider ratio.
LTC3838
11
3838fb
For more information www.linear.com/LTC3838
VOUTSENSE1– (Pin 13/Pin 17): Differential Output Sense
Amplifier (–) Input of Channel 1. Connect this pin to the
negative terminal of the output load capacitor of VOUT1.
SENSE1+, SENSE2+ (Pins 14, 37/Pins 18, 3): Differential
Current Sense Comparator (+) Inputs. The ITH pin voltage
and controlled offsets between the SENSE+ and SENSE–
pins set the current trip threshold. The comparator can
be used for RSENSE sensing or inductor DCR sensing. For
RSENSE sensing, Kelvin (4-wire) connect the SENSE+ pin
to the (+) terminal of RSENSE. For DCR sensing, tie the
SENSE+ pins to the connection between the DCR sense
capacitor and sense resistor tied across the inductor.
SENSE1–, SENSE2– (Pins 15, 36/Pins 19, 2): Differential
Current Sense Comparator (–) Input. The comparator can
be used for RSENSE sensing or inductor DCR sensing.
For RSENSE sensing,
Kelvin (4-wire) connect
the SENSE–
pin to the (–) terminal of RSENSE. For DCR sensing, tie
the SENSE– pin to the DCR sense capacitor tied to the
inductor VOUT node connection. These pins also func-
tion as output voltage sense pins for the top MOSFET
on-time adjustment. The impedance looking into these
pins is different from the SENSE+ pins because there
is an additional 500k internal resistor from each of the
SENSE– pins to SGND.
DTR1, DTR2 (Pins 16, 35/Pins 20, 1): Detect Load-
Release Transient for Overshoot Reduction. When load
current suddenly drops, if voltage on this DTR pin drops
below half of INTVCC, the bottom gate (BG) could turn
off, allowing the inductor current to drop to zero faster,
thus reducing the VOUT overshoot. (Refer to Load-Release
Transient Detection in the Applications Information section
for more details.) An internal 2.5μA current source pulls
this pin toward INTVCC. To disable the DTR feature, simply
tie the DTR pin to INTVCC.
RUN1, RUN2 (Pins 17, 34/Pins 21, 38): Run Control
Inputs. An internal proportional-to-absolute-temperature
(PTAT) pull-up current source (~1.2µA at 25°C) is constantly
connected to this pin. Taking both RUN1 and RUN2 pins
below a threshold voltage (~0.8V at 25°C) shuts down all
bias of INTVCC and DRVCC and places the LTC3838 into
micropower shutdown mode. Allowing either RUN pin to
rise above this threshold would turn on the internal bias
supply and the circuitry for the particular channel. When
a RUN pin rises above 1.2V, its corresponding channel’s
TG and BG drivers are turned on and an additional 5µA
temperature-independent pull-up current is connected
internally to the RUN pin. Either RUN pin can sink up to
50µA, or be forced no higher than 6V.
PGOOD1, PGOOD2 (Pins 18, 33/Pins 22, 37): Power Good
Indicator Outputs. This open-drain logic output is pulled
to ground when the output voltage goes out of a ±7.5%
window around the regulation point, after a 50µs power-
bad-masking delay. Returning to the regulation point, there
is a much shorter delay to power good, and a hysteresis
of around 2% on both sides of the voltage window.
BOOST1, BOOST2 (Pins 19, 32/Pins 23, 36): Boosted
Floating Supplies for Top MOSFET Drivers. The (+) terminal
of the bootstrap capacitor, CB, connects to this pin. The
BOOST pins swing by a VIN between a diode drop below
DRVCC, or (DRVCC – VD) and (VIN + DRVCC – VD).
TG1, TG2 (Pins 20, 31/Pins 24, 35): Top Gate Driver
Outputs. The TG pins drive the gates of the top N-channel
power MOSFET with a voltage swing of VDRVCC between
SW and BOOST.
pin FuncTions
(QFN/TSSOP)
LTC3838
12
3838fb
For more information www.linear.com/LTC3838
SW1, SW2 (Pins 21, 30/Pins 25, 34): Switch Node Con-
nection to Inductors. Voltage swings are from a diode
voltage below ground to VIN. The (–) terminal of the
bootstrap capacitor, CB, connects to this node.
BG1, BG2 (Pins 22, 29/Pins 26, 33): Bottom Gate
Driver Outputs. The BG pins drive the gates of the bottom
N-channel power MOSFET between PGND and DRVCC.
DRVCC1, DRVCC2 (Pins 23, 28/Pins 27, 32): Supplies of
Bottom Gate Drivers. DRVCC1 is also the output of an internal
5.3V regulator. DRVCC2 is also the output of the EXTVCC
switch. Normally the two DRVCC pins are shorted together
on the PCB, and decoupled to PGND with a minimum of
4.7µF ceramic capacitor, CDRVCC.
VIN (Pin 24/Pin 28): Input Voltage Supply. The supply
voltage can range from 4.5V to 38V. For increased noise
immunity decouple this pin to SGND with an RC filter.
Voltage at this pin is also used to adjust top gate on-time,
therefore it is recommended to tie this pin to the main
power input supply through an RC filter.
PGND (Pin 25, Exposed Pad Pin 39/Pin 29, Exposed
Pad Pin 39): Power Ground. Connect this pin as close
as practical to the source of the bottom N-channel power
MOSFET, the (–) terminal of CDRVCC and the (–) terminal
of CIN. Connect the exposed pad and PGND pin to SGND
pin using a single PCB trace under the IC. The exposed
pad must be soldered to the circuit board for electrical
and rated thermal performance.
pin FuncTions
(QFN/TSSOP)
INTVCC (Pin 26/Pin 30): Supply Input for Internal Circuitry
(Not Including Gate Drivers). Normally powered from the
DRVCC pins through a decoupling RC filter to SGND (typi-
cally 2Ω and 1µF).
EXTVCC (Pin 27/Pin 31): External Power Input. When
EXTVCC exceeds the switchover voltage (typically 4.6V),
an internal switch connects this pin to DRVCC2 and shuts
down the internal regulator so that INTVCC and gate driv-
ers draw power from EXTVCC. The VIN pin still needs to
be powered up but draws minimum current.
VFB2 (Pin 38/Pin 4): Error Amplifier Feedback Input for
Channel 2. This pin connects the error amplifier to an
external feedback resistor divider from VOUT2. In nominal
operation the LTC3838 will attempt to regulate the VOUT2
to 0.6V divided by the feedback resistor divider ratio.
Shorting this pin to INTVCC will disable Channel 2’s er-
ror amplifier, and internally connect ITH2 to ITH1. (As a
result, TRACK/SS2 is no longer functional and PGOOD2
is always pulling low.) By doing so, this part can function
as a dual phase, single VOUT step-down controller, and
the two channels use a single Channel1’s error amplifier
for the ITH output and compensation.
LTC3838
13
3838fb
For more information www.linear.com/LTC3838
FuncTional DiagraM
–
+
TG
BOOST
TG
DRV
VIN
UVLO
~0.8V
BG
PGND
SENSE+
SENSE–
TRACK/SS
BG DRV
EN_DRV
5µA
RUN
SW
EXTVCC
INTVCC
DRVCC2
DRVCC1
~4.6V
DB
DRVCC
CB
CINTVCC
CDRVCC
COUT
CSS
3838 FD
RFB2
RFB1
VOUT
VIN
MT
MB
LRSENSE
–
+
–
+
4.2V
–
+
1.2V
250k
START
STOP
250k
SENSE–
VIN
–
+
–
+–
+
1-2µA
PTAT
LOGIC
CONTROL
MODE/PLLIN
ONE-SHOT
TIMER
ON-TIME
ADJUST
ICMP IREV
FORCED
CONTINUOUS
MODE
PHASE
DETECTOR
CLK1
CLK2 TO CHANNEL 2
MODE/CLK
DETECT
CLOCK PLL/
GENERATOR
DUPLICATE DASHED
LINE BOX FOR
CHANNEL 2
IN
LDOEN
OUT SD
RT
RT
CLKOUT
PGOOD
INTVCC
RPGD
gmgmEA
0.6V
+
+
–
1µA
UV
–
+
–
+
DIFFAMP
(A = 1)
0.645V
VRNG ITH DTR
1/2 INTVCC
TO LOGIC
CONTROL
LOAD
RELEASE
DETECTION
0.555V
–
+
OV
DELAY
CITH2
CITH1
INTVCC
VOUTSENSE1+
VOUTSENSE1–
VFB2
SGND
CHANNEL 2 ONLY
RITH2
INTVCC
RITH1
INTVCC
LTC3838
14
3838fb
For more information www.linear.com/LTC3838
operaTion
(Refer to Functional Diagram)
Main Control Loop
The LTC3838 is a controlled on-time, valley current mode
step-down DC/DC dual controller with two channels
operating out of phase. Each channel drives both main
and synchronous N-channel MOSFETs. The two channels
can be either configured to two independently regulated
outputs, or combined into a single output.
The top MOSFET is turned on for a time interval determined
by a one-shot timer. The duration of the one-shot timer is
controlled to maintain a fixed switching frequency. As the
top MOSFET is turned off, the bottom MOSFET is turned
on after a small delay. The delay, or dead time, is to avoid
both top and bottom MOSFETs being on at the same time,
causing shoot-through current from VIN directly to power
ground. The next switching cycle is initiated when the cur-
rent comparator, ICMP, senses that inductor current falls
below the trip level set by voltages at the ITH and VRNG
pins. The bottom MOSFET is turned off immediately and
the top MOSFET on again, restarting the one-shot timer
and repeating the cycle. In order to avoid shoot-through
current, there is also a small dead-time delay before the
top MOSFET turns on. At this moment, the inductor cur-
rent hits its “valley” and starts to rise again.
Inductor current is determined by sensing the voltage
between SENSE+ and SENSE–, either by using an explicit
resistor connected in series with the inductor or by implic-
itly sensing the inductor’s DC resistive (DCR) voltage drop
through an RC filter connected across the inductor. The
trip level of the current comparator, ICMP
, is proportional
to the voltage at the ITH pin, with a zero-current threshold
corresponding to an ITH voltage of around 0.8V.
The error amplifier (EA) adjusts this ITH voltage by com-
paring the feedback signal to the internal 0.6V reference
voltage. On Channel 1, the difference amplifier (DIFFAMP)
converts the differential feedback signal (VOUTSENSE1+ –
VOUTSENSE1–) to a single-ended input for the EA; Channel2
uses VFB2 directly with respect to SGND. Output voltage is
regulated so that the feedback voltage is equal to the internal
0.6V reference. If the load current increases/decreases, it
causes a momentary drop/rise in the differential feedback
voltage relative to the reference. The EA then moves ITH
voltage, or inductor valley current setpoint, higher/lower
until the average inductor current again matches the load
current, so that the output voltage comes back to the
regulated voltage.
The LTC3838 features a detect transient (DTR) pin to detect
“load-release”, or a transient where the load current sud-
denly drops, by monitoring the first derivative of the ITH
voltage. When detected, the bottom gate (BG) is turned
off and inductor current flows through the body diode
in the bottom MOSFET, allowing the SW node voltage to
drop below PGND by the body diode’s forward-conduction
voltage. This creates a more negative differential voltage
(VSW – VOUT) across the inductor, allowing the inductor
current to drop faster to zero, thus creating less overshoot
on VOUT. See Load-Release Transient Detection in Applica-
tions Information for details.
Differential Output Sensing
This dual controller’s first channel features differential
output voltage sensing. The output voltage is resistively
divided externally to create a feedback voltage for the con-
troller. The internal difference amplifier (DIFFAMP) senses
this feedback voltage with respect to the output’s remote
ground reference to create a differential feedback voltage.
This scheme eliminates any ground offsets between local
ground and remote output ground, resulting in a more
accurate output voltage. Channel 1 allows remote output
ground to deviate as much as ±500mV with respect to
local ground (SGND).
DRVCC/EXTVCC/INTVCC Power
DRVCC1,2 are the power for the bottom MOSFET drivers.
Normally the two DRVCC pins are shorted together on
the PCB, and decoupled to PGND with a minimum 4.7µF
ceramic capacitor, CDRVCC. The top MOSFET drivers are
biased from the floating bootstrap capacitors (CB1,2)
which are recharged during each cycle through an external
Schottky diode when the top MOSFET turns off and the
SW pin swings down.
The DRVCC can be powered on two ways: an internal low-
dropout (LDO) linear voltage regulator that is powered
LTC3838
15
3838fb
For more information www.linear.com/LTC3838
from VIN and can output 5.3V to DRVCC1. Alternatively,
an internal EXTVCC switch (with on-resistance of around
2Ω) can short the EXTVCC pin to DRVCC2.
If the EXTVCC pin is below the EXTVCC switchover voltage
(typically 4.6V with 200mV hysteresis, see the Electri-
cal Characteristics Table), then the internal 5.3V LDO is
enabled. If the EXTVCC pin is tied to an external voltage
source greater than this EXTVCC switchover voltage, then
the LDO is shut down and the internal EXTVCC switch
shorts the EXTVCC pin to the DRVCC2 pin, thereby power-
ing DRVCC and INTVCC with the external voltage source
and helping to increase overall efficiency and decrease
internal self heating from power dissipated in the LDO.
This external power source could be the output of the
step-down converter itself (if the output is programmed
to higher than the switchover voltage’s higher limit, 4.8V).
The VIN pin still needs to be powered up but now draws
minimum current.
Power for most internal control circuitry other than gate
drivers is derived from the INTVCC pin. INTVCC can be pow-
ered from the combined DRVCC pins through an external
RC filter to SGND to filter out noises due to switching.
Shutdown and Start-Up
Each of the RUN1 and RUN2 pins has an internal proportion-
al-to-absolute-temperature (PTAT) current source (around
1.2µA at 25°C) to pull up the pins. Taking both RUN1 and
RUN2 pins below a certain threshold voltage (around 0.8V
at 25°C) shuts down all bias of INTVCC and DRVCC and
places the LTC3838 into micropower shutdown mode
with a minimum IQ at the VIN pin. The LTC3838’s DRVCC
(through the internal 5.3V LDO regulator or EXTVCC) and
the corresponding channel’s internal circuitry off INTVCC
will be biased up when either or both RUN pins are pulled
up above the 0.8V threshold, either by the internal pull-up
current or driven directly by external voltage source such
as logic gate output.
A channel of the LTC3838 will not start switching until the
RUN pin of the respective channel is pulled up to 1.2V.
When a RUN pin rises above 1.2V, the corresponding
channel’s TG and BG drivers are enabled, and TRACK/
SS released. An additional 5µA temperature-independent
pull-up current is connected internally to the channel’s
respective RUN pin. To turn off TG, BG and the addi-
tional 5µA pull-up current, RUN needs to be pulled down
below 1.2V by about 100mV. These built-in current and
voltage hystereses prevent false jittery turn-on and turn-off
due to noise. Such features on the RUN pins allow input
undervoltage lockout (UVLO) to be set up using external
voltage dividers from VIN.
The start-up of a channel’s output voltage (VOUT) is
controlled by the voltage on its TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 0.6V internal
reference, the (differential) feedback voltage is regulated to
the TRACK/SS voltage instead of the 0.6V reference. The
TRACK/SS pin can be used to program the output voltage
soft-start ramp-up time by connecting an external capaci-
tor from a TRACK/SS pin to signal ground. An internal
temperature-independent 1µA pull-up current charges
this capacitor, creating a voltage ramp on the TRACK/SS
pin. As the TRACK/SS voltage rises linearly from ground
to 0.6V, the switching starts, VOUT ramps up smoothly to
its final value and the feedback voltage to 0.6V. TRACK/
SS will keep rising beyond 0.6V, until being clamped to
around 3.7V.
Alternatively, the TRACK/SS pin can be used to track an
external supply like in a master slave configuration. Typi-
cally, this requires connecting a resistor divider from the
master supply to the TRACK/SS pin (see the Applications
Information section).
TRACK/SS is pulled low internally when the correspond-
ing channel’s RUN pin is pulled below the 1.2V threshold
(hysteresis applies), or when INTVCC or either of the
DRVCC1,2 pins drop below their respective undervoltage
lockout (UVLO) thresholds.
Light Load Current Operation
If the MODE/PLLIN pin is tied to INTVCC or an external clock
is applied to MODE/PLLIN, the LTC3838 will be forced to
operate in continuous mode. With load current less than
one-half of the full load peak-to-peak ripple, the inductor
current valley can drop to zero or become negative. This
allows constant-frequency operation but at the cost of low
efficiency at light loads.
operaTion
(Refer to Functional Diagram)
LTC3838
16
3838fb
For more information www.linear.com/LTC3838
If the MODE/PLLIN pin is left open or connected to signal
ground, the channel will transition into discontinuous mode
operation, where a current reversal comparator (IREV) shuts
off the bottom MOSFET (MB) as the inductor current ap-
proaches zero, thus preventing negative inductor current
and improving light-load efficiency. In this mode, both
switches can remain off for extended periods of time. As
the output capacitor discharges by load current and the
output voltage droops lower, EA will eventually move the
ITH voltage above the zero current level (0.8V) to initiate
another switching cycle.
Power Good and Fault Protection
Each PGOOD pin is connected to an internal open-drain
N-channel MOSFET. An external resistor or current source
can be used to pull this pin up to 6V (e.g., VOUT1,2 or DRVCC).
Overvoltage or undervoltage comparators (OV, UV) turn on
the MOSFET and pull the PGOOD pin low when the feedback
voltage is outside the ±7.5% window of the 0.6V refer-
ence voltage. The PGOOD pin is also pulled low when the
channel’s RUN pin is below the 1.2V threshold (hysteresis
applies), or in undervoltage lockout (UVLO). Note that feed-
back voltage of Channel 1 is sensed differentially through
VOUTSENSE1+ with respect to VOUTSENSE1–, while Channel 2
is sensed through VFB2 with respect to SGND.
When the feedback voltage is within the ±7.5% window,
the open-drain NMOS is turned off and the pin is pulled
up by the external source. The PGOOD pin will indicate
power good immediately after the feedback is within the
window. But when a feedback voltage of a channel goes
out of the window, there is an internal 50µs delay before
its PGOOD is pulled low. In an overvoltage (OV) condition,
MT is turned off and MB is turned on immediately without
delay and held on until the overvoltage condition clears.
Foldback current limiting is provided if the output is below
one-half of the regulated voltage, such as being shorted to
ground. As the feedback approaches 0V, the internal clamp
voltage for the ITH pin drops from 2.4V to around 1.27V,
which reduces the inductor valley current level to about
30% of its maximum value. Foldback current limiting is
disabled at start-up.
Frequency Selection and External Clock
Synchronization
An internal oscillator (clock generator) provides phase-
interleaved internal clock signals for individual channels
to lock up to. The switching frequency and phase of each
switching channel is independently controlled by adjust-
ing the top MOSFET turn-on time (on-time) through the
one-shot timer. This is achieved by sensing the phase
relationship between a top MOSFET turn-on signal and
its internal reference clock through a phase detector, and
the time interval of the one-shot timer is adjusted on a
cycle-by-cycle basis, so that the rising edge of the top
MOSFET turn-on is always trying to synchronize to the
internal reference clock signal for the respective channel.
The frequency of the internal oscillator can be programmed
from 200kHz to 2MHz by connecting a resistor, RT
, from the
RT pin to signal ground (SGND). The RT pin is regulated
to 1.2V internally.
For applications with stringent frequency or interference
requirements, an external clock source connected to the
MODE/PLLIN pin can be used to synchronize the internal
clock signals through a clock phase-locked loop (Clock
PLL). The LTC3838 operates in forced continuous mode
of operation when it is synchronized to the external clock.
The external clock frequency has to be within ±30% of the
internal oscillator frequency for successful synchroniza-
tion. The clock input levels should be no less than 2V for
“high” and no greater than 0.5V for “low”. The MODE/
PLLIN pin has an internal 600k pull-down resistor.
Multichip Operations
The PHASMD pin determines the relative phases between
the internal reference clock signals for the two channels
as well as the CLKOUT signal, as shown in Table 2. The
phases tabulated are relative to zero degree (0°) being
defined as the rising edge of the internal reference clock
signal of Channel 1. The CLKOUT signal can be used to
synchronize additional power stages in a multiphase power
supply solution feeding either a single high current output,
or separate outputs.
operaTion
(Refer to Functional Diagram)
LTC3838
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The system can be configured for up to 12-phase opera-
tion with a multichip solution. Typical configurations are
shown in Table 3 to interleave the phases of the channels.
Table 2
PHASMD SGND FLOAT INTVCC
Channel 1 0° 0° 0°
Channel 2 180° 180° 240°
CLKOUT 60° 90° 120°
Table 3
NUMBER OF
PHASES
NUMBER OF
LTC3838
PIN CONNECTIONS
[PIN NAME (CHIP NUMBER)]
2 1 PHASMD(1) = FLOAT or SGND
3 2, or 1 +
LTC3833 PHASMD(1) = INTVCC
MODE/PLLIN(2) = CLKOUT(1)
4 2 PHASMD(1) = FLOAT
PHASMD(2) = FLOAT or SGND
MODE/PLLIN(2) = CLKOUT(1)
6 3 PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT or SGND
MODE/PLLIN(3) = CLKOUT(2)
12 6 PHASMD(1) = SGND
PHASMD(2) = SGND
MODE/PLLIN(2) = CLKOUT(1)
PHASMD(3) = FLOAT
MODE/PLLIN(3) = CLKOUT(2)
PHASMD(4) = SGND
MODE/PLLIN(4) = CLKOUT(3)
PHASMD(5) = SGND
MODE/PLLIN(5) = CLKOUT(4)
PHASMD(6) = FLOAT or SGND
MODE/PLLIN(6) = CLKOUT(5)
Single-Output PolyPhase Configurations
To use LTC3838 for a 2-phase single output step-down
controller: Tie the VFB2 pin to INTVCC, which will disable
Channel 2’s error amplifier and internally connect ITH2 to
ITH1. Tie the compensation R-C components to the ITH1
pin. The ITH2 pin can be either left open or shorted to ITH1
externally. The TRACK/SS2 and PGOOD2 pins become
defunct and can be left open. Note that the RUN1, RUN2,
DTR1, DTR2, VRNG1 and VRNG2 pins still function for
the two channels individually, therefore should be shorted
externally for single-output applications. Set PHASMD
to SGND or FLOAT so that the two channels are 180°
out-of-phase. Efficiency losses may be substantially
reduced because the peak current drawn from the input
capacitor is effectively divided by the number of phases
used and power loss is proportional to the RMS current
squared. A 2-phase implementation can reduce the input
path power loss by up to 75%.
To make a single-output converter of three or more phases,
additional LTC3838 or LTC3833 chips can be used. The first
chip should be tied the same way as the 2-phase above. If
only one more channel of an additional LTC3838 is needed,
use Channel 1 for the additional phase:
• Tie the ITH1 pin to the ITH1 pin of the first chip
• Tie the RUN1 pin to the RUN pins of the first chip
• Tie the VOUTSENSE1+ pin to the VOUTSENSE1+ pin of the
first chip
• Tie the VOUTSENSE1– pin to the VOUTSENSE1– pin of the
first chip
• Tie the TRACK/SS1 pin to the TRACK/SS1 pin of the
first chip
If both channels are needed, the additional LTC3838 chip
should be tied the same way as the first LTC3838 chip to
disable the second channel’s EA:
• Tie the VFB2 pin to the chip’s own INTVCC
• Tie the ITH1 pin to the ITH1 pin of the first chip
• Tie the RUN pins to the RUN pins of the first chip
• Tie the VOUTSENSE1+ pin to the VOUTSENSE1+ pin of the
first chip
• Tie the VOUTSENSE1– pin to the VOUTSENSE1– pin of the
first chip
• Tie the TRACK/SS1 pin to the TRACK/SS1 pin of the
first chip
operaTion
(Refer to Functional Diagram)
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applicaTions inForMaTion
Once the required output voltage and operating frequency
have been determined, external component selection is
driven by load requirement, and begins with the selec-
tion of inductors and current sense method (either sense
resistors RSENSE or inductor DCR sensing). Next, power
MOSFETs are selected. Finally, input and output capaci-
tors are selected.
Output Voltage Programming
As shown in Figure 1, external resistor dividers are used
from the regulated outputs to their respective ground refer-
ences to program the output voltages. On Channel 1, the
resistive divider is tapped by the VOUTSENSE1+ pin, and the
ground reference is remotely sensed by the VOUTSENSE1–
pin, this voltage is sensed differentially. On Channel 2, the
resistive divider is tapped by the VFB2 pin, with respect to
signal ground at the SGND pin. By regulating the tapped
(differential) feedback voltages to the internal reference
0.6V, the resulting output voltages are:
VOUT1 – VOUTSENSE1– = 0.6V • (1 + RFB2/RFB1)
and
VOUT2 = 0.6V • (1 + RFB2/RFB1)
For example, if VOUT1 is programmed to 5V and the out-
put ground reference is sitting at –0.5V with respect to
SGND, then the absolute value of the output will be 4.5V
with respect to SGND. The minimum (differential) output
voltages are limited to the internal reference 0.6V, and the
maximum are 5.5V
.
The VOUTSENSE1+ pin is a high impedance pin with no
input bias current other than leakage in the nA range. The
VOUTSENSE1– pin has about 30µA of current flowing out
of the pin. The VFB2 pin is quasi-high impedance pin with
minimum bias current out of the pin.
Differential output sensing allows for more accurate output
regulation in high power distributed systems having large
line losses. Figure 2 illustrates the potential variations in
the power and ground lines due to parasitic elements.
The variations may be exacerbated in multi-application
systems with shared ground planes. Without differential
output sensing, these variations directly reflect as an error
in the regulated output voltage. The LTC3838 Channel 1’s
differential output sensing can correct for up to ±500mV
of variation in the output’s power and ground lines.
The LTC3838 Channel 1’s differential output sensing
scheme is distinct from conventional schemes where the
regulated output and its ground reference are directly
sensed with a difference amplifier whose output is then
divided down with an external resistor divider and fed
into the error amplifier input. This conventional scheme
is limited by the common mode input range of the differ-
ence amplifier and typically limits differential sensing to
the lower range of output voltages.
The LTC3838’s Channel 1 allows for seamless differential
output sensing by sensing the resistively divided feedback
voltage differentially. This allows for differential sensing
in the full output range from 0.6V to 5.5V. The difference
amplifier (DIFFAMP) has a bandwidth of 8MHz, high
RFB2
VOUTSENSE1+/VFB2
LTC3838
VOUTSENSE1–/SGND
COUT
3838 F01
V
OUT
RFB1
Figure 1. Setting Output Voltage
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enough so that it will not affect main loop compensation
and transient behavior.
To avoid noise coupling into the feedback voltages
(VOUTSENSE1+ or VFB2), the resistor dividers should be
placed close to the VOUTSENSE1+ and VOUTSENSE1–, or
VFB2 and SGND pins. Remote output and ground traces
should be routed together as a differential pair to the
remote output. For best accuracy, these traces to the
remote output and ground should be connected as close
as possible to the desired regulation point.
Switching Frequency Programming
The choice of operating frequency is a trade-off between
efficiency and component size. Lowering the operating fre-
quency improves efficiency by reducing MOSFET switching
losses but requires larger inductance and/or capacitance
to maintain low output ripple voltage. Conversely, raising
the operating frequency degrades efficiency but reduces
component size.
The switching frequency of the LTC3838 can be pro-
grammed from 200kHz to 2MHz by connecting a resistor
RFB1
MB
RFB2
MTL
CIN VIN
COUT1 COUT2
3838 F02
ILOAD
OTHER CURRENTS
FLOWING IN
SHARED GROUND
PLANE
POWER TRACE
PARASITICS
±VDROP(PWR)
+
–
GROUND TRACE
PARASITICS
±VDROP(GND)
ILOAD
LTC3838
VOUTSENSE1+VOUTSENSE1–
Figure 2. Differential Output Sensing Used to Correct Line Loss Variations
in a High Power Distributed System with a Shared Ground Plane
from the RT pin to signal ground. The value of this resistor
can be chosen according to the following formula:
RTkΩ
[ ]
=
41550
f kHz
[ ]
– 2.2
The overall controller system, including the clock PLL
and switching channels, has a synchronization range of
no less than ±30% around this programmed frequency.
Therefore, during external clock synchronization be sure
that the external clock frequency is within this ±30% range
of the RT programmed frequency. It is advisable that the
RT programmed frequency be equal the external clock for
maximum synchronization margin. Refer to the “Phase
and Frequency Synchronization” section for more details.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower efficiency because of MOSFET
gate charge losses. In addition to this basic trade-off, the
effect of inductor value on ripple current and low current
operation must also be considered.
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The inductor value has a direct effect on ripple current.
The inductor ripple current ∆IL decreases with higher
inductance or frequency and increases with higher VIN:
∆IL=VOUT
f•L
1– VOUT
VIN
Accepting larger values of ∆IL allows the use of low induc-
tances, but results in higher output voltage ripple, higher
ESR losses in the output capacitor, and greater core losses.
A reasonable starting point for setting ripple current is ∆IL
= 0.4 • IMAX. The maximum ∆IL occurs at the maximum
input voltage. To guarantee that ripple current does not
exceed a specified maximum, the inductance should be
chosen according to:
L=VOUT
f•∆IL(MAX)
1– VOUT
VIN(MAX)
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. The two basic types are iron powder and fer-
rite. The iron powder types have a soft saturation curve
which means they do not saturate hard like ferrites do.
However, iron powder type inductors have higher core
losses. Ferrite designs have very low core loss and are
preferred at high switching frequencies, so design goals
can concentrate on copper loss and preventing saturation.
Core loss is independent of core size for a fixed inductor
value, but it is very dependent on inductance selected. As
inductance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite core material saturates hard, which means that in-
ductance collapses abruptly when the peak design current
is exceeded. This results an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
A variety of inductors designed for high current, low volt-
age applications are available from manufacturers such as
Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,
Pulse and Würth.
Current Sense Pins
Inductor current is sensed through voltage between
SENSE+ and SENSE– pins, the inputs of the internal current
comparators. The input voltage range of the SENSE pins is
–0.5V to 5.5V. Care must be taken not to float these pins
during normal operation. The SENSE+ pins are quasi-high
impedance inputs. There is no bias current into a SENSE+
pin when its corresponding channel’s SENSE– pin ramps
up from below 1.1V and stays below 1.4V. But there is a
small (~1μA) current flowing into a SENSE+ pin when its
corresponding SENSE– pin ramps down from 1.4V and
stays above 1.1V. Such currents also exist on SENSE– pins.
But in addition, each SENSE– pin has an internal 500k
resistor to SGND. The resulted current (VOUT/500k) will
dominate the total current flowing into the SENSE– pins.
SENSE+ and SENSE– pin currents have to be taken into
account when designing either RSENSE or DCR inductor
current sensing.
Current Limit Programming
The current sense comparators’ maximum trip voltage
between SENSE+ and SENSE– (or “sense voltage”), when
ITH is clamped at its maximum 2.4V, is set by the voltage
applied to the VRNG pin and is given by:
VSENSE(MAX) = 0.05VRNG
The valley current mode control loop does not allow the
inductor current valley to exceed 0.05VRNG. In practice,
one should allow sufficient margin, to account for tolerance
of the parts and external component values. Note that ITH
is close to 2.4V when in current limit.
An external resistive divider from INTVCC can be used to set
the voltage on a VRNG pin between 0.6V and 2V, resulting
in a maximum sense voltage between 30mV and 100mV.
Such wide voltage range allows for variety of applications.
The VRNG pin can also be tied to either SGND or INTVCC
to force internal defaults. When VRNG is tied to SGND, the
device has an equivalent VRNG of 0.6V. When the VRNG pin
is tied to INTVCC, the device has an equivalent VRNG of 1V.
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applicaTions inForMaTion
RF
R ESL
R
SENSE
RESISTOR
AND
PARASITIC INDUCTANCE
CF • 2RF ≤ ESL/RS
POLE-ZERO
CANCELLATION
FILTER COMPONENTS
PLACED NEAR SENSE PINS
RF
SENSE+
LTC3838
SENSE–
CF
3838 F03a
V
OUT
COUT
TO SENSE FILTER,
NEXT TO THE CONTROLLER
R
SENSE
3838 F03b
Figure 3a. RSENSE Current Sensing
Figure 3b. Sense Lines Placement with Sense Resistor
RSENSE Inductor Current Sensing
The LTC3838 can be configured to sense the inductor
currents through either low value series current sensing
resistors (RSENSE) or inductor DC resistance (DCR). The
choice between the two current sensing schemes is largely
a design trade-off between cost, power consumption and
accuracy. DCR sensing is becoming popular because it
saves expensive current sensing resistors and is more
power efficient, especially in high current applications.
However, current sensing resistors provide the most ac-
curate current limits for the controller.
A typical RSENSE inductor current sensing scheme is shown
in Figure 3a. The filter components (RF , CF) need to be
placed close to the IC. The positive and negative sense
traces need to be routed as a differential pair close to-
gether and Kelvin (4-wire) connected underneath the sense
resistor, as shown in Figure 3b. Sensing current elsewhere
can effectively add parasitic inductance to the current sense
element, degrading the information at the sense terminals
and making the programmed current limit unpredictable.
RSENSE is chosen based on the required maximum output
current. Given the maximum current, IOUT(MAX), maximum
sense voltage, VSENSE(MAX), set by VRNG, and maximum
inductor ripple current ∆IL(MAX), the value of RSENSE can
be chosen as:
RSENSE =
V
SENSE(MAX)
IOUT(MAX) –∆IL(MAX)
2
Conversely, given RSENSE and IOUT(MAX), VSENSE(MAX) and
thus VRNG voltage can be determined from the above equa-
tion. To ensure the maximum output current, sufficient
margin should be built in the calculations to account for
variations of LTC3838 under different operating conditions
and tolerances of external components.
Because of possible PCB noise in the current sensing
loop, the current sensing voltage ripple ∆VSENSE = ∆IL •
RSENSE also needs to be checked in the design to get a
good signal-to-noise ratio. In general, for a reasonably
good PCB layout, 10mV of ∆VSENSE is recommended as
a conservative number to start with, either for RSENSE or
Inductor DCR sensing applications.
For today’s highest current density solutions the value
of the sense resistor can be less than 1mΩ and the
peak sense voltage can be as low as 20mV. In addition,
inductor ripple currents greater than 50% with operation
up to 2MHz are becoming more common. Under these
conditions, the voltage drop across the sense resistor’s
parasitic inductance becomes more relevant. A small RC
filter placed near the IC has been traditionally used to re-
duce the effects of capacitive and inductive noise coupled
in the sense traces on the PCB. A typical filter consists of
two series 10Ω resistors connected to a parallel 1000pF
capacitor, resulting in a time constant of 20ns.
This same RC filter, with minor modifications, can be
used to extract the resistive component of the current
sense signal in the presence of parasitic inductance.
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500ns/DIV
VSENSE
20mV/DIV
3838 F04b
Figure 4a. Voltage Waveform Measured
Directly Across the Sense Resistor
Figure 4b. Voltage Waveform Measured After the
Sense Resistor Filter. CF = 1000pF, RF = 100Ω
For example, Figure 4a illustrates the voltage waveform
across a 2mΩ sense resistor with a 2010 footprint for a
1.2V/15A converter operating at 100% load. The waveform
is the superposition of a purely resistive component and a
purely inductive component. It was measured using two
scope probes and waveform math to obtain a differential
measurement. Based on additional measurements of the
inductor ripple current and the on-time and off-time of
the top switch, the value of the parasitic inductance was
determined to be 0.5nH using the equation:
ESL =
V
ESL(STEP)
∆IL
•tON •tOFF
tON +tOFF
where VESL(STEP) is the voltage step caused by the ESL
and shown in Figure 4a, and tON and tOFF are top MOSFET
on-time and off-time respectively. If the RC time constant
is chosen to be close to the parasitic inductance divided by
the sense resistor (L/R), the resulting waveform looks re-
sistive again, as shown in Figure 4b. For applications using
low VSENSE(MAX), check the sense resistor manufacturer’s
data sheet for information about parasitic inductance. In
the absence of data, measure the voltage drop directly
across the sense resistor to extract the magnitude of the
ESL step and use the equation above to determine the ESL.
However, do not over filter. Keep the RC time constant less
than or equal to the inductor time constant to maintain a
high enough ripple voltage on VRSENSE.
Note that the SENSE1– and SENSE2– pins are also used
for sensing the output voltage for the adjustment of top
gate on time, tON. For this purpose, there is an additional
internal 500k resistor from each SENSE– pin to SGND,
therefore there is an impedance mismatch with their cor-
responding SENSE+ pins. The voltage drop across the
RF causes an offset in sense voltage. For example, with
RF = 100Ω, at VOUT = VSENSE– = 5V, the sense-voltage
offset VSENSE(OFFSET) = VSENSE– • RF/500k = 1mV. Such
small offset may seem harmless for current limit, but
could be significant for current reversal detection (IREV),
causing excess negative inductor current at discontinuous
mode. Also, at VSENSE(MAX) = 30mV, a mere 1mV offset
will cause a significant shift of zero-current ITH voltage
by (2.4V – 0.8V) • 1mV/30mV = 53mV. Too much shift
may not allow the output voltage to return to its regulated
value after the output is shorted due to ITH foldback.
Therefore, when a larger filter resistor RF value is used,
it is recommended to use an external 500k resistor from
each SENSE+ pin to SGND, to balance the internal 500k
resistor at its corresponding SENSE– pin.
The previous discussion generally applies to high density/
high current applications where IOUT(MAX) > 10A and low
inductor values are used. For applications where IOUT(MAX)
500ns/DIV
VSENSE
20mV/DIV
3838 F04a
V
ESL(STEP)
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R1
R2
(OPT)
DCRL
INDUCTOR
L/DCR = (R1||R2) C1
C1 NEAR SENSE PINS
SENSE+
LTC3838
SENSE–
C1
3838 F05
V
OUT
COUT
Figure 5. DCR Current Sensing
applicaTions inForMaTion
< 10A, set RF to 10Ω and CF to 1000pF. This will provide
a good starting point.
The filter components need to be placed close to the IC.
The positive and negative sense traces need to be routed
as a differential pair and Kelvin (4-wire) connected to the
sense resistor.
DCR Inductor Current Sensing
For applications requiring higher efficiency at high load
currents, the LTC3838 is capable of sensing the voltage
drop across the inductor DCR, as shown in Figure 5. The
DCR of the inductor represents the small amount of DC
winding resistance, which can be less than 1mΩ for today’s
low value, high current inductors.
In a high current application requiring such an inductor,
conduction loss through a sense resistor would cost several
points of efficiency compared to DCR sensing.
The inductor DCR is sensed by connecting an RC filter
across the inductor. This filter typically consists of one or
two resistors (R1 and R2) and one capacitor (C1) as shown
in Figure 5. If the external (R1||R2) • C1 time constant is
chosen to be exactly equal to the L/DCR time constant, the
voltage drop across the external capacitor is equal to the
voltage drop across the inductor DCR multiplied by R2/
(R1 + R2). Therefore, R2 may be used to scale the voltage
across the sense terminals when the DCR is greater than
the target sense resistance. With the ability to program
current limit through the VRNG pin, R2 may be optional. C1
is usually selected in the range of 0.01µF to 0.47µF. This
forces R1||R2 to around 2k to 4k, reducing error that might
have been caused by the SENSE pins’ input bias currents.
Resistor R1 should be placed close to the switching node,
to prevent noise from coupling into sensitive small-signal
nodes. Capacitor C1 should be placed close to the IC pins.
The first step in designing DCR current sensing is to
determine the DCR of the inductor. Where provided, use
the manufacturer’s maximum value, usually given at 25°C.
Increase this value to account for the temperature coef-
ficient of resistance, which is approximately 0.4%/°C. A
conservative value for inductor temperature TL is 100°C.
The DCR of the inductor can also be measured using a good
RLC meter, but the DCR tolerance is not always the same
and varies with temperature; consult the manufacturers’
data sheets for detailed information.
From the DCR value, VSENSE(MAX) is easily calculated as:
V
SENSE(MAX)
=DCR
MAX(25°C)
•1+0.4% TL(MAX) – 25°C
( )
•IOUT(MAX) –∆IL
2
If VSENSE(MAX) is within the maximum sense voltage (30mV
to 100mV) of the LTC3838 as programmed by the VRNG
pin, then the RC filter only needs R1. If VSENSE(MAX) is
higher, then R2 may be used to scale down the maximum
sense voltage so that it falls within range.
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The maximum power loss in R1 is related to duty cycle,
and will occur in continuous mode at the maximum input
voltage:
P
LOSS R1
( )
=VIN(MAX) – VOUT
( )
•VOUT
R1
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
RSENSE sensing. Light load power loss can be modestly
higher with a DCR network than with a sense resistor due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, start with a ∆VSENSE of 10mV. For a DCR
sensing application, the actual ripple voltage will be de-
termined by:
∆VSENSE =
V
IN
– V
OUT
R1•C1 •
V
OUT
V
IN
•f
Power MOSFET Selection
Two external N-channel power MOSFETs must be selected
for each channel of the LTC3838 controller: one for the
top (main) switch and one for the bottom (synchronous)
switch. The gate drive levels are set by the DRVCC voltage.
This voltage is typically 5.3V. Pay close attention to the
BVDSS specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data sheet.
CMILLER is equal to the increase in gate charge along the
horizontal axis while the curve is approximately flat (or
the parameter QGD if specified on a manufacturer’s data
sheet), divided by the specified VDS test voltage:
CMILLER ≅
Q
GD
VDS(TEST)
When the IC is operating in continuous mode, the duty
cycles for the top and bottom MOSFETs are given by:
DTOP =
V
OUT
VIN
DBOT =1– VOUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
P
TOP
=
DTOP •IOUT(MAX)2•RDS(ON)(MAX) 1
+δ
( )
+
VIN2
•IOUT(MAX)
2
•CMILLER
RTG(UP)
VDRVCC – VMILLER
+RTG(DOWN)
VMILLER
•f
PBOT = DBOT • IOUT(MAX)2 • RDS(ON)(MAX) • (1 + δ )
where δ is the temperature dependency of RDS(ON), RTG(UP)
is the TG pull-up resistance, and RTG(DOWN) is the TG pull-
down resistance. VMILLER is the Miller effect VGS voltage
and is taken graphically from the MOSFET ’s data sheet.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V,
the high current efficiency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
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+
+
–
L
IN
1µH
ESR(BULK)
VIN ESL(BULK)
CIN(BULK)
ESR(CERAMIC)
ESL(CERAMIC) IPULSE(PHASE1)
CIN(CERAMIC)
I
PULSE(PHASE2)
3838 F06
Figure 6. Circuit Model for Input Capacitor
Ripple Current Simulation
applicaTions inForMaTion
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs temperature curve in the
power MOSFET data sheet. For low voltage MOSFETs,
0.5% per degree (°C) can be used to estimate δ as an
approximation of percentage change of RDS(ON):
δ = 0.005/°C • (TJ – TA)
where TJ is estimated junction temperature of the MOSFET
and TA is ambient temperature.
CIN Selection
In continuous mode, the source current of the top N-
channel MOSFET is a square wave of duty cycle VOUT/
VIN. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The worst-case RMS current occurs by assuming
a single-phase application. The maximum RMS capacitor
current is given by:
IRMS ≅IOUT(MAX) •VOUT
VIN
•VIN
VOUT
– 1
This formula has a maximum at VIN = 2VOUT
, where
IRMS = IOUT(MAX)/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that capacitor
manufacturers’ ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. Due to the high operating frequency of the
LTC3838, additional ceramic capacitors should also be
used in parallel for CIN close to the IC and power switches
to bypass the high frequency switching noises. Typically
multiple X5R or X7R ceramic capacitors are put in parallel
with either conductive-polymer or aluminum-electrolytic
types of bulk capacitors. Because of its low ESR, the
ceramic capacitors will take most of the RMS ripple cur-
rent. Vendors do not consistently specify the ripple current
rating for ceramics, but ceramics could also fail due to
excessive ripple current. Always consult the manufacturer
if there is any question.
Figure 6 represents a simplified circuit model for calculat-
ing the ripple currents in each of these capacitors. The
input inductance (LIN) between the input source and the
input of the converter will affect the ripple current through
the capacitors. A lower input inductance will result in less
ripple current through the input capacitors since more
ripple current will now be flowing out of the input source.
For simulations with this model, look at the ripple current
during steady-state for the case where one phase is fully
loaded and the other was not loaded. This will in general
be the worst case for ripple current since the ripple cur-
rent from one phase will not be cancelled by ripple current
from the other phase.
Note that the bulk capacitor also has to be chosen for
RMS rating with ample margin beyond its RMS current
per simulation with the circuit model provided. For a lower
VIN range, a conductive-polymer type (such as Sanyo
OS-CON) can be used for its higher ripple current rating
and lower ESR. For a wide VIN range that also require
higher voltage rating, aluminum-electrolytic capacitors are
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more attractive since it can provide a larger capacitance
for more damping. An aluminum-electrolytic capacitor
with a ripple current rating that is high enough to handle
all of the ripple current by itself will be very large. But
when in parallel with ceramics, an aluminum-electrolytic
capacitor will take a much smaller portion of the RMS
ripple current due to its high ESR. However, it is crucial
that the ripple current through the aluminum-electrolytic
capacitor should not exceed its rating since this will
produce significant heat, which will cause the electrolyte
inside the capacitor to dry over time and its capacitance
to go down and ESR to go up.
The benefit of PolyPhase operation is reduced RMS cur-
rents and therefore less power loss on the input capaci-
tors. Also, the input protection fuse resistance, battery
resistance, and PC board trace resistance losses are also
reduced due to the reduced peak currents in a PolyPhase
system. The details of a close form equation can be found
in Application Note 77 “High Efficiency, High Density,
PolyPhase Converters for High Current Applications”.
Figure 7 shows the input capacitor RMS ripple currents
normalized against the DC output currents with respect
to the duty cycle. This graph can be used to estimate the
maximum RMS capacitor current for a multiple-phase
application, assuming the channels are identical and their
phases are fully interleaved.
Figure 7 shows that the use of more phases will reduce
the ripple current through the input capacitors due to
ripple current cancellation. However, since LTC3838 is
only truly phase-interleaved at steady state, transient RMS
currents could be higher than the curves for the designated
number of phase. Therefore, it is advisable to choose
capacitors by taking account the specific load situations
of the applications. It is always the safest to choose input
capacitors’ RMS current rating closer to the worst case of
a single-phase application discussed above, calculated by
assuming the loss that would have resulted if controller
channels switched on at the same time.
However, it is generally not needed to size the input capaci-
tor for such worst-case conditions where on-times of the
phases coincide all the time. During a load step event, the
overlap of on-time will only occur for a small percentage
of time, especially when duty cycles are low. A transient
event where the switch nodes align for several cycles at
a time should not damage the capacitor. In most applica-
tions, sizing the input capacitors for 100% steady-state
load should be adequate. For example, a microprocessor
load may cause frequent overlap of the on-times, which
makes the ripple current higher, but the load current may
rarely be at 100% of IOUT(MAX). Using the worst-case load
current should already have margin built in for transient
conditions.
The VIN sources of the top MOSFETs should be placed
close to each other and share common CIN(s). Separating
the sources and CIN may produce undesirable voltage and
current resonances at VIN.
A small (0.1µF to 1µF) bypass capacitor between the IC’s
VIN pin and ground, placed close to the IC, is suggested.
A 2.2Ω to 10Ω resistor placed between CIN and the VIN
pin is also recommended as it provides further isolation
from switching noise of the two channels.
Figure 7. Normalized RMS Input Ripple Current
DUTY FACTOR (VO/VIN)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3838 F07
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
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COUT Selection
The selection of output capacitance COUT is primarily
determined by the effective series resistance, ESR, to
minimize voltage ripple. The output voltage ripple ∆VOUT
,
in continuous mode is determined by:
∆VOUT ≤ ∆ILRESR +1
8•f•COUT
where f is operating frequency, and ∆IL is ripple current
in the inductor. The output ripple is highest at maximum
input voltage since ∆IL increases with input voltage. Typi-
cally, once the ESR requirement for COUT has been met,
the RMS current rating generally far exceeds that required
from ripple current.
In multiphase single-output applications, it is advisable to
consider ripple requirements at specific load conditions.
At steady state, the LTC3838’s individual phases are inter-
leaved, and their ripples cancel each other at the output,
so ripple on COUT is reduced. During transient, when the
phases are not fully interleaved, the ripple cancellation
may not be as effective. While the worst-case ∆IL is the
sum of the ∆ILs of individual phases aligned during a
fast transient, such ripple tends to counteract the effect
of load transient itself and lasts for only a short time. For
example, during sudden load current increase, the phases
align to ramp up the total inductor current to quickly pull
the VOUT up from the droop.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount pack-
ages. Special polymer capacitors offer very low ESR but
have lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
but can have a high voltage coefficient and audible piezo-
electric effects. The high Q of ceramic capacitors with trace
inductance can also lead to significant ringing. When used
as input capacitors, care must be taken to ensure that ring-
ing from inrush currents and switching does not pose an
overvoltage hazard to the power switches and controller.
For high switching frequencies, reducing output ripple and
better EMI filtering may require small value capacitors that
have low ESL (and correspondingly higher self-resonant
frequencies) to be placed in parallel with larger value
capacitors that have higher ESL. This will ensure good
noise and EMI filtering in the entire frequency spectrum
of interest. Even though ceramic capacitors generally
have good high frequency performance, small ceramic
capacitors may still have to be parallel connected with
large ones to optimize performance.
High performance through-hole capacitors may also be
used, but an additional ceramic capacitor in parallel is
recommended to reduce the effect of their lead inductance.
Remember also to place high frequency decoupling capaci-
tors as close as possible to the power pins of the load.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor, CB, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode DB from
DRVCC when the switch node is low. When the top MOSFET
turns on, the switch node rises to VIN and the BOOST pin
rises to approximately VIN + INTVCC. The boost capacitor
needs to store approximately 100 times the gate charge
required by the top MOSFET. In most applications a 0.1µF
to 0.47µF, X5R or X7R dielectric capacitor is adequate. It
is recommended that the BOOST capacitor be no larger
than 10% of the DRVCC capacitor, CDRVCC, to ensure that
the CDRVCC can supply the upper MOSFET gate charge
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and BOOST capacitor under all operating conditions. Vari-
able frequency in response to load steps offers superior
transient performance but requires higher instantaneous
gate drive. Gate charge demands are greatest in high
frequency low duty factor applications under high load
steps and at start-up.
DRVCC Regulator and EXTVCC Power
The LTC3838 features a PMOS low dropout (LDO) linear
regulator that supplies power to DRVCC from the VIN supply.
The LDO regulates its output at the DRVCC1 pin to 5.3V.
The LDO can supply a maximum current of 100mA and
must be bypassed to ground with a minimum of 4.7µF
ceramic capacitor. Good bypassing is needed to supply
the high transient currents required by the MOSFET gate
drivers and to minimize interaction between the channels.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC3838 to be
exceeded, especially if the LDO is active and provides
DRVCC. Power dissipation for the IC in this case is high-
est and is approximately equal to VIN • IDRVCC. The gate
charge current is dependent on operating frequency as
discussed in the Efficiency Considerations section. The
junction temperature can be estimated by using the equa-
tion given in Note 2 of the Electrical Characteristics. For
example, when using the LDO, LTC3838’s DRVCC current
is limited to less than 52mA from a 38V supply at TA =
70°C in the FE package:
TJ = 70°C + (52mA)(38V)(28°C/W) = 125°C
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked while
operating in continuous conduction mode at maximum VIN.
When the voltage applied to the EXTVCC pin rises above
the switchover voltage (typically 4.6V), the VIN LDO is
turned off and the EXTVCC is connected to DRVCC2 pin with
an internal switch. This switch remains on as long as the
voltage applied to EXTVCC remains above the hysteresis
(around 200mV) below the switchover voltage. Using
EXTVCC allows the MOSFET driver and control power to
be derived from the LTC3838’s switching regulator output
VOUT during normal operation and from the LDO when the
output is out of regulation (e.g., start up, short circuit). If
more current is required through the EXTVCC than is speci-
fied, an external Schottky diode can be added between the
EXTVCC and DRVCC pins. Do not apply more than 6V to the
EXTVCC pin and make sure that EXTVCC is less than VIN.
Significant efficiency and thermal gains can be realized
by powering DRVCC from the switching converter output,
since the VIN current resulting from the driver and control
currents will be scaled by a factor of (Duty Cycle)/(Switcher
Efficiency).
Tying the EXTVCC pin to a 5V supply reduces the junction
temperature in the previous example from 125°C to:
TJ = 70°C + (52mA)(5V)(28°C/W) = 77°C
However, for 3.3V and other low voltage outputs, ad-
ditional circuitry is required to derive DRVCC power from
the converter output.
The following list summarizes the four possible connec-
tions for EXTVCC:
1. EXTVCC left open (or grounded). This will cause INTVCC
to be powered from the internal 5.3V LDO resulting
in an efficiency penalty of up to 10% at high input
voltages.
2. EXTVCC connected directly to switching converter output
VOUT is higher than the switchover voltage’s higher limit
(4.8V). This provides the highest efficiency.
3. EXTVCC connected to an external supply. If a 4.8V or
greater external supply is available, it may be used to
power EXTVCC providing that the external supply is
sufficient for MOSFET gate drive requirements.
4. EXTVCC connected to an output-derived boost network.
For 3.3V and other low voltage converters, efficiency
gains can still be realized by connecting EXTVCC to an
output-derived voltage that has been boosted to greater
than 4.8V.
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Figure 8. Setup for VIN ≤ 5.3V
DRVCC2
LTC3838
DRVCC1
CDRVCC
RDRVCC
3838 F08
V
IN
CIN
applicaTions inForMaTion
For applications where the main input power never exceeds
5.3V, tie the DRVCC1 and DRVCC2 pins to the VIN input
through a small resistor, (such as 1Ω to 2Ω) as shown
in Figure 8 to minimize the voltage drop caused by the
gate charge current. This will override the LDO and will
prevent DRVCC from dropping too low due to the dropout
voltage. Make sure the DRVCC voltage exceeds the RDS(ON)
test voltage for the external MOSFET which is typically at
4.5V for logic-level devices.
Generally for VIN > 6V, a UVLO can be set through monitoring
the VIN supply by using external voltage dividers at the RUN
pins from VIN to SGND. To design the voltage divider, note
that both RUN pins have two levels of threshold voltages.
The precision gate-drive-enable threshold voltage of 1.2V
can be used to set a VIN to turn on a channel’s switching.
If resistor dividers are used on both RUN pins, when VIN
is low enough and both RUN pins are pulled below the
~0.8V threshold, the part will shut down all bias of INTVCC
and DRVCC and be put in micropower shutdown mode.
The RUN pins’ bias currents depend on the RUN voltages.
The bias current changes should be taken into account
when designing the external voltage divider UVLO circuit.
An internal proportional-to-absolute-temperature (PTAT)
pull-up current source (~1.2µA at 25°C) is constantly con-
nected to this pin. When a RUN pin rises above 1.2V, the
corresponding channel’s TG and BG drives are turned on
and an additional 5µA temperature-independent pull-up
current is connected internally to the RUN pin. Pulling the
RUN pin to fall below 1.2V by more than an 80mV hyster-
esis turns off TG and BG of the corresponding channel,
and the additional 5µA pull-up current is disconnected.
As voltage on a RUN pin increases, typically beyond 3V
,
its bias current will start to reverse direction and flow into
the RUN pin. Keep in mind that neither of the RUN pins
can sink more than 50µA; Even if a RUN pin may slightly
exceed 6V when sinking 50µA, a RUN pin should never
be forced to higher than 6V by a low impedance voltage
source to prevent faulty conditions.
Soft-Start and Tracking
The LTC3838 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
an external supply. Note that the soft-start and tracking
features are achieved not by limiting the maximum output
current of the controller, but by controlling the output ramp
voltage according to the ramp rate on the TRACK/SS pin.
Input Undervoltage Lockout (UVLO)
The LTC3838 has two functions that help protect the con-
troller in case of input undervoltage conditions. An internal
UVLO comparator constantly monitors the INTVCC and
DRVCC voltages to ensure that adequate voltages are pres-
ent. The comparator enables internal UVLO signal, which
locks out the switching action of both channels, until the
INTVCC and DRVCC1,2 pins are all above their respective
UVLO thresholds. The rising threshold (to release UVLO)
of the INTVCC is typically 4.2V, with 0.5V falling hysteresis
(to re-enable UVLO). The UVLO thresholds for DRVCC1,2 are
lower than that of INTVCC but higher than typical threshold
voltages of power MOSFETs, to prevent them from turning
on without sufficient gate drive voltages.
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When a channel is configured to soft-start by itself, a ca-
pacitor should be connected to its TRACK/SS pin. TRACK/
SS is pulled low until the RUN pin voltage exceeds 1.2V
and UVLO is released, at which point an internal current
of 1µA charges the soft-start capacitor, CSS, connected
to the TRACK/SS pin. Current-limit foldback is disabled
during this phase to ensure smooth soft-start or track-
ing. The soft-start or tracking range is defined to be the
voltage range from 0V to 0.6V on the TRACK/SS pin. The
total soft-start time can be calculated as:
tSS(SEC)=0.6(V)•
C
SS
(µF)
1(µA)
When one particular channel is configured to track an
external supply, a voltage divider can be used from the
external supply to the TRACK/SS pin to scale the ramp
rate appropriately. Two common implementations are co-
incidental tracking and ratiometric tracking. For coincident
tracking, make the divider ratio from the external supply
the same as the divider ratio for the differential feedback
voltage. Ratiometric tracking could be achieved by using
a different ratio than the differential feedback.
Note that the 1µA soft-start capacitor charging current is
still flowing, producing a small offset error. To minimize
this error, select the tracking resistive divider values to be
small enough to make this offset error negligible.
The LTC3838 allows the user to program how its two
channels’ outputs track each other ramping up or down.
In the following discussions, VOUT1 refers to the LTC3838’s
output 1 as a master channel and VOUT2 refers to the
LTC3838’s output 2 as a slave channel. In practice though,
either channel can be used as the master.
By selecting different resistors, the LTC3838 can achieve
different modes of tracking including the two in Figure 9.
To implement the coincident tracking, connect an addi-
tional resistive divider to VOUT1 and connect its midpoint
to the TRACK/SS pin of the slave channel. The ratio of this
divider should be the same as that of the slave channel’s
feedback divider shown in Figure 9b. In this tracking mode,
Figure 9a. Two Different Modes of Output Tracking
Figure 9b. Setup for Coincident and Ratiometric Tracking
TIME
Coincident Tracking
VOUT1
VOUT2
OUTPUT VOLTAGE
V
OUT1
V
OUT2
TIME 3838 F09a
Ratiometric Tracking
OUTPUT VOLTAGE
RFB2(1)
RFB1(1)
RFB2(2)
RFB1(2)
RFB2(2)
V
OUT2
RFB1(2)
Coincident Tracking Setup
TO
VOUTSENSE1+
PIN
TO
VOUTSENSE1–
PIN
TO
TRACK/SS2
PIN
TO
VFB2
PIN
V
OUT1
RFB2(1)
RFB1(1)
RFB2(2)
VOUT2
RFB1(2)
3838 F09b
Ratiometric Tracking Setup
TO
VOUTSENSE1+
PIN
TO
VOUTSENSE1–
PIN
TO
TRACK/SS2
PIN
TO
VFB2
PIN
V
OUT1
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VOUT1 must be set higher than VOUT2. To implement the
ratiometric tracking, the master channel’s feedback divider
can be also used to provide TRACK/SS voltage for the slave
channel, since the additional divider, if used, should be of
the same ratio as the master channel’s feedback divider.
So which mode should be programmed? While either
mode satisfies most practical applications, some trade-
offs exist. The ratiometric mode saves a pair of resistors,
but the coincident mode offers better output regulation.
When the master channel’s output experiences dynamic
excursion (under load transient, for example), the slave
channel output will be affected as well. For better output
regulation, use the coincident tracking mode instead of
ratiometric.
Phase and Frequency Synchronization
For applications that require better control of EMI and
switching noise or have special synchronization needs, the
LTC3838 can synchronize the turn-on of the top MOSFET
to an external clock signal applied to the MODE/PLLIN pin.
The applied clock signal needs to be within ±30% of the
RT programmed frequency to ensure proper frequency
and phase lock. The clock signal levels should generally
comply to VPLLIN(H) > 2V and VPLLIN(L) < 0.5V. The MODE/
PLLIN pin has an internal 600k pull-down resistor to ensure
discontinuous current mode operation if the pin is left open.
The LTC3838 uses the voltages on VIN and VOUT as well
as RT to adjust the top gate on-time in order to maintain
phase and frequency lock for wide ranges of VIN, VOUT
and RT-programmed switching frequency f:
tON ≈
V
OUT
VIN •f
As the on-time is a function of the switching regulator’s
output voltage, this output is measured by the SENSE– pin
to set the required on-time. The SENSE– pin is tied to the
regulator’s local output point to the IC for most applica-
tions, as the remotely regulated output point could be
significantly different from the local output point due to
line losses, and local output versus local ground is typically
the VOUT required for the calculation of tON.
However, there could be circumstances where this VOUT
programmed on-time differs significantly different from
the on-time required in order to maintain frequency
and phase lock. For example, lower efficiencies in the
switching regulator can cause the required on-time to be
substantially higher than the internally set on-time (see
Efficiency Considerations). If a regulated VOUT is relatively
low, proportionally there could be significant error caused
by the difference between the local ground and remote
ground, due to other currents flowing through the shared
ground plane.
If necessary, the RT resistor value, voltage on the VIN pin,
or even the common mode voltage of the SENSE pins may
be programmed externally to correct for such systematic
errors. The goal is to set the on-time programmed by VIN,
VOUT and RT close to the stready-state on-time so that the
system will have sufficient range to correct for component
and operating condition variations, or to synchronize to the
external clock. Note that there is an internal 500k resistor
on each SENSE– pin to SGND, but not on the SENSE+ pin.
During dynamic transient conditions either in the line
voltage or load current (e.g., load step or release), the top
switch will turn on more or less frequently in response
to achieve faster transient response. This is the benefit
of the LTC3838’s controlled on-time, valley current mode
architecture. However, this process may understandably
lose phase and even frequency lock momentarily. For
relatively slow changes, phase and frequency lock can
still be maintained. For large load current steps with fast
slew rates, phase lock will be lost until the system returns
back to a steady-state condition (see Figure 10). It may
take up to several hundred microseconds to fully resume
the phase lock, but the frequency lock generally recovers
quickly, long before phase lock does.
For light load conditions, the phase and frequency syn-
chronization depends on the MODE/PLLIN pin setting. If
the external clock is applied, synchronization will be active
and switching in continuous mode. If MODE/PLLIN is tied
to INTVCC, it will operate in forced continuous mode at
the RT-programmed frequency. If the MODE/PLLIN pin is
tied to SGND, the LTC3838 will operate in discontinuous
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mode at light load and switch into continuous conduction
at the RT programmed frequency as load increases. The TG
on-time during discontinuous conduction is intentionally
slightly extended (approximately 1.2 times the continuous
conduction on-time as calculated from VIN, VOUT and f) to
create hysteresis at the load-current boundary of continu-
ous/discontinuous conduction.
If an application requires very low (approaching minimum)
on-time, the system may not be able to maintain its full
frequency synchronization range. Getting closer to mini-
mum on-time, it may even lose phase/frequency lock at no
load or light load conditions, under which the SW on-time
is effectively longer than TG on-time due to TG/BG dead
times. This is discussed further under Minimum On-Time,
Minimum Off-Time and Dropout Operation.
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration that
LTC3838’s TG (top gate) pin can be in high or “on” state.
It has dependency on the operating conditions of the
switching regulator, and is a function of voltages on the
VIN and VOUT pins, as well as the value of external resistor
RT. A minimum on-time of 30ns can be achieved when the
VOUT pin is tied to its minimum value of 0.6V while the VIN
is tied to its maximum value of 38V. For larger values of
VOUT and/or smaller values of VIN, the minimum achievable
on-time will be longer. The valley mode control architecture
allows low on-time, making the LTC3838 suitable for high
step-down ratio applications.
The effective on-time, as determined by the SW node
pulse width, can be different from this TG on-time, as it
also depends on external components, as well as loading
conditions of the switching regulator. One of the factors that
contributes to this discrepancy is the characteristics of the
power MOSFETs. For example, if the top power MOSFET’s
turn-on delay is much smaller than the turn-off delay,
the effective on-time will be longer than the TG on-time,
limiting the effective minimum on-time to a larger value.
Light-load operation, in forced continuous mode, will
further elongate the effective on-time due to the dead
times between the “on” states of TG and BG, as shown in
Figure 11. During the dead time from BG turn-off to TG
turn-on, the inductor current flows in the reverse direction,
charging the SW node high before the TG actually turns
on. The reverse current is typically small, causing a slow
rising edge. On the falling edge, after the top FET turns off
and before the bottom FET turns on, the SW node lingers
high for a longer duration due to a smaller peak inductor
current available in light load to pull the SW node low. As
a result of the sluggish SW node rising and falling edges,
the effective on-time is extended and not fully controlled
by the TG on-time. Closer to minimum on-time, this may
cause some phase jitter to appear at light load. As load
current increase, the edges become sharper, and the phase
locking behavior improves.
Figure 10. Phase and Frequency Locking Behavior During Transient Conditions
PHASE AND
FREQUENCY
LOCK LOST
DUE TO FAST
LOAD STEP
FREQUENCY
RESTORED
QUICKLY
PHASE AND
FREQUENCY
LOCK LOST
DUE TO FAST
LOAD STEP
FREQUENCY
RESTORED
QUICKLY
PHASE LOCK
RESUMED
3838 F10
PHASE AND
FREQUENCY
LOCKED
ILOAD
CLOCK
INPUT
SW
VOUT
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In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
DMIN = f • tON(MIN)
where tON(MIN) is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint. If the minimum on-time that LTC3838 can
provide is longer than the on-time required by the duty
cycle to maintain the switching frequency, the switching
frequency will have to decrease to maintain the duty cycle,
but the output voltage will still remain in regulation. This is
generally more preferable to skipping cycles and causing
larger ripple at the output, which is typically seen in fixed
frequency switching regulators.
The tON(MIN) curves in the Typical Performance Charac-
teristics are measured with minimum load on TG and
BG, at extreme cases of VIN = 38V, and/or VOUT = 0.6V,
and/or programmed f = 2MHz (i.e., RT = 18k). In applica-
tions with different VIN, VOUT and/or f, the tON(MIN) that
can be achieved will generally be larger. Also, to guarantee
frequency and phase locking at light load, sufficient margin
needs to be added to account for the dead times (tD(TG/BG)
+ tD(TG/BG) in the Electrical Characteristics).
For applications that require relatively low on-time, proper
caution has to be taken when choosing the power MOSFET.
If the gate of the MOSFET is not able to fully turn on due
to insufficient on-time, there could be significant heat dis-
sipation and efficiency loss as a result of larger RDS(ON).
This may even cause early failure of the power MOSFET.
The minimum off-time is the smallest duration of time
that the TG pin can be turned low and then immediately
turned back high. This minimum off-time includes the
time to turn on the BG (bottom gate) and turn it back off,
plus the dead-time delays from TG off to BG on and from
BG off to TG on. The minimum off-time that the LTC3838
can achieve is 90ns.
The effective minimum off-time of the switching regulator,
or the shortest period of time that the SW node can stay
low, can be different from this minimum off-time. The main
factor impacting the effective minimum off-time is the top
and bottom power MOSFETs’ electrical characteristics,
such as Qg and turn-on/off delays. These characteristics
can either extend or shorten the SW nodes’ effective
minimum off-time. Large size (high Qg) power MOSFETs
generally tend to increase the effective minimum off-time
due to longer gate charging and discharging times. On
the other hand, imbalances in turn-on and turn-off delays
could reduce the effective minimum off-time.
The minimum off-time limit imposes a maximum duty
cycle of:
DMAX = 1 – f • tOFF(MIN)
where tOFF(MIN) is the effective minimum off-time of the
switching regulator. Reducing the operating frequency can
alleviate the maximum duty cycle constraint.
Figure 11. Light Loading On-Time Extension for Forced
Continuous Mode Operation
DEAD-TIME
DELAYS
NEGATIVE
INDUCTOR
CURRENT
IN FCM
DURING BG-TG DEAD TIME,
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
3838 F11
TG-SW
(V
GS OF TOP
MOSFET)
BG
(VGS OF
BOTTOM
MOSFET)
IL
SW
0
VIN
+
–
ILVIN
L
SW
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
L
TOTAL CAPACITANCE
ON THE SW NODE
IL
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If the maximum duty cycle is reached, due to a drooping
input voltage for example, the output will drop out of
regulation. The minimum input voltage to avoid dropout is:
VIN(MIN) =
V
OUT
DMAX
At the onset of drop-out, there is a region of VIN of about
500mV that generates two discrete off-times, one being
the minimum off time and the other being an off-time that
is about 40ns to 60ns longer than the minimum off-time.
This secondary off-time is due to the extra delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation. There may be higher SW node jitter, apparent
especially when synchronized to an external clock, but the
output voltage ripple remains relatively small.
Fault Conditions: Current Limiting and Overvoltage
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage.
In the LTC3838, the maximum sense voltage is controlled
by the voltage on the VRNG pin. With valley current mode
control, the maximum sense voltage and the sense re-
sistance determine the maximum allowed inductor valley
current. The corresponding output current limit is:
ILIMIT =
V
SENSE(MAX)
R
SENSE
+1
2•∆IL
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The current limit value should
be greater than the inductor current required to produce
maximum output power at the worst-case efficiency.
Worst-case efficiency typically occurs at the highest VIN
and highest ambient temperature. It is important to check
for consistency between the assumed MOSFET junction
temperatures and the resulting value of ILIMIT which heats
the MOSFET switches.
To further limit current in the event of a short circuit to
ground, the LTC3838 includes foldback current limiting.
If the output falls by more than 50%, the maximum sense
voltage is progressively lowered, to about one-fourth of
its full value as the feedback voltage reaches 0V.
A feedback voltage exceeding 7.5% of the regulated target
of 0.6V is considered as overvoltage (OV). In such an OV
condition, the top MOSFET is immediately turned off and
the bottom MOSFET is turned on indefinitely until the OV
condition is removed, i.e., the feedback voltage falling
back below the 7.5% threshold by more than a hysteresis
of typical 2%. Current limiting is not active during an OV.
If the OV persists, and the BG turns on for a longer time,
the current through the inductor and the bottom MOSFET
may exceed their maximum ratings, sacrificing themselves
to protect the load.
OPTI-LOOP Compensation
OPTI-LOOP compensation, through the availability of the
ITH pin, allows the transient response to be optimized for
a wide range of loads and output capacitors. The ITH pin
not only allows optimization of the control-loop behavior
but also provides a DC-coupled and AC-filtered closed-loop
response test point. The DC step, rise time and settling
at this test point truly reflects the closed-loop response.
Assuming a predominantly 2nd order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin.
The external series RITH-CITH1 filter at the ITH pin sets the
dominant pole-zero loop compensation. The values can
be adjusted to optimize transient response once the final
PCB layout is done and the particular output capacitor type
and value have been determined. The output capacitors
need to be selected first because their various types and
values determine the loop feedback factor gain and phase.
An additional small capacitor, CITH2, can be placed from
the ITH pin to SGND to attenuate high frequency noise.
Note this CITH2 contributes an additional pole in the loop
gain therefore can affect system stability if too large. It
should be chosen so that the added pole is higher than
the loop bandwidth by a significant margin.
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The regulator loop response can also be checked by
looking at the load transient response. An output current
pulse of 20% to 100% of full-load current having a rise
time of 1µs to 10µs will produce VOUT and ITH voltage
transient-response waveforms that can give a sense of the
overall loop stability without breaking the feedback loop.
For a detailed explanation of OPTI-LOOP compensation,
refer to Application Note 76.
Switching regulators take several cycles to respond to
a step in load current. When a load step occurs, VOUT
immediately shifts by an amount equal to ∆ILOAD • ESR,
where ESR is the effective series resistance of COUT
. ∆ILOAD
also begins to charge or discharge COUT
, generating a
feedback error signal used by the regulator to return VOUT
to its steady-state value. During this recovery time, VOUT
can be monitored for overshoot or ringing that would
indicate a stability problem.
Connecting a resistive load in series with a power MOSFET,
then placing the two directly across the output capacitor
and driving the gate with an appropriate signal generator
is a practical way to produce a realistic load step condi-
tion. The initial output voltage step resulting from the step
change in load current may not be within the bandwidth
of the feedback loop, so it cannot be used to determine
phase margin. The output voltage settling behavior is more
related to the stability of the closed-loop system. However,
it is better to look at the filtered and compensated feedback
loop response at the ITH pin.
The gain of the loop increases with the RITH and the band-
width of the loop increases with decreasing CITH1. If RITH
is increased by the same factor that CITH1 is decreased, the
zero frequency will be kept the same, thereby keeping the
phase the same in the most critical frequency range of the
feedback loop. In addition, a feedforward capacitor, CFF
,
can be added to improve the high frequency response, as
shown in Figure 1. Capacitor CFF provides phase lead by
creating a high frequency zero with RFB2 which improves
the phase margin.
A more severe transient can be caused by switching in
loads with large supply bypass capacitors. The discharged
bypass capacitors of the load are effectively put in parallel
with the converter’s COUT
, causing a rapid drop in VOUT
.
No regulator can deliver current quick enough to prevent
this sudden step change in output voltage, if the switch
connecting the COUT to the load has low resistance and is
driven quickly. The solution is to limit the turn-on speed of
the load switch driver. Hot swap controllers are designed
specifically for this purpose and usually incorporate cur-
rent limiting, short-circuit protection and soft starting.
Load-Release Transient Detection
As the output voltage requirement of step-down switching
regulators becomes lower, VIN to VOUT step-down ratio
increases, and load transients become faster, a major
challenge is to limit the overshoot in VOUT during a fast
load current drop, or “load-release” transient.
Inductor current slew rate diL/dt = VL/L is proportional
to voltage across the inductor VL = VSW – VOUT. When
the top MOSFET is turned on, VL = VIN – VOUT, inductor
current ramps up. When bottom MOSFET turns on, VL =
VSW – VOUT = –VOUT, inductor current ramps down. At
very low VOUT, the low differential voltage, VL, across the
inductor during the ramp down makes the slew rate of the
inductor current much slower than needed to follow the
load current change. The excess inductor current charges
up the output capacitor, which causes overshoot at VOUT.
If the bottom MOSFET could be turned off during the load-
release transient, the inductor current would flow through
the body diode of the bottom MOSFET, and the equation
can be modified to include the bottom MOSFET body
diode drop to become VL = –(VOUT + VBD). Obviously the
benefit increases as the output voltage gets lower, since
VBD would increase the sum significantly, compared to a
single VOUT only.
The load-release overshoot at VOUT causes the error ampli-
fier output, ITH, to drop quickly. ITH voltage is proportional
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to the inductor current setpoint. A load transient will
result in a quick change of this load current setpoint, i.e.,
a negative spike of the first derivative of the ITH voltage.
The LTC3838 uses a detect transient (DTR) pin to monitor
the first derivative of the ITH voltage, and detect the load-
release transient. Referring to the Functional Diagram, the
DTR pin is the input of a DTR comparator, and the internal
reference voltage for the DTR comparator is half of INTVCC.
To use this pin for transient detection, ITH compensation
needs an additional RITH resistor tied to INTVCC, and con-
nects the junction point of ITH compensation components
CITH1, RITH1 and RITH2 to the DTR pin as shown in the
Functional Diagram. The DTR pin is now proportional to
the first derivative of the inductor current setpoint, through
the highpass filter of CITH1 and (RITH1//RITH2).
The two RITH resistors establish a voltage divider from
INTVCC to SGND, and bias the DC voltage on DTR pin (at
steady-state load or ITH voltage) slightly above half of
INTVCC. Compensation performance will be identical by
using the same CITH1 and make RITH1//RITH2 equal the
RITH as used in conventional single resistor OPTI-LOOP
compensation. This will also provide the R-C time constant
needed for the DTR duration. The DTR sensitivity can be
adjusted by the DC bias voltage difference between DTR
and half INTVCC. This difference could be set as low as
200mV, as long as the ITH ripple voltage with DC load
current does not trigger the DTR.
Note the internal 2.5µA pull-up current from the DTR pin
will generate an additional offset on top of the resistor
divider itself, making the total difference between the DC
bias voltage on the DTR pin and half INTVCC:
VDTR – 0.5VINTVCC =RITH1
(RITH1+RITH2)– 0.5
•5.3V
+2.5µA •R
ITH1
/ /R
ITH2
( )
As illustrated in Figure 12, when load current suddenly
drops, VOUT overshoots, and ITH drops quickly. The voltage
on the DTR pin will also drop quickly, since it is coupled
to the ITH pin through a capacitor. If the load transient
is fast enough that the DTR voltage drops below half of
INTVCC, a load release event is detected. The bottom gate
(BG) will be turned off, so that the inductor current flows
through the body diode in the bottom MOSFET. This al-
lows the SW node to drop below PGND by a voltage of
a forward-conducted silicon diode. This creates a more
negative differential voltage (VSW – VOUT) across the
inductor, allowing the inductor current to drop at a faster
rate to zero, therefore creating less overshoot on VOUT.
The DTR comparator output is overridden by reverse
inductor current detection (IREV) and overvoltage (OV)
condition. This means BG will be turned off when SENSE+
is higher than SENSE– (i.e., inductor current is positive),
Figure 12. Comparison of VOUT Overshoot with Detect Transient (DTR) Feature Enabled and Disabled
(12a) DTR Enabled
3838 F12
(12b) DTR Disabled
BG
5V/DIV
DTR
1V/DIV
IL
10A/DIV
DTR DETECTS LOAD
RELEASE, TURNS OFF BG
FOR FASTER INDUCTOR
CURRENT (IL) DECAY
5µs/DIVLOAD RELEASE = 15A TO 0A
VIN = 5V
VOUT = 0.6V
BG TURNS BACK ON, INDUCTOR
CURRENT (IL) GOES NEGATIVE
SW
5V/DIV
SW
5V/DIV
BG
5V/DIV
ITH
1V/DIV
IL
10A/DIV
5µs/DIV
LOAD RELEASE = 15A TO 0A
VIN = 5V
VOUT = 0.6V
BG REMAINS ON
DURING THE LOAD
RELEASE EVENT
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as long as the OV condition is not present. When inductor
current drops to zero and starts to reverse, BG will turn
back on in forced continuous mode (e.g., the MODE/
PLLIN pin tied to INTVCC, or an input clock is present),
even if DTR is still below half INTVCC. This is to allow the
inductor current to go negative to quickly pull down the
VOUT overshoot. Of course, if the MODE/PLLIN pin is set
to discontinuous mode (i.e., tied to SGND), BG will stay
off as inductor current reverse, as it would with the DTR
feature disabled.
Also, if VOUT gets higher than the OV window (7.5%
typical), the DTR function is defeated and BG will turn
on regardless. Therefore, in order for the DTR feature
to reduce VOUT overshoot effectively,sufficient output
capacitance needs to be used in the application so that
OV is not triggered with the amount of load step desired
to have its overshoot suppressed.
Experimenting with a 0.6V output application (modified
from the design example circuit by setting VOUT to 0.6V
and ITH compensation adjusted accordingly) shows this
detect transient feature significantly reduces the overshoot
peak voltage, as well as time to resume regulation during
load release steps (see application examples in Typical
Performance Characteristics).
Note that it is expected that this DTR feature will cause
additional loss on the bottom MOSFET, due to its body
diode conduction. The bottom MOSFET temperature may
be higher with a load of frequent and large load steps. This
is an important design consideration. Experiments on the
demo board shows a 20°C increase when a continuous
100% to 50% load step pulse train with 50% duty cycle
and 100kHz frequency is applied to the output.
If not needed, this DTR feature can be disabled by tying
the DTR pin to INTVCC, or simply leave the DTR pin open
so that an internal 2.5µA current source will pull itself up
to INTVCC.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percentage efficiency
can be expressed as:
%Efficiency = 100% – (L1% + L2% + L3% + ...)
where L1%, L2%, etc. are the individual losses as a per-
centage of input power. Although all dissipative elements
in the circuit produce power losses, several main sources
usually account for most of the losses in LTC3838 circuits:
1. I2R loss. These arise from the DC resistances of the
MOSFETs, inductor, current sense resistor and is the ma-
jority of power loss at high output currents. In continu-
ous mode the average output current flows though the
inductor L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same RDS(ON), then the resistance of one MOSFET can
simply be summed with the inductor’s DC resistances
(DCR) and the board traces to obtain the I2R loss. For
example, if each RDS(ON) = 8mΩ, RL = 5mΩ, and RSENSE
= 2mΩ the loss will range from 15mW to 1.5W as the
output current varies from 1A to 10A. This results in loss
from 0.3% to 3% a 5V output, or 1% to 10% for a 1.5V
output. Efficiency varies as the inverse square of VOUT
for the same external components and output power
level. The combined effects of lower output voltages
and higher currents load demands greater importance
of this loss term in the switching regulator system.
2. Transition loss. This loss mostly arises from the brief
amount of time the top MOSFET spends in the satura-
tion (Miller) region during switch node transitions. It
depends upon the input voltage, load current, driver
strength and MOSFET capacitance, among other fac-
tors, and can be significant at higher input voltages or
higher switching frequencies.
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3. DRVCC current. This is the sum of the MOSFET driver
and INTVCC control currents. The MOSFET driver cur-
rents result from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from DRVCC to ground. The resulting dQ/dt is a
current out of DRVCC that is typically much larger than
the controller IQ current. In continuous mode,
IGATECHG = f • (Qg(TOP) + Qg(BOT)),
where Qg(TOP) and Qg(BOT) are the gate charges of the
top and bottom MOSFETs, respectively.
Supplying DRVCC power through EXTVCC could save
several percents of efficiency, especially for high VIN
applications. Connecting EXTVCC to an output-derived
source will scale the VIN current required for the driver
and controller circuits by a factor of (Duty Cycle)/(Ef-
ficiency). For example, in a 20V to 5V application, 10mA
of DRVCC current results in approximately 2.5mA of VIN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from VIN)
to only a few percent.
4. CIN loss. The input capacitor filters large square-wave
input current drawn by the regulator into an averaged
DC current from the supply. The capacitor itself has
a zero average DC current, but square-wave-like AC
current flows through it. Therefore the input capacitor
must have a very low ESR to minimize the RMS current
loss on ESR. It must also have sufficient capacitance
to filter out the AC component of the input current to
prevent additional RMS losses in upstream cabling,
fuses or batteries. The LTC3838 2-phase architecture
improves the ESR loss.
“Hidden” copper trace, fuse and battery resistance, even
at DC current, can cause a significant amount of efficiency
degradation, so it is important to consider them during
the design phase. Other losses, which include the COUT
ESR loss, bottom MOSFET ’s body diode reverse-recovery
loss, and inductor core loss generally account for less
than 2% additional loss.
Power losses in the switching regulator will reflect as
a higher than ideal duty cycle, or a longer on-time for a
constant frequency. This efficiency accounted on-time
can be calculated as:
tON ≈ tON(IDEAL)/Efficiency
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased.
Design Example
Consider a channel of step-down converter from VIN =
4.5V to 26V to VOUT = 1.2V, with IOUT(MAX) = 15A, and
f = 350kHz (see Figure 13, Channel 1.
The regulated output voltage is determined by:
VOUT =0.6V •1+RFB2
RFB1
Using a 10k resistor for RFB1, RFB2 is also 10k.
The frequency is programmed by:
RTkΩ
[ ]
=
41550
f kHz
[ ]
– 2.2 =
41550
350 – 2.2 ≈116.5
Use the nearest 1% resistor standard value of 115k.
The minimum on-time occurs for maximum VIN. Using the
tON(MIN) curves in the Typical Performance Characteristics
as references, make sure that the tON(MIN) at maximum VIN
is greater than that the LTC3838 can achieve, and allow
sufficient margin to account for the extension of effective
on-time at light load due to the dead times (tD(TG/BG) +
tD(TG/BG) in the Electrical Characteristics). The minimum
on-time for this application is:
tON(MIN) =
V
OUT
VIN(MAX) •f=1.2V
24V •350kHz =143ns
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Figure 13. Design Example: 4.5V to 26V Input, 1.2V/15A and 1.5V/15A Dual Outputs,
350kHz, DCR Sense, DTR Enabled, Step-Down Converter
100k
90.9k
82.5k
3838 F13a
0.1µF
0.1µF
0.01µF
22pF
220pF
L2
0.56µH
COUT3
100µF
×2
COUT4
330µF
×2
V
OUT2
1.5V
15A
15k
DB2
MT2
MB2
3.57k
+
LTC3838
2.2Ω
2.2Ω
10k 15k
100k
90.9k
82.5k
115k
VIN
1µF
0.1µF
4.7µF
0.1µF
0.01µF
22pF
220pF
L1
0.56µH
COUT2
330µF
×2
COUT1
100µF
×2
V
OUT1
1.2V
15A
V
IN
4.5V TO 26V
15k
10k 10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
MT1
3.57k
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
MB1
1µF
CIN2
10µF
×3
+
CIN1
220µF
+
CIN1: PANASONIC EEEFK1V221P
CIN2: TAIYO YUDEN GMK325BJ106MN-T
COUT2, COUT4: SANYO 2R5TPE330M9
COUT1, COUT3: MURATA GRM31CR60J107ME39L
DB1, DB2: CENTRAL SEMI CMDSH-4ETR
L1, L2: VISHAY IHLP4040DZERR56M01
MT1, MT2: RENESAS RJK0305DPB
MB1, MB2: RENESAS RJK0330DPB
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
100
1 10
3838 F13b
90
0
0.5
1.0
1.5
2.0
3.0
2.5
EFFICIENCY
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
POWER
LOSS
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
100
1 10
3838 F13c
90
0
0.5
1.0
1.5
2.0
3.0
2.5
EFFICIENCY
VIN = 12V
VOUT = 1.5V
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
POWER
LOSS
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Set the inductor value to give 40% ripple current at maxi-
mum VIN using the adjusted operating frequency:
L=1.2V
350kHz •40% •15A
1– 1.2V
24V
=0.54µH
Select 0.56µH which is the nearest standard value.
The resulting maximum ripple current is:
∆IL=1.2V
350kHz •0.56µH
1– 1.2V
24V
=5.8A
Often in a high power application, DCR current sensing is
preferred over RSENSE in order to maximize efficiency. In
order to determine the DCR filter values, first the inductor
manufacturer has to be chosen. For this design, the Vishay
IHLP-4040DZ-01 model is chosen with a value of 0.56µH
and a DCRMAX =1.8mΩ. This implies that:
VSENSE(MAX) = 1.8mΩ • [1 + (100°C – 25°C) • 0.4%/°C]
• (15A – 5.8A/2) = 28mV
The maximum sense voltage, VSENSE(MAX), is within the
range that LTC3838 can handle without any additional
scaling. Therefore, the DCR filter can use a simple RC
filter across the inductor. If the C is chosen to be 0.1µF,
then the R can be calculated as:
RDCR =
L
DCR •C
DCR
=
0.56µH
1.8mΩ•0.1µF =3.1kΩ
The resulting VRNG pin voltage is:
VRNG =VSENSE(MAX)
0.05
=28mV •20 =0.56V
This voltage can be generated with a resistive divider from
the INTVCC pin to signal ground (SGND). To make sure that
the maximum load current of 15A can be supplied under
all conditions, such as lower INTVCC due to a lower VIN,
and account for the range of LTC3838’s own VSENSE(MAX)
variation within specification, a higher VRNG should be
used to provide margin.
A better and the recommended way to set VRNG is to simply
tie the VRNG pin to SGND for an equivalent of VRNG = 0.6V,
while using an additional resistor in the DCR filter, as
discussed in DCR Inductor Current Sensing, to scale the
VSENSE(MAX) down by a comfortable margin below the
lower limit of the LTC3838’s own VSENSE(MAX) specification,
so that the maximum output current can be guaranteed.
In this design example, a 3.57k and 15k resistor divider is
used. The previously calculated VSENSE(MAX) is scaled down
from 28mV to 22.6mV, which is close to the lower limit of
LTC3838’s VSENSE(MAX) specification at VRNG = 0.6V. Note
the equivalent RDCR = 3.57k//15k = 2.9k, slightly lower
than the 3.1k calculated above for a matched RDCR-CDCR
and L-DCR network. The resulted mismatch allows for a
slightly higher ripple in VSENSE.
Remember to check the peak inductor current, considering
the upper spec limit of VSENSE(MAX) and the DCR(MIN) at
lowest operating temperature, is not going to saturate the
inductor or exceed the rating of power MOSFETs.
For the external N-channel MOSFETs, Renesas
RJK0305DBP (RDS(ON) = 13mΩ max, CMILLER = 150pF, VGS
= 4.5V, θJA = 40°C/W, TJ(MAX) = 150°C) is chosen for the top
MOSFET (main switch). RJK0330DBP (RDS(ON) = 3.9mΩ
max, VGS = 4.5V, θJA
= 40°C/W, TJ(MAX) = 150°C) is chosen for
the bottom MOSFET (synchronous switch). The power dis-
sipation for each MOSFET can be calculated for VIN = 24V and
typical TJ = 125°C:
P
TOP =1.2V
24V
15A
( )
213mΩ
( )
1+0.4% 125°C – 25°C
( )
+24V
( )
215A
2
150pF
( )
2.5Ω
5.3V – 3V +1.2Ω
3V
350kHz
( )
=0.54W
P
BOT =24V – 1.2V
24V
15A
( )
23.9mΩ
( )
1+0.4% 125°C – 25°C
( )
=1.2W
The resulted junction temperatures at an ambient tem-
perature TA = 75°C are:
TJ(TOP) = 75°C + (0.54W)(40°C/W) = 97°C
TJ(BOT) = 75°C + (1.2W)(40°C/W) = 123°C
LTC3838
41
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For more information www.linear.com/LTC3838
applicaTions inForMaTion
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select the CIN capacitors to give ample capacitance and
RMS ripple current rating. Consider worst-case duty cycles
per Figure 6: If operated at steady-state with SW nodes
fully interleaved, the two channels would generate not
more than 7.5A RMS at full load. In this design example,
3 × 10µF 35V X5R ceramic capacitors are put in parallel
to take the RMS ripple current, with a 220µF aluminum-
electrolytic bulk capacitor for stability. For 10µF 1210 X5R
ceramic capacitors, try to keep the ripple current less
than 3A RMS through each device. The bulk capacitor
is chosen for RMS rating per simulation with the circuit
model provided.
The output capacitor COUT is chosen for a low ESR of
4.5mΩ to minimize output voltage changes due to inductor
ripple current and load steps. The output voltage ripple
is given as:
∆VOUT(RIPPLE) = ∆IL(MAX) • ESR = 5.85A • 4.5mΩ = 26mV
However, a 10A load step will cause an output change of
up to:
∆VOUT(STEP) = ∆ILOAD • ESR = 10A • 4.5mΩ = 45mV
Optional 2 × 100µF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
The ITH compensation resistor RITH of 40k and a CITH of
220pF are chosen empirically for fast transient response,
and an additional CITH2 = 22pF is added directly from
ITH pin to SGND, to roll off the system gain at switching
frequency and attenuate high frequency noise.
To set up the detect transient (DTR) feature, pick resistors
for an equivalent RITH = RITH1//RITH2 close to the 40k.
Here, 1% resistors RITH1 = 90.9k (low side) and RITH2
= 82.5k (high side) are used, which yields an equivalent
RITH of 43.2k, and a DC-bias threshold of 128mV above
one-half of INTVCC. Note that even though the accuracy
of the equivalent compensation resistance RITH is not as
important, always use 1% or better resistors for the resis-
tor divider from INTVCC to SGND to guarantee the relative
accuracy of this DC-bias threshold. To disable the DTR
feature, simply use a single RITH resistor to SGND, and
tie the DTR pin to INTVCC.
PCB Layout Checklist
The printed circuit board layout is illustrated graphically
in Figure 14. Figure 15 illustrates the current waveforms
present in the various branches of 2-phase synchronous
regulators operating in continuous mode. Use the follow-
ing checklist to ensure proper operation of the LTC3838:
• A multilayer printed circuit board with dedicated ground
planes is generally preferred to reduce noise coupling
and improve heat sinking. The ground plane layer
should be immediately next to the routing layer for the
power components, e.g., MOSFETs, inductors, sense
resistors, input and output capacitors etc.
• Keep SGND and PGND separate. Upon finishing the
layout, connect SGND and PGND together with a single
PCB trace underneath the IC from the SGND pin through
the exposed PGND pad to the PGND pin.
• All power train components should be referenced to
PGND; all components connected to noise-sensitive
pins, e.g., ITH, RT
, TRACK/SS and VRNG, should return
to the SGND pin. Keep PGND ample, but SGND area
compact. Use a modified “star ground” technique: a low
impedance, large copper area central PCB point on the
same side of the as the input and output capacitors.
• Place power components, such as CIN, COUT
, MOSFETs,
DB and inductors, in one compact area. Use wide but
shortest possible traces for high current paths (e.g.,
VIN, VOUT
, PGND etc.) to this area to minimize copper
loss.
LTC3838
42
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For more information www.linear.com/LTC3838
applicaTions inForMaTion
• Keep the switch nodes (SW1,2), top gates (TG1,2) and
boost nodes (BOOST1,2) away from noise-sensitive
small-signal nodes, especially from the opposite
channel’s voltage and current sensing feedback pins.
These nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3838 (power-related pins are toward the right
hand side of the IC), and occupy minimum PC trace
area. Use compact switch node (SW) planes to improve
cooling of the MOSFETs and to keep EMI down. If DCR
sensing is used, place the top filter resistor (R1 only in
Figure 5) close to the switch node.
DTR2 RUN2
SENSE2–
SENSE2+
VFB2
TRACK/SS2
ITH2
RFB2(2)
RITH2(2)
CSS2
CITH1(2)
CITH2(2)
LOCALIZED
SGND TRACE
PGOOD2
BOOST2
TG2
CB2
DB2
DB1
RINTVCC
SW2
DRVCC2
EXTVCC
VIN
DRVCC1
BG1
SW1
TG1
BOOST1
PGOOD1
RUN1
DTR1
PGND
INTVCC
BG2
CINTVCC
CVIN
RVIN
CDRVCC
CB1
CIN
CERAMIC
CERAMIC
MT2 MB2
MT1 MB1
+
VIN
L2
L1
COUT2
VOUT2
PGND
VOUT1
BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH.
+
COUT1
+
RSENSE1
RSENSE2
RT
RT
VRNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
VRNG1
RITH1(2)
RFB1(2)
CITH2(1)
CITH1(1)
CSS1
RFB1(1)
RITH1(1) ITH1
TRACK/SS1
VOUTSENSE1+
VOUTSENSE1–
SENSE1+
SENSE1–
RITH2(1)
RFB2(1)
Figure 14. Recommended PCB Layout Diagram
LTC3838
43
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For more information www.linear.com/LTC3838
applicaTions inForMaTion
R
L2
L2
SW1
RSENSE2 VOUT2
COUT2
VIN
CIN
R
IN
R
L1
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L1
SW2
3838 F15
RSENSE1 VOUT1
COUT1
Figure 15. Branch Current Waveforms
• The top N-channel MOSFETs of the two channels have
to be located within a short distance from (preferably
<1cm) each other with a common drain connection at
CIN. Do not attempt to split the input decoupling for the
two channels as it can result in a large resonant loop.
• Connect the input capacitor(s), CIN, close to the power
MOSFETs. This capacitor provides the MOSFET transient
spike current. Connect the drain of the top MOSFET as
close as possible to the (+) plate of the ceramic portion
of input capacitors CIN. Connect the source of the bot-
tom MOSFET as close as possible to the (–) terminal
of the same ceramic CIN capacitor(s). These ceramic
capacitor(s) bypass the high di/dt current locally, and
both top and bottom MOSFET should have short PCB
trace lengths to minimize high frequency EMI and
prevent MOSFET voltage stress from inductive ringing.
LTC3838
44
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For more information www.linear.com/LTC3838
• The path formed by the top and bottom N-channel
MOSFETs, and the CIN capacitors should have short
leads and PCB trace. The (–) terminal of output capaci-
tors should be connected close to the (–) terminal of
CIN, but away from the loop described above. This is
to achieve an effect of Kevin (4-wire) connection to the
input ground so that the “chopped” switching current
will not flow through the path between the input ground
and the output ground, and cause common mode output
voltage ripple.
• Several smaller sized ceramic output capacitors, COUT
,
can be placed close to the sense resistors and before
the rest bulk output capacitors.
• The filter capacitor between the SENSE+ and SENSE– pins
should always be as close as possible to these pins.
Ensure accurate current sensing with Kevin (4-wire)
connections to the soldering pads from underneath
the sense resistors or inductor. A pair of sense traces
should be routed together with minimum spacing.
RSENSE, if used, should be connected to the inductor
on the noiseless output side, and its filter resistors
close to the SENSE+/SENSE– pins. For DCR sensing,
however, filter resistor should be placed close to the
inductor, and away from the SENSE+/SENSE– pins, as
its terminal is the SW node.
• Keep small-signal components connected noise-sensi-
tive pins (give priority to SENSE+/SENSE–, VOUTSENSE1+/
VOUTSENSE1–, VFB2, RT
, ITH, VRNG pins) on the left hand
side of the IC as close to their respective pins as pos-
sible. This minimizes the possibility of noise coupling
into these pins. If the LTC3838 can be placed on the
bottom side of a multilayer board, use ground planes
to isolate from the major power components on the top
side of the board, and prevent noise coupling to noise
sensitive components on the bottom side.
• Place the resistor feedback divider RFB1, RFB2 close to
VOUTSENSE1+ and VOUTSENSE1– pins for Channel 1, or
VFB2 pin for Channel 2, so that the feedback voltage
tapped from the resistor divider will not be disturbed by
noise sources. Route remote sense PCB traces (use a
pair of wires closely together for differential sensing in
Channel 1) directly to the terminals of output capacitors
for best output regulation.
• Place decoupling capacitors CITH2 next to the ITH and
SGND pins with short, direct trace connections.
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor CINTVCC between
the INTVCC pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor CDRVCC close
to the IC, between the combined DRVCC1,2 pins and
PGND.
• Filter the VIN input to the LTC3838 with an RC filter.
Place the filter capacitor close to the VIN pin.
• If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of LTC3838.
Use multiple large vias for power components.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.
PCB Layout Debugging
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. It is helpful to use a current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator output CLKOUT, or
external clock if used. Probe the actual output voltage as
well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range. The phase should be maintained
applicaTions inForMaTion
LTC3838
45
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For more information www.linear.com/LTC3838
from cycle to cycle in a well designed, low noise PCB
implementation. Variation in the phase of SW node pulse
can suggest noise pickup at the current or voltage sensing
inputs or inadequate loop compensation. Overcompensa-
tion of the loop can be used to tame a poor PCB layout if
regulator bandwidth optimization is not required.
Pay special attention to the region of operation when one
controller channel is turning on (right after its current
comparator trip point) while the other channel is turning
off its top MOSFET at the end of its on-time. This may
cause minor phase-lock jitter at either channel due to
noise coupling.
Reduce VIN from its nominal level to verify operation of
the regulator in dropout. Check the operation of the un-
dervoltage lockout circuit by further lowering VIN while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG,
and possibly BG connections and the sensitive voltage
and current pins.
applicaTions inForMaTion
The capacitor placed across the current sensing pins needs
to be placed immediately adjacent to the pins of the IC.
This capacitor helps to minimize the effects of differential
noise injection due to high frequency capacitive coupling.
If problems are encountered with high current output
loading at lower input voltages, look for inductive coupling
between CIN, top and bottom MOSFET components to the
sensitive current and voltage sensing traces.
In addition, investigate common ground path voltage pickup
between these components and the SGND pin of the IC.
High Switching Frequency Operation
At high switching frequencies there may be an increased
sensitivity to noise. Special care may need to be taken to
prevent cycle-by-cycle instability and/or phase-lock jitter.
First, carefully follow the recommended layout techniques
to reduce coupling from the high switching voltage/current
traces. Additionally, use low ESR and low impedance X5R
or X7R ceramic input capacitors: up to 5μF per Ampere of
load current may be needed. If necessary, increase ripple
sense voltage by increasing sense resistance value and
VRNG setting, to improve noise immunity.
LTC3838
46
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For more information www.linear.com/LTC3838
Typical applicaTions
Figure 16. 4.5V to 38V Input, 1.2V/15A and 1.5V/15A Dual Output, 350kHz, DCR Sense, Step-Down Converter
100k
40.2k
3838 F16a
0.1µF
0.1µF
0.01µF
22pF
220pF
L2
0.56µH
COUT3
100µF
×2
COUT4
330µF
×2
V
OUT2
1.5V
15A
15k
DB2
MT2
MB2
3.57k
+
LTC3838
2.2Ω
2.2Ω
10k 15k
100k
40.2k
115k
VIN
1µF
0.1µF
4.7µF
0.1µF
0.01µF
22pF
220pF
L1
0.56µH
COUT2
330µF
×2
COUT1
100µF
×2
V
OUT1
1.2V
15A
V
IN
4.5V TO 38V
15k
10k 10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
MT1
3.57k
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
MB1
1µF
CIN2
10µF
×3
+
CIN1
100µF
+
CIN1: NICHICON UCJ1H101MCL165
CIN2: MURATA GRM32ER71H106K
COUT2, COUT4: SANYO 2R5TPE330M9
COUT1, COUT3: MURATA GRM31CR60J107ME39L
DB1, DB2: DIODES INC. SDM10K45
L1, L2: TOKO FDA1055-R56M
MT1, MT2: INFINEON BSC093N04LSG
MB1, MB2: INFINEON BSC035N04LSG
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
1
EFFICIENCY
10
3838 F16b
70
60
50
0
1.5
2.0
2.5
1.0
0.5
VIN = 12V
VOUT = 1.2V
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
POWER
LOSS
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
100
1 10
3838 F16c
90
0
0.5
1.0
1.5
2.0
3.0
2.5
EFFICIENCY
VIN = 12V
VOUT = 1.5V
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
POWER
LOSS
LTC3838
47
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For more information www.linear.com/LTC3838
Typical applicaTions
Figure 17. 6V to 26V Input, 1.2V/15A and 1.5V/15A Dual Output, 350kHz, RSENSE, Step-Down Converter
100k
3838 F17
1nF
0.1µF
L2
0.47µH
COUT4
100µF
×2
COUT3
330µF
×2
DB2
MT2
MB2
+
LTC3838
2.2Ω
2.2Ω
10k
22pF 22pF
220pF 220pF
39.2k 39.2k
100k
115k
10k 10k
60.4k 60.4k
VIN
1µF
1nF
4.7µF
0.1µF
0.01µF 0.01µF
L1
0.47µH
RS1
0.002Ω RS2
0.002Ω
COUT2
330µF
×2
COUT1
100µF
×2
V
OUT1
1.2V
12A
VOUT2
1.5V
12A
V
IN
6V TO 26V
10k
15k
10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
MB1
MT1
1µF
CIN2
10µF
×3
+
CIN1
220µF
+
100Ω
100Ω
100Ω
100Ω
CIN1: PANASONIC EEEFK1V221P
CIN2: TAIYO YUDEN GMK325BJ106MN-T
COUT1, COUT4
: MURATA GRM31CR60J107ME39L
COUT2, COUT3: SANYO 2R5TPE330M9
DB1, DB2: CENTRAL SEMI CMDSH-4ETR
L1, L2: WÜRTH 7443330047
MT1, MT2: RENESAS RJK0305DPB
MB1, MB2: RENESAS RJK0330DPB
LTC3838
48
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For more information www.linear.com/LTC3838
Typical applicaTions
Figure 18. 4.5V to 14V Input, 1.2V/50A 2-Phase Single Output, 300kHz, DCR Sense, DTR Enabled, Step-Down Converter
LOAD CURRENT (A)
0.1
50
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
1 10
3838 F18b
70
60
0
6
8
10
4
2
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
VIN = 12V
VOUT = 1.2V
EFFICIENCY POWER
LOSS
LOAD CURRENT (A)
0.1
50
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
1 10
3838 F18c
70
60
0
6
8
10
4
2
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
VIN = 5V
VOUT = 1.2V
EFFICIENCY POWER
LOSS
3838 F18
0.1µF
0.1µF
L2
0.36µH
L1
0.36µH
COUT4
100µF
×2
COUT3
330µF
×2
DB2
MT2
MB2
2.55k
+
LTC3838
2.2Ω
2.2Ω
10k
100k
35.7k
41.2k
137k
VIN
1µF
0.1µF
4.7µF
0.1µF
0.01µF
47pF
470pF
COUT2
330µF
×2
COUT1
100µF
×2
VOUT
1.2V
50A
VIN
4.5V TO 14V
10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD
MB1
MT1
1µF
CIN2
22µF
×4
+
CIN1
180µF
+
2.55k
CIN1: SANYO 16SVP180MX
CIN2: TDK C3225X5R1C226MT
COUT1, COUT4: MURATA GRM31CR60J107ME39L
COUT2, COUT3: SANYO 2R5TPE330M9
DB1, DB2: CENTRAL SEMI CMDSH-4ETR
L1, L2: VISHAY IHLP4040DZERR36M01
MT1, MT2: INFINEON BSC050NE2LS
MB1, MB2: INFINEON BSC010NE2LS
LTC3838
49
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For more information www.linear.com/LTC3838
Typical applicaTions
Figure 19. 6.5V to 34V Input, 5V/12A and 3.3V/12A Dual Output, 300kHz, RSENSE, 5V Output Tied to EXTVCC, Step-Down Converter
100k
3838 F19
1nF
0.1µF
L2
1.3µH
COUT4
100µF
COUT3
330µF
DB2
VOUT1
MT2
MB2
+
LTC3838
2.2Ω
2.2Ω
73.2k
100k
137k
220pF 220pF
22pF 22pF
53.6k 45.3k
VIN
1µF
1nF
4.7µF
0.1µF
0.01µF 0.01µF
L1
2.2µH
RS1
0.002Ω RS2
0.002Ω
COUT2
150µF
×2
COUT1
100µF
V
OUT1
5V
12A
VOUT2
3.3V
12A
V
IN
6.5V TO 34V
45.3k
10k
10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
MB1
MT1
1µF
CIN2
10µF
×3
+
CIN1
220µF
+
20Ω
20Ω
20Ω
20Ω
CIN1: PANASONIC EEEFK1V221P
CIN2: TAIYO YUDEN GMK325BJ106MN-T
COUT1, COUT4
: MURATA GRM31CR60J107ME39L
COUT2: SANYO 6TPE150MIC2
COUT3: SANYO 4TPD330M
DB1, DB2: DIODES INC. SDM10K45
L1: WÜRTH 7443320220
L2: WÜRTH 7443551130
MT1, MT2: INFINEON BSC093N04LSG
MB1, MB2: INFINEON BSC035N04LSG
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
100
1 10
3838 F19b
90
0
0.5
1.0
1.5
2.0
3.0
2.5
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
EFFICIENCY
POWER
LOSS
VIN = 12V
VOUT = 5V
LOAD CURRENT (A)
0.1
40
EFFICIENCY (%)
POWER LOSS (W)
50
60
70
80
100
1 10
3838 F19c
90
0
0.5
1.0
1.5
2.0
3.0
2.5
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
EFFICIENCY
POWER
LOSS
VIN = 12V
VOUT = 3.3V
LTC3838
50
3838fb
For more information www.linear.com/LTC3838
Typical applicaTions
Figure 20. 7V to 14V Input, 5V/5A and 3.3V/5A Dual Output, 2MHz, RSENSE, Step-Down Converter with EXTVCC Tied to 5V Output
LOAD CURRENT (A)
0.01
50
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
0.1 1
3838 F20b
70
60
0
1.5
2.0
2.5
1.0
0.5
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
VIN = 12V
VOUT = 5V
EXTV
CC
TIED TO V
OUT
EFFICIENCY POWER
LOSS
LOAD CURRENT (A)
0.01
50
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
0.1 1
3838 F20c
70
60
0
1.5
2.0
2.5
1.0
0.5
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
VIN = 12V
VOUT = 3.3V
EXTVCC TIED TO 5V BIAS SUPPLY
EFFICIENCY MEASUREMENTS INCLUDE POWER
FROM THE 5V BIAS SUPPLY
EFFICIENCY
POWER
LOSS
LOAD CURRENT (A)
0.01
50
EFFICIENCY (%)
POWER LOSS (W)
80
90
100
0.1 1
3838 F20d
70
60
0
1.5
2.0
2.5
1.0
0.5
FORCED CONTINUOUS MODE
DISCONTINUOUS MODE
VIN = 12V
VOUT = 3.3V
EXTV
CC
FLOATING
EFFICIENCY
POWER
LOSS
100k
45.3k
3838 F20a
1nF
0.1µF
L2
0.8µH
COUT2
47µF
×2
DB2
VOUT1
MT2
MB2
LTC3838
2.2Ω
2.2Ω
73.2k
100k
24.9k
18.7k
VIN
1µF
1nF
4.7µF
0.1µF
0.01µF
47pF
0.01µF
22pF 22pF
330pF 330pF
L1
0.8µH
RS1
0.008Ω RS2
0.008Ω
COUT1
47µF
×2
VOUT1
5V
5A
VOUT2
3.3V
5A
VIN
7V TO 14V
10k 10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
MB1
MT1
1µF
CIN2
10µF
×3
CIN1
39µF
+
10Ω
10Ω
10Ω
10Ω
35.7k
CIN1: SANYO 16SVP39M
CIN2: MURATA GRM32DR61E106K
COUT1, COUT2: TAIYO YUDEN LMK325BJ476MM-T
DB1, DB2: CENTRAL CMDSH-3
L1, L2: COILCRAFT XAL5030-801MEB
MT1, MB1, MT2, MB2: VISHAY SI7114ADN
68pF
LTC3838
51
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For more information www.linear.com/LTC3838
5.00 ±0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF 5.15 ±0.10
7.00
±0.10
0.75 ±0.05
R = 0.125
TYP R = 0.10
TYP
0.25 ±0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ±0.10
0.40 ±0.10
0.70 ±0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ±0.05
4.10 ±0.05
5.50 ±0.05 5.15 ±0.05
6.10 ±0.05
7.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°
CHAMFER
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
package DescripTion
Please refer to http://www.linear.com/product/LTC3838#packaging for the most recent package drawings.
LTC3838
52
3838fb
For more information www.linear.com/LTC3838
4.75
(.187) REF
FE38 (AA) TSSOP REV C 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
119
20
REF
9.60 – 9.80*
(.378 – .386)
38
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.50
(.0196)
BSC 0.17 – 0.27
(.0067 – .0106)
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.315 ±0.05
0.50 BSC
4.50 REF
6.60 ±0.10
1.05 ±0.10
4.75 REF
2.74 REF
2.74
(.108)
MILLIMETERS
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
38-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1772 Rev C)
Exposed Pad Variation AA
package DescripTion
Please refer to http://www.linear.com/product/LTC3838#packaging for the most recent package drawings.
LTC3838
53
3838fb
For more information www.linear.com/LTC3838
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 6/12 Electrical specs clarification, 4.6V EXTVCC switch over 3, 4, 5, 13
B 3/16 Modified Table 1 2
LTC3838
54
3838fb
For more information www.linear.com/LTC3838
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
LINEAR TECHNOLOGY CORPORATION 2011
LT 0316 REV B • PRINTED IN USA
relaTeD parTs
Typical applicaTion
4.5V to 26V Input, 2.5V/4A and 1.8V/4A Dual Output, 1MHz, RSENSE, Dual Channel Power FETs, Step-Down Converter
PART NUMBER DESCRIPTION COMMENTS
LTC3838-1/
LTC3838-2 Dual or Single Output, Controlled On-Time, Synchronous Step-
Down Controller, Differential VOUT Sense, Internal/External VREF
PLL, 200kHz to 2MHz Operating Frequency, 4.5V ≤ VIN ≤ 38V,
0.6V/0.4V ≤ VOUT ≤ 5.5V, 5mm × 7mm QFN-38, TSSOP-38 (Table 1)
LTC3839 Single Output, 2-Phase, Controlled On-Time, Synchronous Step-
Down Controller with Differential VOUT Sense PLL, 200kHz to 2MHz Operating Frequency, 4.5V ≤ VIN ≤ 38V,
0.6V ≤ VOUT ≤ 5.5V, 5mm × 5mm QFN-32
LTM4650 Dual 25A or Single 50A DC/DC μModule
®
Regulator with
Multiphase Operation and Differential VOUT Sense 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 14V 16mm × 16mm × 5mm Package
LTM4630A Dual 18A or Single 36A DC/DC μModule Regulator with
Multiphase Operation and Differential VOUT Sense 4.5V ≤ VIN ≤ 15V, 0.6V ≤ VOUT ≤ 5.3V 16mm × 16mm × 4.41mm
Package
LTC7851/
LTC7851-1 Quad Output, Multiphase Step-Down Voltage Mode DC/DC
Controller with Accurate Current Sharing Operates with DrMOS, Power Blocks or External Drivers/MOSFETs,
3V ≤ VIN ≤ 27V
LTC3774 Dual, Multiphase Current Mode Synchronous Step-Down
Controller with Sub-Milliohm DCR Sensing, Up to 12 Phases Operates with DrMOS, Power Blocks or External Drivers/MOSFETs,
4.5V ≤ VIN ≤ 38V, 0.6V ≤ VOUT ≤ 3.5V with Remote VOUT Sense
LTC3855 Dual, Multiphase, Synchronous Step-Down DC/DC Controller
with Diff Amp and DCR Temperature Compensation Phase-Lockable Fixed Frequency 250kHz to 770kHz, 4.5V ≤ VIN ≤ 38V,
0.8V ≤ VOUT ≤ 12V
LTC3869/
LTC3869-2 Dual Output, 2-Phase Synchronous Step-Down DC/DC
Controller, with Accurate Current Share 4V ≤ VIN ≤ 38V, VOUT3 Up to 12.5V PLL Fixed 250kHz to 750kHz
Frequency
LTC3861/
LTC3861-1 Dual, Multiphase Synchronous Step-Down DC/DC Controller
with Multiphase Operation and Differential VOUT Sense Operates with Power Blocks, DR MOS or External Drivers/MOSFETs
3V ≤ VIN ≤ 24V, 5mm × 6mm QFN-36
100k
20k
3838 TA02
1nF
0.1µF
L2
1.2µH
COUT2
100µF
×2
DB2
M2
LTC3838
2.2Ω
2.2Ω
31.6k
100k
39.2k
VIN
1µF
1nF
4.7µF
0.1µF
0.01µF
75k 61.9k
100pF 100pF
0.01µF
L1
1.2µH
RS1
0.006Ω RS2
0.006Ω
COUT1
100µF
×2
VOUT1
2.5V
4A
VOUT2
1.8V
4A
V
IN
4.5V TO 26V
10k 10k
SENSE1–
SENSE1+
BOOST1
TG1
SW1
SENSE2+
BOOST2
TG2
SW2
DRVCC1
INTVCC
DRVCC2
EXTVCC
DB1
SENSE2–
BG1 BG2
VFB2
PGND
VOUTSENSE1+
VOUTSENSE1–
PGOOD1 PGOOD2
TRACK/SS1
ITH1
DTR1
VRNG1
TRACK/SS2
ITH2
DTR2
PHASMD
MODE/PLLIN
CLKOUT
RUN2
VRNG2
SGND
RUN1
RT
PGOOD1 PGOOD2
M1
1µF
CIN2
10µF
×3
CIN1
47µF
+
20Ω
20Ω
20Ω
20Ω
CIN1: SUN CON 35HVP47M
CIN2: TAIYO YUDEN GMK325BJ106MN-T
COUT1,COUT2
: MURATA GRM31CR60J107ME39L
COUT2, COUT4: SANYO 4TPC150M
DB1, DB2: CENTRAL SEMI CMDSH-4ETR
L1, L2: COILCRAFT XAL5030-122MEB
M1, M2: SILICONIX SI4816DY
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3838