STM32L151xD STM32L152xD Ultra-low-power 32-bit MCU ARM-based Cortex-M3, 384KB Flash, 48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F Datasheet production data Features Ultra-low-power platform - 1.65 V to 3.6 V power supply - -40C to 85C/105C Temperature range - 0.35 A Standby mode (3 wakeup pins) - 1.3 A Standby mode + RTC - 0.65 A Stop mode (16 wakeup lines) - 1.7 A Stop mode + RTC - 11 A Low-power Run mode - 238 A/MHz Run mode - 10 nA ultra-low I/O leakage - 8 s wakeup time Core: ARM 32-bit CortexTM-M3 CPU - From 32 kHz up to 32 MHz max - 33.3 DMIPS peak (Dhrystone 2.1) - Memory protection unit Up to 34 capacitive sensing channels CRC calculation unit, 96-bit unique ID Reset and supply management - Low power, ultrasafe BOR (brownout reset) with 5 selectable thresholds - Ultralow power POR/PDR - Programmable voltage detector (PVD) Clock sources - 1 to 24 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - High Speed Internal 16 MHz factorytrimmed RC (+/- 1%) - Internal low power 37 kHz RC - Internal multispeed low power 65 kHz to 4.2 MHz - PLL for CPU clock and USB (48 MHz) Pre-programmed bootloader - USB and USART supported Serial wire debug, JTAG and trace October 2012 This is information on a product in full production. LQFP144 (20 x 20 mm) LQFP100 (14 x 14 mm) LQFP64 (10 x 10 mm) UFBGA132 (7 x 7 mm) WLCSP64 (0.400 mm pitch) Up to 116 fast I/Os (102 I/Os 5V tolerant), all mappable on 16 external interrupt vectors Memories - 384 KB Flash with ECC (with 2 bank of 192 KB enabling Rww capability) - 48 KB RAM - 12 KB of true EEPROM with ECC - 128 Byte Backup Register - Memory interface controller supporting SRAM, PSRAM and NOR Flash LCD driver for up to 8x40 segments (contrast adjustment, blinking mode, step-up converter) Rich analog peripherals (down to 1.8V) - 3x Operational Amplifier - 12-bit ADC 1 Msps up to 40 channels - 12-bit DAC 2 ch with output buffers - 2x ultra-low-power-comparators (window mode and wake up capability) DMA controller 12x channels 12x peripherals communication interface - 1x USB 2.0 (internal 48 MHz PLL) - 5x USART - 3x SPI 16 Mbits/s (2x SPI with I2S) - 2x I2C (SMBus/PMBus) - 1x SDIO interface 11x timers: 1x 32-bit, 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timer, 2x watchdog timers (independent and window) Table 1. Device summary Reference Part number STM32L151xx STM32L151QD STM32L151RD STM32L151VD STM32L151ZD STM32L152xx STM32L152QD STM32L152RD STM32L152VD STM32L152ZD Doc ID 022027 Rev 5 1/141 www.st.com 1 Contents STM32L151xD STM32L152xD Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/141 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 ARM(R) CortexTM-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Low power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 23 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.8 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.9 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.11.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.12 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.13 Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 28 3.15 System configuration controller and routing interface . . . . . . . . . . . . . . . 28 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Contents 3.16 Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.18 3.17.1 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.17.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.1 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.18.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 30 3.18.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.4 Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.5 SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.18.6 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.19 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 31 3.20 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 57 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Doc ID 022027 Rev 5 3/141 Contents 7 STM32L151xD STM32L152xD 6.3.5 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.7 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.8 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.3.9 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 96 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.16 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.17 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.18 SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.23 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.3.24 LCD controller (STM32L152xD only) . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 7.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 4/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L15xxD device features and peripheral counts . . . . . . . . . . . . . . . 11 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 16 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16 Functionalities depending on the working mode (from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32L15xxD pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 58 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Current consumption in Run mode, code with data processing running from Flash. . . . . . 61 Current consumption in Run mode, code with data processing running from RAM . . . . . . 62 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 67 Typical and maximum timings in Low power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 HSE 1-24 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 83 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 85 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 86 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 93 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Doc ID 022027 Rev 5 5/141 List of tables Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. 6/141 STM32L151xD STM32L152xD Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 127 LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 129 LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 130 UFBGA132 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data . . . . . . . . . . 134 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 STM32L15xxD ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Ultra-low-power STM32L15xxD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 STM32L15xZD LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STM32L15xQD BGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 STM32L15xVD LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32L15xRD LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32L15xRD WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 84 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 85 Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 86 Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 87 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 93 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 SDIO timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum dynamic current consumption on VREF+ supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 117 Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 117 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 126 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 128 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 130 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . . 132 Doc ID 022027 Rev 5 7/141 List of figures Figure 48. Figure 49. 8/141 STM32L151xD STM32L152xD WLCSP64, 0.400 mm pitch wafer level chip size package outline . . . . . . . . . . . . . . . . . . 133 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L151xD and STM32L152xD ultra-low-power ARM CortexTM-based microcontrollers product line. STM32L15xD devices are microcontrollers with a Flash memory density of 384 Kbytes. The ultra-low-power STM32L15xxD family includes devices in 5 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L15xxD microcontroller family suitable for a wide range of applications: Medical and handheld equipment Application control and user interface PC peripherals, gaming, GPS and sport equipment Alarm systems, wired and wireless sensors, Video intercom Utility metering This STM32L151xD and STM32L152xD datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The document "Getting started with STM32L1xxx hardware development" AN3216 gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the CortexTM-M3 core please refer to the CortexTM-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337g. Figure 1 shows the general block diagram of the device family. Doc ID 022027 Rev 5 9/141 Description 2 STM32L151xD STM32L152xD Description The ultra-low-power STM32L15xxD incorporates the connectivity power of the universal serial bus (USB) with the high-performance ARM CortexTM-M3 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes and RAM up to 48 Kbytes), a flexible static memory controller (FSMC) interface (for devices with packages of 100 pins and more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. The STM32L15xxD devices offer three operational amplifiers, one 12-bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six general-purpose 16bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L15xxD devices contain standard and advanced communication interfaces: up to two I2Cs, three SPIs, two I2S, one SDIO, three USARTs, two UARTs and a USB. The STM32L15xxD devices offer up to 34 capacitive sensing channels to simply add touch sensing functionality to any application. They also include a real-time clock and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows you to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage. The ultra-low-power STM32L15xxD operates from a 1.8 to 3.6 V power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without BOR option. It is available in the -40 to +85 C temperature range, extended to 105C in low power dissipation state. A comprehensive set of power-saving modes allows the design of lowpower applications. 10/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Description 2.1 Device overview Table 2. Ultra-low-power STM32L15xxD device features and peripheral counts Peripheral STM32L15xRD STM32L15xVD STM32L15xQD Flash (Kbytes) 384 Data EEPROM (Kbytes) 12 RAM (Kbytes) 48 FSMC Timers No multiplexed only Yes 32 bit 1 General-purpose 6 Basic 2 3/(2) SPI/(I2S) Communication interfaces I2C 2 USART 5 USB 1 SDIO 1 GPIOs 51 83 Operation amplifiers 12-bit synchronized ADC Number of channels 1 21 1 25 1 40 1 40 1 1 4x32 or 8x28 4x44 or 8x40 2 Capacitive sensing channels 23 33 Max. CPU frequency 34 32 MHz 1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option 1.65 V to 3.6 V without BOR option Ambient temperature: -40 to +85 C Junction temperature: -40 to +105 C Operating temperatures Packages 115 2 2 Comparators Operating voltage 109 3 12-bit DAC Number of channels LCD (1) COM x SEG STM32L15xZD LQFP64, WLCSP64 LQFP100 BGA132 LQFP144 1. STM32L152xx devices only. Doc ID 022027 Rev 5 11/141 Description 2.2 STM32L151xD STM32L152xD Ultra-low-power device continuum The ultra-low-power STM32L15xxD, STM32L162xD, STM32L15xxC and STM32L162xC are fully pin-to-pin and software compatible. Besides the full compatibility within the family, the devices are part of STMicroelectronics microcontrollers ultra-low-power strategy which also includes STM8L101xx and STM8L15xx devices. The STM8L and STM32L families allow a continuum of performance, peripherals, system architecture and features. They are all based on STMicroelectronics ultralow leakage process. Note: The ultra-low-power STM32L and general-purpose STM32Fxxxx families are pin-to-pin compatible. The STM8L15xxx devices are pin-to-pin compatible with the STM8L101xx devices. Please refer to the STM32F and STM8L documentation for more information on these devices. 2.2.1 Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM CortexTM-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx and STM32L15xxx share identical peripherals which ensure a very easy migration from one family to another: 2.2.3 Analog peripherals: ADC, DAC and comparators Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L15xxx and STM32L15xxx families use a common architecture: 2.2.4 Same power supply range from 1.65 V to 3.6 V Architecture optimized to reach ultralow consumption both in low power modes and Run mode Fast startup strategy from low power modes Flexible system clock Ultrasafe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector Features ST ultra-low-power continuum also lies in feature compatibility: 12/141 More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm Memory density ranging from 4 to 384 Kbytes Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 3 Functional overview Figure 1. Ultra-low-power STM32L15xxD block diagram 42!#%#+ 42!#%$ 42!#%$ 42!#%$ 42!#%$ *4!' 37 $BU S 3YSTEM .6)# '0 $-! CHANNELS "/2 '0)/ 0/24 " 0#;= '0)/ 0/24# 0$;= '0)/ 0/24 $ 0%;= '0)/ 0/24 % 0(;= '0)/ 0/24 ( 0&;= '0)/ 0/24 & 0';= '0)/ 0/24 ' !& %84)4 7+50 -/3) -)3/ 3#+ .33 AS !& 30) 3$)/ #+ 'ENERAL PURPOSE TIMERS 6$$ #HANNEL 4)-%2 #HANNEL 4)-%2 ,#$ "OOSTER 4)-%2 #HANNELS 4)-%2 #HANNELS 4)-%2 #HANNELS 4)-%2 BITS #HANNELS 53!24 28 48 #43 243 3MART#ARD AS !& 53!24 28 48 AS !& 7*/1 7*/. 7065 Doc ID 022027 Rev 5 28 48 AS !& 30))3 XXBIT 30))3 XXBIT -/3) -)3/ 3#+ .33 73 #+ -#+ 3$ AS !& )# 3#, 3$! AS !& )# 3#, 3$! 3-"US 0-"US AS !& 53" &3 DEVICE #AP SENSING ,#$ X 53"? $0 53"? $0X 3%'X #/-X 6$$! /0!-0 7*/1 7*/. 7065 28 48 #43 243 3MART#ARD AS !& -/3) -)3/ 3#+ .33 73 #+ -#+ 3$ AS !& /0!-0 7*/1 7*/. 7065 53!24 53!24 /0!-0 6,#$ 6 TO 6 4)-%2 !(" !0" 4)-%2 4)-%2 4!-0%2 "ACKUP INTERFACE 7IN7!4#($/' )& /3#?). /3#?/54 24#?/54 24# 6 "ACK UP REG !7 5 !"0 F -!8 -(Z BIT !$# /3#?). /3#?/54 7$'+ 84!, K(Z 53" 32!- " 6$$! .234 3TANDBY INTERFACE 53!24 4EMP SENSOR #HANN ELS 0,, #LOCK -GMT 2# ,3) 6$$! !(" !0" 6332%&?!$# $ #-$ 6$$! !"0 F -!8 -(Z !& 6$$2%&?!$# 84!, /3# -(Z 2# -3) )NT '0)/ 0/24 ! 0";= 0$2 2# (3) '0 #OMP 05 0$ 6REF 6$$ !("0#,+ !0"0#,+ (#,+ &#,+ #AP SENS #/-0X?).X 633 0$2 6,#$ 3UPPLY MONITORING "/2 "GAP 6$$6 TO 6 3UPPLY MONITORING 6$$! &3-# 06$ 28 48 #43 243 3MART#ARD AS !& BIT +" 02/'2!+" $!4! +" "//4 $5!, "!.+ 277 '0 $-! CHANNELS 6$$! 633! 0!;= %%02/- 32!- + !(" &MAX -(Z ! $ #,+ /%. 7%. 7! )4. %"!2 ,"! 2 ",. %% OBL )NTERFACE F MAX -(Z -05 6/,4 2%' )BUS - #05 "US-ATRIX -3 .*4234 *4$) *4#+37#,+ *4-337$!4 *4$/ AS !& 6$$ 0/7%2 6$$#/2% 4RACE #ONTROLLER %4- PBUS BIT $!# $!#?/54 AS !& BIT $!# $!#?/54 AS !& )& ))& & -36 13/141 Functional overview STM32L151xD STM32L152xD 1. Legend: AF: alternate function ADC: analog-to-digital converter BOR: brown out reset DMA: direct memory access DAC: digital-to-analog converter IC: inter-integrated circuit multimaster interface 3.1 Low power modes The ultra-low-power STM32L15xxD supports dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system's maximum operating frequency and the external voltage supply. There are three power consumption ranges: Range 1 (VDD range limited to 2.0V-3.6V), with the CPU running at up to 32 MHz Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated only with the multispeed internal RC oscillator clock source) Seven low power modes are provided to achieve the best compromise between low power consumption, short startup time and available wakeup sources: Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at 16 MHz is about 1 mA with all peripherals off. Low power run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the minimum clock (131 kHz), execution from SRAM or Flash memory, and internal regulator in low power mode to minimize the regulator's operating current. In Low power run mode, the clock frequency and the number of enabled peripherals are both limited. Low power sleep mode This mode is achieved by entering Sleep mode with the internal voltage regulator in Low power mode to minimize the regulator's operating current. In Low power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. 14/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode. Doc ID 022027 Rev 5 15/141 Functional overview Table 3. STM32L151xD STM32L152xD Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range I/O operation VDD = 1.65 to 1.8 V Not functional Not functional Range 2 or range 3 Degraded speed performance VDD = 1.8 to 2.0 V Conversion time Not functional up to 500 Ksps Range 2 or range 3 Degraded speed performance VDD = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(1) Range 1, range 2 or range 3 Full speed operation VDD = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(1) Range 1, range 2 or range 3 Full speed operation 1. To be USB compliant from the IO voltage standpoint, the minimum VDD is 3.0 V. Table 4. 16/141 CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 3 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 5. Functional overview Functionalities depending on the working mode (from Run/active down to standby) Standby Run/Active Sleep CPU Y -- Y -- -- -- Flash Y Y Y N -- -- RAM Y Y Y Y Y -- Backup Registers Y Y Y Y Y Y EEPROM Y -- Y Y Y -- Brown-out rest (BOR) Y Y Y Y Y DMA Y Y Y Y -- Programable Voltage Detector (PVD) Y Y Y Y Y Y Y Power On Reset (POR) Y Y Y Y Y Y Y Power Down Rest (PDR) Y Y Y Y Y Y High Speed Internal (HSI) Y Y -- -- -- -- High Speed External (HSE) Y Y -- -- -- -- Low Speed Internal (LSI) Y Y Y Y Y -- Low Speed External (LSE) Y Y Y Y Y -- Multi-Speed Internal (MSI) Y Y Y Y -- -- Inter-Connect Controler Y Y Y Y -- -- RTC Y Y Y Y Y Y Y RTC Tamper Y Y Y Y Y Y Y Y Auto WakeUp (AWU) Y Y Y Y Y Y Y Y LCD Y Y Y Y Y USB Y Y -- -- -- Y -- Y (1) -- Ips Lowpower Sleep Stop Lowpower Run USART Y Y Y Y SPI Y Y Y Y I2C Y Y Y Y Doc ID 022027 Rev 5 Wakeup capability Y Wakeup capability Y -- -- -(1) -- 17/141 Functional overview Table 5. STM32L151xD STM32L152xD Functionalities depending on the working mode (from Run/active down to standby) (continued) Standby Run/Active Sleep ADC Y Y -- -- -- -- DAC Y Y Y Y Y -- Tempsensor Y Y Y Y Y -- OP amp Y Y -- -- Comparators Y Y Y Y Y 16-bit and 32-bit Timers Y Y Y Y -- -- Touch sensing Y Y -- -- -- -- Systic Timer Y Y Y Y GPIOs Y Y Y Y 0 s 0.36 s 3 s 32 s Ips Wakeup time to Run mode Consumption VDD=1.8V to 3.6V (Typ) Down to 238 A/MHz (from Flash) Down to 55 A/MHz (from Flash) Down to 11 A Lowpower Sleep Stop Lowpower Run Down to 4.4 A Wakeup capability Wakeup capability -Y -- -Y Y 3Pins < 8 s 50 s 0.65 A (No RTC) VDD=1.8V 0.35 A (No RTC) VDD=1.8V 1.5 A (with RTC) VDD=1.8V 1 A (with RTC) VDD=1.8V 0.65A (No RTC) VDD=3.0V 0.35 A (No RTC) VDD=3.0V 1.7 A (with RTC) VDD=3.0V 1.3 A (with RTC) VDD=3.0V 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. 3.2 ARM(R) CortexTM-M3 core with MPU The ARM CortexTM-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM CortexTM-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L15xxD is compatible with all ARM tools and software. 18/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L15xxD embeds a nested vectored interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16 interrupt lines of CortexTM-M3) and 16 priority levels. Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving, higher-priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 Reset and supply management 3.3.1 Power supply schemes 3.3.2 VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. The device exists in two versions: The version with BOR activated at power-on operates between 1.8 V and 3.6 V. The other version without BOR operates between 1.65 V and 3.6 V. After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes 1.65 V (whatever the version, BOR active or not, at power-on). When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits the POR area. Doc ID 022027 Rev 5 19/141 Functional overview STM32L151xD STM32L152xD Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. 3.3.4 MR is used in Run mode (nominal regulation) LPR is used in the Low power run, Low power sleep and Stop modes Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Boot modes At startup, boot pins are used to select one of three boot options: Boot from Flash memory Boot from System memory Boot from embedded RAM The boot from Flash usually boots at the beginning of the Flash (bank 1). An additional boot mechanism is available through user option byte, to allow booting from bank 2 when bank 2 contains valid code. This dual boot capability can be used to easily implement a secure field software update mechanism. The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1, USART2 or USB. See STM32TM microcontroller system memory boot mode AN2606 for details. 20/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 3.4 Functional overview Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. It features: Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. System clock source: three different clock sources can be used to drive the master clock SYSCLK: - 1-24 MHz high-speed external crystal (HSE), that can supply a PLL - 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL - Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a 0.5% accuracy. Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: - 32.768 kHz low-speed external crystal (LSE) - 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. Doc ID 022027 Rev 5 21/141 Functional overview STM32L151xD STM32L152xD Figure 2. Clock tree 3TANDBY SUPPLIED VOLTAGE DOMAIN ENABLE 7ATCHDOG ,3) 2# 7ATCHDOG ,3 ,3) TEMPO 24# ENABLE 24# ,3% /3# ,3% TEMPO ,3 ,3 ,3 ,3 6$$#/2% -(Z ,#$ ENABLE 6 -3) 2# LEVEL SHIFTERS 6$$#/2% #+?!$# !$# ENABLE CK?LSI CK?LSE #+?,#$ -#/ NOT DEEPSLEEP #+?072 6 NOT DEEPSLEEP (3) 2# NOT SLEEP OR DEEPSLEEP LEVEL SHIFTERS 6$$#/2% 3YSTEM CLOCK 6 (3% /3# CK?MSI CK?HSI CK?HSE LEVEL SHIFTERS 6$$#/2% CK?PLLIN ,3 6 -(Z CLOCK DETECTOR NOT SLEEP OR DEEPSLEEP !(" PRESCALER 6 CK?PLL 0,, 8 #+?&#,+ #+?#05 #+?4)-393 !0" !0" PRESCALER PRESCALER ,3 #+?53" (3% PRESENT OR NOT LEVEL SHIFTERS 6$$#/2% #LOCK SOURCE CONTROL USBEN AND NOT DEEPSLEEP CK?USB 6CO 6CO MUST BE AT -(Z #+?4)-4'/ #+?!0" #+?!0" TIMEREN AND NOT DEEPSLEEP APB PERIPHEN AND NOT DEEPSLEEP IF !0" PRESC X X ELSE APB PERIPHEN AND NOT DEEPSLEEP -36 1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 24 MHz or 32 MHz. 22/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 3.5 Functional overview Low power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 s to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable powerline. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronisation. A time stamp can record an external event occurrence, and generates an interrupt. There are thirty-two 32-bit backup registers provided to store 128 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB, comparator events or capacitive sensing acquisition. Doc ID 022027 Rev 5 23/141 Functional overview 3.7 STM32L151xD STM32L152xD Memories The STM32L15xxD devices have the following features: 48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). The non-volatile memory is divided into three arrays: - 384 Kbytes of embedded Flash program memory - 12 Kbytes of data EEPROM - Options bytes Flash program and data EEPROM are divided into two banks, this enables writing in one bank while running code or reading data in the other bank. The options bytes are used to write-protect the memory (with 4 KB granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 FSMC (flexible static memory controller) The FSMC supports the following modes: SRAM, PSRAM, NOR Flash. Functionality overview: 3.9 Up to 26 bit address bus Up to 16-bit data bus Write FIFO Burst mode Code execution from external memory Four chip select signals Up to 32 MHz external access DMA (direct memory access) The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, SDIO, general-purpose timers, DAC and ADC. 24/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 3.10 Functional overview LCD (liquid crystal display) The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels. 3.11 Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD Supports static, 1/2, 1/3, 1/4 and 1/8 duty Supports static, 1/2, 1/3 and 1/4 bias Phase inversion to reduce power consumption and EMI Up to 8 pixels can be programmed to blink Unneeded segments and common pins can be used as general I/O pins LCD RAM can be updated at any time owing to a double-buffer The LCD controller can operate in Stop mode ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L15xxD devices with up to 40 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs with up to 29 external channel in a group. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC's runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. 3.11.1 Temperature sensor The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. Doc ID 022027 Rev 5 25/141 Functional overview STM32L151xD STM32L152xD To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. Table 6. Temperature sensor calibration values Calibration value name 3.11.2 Description Memory address TSENSE_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3 V 0x1FF8 00FA - 0x1FF8 00FB TSENSE_CAL2 TS ADC raw data acquired at temperature of 110 C VDDA= 3 V 0x1FF8 00FE - 0x1FF8 00FF Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available for ADC). The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in readonly mode. Table 7. Internal voltage reference measured values Calibration value name VREFINT_CAL 3.12 Description Raw data acquired at temperature of 30 C VDDA= 3 V Memory address 0x1FF8 00F8 - 0x1FF8 00F9 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: 26/141 Two DAC converters: one for each output channel Up to 10-bit output Left or right data alignment in 12-bit mode Synchronized update capability Noise-wave generation Triangular-wave generation Dual DAC channels, independent or simultaneous conversions DMA capability for each channel (including the underrun interrupt) External triggers for conversion Input reference voltage VREF+ Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview Eight DAC trigger inputs are used in the STM32L15xxD. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.13 Operational amplifier The STM32L15xxD embeds three operational amplifiers with external or internal follower routing capability (or even amplifier and filter capability with external components). When one operational amplifier is selected, one external ADC channel is used to enable output measurement. The operational amplifiers feature: 3.14 Low input bias current Low offset voltage Low power mode Rail-to-rail input Ultra-low-power comparators and reference voltage The STM32L15xxD embeds two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). One comparator with fixed threshold One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: - DAC output - External I/O - Internal reference voltage (VREFINT) or a submultiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low power / low current output buffer (driving current capability of 1 A typical). 3.15 System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I/O ports. The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage VREFINT. 3.16 Touch sensing The STM32L15xxD devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 34 capacitive sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive sensing acquisition modes are supported. Doc ID 022027 Rev 5 27/141 Functional overview STM32L151xD STM32L152xD Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. The capacitive sensing acquisition only requires few external components to operate. Reliable touch sensing functionality can be quickly and easily implemented using the free STM32L1xx STMTouch touch sensing firmware library. 3.17 Timers and watchdogs The ultra-low-power STM32L15xxD devices include seven general-purpose timers, two basic timers, and two watchdog timers. Table 8 compares the features of the general-purpose and basic timers. Table 8. Timer feature comparison Timer Counter resolution Counter type Prescaler factor TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM5 32-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No 3.17.1 DMA request Capture/compare Complementary generation channels outputs General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11) There are seven synchronizable general-purpose timers embedded in the STM32L15xxD devices (see Table 8 for differences). TIM2, TIM3, TIM4, TIM5 TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures/output compares/PWMs on the largest packages. TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. 28/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.17.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.17.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.17.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.17.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.18 Communication interfaces 3.18.1 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. Doc ID 022027 Rev 5 29/141 Functional overview 3.18.2 STM32L151xD STM32L152xD Universal synchronous/asynchronous receiver transmitter (USART) The three USART and two UART interfaces are able to communicate at speeds of up to 4 Mbit/s. They support IrDA SIR ENDEC, are ISO 7816 compliant and have LIN Master/Slave capability. The three USARTs provide hardware management of the CTS and RTS signals. All USART/UART interfaces can be served by the DMA controller. 3.18.3 Serial peripheral interface (SPI) Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPIs can be served by the DMA controller. 3.18.4 Inter-integrated sound (I2S) Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the I2S interfaces is/are configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. The I2Ss can be served by the DMA controller. 3.18.5 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 24 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.18.6 Universal serial bus (USB) The STM32L15xxD embeds a USB device peripheral compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 30/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Functional overview 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.19 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.20 Development support Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. Embedded Trace MacrocellTM The ARM(R) Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L15xxD through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. Doc ID 022027 Rev 5 31/141 Pin descriptions STM32L151xD STM32L152xD Pin descriptions Figure 3. STM32L15xZD LQFP144 pinout 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 4 ,1&0 6$$? 633? 0( 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0& 0& 0% 0% 0% 0% 0% 7+50 6,#$ 0# 7+50 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7+50 0! 0! -36 32/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Figure 4. Pin descriptions STM32L15xQD BGA132 ballout ! 0% 0% 0" "//4 0$ 0$ 0" 0" " 0% 0% 0" 0" 0" 0$ 0$ 0% 0% 6$$? 0" 0' 0& 0& 0! 0! 0! 0! 0$ 0$ 0# 0# 0! 0' 0$ 0$ 0# 0( 0! 0' 0' 0' 0! 0! 0# 0' 0# 0# 0# # 0# 7+50 $ 0# 0% /3# 7+50 ?). 633? 0& % 0# /3# ?/54 6,#$ 633? 0& & 0( /3#?). 633? 0& 0& 633? 633? 0' 0' 633? 633? ' 0( /3#? /54 6$$? 0& 0& 6$$? 6$$? 0' 0' 6$$? 6$$? 6$$? 0& 0' 0$ 0$ 0$ ( 0# .234 * 633! 0# 0# 0! 0! 0& 0& 0& 0& 0$ 0$ 0$ + /0!-0 ?6).- 0# 0! 0! 0# 0& 0& 0$ 0$ 0" 0" 0" , 62%& 0! 7+50 0! 0! 0# 0" 0% 0% 0% 0" 0" 0" - 6$$! 0! 0" 0" 0% 0% 0% 0% 0% 0% /0!-0 /0!-0 ?6).- ?6).- -36 1. This figure shows the package top view. Doc ID 022027 Rev 5 33/141 Pin descriptions STM32L15xVD LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 5. STM32L151xD STM32L152xD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LQFP100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDD_2 VSS_2 PH2 PA 13 PA 12 PA 11 PA 10 PA 9 PA 8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PB10 PB11 VSS_1 VDD_1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PE2 PE3 PE4 PE5 PE6-WKUP3 VLCD PC13-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT VSS_5 VDD_5 PH0-OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VREFVREF+ VDDA PA0-WKUP1 PA1 PA2 34/141 Doc ID 022027 Rev 5 ai15692c STM32L151xD STM32L152xD VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 STM32L15xRD LQFP64 pinout VLCD PC13-WKUP2 PC14-OSC32_IN PC15-OSC32_OUT PH0 -OSC_IN PH1-OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP1 PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_ 2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 Figure 6. Pin descriptions ai15693c Doc ID 022027 Rev 5 35/141 Pin descriptions Figure 7. STM32L151xD STM32L152xD STM32L15xRD WLCSP64 ballout ! 6$$? 0# 0$ 0" 0" "//4 633? " 633? 0! 0# 0" 0" 0" # 0! 0! 0! 0# 0" 6,#$ 0# 0! 0! 0! 0" 0# 0# 0# 0# 0! 0! 0! 633! 0# 0" 0" 0" 0" 633? 0! 7+50 0# 0# 0" 0" 0" 0! 0! 6$$? 0! 6$$! 6$$? 633? 0" 0" 0# 0# 0! 0! $ % & ' ( 6$$? 0# /3#?). 0# /3#?/54 .234 0# 7+50 0( 0( /3#?/54 /3#?). -36 1. This figure shows the package top view. 36/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD STM32L15xxD pin definitions LQFP100 LQFP64 WLCSP64 Alternate functions UFBGA132 Main function(3) (after reset) LQFP144 Type(1) Pins I / O Level(2) Table 9. Pin descriptions 1 B2 1 - - PE2 I/O FT PE2 TIM3_ETR/LCD_SEG38/FSMC_A23/TRACECLK 2 A1 2 - - PE3 I/O FT PE3 TIM3_CH1/LCD_SEG39/FSMC_A19/TRACED0 3 B1 3 - - PE4 I/O FT PE4 TIM3_CH2/FSMC_A20/TRACED1 4 C2 4 - - PE5 I/O FT PE5 TIM9_CH1/FSMC_A21/TRACED2 5 D2 5 - - PE6WKUP3 I/O FT PE6 WKUP3/RTC_TAMP3/TIM9_CH2/TRACED3 6 E2 6 1 C6 7 C1 7 2 C8 PC13-WKUP2 I/O FT PC13 WKUP2/RTC_TAMP1/RTC_TS/RTC_OUT 8 D1 8 3 B8 PC14OSC32_IN(5) I/O PC14 OSC32_IN 9 E1 9 4 B7 PC15I/O OSC32_OUT PC15 OSC32_OUT 10 D6 - - - PF0 I/O FT PF0 FSMC_A0 11 D5 - - - PF1 I/O FT PF1 FSMC_A1 12 D4 - - - PF2 I/O FT PF2 FSMC_A2 13 E4 - - - PF3 I/O FT PF3 FSMC_A3 14 F3 - - - PF4 I/O FT PF4 FSMC_A4 15 F4 - - - PF5 I/O FT PF5 FSMC_A5 16 F2 10 - - VSS_5 S VSS_5 17 G2 11 - - VDD_5 S VDD_5 Pin name VLCD(4) S VLCD 18 G3 - - - PF6 I/O FT PF6 TIM5_CH1/TIM5_ETR/ADC_IN27 19 G4 - - - PF7 I/O FT PF7 TIM5_CH2/ADC_IN28/COMP1_INP 20 H4 - - - PF8 I/O FT PF8 TIM5_CH3/ADC_IN29/COMP1_INP 21 - - - PF9 I/O FT PF9 TIM5_CH4/ADC_IN30/COMP1_INP - - - PF10 I/O FT PF10 ADC_IN30/COMP1_INP PH0 OSC_IN OSC_OUT J6 22 - 23 F1 12 5 D8 PH0-OSC_IN(6) I 24 G1 13 6 D7 PH1OSC_OUT(6) O PH1 25 H2 14 7 C7 NRST I/O NRST 26 H1 15 8 E8 PC0 I/O FT PC0 LCD_SEG18/ADC_IN10/COMP1_INP 27 16 9 F8 PC1 I/O FT PC1 LCD_SEG19/ADC_IN11/COMP1_INP /OPAMP3_VINP 17 10 D6 PC2 I/O FT PC2 LCD_SEG20/ADC_IN12/COMP1_INP /OPAMP3_VINM PC2 I/O FT PC2 LCD_SEG20/ADC_IN12/COMP1_INP J2 28 J3 - K1 - OPAMP3_VINM I OPAMP3 _VINM Doc ID 022027 Rev 5 37/141 Pin descriptions STM32L15xxD pin definitions (continued) Alternate functions LCD_SEG21/ADC_IN13/COMP1_INP /OPAMP3_VOUT PC3 I/O PC3 30 J1 19 12 E7 VSSA S VSSA 31 - 20 - - VREF- S VREF- 32 L1 21 - - VREF+ S VREF+ VDDA S VDDA WLCSP64 K2 18 11 F7 LQFP64 29 LQFP100 UFBGA132 Main function(3) (after reset) LQFP144 Pin name Type(1) Pins I / O Level(2) Table 9. STM32L151xD STM32L152xD 33 M1 22 13 G8 PA0-WKUP1 I/O FT PA0 WKUP1/RTC_TAMP2/TIM2_CH1_ETR/TIM5_CH1/ USART2_CTS/ADC_IN0/COMP1_INP 35 M2 24 15 E6 PA1 I/O FT PA1 TIM2_CH2/TIM5_CH2/ USART2_RTS/LCD_SEG0/ ADC_IN1/COMP1_INP/OPAMP1_VINP 36 PA2 I/O FT PA2 TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/ LCD_SEG1/ADC_IN2/ COMP1_INP/OPAMP1_VINM PA2 I/O FT PA2 TIM2_CH3/TIM5_CH3/TIM9_CH1/USART2_TX/ LCD_SEG1/ADC_IN2/COMP1_INP 34 L2 23 14 F6 25 16 H8 K3 - M3 - OPAMP1_VINM I OPAMP1_ VINM TIM2_CH4/TIM5_CH4/TIM9_CH2/USART2_RX/ LCD_SEG2/ ADC_IN3/COMP1_INP/OPAMP1_VOUT 37 L3 26 17 G7 PA3 I/O PA3 38 - 27 18 F5 VSS_4 S VSS_4 39 - 28 19 G6 VDD_4 S VDD_4 40 J4 29 20 H7 PA4 I/O PA4 SPI1_NSS/SPI3_NSS/I2S3_WS/USART2_CK/ ADC_IN4/DAC_OUT1/COMP1_INP 41 K4 30 21 E5 PA5 I/O PA5 TIM2_CH1_ETR/SPI1_SCK/ADC_IN5/DAC_OUT2/ COMP1_INP 42 L4 31 22 G5 PA6 I/O FT PA6 TIM3_CH1/TIM10_CH1/SPI1_MISO/LCD_SEG3/ ADC_IN6/COMP1_INP/OPAMP2_VINP 32 23 G4 PA7 I/O FT PA7 TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/ ADC_IN7/COMP1_INP/OPAMP2_VINM PA7 I/O FT PA7 TIM3_CH2/TIM11_CH1/ SPI1_MOSI/LCD_SEG4/ ADC_IN7/COMP1_INP 43 J5 - M4 - OPAMP2_VINM I OPAMP2_VI NM 44 K5 33 24 H6 PC4 I/O FT PC4 45 L5 PC5 I/O FT PC5 LCD_SEG23/ADC_IN15/COMP1_INP 34 25 H5 LCD_SEG22/ADC_IN14/COMP1_INP 46 M5 35 26 H4 PB0 I/O PB0 TIM3_CH3/LCD_SEG5/ADC_IN8/COMP1_INP/ VREF_OUT/ OPAMP2_VOUT 47 M6 36 27 F4 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6/ADC_IN9/COMP1_INP/ VREF_OUT PB2 I/O FT PB2/BOOT1 COMP1_INP PB2 I/O FT PB2/BOOT1 ADC_IN0b/COMP1_INP - - 48 L6 38/141 37 28 H3 - - Doc ID 022027 Rev 5 STM32L151xD STM32L152xD STM32L15xxD pin definitions (continued) UFBGA132 LQFP100 LQFP64 WLCSP64 49 K6 - - - Pin name Type(1) LQFP144 Pins I / O Level(2) Table 9. Pin descriptions PF11 I/O FT I/O FT Main function(3) (after reset) Alternate functions PF11 ADC_IN1b/COMP1_INP PF12 ADC_IN2b/COMP1_INP/FSMC_A6 50 J7 - - - PF12 51 E3 - - - VSS_6 S VSS_6 52 H3 - - - VDD_6 S VDD_6 53 K7 - - - PF13 I/O FT PF13 ADC_IN3b/COMP1_INP/FSMC_A7 54 J8 - - - PF14 I/O FT PF14 ADC_IN6b/COMP1_INP/FSMC_A8 55 J9 - - - PF15 I/O FT PF15 ADC_IN7b/COMP1_INP/FSMC_A9 56 H9 - - - PG0 I/O FT PG0 ADC_IN8b/COMP1_INP/FSMC_A10 57 G9 - - - PG1 I/O FT PG1 ADC_IN9b/COMP1_INP/FSMC_A11 58 M7 38 - - PE7 I/O PE7 FSMC_D4/ADC_IN22/COMP1_INP 59 39 - - PE8 I/O PE8 FSMC_D5/ADC_IN23/COMP1_INP 60 M8 - - - PE9 I/O PE9 TIM2_CH1_ETR/FSMC_D6/ ADC_IN24/COMP1_INP 61 - - - VSS_7 S VSS_7 L7 - 62 - - - - VDD_7 S VDD_7 63 L8 41 - - PE10 I/O PE10 TIM2_CH2/ FSMC_D7/ADC_IN25/COMP1_INP 64 M9 42 - - PE11 I/O FT PE11 TIM2_CH3/FSMC_D8 65 - - PE12 I/O FT PE12 TIM2_CH4/SPI1_NSS/FSMC_D9 L9 43 66 M10 44 - - PE13 I/O FT PE13 SPI1_SCK/FSMC_D10 67 M11 45 - - PE14 I/O FT PE14 SPI1_MISO/FSMC_D11 68 M12 46 - - PE15 I/O FT PE15 SPI1_MOSI/FSMC_D12 PB10 I/O FT PB10 TIM2_CH3/I2C2_SCL/USART3_TX/LCD_SEG10 70 L11 48 30 F3 PB11 I/O FT PB11 TIM2_CH4/I2C2_SDA/ USART3_RX/LCD_SEG11 71 F12 49 31 H2 VSS_1 S VSS_1 72 G12 50 32 H1 VDD_1 S VDD_1 73 L12 51 33 G2 PB12 I/O FT PB12 TIM10_CH1/I2C2_SMBA/SPI2_NSS/I2S2_WS/ USART3_CK/ LCD_SEG12/ADC_IN18/COMP1_INP 74 K12 52 34 G1 PB13 I/O FT PB13 TIM9_CH1/SPI2_SCK/ I2S2_CK/ USART3_CTS/ LCD_SEG13/ADC_IN19/COMP1_INP 75 K11 53 35 F2 PB14 I/O FT PB14 TIM9_CH2/SPI2_MISO/ USART3_RTS/LCD_SEG14/ ADC_IN20/COMP1_INP 76 K10 54 36 F1 PB15 I/O FT PB15 TIM11_CH1/SPI2_MOSI/I2S2_SD/LCD_SEG15/ ADC_IN21/COMP1_INP/RTC_REFIN 77 K9 55 PD8 I/O FT PD8 USART3_TX/LCD_SEG28/FSMC_D13 78 69 L10 47 29 G3 - - K8 56 - - PD9 I/O FT PD9 USART3_RX/LCD_SEG29/FSMC_D14 79 J12 57 - - PD10 I/O FT PD10 USART3_CK/LCD_SEG30/FSMC_D15 80 J11 58 - - PD11 I/O FT PD11 USART3_CTS/LCD_SEG31/FSMC_A16 81 J10 59 - - PD12 I/O FT PD12 TIM4_CH1 / USART3_RTS/LCD_SEG32/FSMC_A17 Doc ID 022027 Rev 5 39/141 Pin descriptions STM32L15xxD pin definitions (continued) Type(1) Alternate functions PD13 TIM4_CH2/LCD_SEG33/FSMC_A18 - - 83 - - - - VSS_8 S VSS_8 84 - - - - VDD_8 S VDD_8 85 H11 61 - - PD14 I/O FT PD14 TIM4_CH3/LCD_SEG34/FSMC_D0 86 H10 62 - - PD15 I/O FT PD15 TIM4_CH4/LCD_SEG35/FSMC_D1 LQFP100 82 H12 60 LQFP144 WLCSP64 Main function(3) (after reset) LQFP64 UFBGA132 Pins I / O Level(2) Table 9. STM32L151xD STM32L152xD Pin name PD13 I/O FT 87 G10 - - - PG2 I/O FT PG2 FSMC_A12/ADC_IN10b/COMP1_INP 88 F9 - - - PG3 I/O FT PG3 FSMC_A13/ADC_IN11b/COMP1_INP 89 F10 - - - PG4 I/O FT PG4 FSMC_A14/ADC_IN12b/COMP1_INP 90 E9 - - - PG5 I/O FT PG5 FSMC_A15 91 - - - - PG6 I/O FT PG6 92 - - - - PG7 I/O FT PG7 93 - - - - PG8 I/O FT PG8 94 F6 - - - VSS_9 95 G6 - - - VDD_9 S VSS_9 S VDD_9 96 E12 63 37 E1 PC6 I/O FT PC6 TIM3_CH1/I2S2_MCK/LCD_SEG24/SDIO_D6 97 E11 64 38 E2 PC7 I/O FT PC7 TIM3_CH2/I2S3_MCK/LCD_SEG25/SDIO_D7 98 E10 65 39 E3 PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26/SDIO_D0 99 D12 66 40 D1 PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27/SDIO_D1 100 D11 67 41 E4 PA8 I/O FT PA8 USART1_CK/MCO/LCD_COM0 101 D10 68 42 D2 PA9 I/O FT PA9 USART1_TX / LCD_COM1 102 C12 69 43 D3 PA10 I/O FT PA10 USART1_RX / LCD_COM2 103 B12 70 44 C1 PA11 I/O FT PA11 USART1_CTS/ USB_DM/SPI1_MISO 104 A12 71 45 C2 PA12 I/O FT PA12 USART1_RTS/USB_DP/SPI1_MOSI 105 A11 72 46 D4 PA13 I/O FT JTMSSWDAT PH2 I/O FT 106 C11 73 - - PH2 FSMC_A22 107 F11 74 47 B1 VSS_2 S VSS_2 108 G11 75 48 A1 VDD_2 S VDD_2 109 A10 76 49 B2 PA14 I/O FT JTCKSWCLK 110 A9 77 50 C3 PA15 I/O FT JTDI TIM2_CH1_ETR/ SPI1_NSS/SPI3_NSS/ I2S3_WS/LCD_SEG17 111 B11 78 51 A2 PC10 I/O FT PC10 SPI3_SCK/I2S3_CK/USART3_TX/ UART4_TX/ LCD_SEG28/LCD_SEG40/LCD_COM4/SDIO_D2 112 C10 79 52 B3 PC11 I/O FT PC11 SPI3_MISO/USART3_RX/UART4_RX/ LCD_SEG29/LCD_SEG41/LCD_COM5/SDIO_D3 113 B10 80 53 C4 PC12 I/O FT PC12 SPI3_MOSI/I2S3_SD/USART3_CK/ UART5_TX/ LCD_SEG30/ LCD_SEG42/LCD_COM6/SDIO_CK 40/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD STM32L15xxD pin definitions (continued) Type(1) Alternate functions TIM9_CH1/SPI2_NSS/I2S2_WS/ FSMC_D2 - - PD0 I/O FT PD0 115 B9 82 - - PD1 I/O FT PD1 SPI2_SCK/I2S2_CK/FSMC_D3 LQFP100 114 C9 81 LQFP144 WLCSP64 Main function(3) (after reset) LQFP64 UFBGA132 Pins I / O Level(2) Table 9. Pin descriptions Pin name 116 C8 83 54 A3 PD2 I/O FT PD2 TIM3_ETR/UART5_RX/LCD_SEG31/LCD_SEG43/ LCD_COM7/SDIO_CMD 117 B8 84 - - PD3 I/O FT PD3 SPI2_MISO/USART2_CTS/FSMC_CLK 118 B7 85 - - PD4 I/O FT PD4 SPI2_MOSI/I2S2_SD/USART2_RTS/FSMC_NOE 119 A6 86 - - PD5 I/O FT PD5 USART2_TX/FSMC_NWE 120 F7 - - - VSS_10 S VSS_10 121 G7 - - - VDD_10 S VDD_10 122 B6 87 - - PD6 I/O FT PD6 USART2_RX/FSMC_NWAIT 123 A5 88 - - PD7 I/O FT PD7 TIM9_CH2/USART2_CK/FSMC_NE1 124 D9 - - - PG9 I/O FT PG9 FSMC_NE2 125 D8 - - - PG10 I/O FT PG10 FSMC_NE3 126 - - - PG11 I/O FT PG11 127 D7 - - - - PG12 I/O FT PG12 FSMC_NE4 128 C7 - - - PG13 I/O FT PG13 FSMC_A24 129 C6 - - - PG14 I/O FT PG14 FSMC_A25 130 - - - - VSS_11 S VSS_11 131 - - - - VDD_11 S VDD_11 132 - - - - PG15 I/O FT PG15 133 A8 89 55 A4 PB3 I/O FT JTDO TIM2_CH2/SPI1_SCK/SPI3_SCK/ I2S3_CK/ LCD_SEG7/COMP2_INM 134 A7 90 56 B4 PB4 I/O FT NJTRST TIM3_CH1/ SPI1_MISO/SPI3_MISO/LCD_SEG8/ COMP2_INP 135 C5 91 57 A5 PB5 I/O FT PB5 TIM3_CH2 /I2C1_SMBA/SPI1_MOSI/SPI3_MOSI/ I2S3_SD/LCD_SEG9/COMP2_INP 136 B5 92 58 B5 PB6 I/O FT PB6 TIM4_CH1/I2C1_SCL/USART1_TX/COMP2_INP 137 B4 93 59 C5 PB7 I/O FT PB7 TIM4_CH2/I2C1_SDA/USART1_RX/PVD_IN/ FSMC_NADV/ COMP2_INP 138 A4 94 60 A6 BOOT0 139 A3 95 61 D5 PB8 I/O FT PB8 TIM4_CH3/TIM10_CH1/I2C1_SCL/LCD_SEG16/ SDIO_D4 140 B3 96 62 B6 PB9 I/O FT PB9 TIM4_CH4/ TIM11_CH1/I2C1_SDA/LCD_COM3/ SDIO_D5 141 C3 97 - - PE0 I/O FT PE0 TIM4_ETR/TIM10_CH1/LCD_SEG36 /FSMC_NBL0 142 A2 98 - - PE1 I/O FT PE1 TIM11_CH1/LCD_SEG37/FSMC_NBL1 I BOOT0 143 D3 99 63 A7 VSS_3 S VSS_3 144 C4 100 64 A8 VDD_3 S VDD_3 Doc ID 022027 Rev 5 41/141 Pin descriptions STM32L151xD STM32L152xD 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. Applicable to STM32L152xD devices only. In STM32L151xD devices, this pin should be connected to VDD. 5. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038). 6. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO function. 42/141 Doc ID 022027 Rev 5 Alternate function input/output Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM BOOT0 BOOT0 NRST NRST TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 LCD FSMC/ SDIO EVENT OUT Doc ID 022027 Rev 5 COMP1_INP/ TIMx_IC1_0/ G1IO1 EVENT OUT SEG0 COMP1_INP/ TIMx_IC2_0 G1IO2 EVENT OUT USART2_TX SEG1 COMP1_INP/ TIMx_IC3_0/ G1IO3 EVENT OUT USART2_RX SEG2 COMP1_INP/ TIMx_IC4_0/ G1IO4 EVENT OUT COMP1_INP/ TIMx_IC1_1 EVENT OUT COMP1_INP/ TIMx_IC2_1 EVENT OUT PA0WKUP1/ WKUP1 TAMPER2 TIM2_CH1_ ETR TIM5_CH1 USART2_CTS PA1 TIM2_CH2 TIM5_CH2 USART2_RTS PA2 TIM2_CH3 TIM5_CH3 TIM9_CH1 PA3 TIM2_CH4 TIM5_CH4 TIM9_CH2 PA4 SPI1_NSS PA5 USB TIM2_CH1_ETR SPI3_NSS USART2_CK I2S3_WS SPI1_SCK TIM3_CH1 TIM10_ CH1 SPI1_MISO SEG3 COMP1_INP/ TIMx_IC3_1 G2IO1 EVENT OUT PA7 TIM3_CH2 TIM11_ CH1 SPI1_MOSI SEG4 COMP1_INP/ TIMx_IC4_1/ G2IO2 EVENT OUT USART1_CK COM0 TIMx_IC1_2/ G4IO1 EVENT OUT PA9 USART1_TX COM1 TIMx_IC2_2/ G4IO2 EVENT OUT PA10 USART1_RX COM2 TIMx_IC3_2/ G4IO3 EVENT OUT PA8 MCO 43/141 Pin descriptions PA6 STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO PA11 SPI1_MISO USART1_CTS USBDM TIMx_IC4_2/ G4IO4 EVENT OUT PA12 SPI1_MOSI USART1_RTS USBDP TIMx_IC1_3/ EVENT OUT Doc ID 022027 Rev 5 PA13 JTMS-SWDIO TIMx_IC2_3/ G5IO1 EVENT OUT PA14 JTCK-SWCLK TIMx_IC3_3/ G5IO2 EVEN TOUT PA15 JTDI SEG17 TIMx_IC4_3/ G5IO3 EVEN TOUT TIM2_CH1_ETR SPI1_NSS SPI3_NSS I2S3_WS PB0 TIM3_CH3 SEG5 COMP1_INP/ G3IO1 EVEN TOUT PB1 TIM3_CH4 SEG6 COMP1_INP/ G3IO2 EVENT OUT COMP1_INP/ G3IO3 EVENT OUT BOOT1 PB3 JTDO PB4 JTRST TIM2_CH2 SPI1_SCK TIM3_CH1 SPI3_SCK I2S3_CK EVENT OUT SEG7 SPI1_MISO SPI3_MISO SEG8 G6IO1 EVENT OUT SPI3_MOSI I2S3_SD SEG9 G6IO2 EVENT OUT G6IO3 EVENT OUT G6IO4 EVENT OUT PB5 TIM3_CH2 I2C1_ SMBA PB6 TIM4_CH1 I2C1_SCL USART1_TX PB7 TIM4_CH2 I2C1_SDA USART1_RX PB8 TIM4_CH3 TIM10_ CH1 I2C1_SCL SEG16 SDIO_D4 EVENT OUT PB9 TIM4_CH4 TIM11_ CH1 I2C1_SDA COM3 SDIO_D5 EVENT OUT SPI1_MOSI NADV STM32L151xD STM32L152xD PB2 Pin descriptions 44/ Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO PB10 TIM2_CH3 I2C2_SCL USART3_TX SEG10 EVENT OUT PB11 TIM2_CH4 I2C2_SDA USART3_RX SEG11 EVENT OUT SPI2_NSS I2S2_WS USART3_CK SEG12 COMP1_INP/ G7IO1 EVENT OUT Doc ID 022027 Rev 5 TIM10_ CH1 PB13 TIM9_ CH1 SPI2_SCK I2S2_CK USART3_CTS SEG13 COMP1_INP/ G7IO2 EVENT OUT PB14 TIM9_ CH2 SPI2_MISO USART3_RTS SEG14 COMP1_INP/ G7IO3 EVENT OUT TIM11_ CH1 SPI2_MOSI I2S2_SD SEG15 COMP1_INP/ G7IO4 EVENT OUT PC0 SEG18 COMP1_INP/ TIMx_IC1_4/ G8IO1 EVENT OUT PC1 SEG19 COMP1_INP/ TIMx_IC2_4/ G8IO2 EVENT OUT PC2 SEG20 COMP1_INP/ TIMx_IC3_4/ G8IO3 EVENT OUT PC3 SEG21 COMP1_INP/ TIMx_IC4_4/ G8IO4 EVENT OUT PC4 SEG22 COMP1_INP/ TIMx_IC1_5/ G9IO1 EVENT OUT PC5 SEG23 COMP1_INP/ TIMx_IC2_5/ G9IO2 EVENT OUT TIMx_IC3_5/ G10IO1 EVENT OUT PB15 PC6 RTC_REFIN TIM3_CH1 I2C2_SMBA I2S2_MCK SEG24 SDIO_D6 Pin descriptions 45/141 PB12 STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 FSMC/ SDIO CPRI SYSTEM SEG25 SDIO_D7 TIMx_IC4_5/ G10IO2 EVENT OUT Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 I2S3_MCK USB LCD PC7 TIM3_CH2 PC8 TIM3_CH3 SEG26 SDIO_D0 TIMx_IC1_6/ G10IO3 EVENT OUT PC9 TIM3_CH4 SEG27 SDIO_D1 TIMx_IC2_6/ G10IO4 EVENT OUT Doc ID 022027 Rev 5 SPI3_SCK USART3_TX I2S3_CK UART4_TX COM4/ SEG28/ SEG40 SDIO_D2 TIMx_IC3_6/ G5IO4 EVENT OUT PC11 SPI3_MISO USART3_RX UART4_RX COM5/ SEG29 /SEG41 SDIO_D3 TIMx_IC4_6 EVENT OUT PC12 SPI3_MOSI USART3_CK I2S3_SD UART5_TX COM6/ SEG30/ SEG42 SDIO_CK TIMx_IC1_7 EVENT OUT WKUP2/ TAMPER1/ PC13TIMESTAMP/ WKUP2 ALARM_OUT/ 512Hz TIMx_IC2_7 EVENT OUT PC14 OSC32_ OSC32_IN IN TIMx_IC3_7 EVENT OUT PC15 OSC32_ OSC32_OUT OUT TIMx_IC4_7 EVENT OUT PD0 TIM9_CH1 PD1 PD2 TIM3_ETR SPI2_NSS I2S2_WS D2 /DA2 TIMx_IC1_8 EVENT OUT SPI2 SCK I2S2_CK D3 /DA3 TIMx_IC2_8 EVENT OUT SDIO_ CMD TIMx_IC3_8 EVENT OUT UART5_RX COM7/ SEG31/ SEG43 STM32L151xD STM32L152xD PC10 Pin descriptions 46/ Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO Doc ID 022027 Rev 5 PD3 SPI2_MISO USART2_CTS CLK TIMx_IC4_8 EVENT OUT PD4 SPI2_MOSI I2S2_SD USART2_RTS NOE TIMx_IC1_9 EVENT OUT PD5 USART2_TX NWE TIMx_IC2_9 EVENT OUT PD6 USART2_RX NWAIT TIMx_IC3_9 EVENT OUT USART2_CK NE1 TIMx_IC4_9 EVENT OUT PD7 TIM9_CH2 PD8 USART3_TX SEG28 D13/DA13 TIMx_IC1_10 EVENT OUT PD9 USART3_RX SEG29 D14/DA14 TIMx_IC2_10 EVENT OUT PD10 USART3_CK SEG30 D15/DA15 TIMx_IC3_10 EVENT OUT PD11 USART3_CTS SEG31 A16 TIMx_IC4_10 EVENT OUT USART3_RTS SEG32 A17 TIMx_IC1_11 EVENT OUT TIM4_CH1 PD13 TIM4_CH2 SEG33 A18 TIMx_IC2_11 EVENT OUT PD14 TIM4_CH3 SEG34 D0/DA0 TIMx_IC3_11 EVENT OUT PD15 TIM4_CH4 SEG35 D1/DA1 TIMx_IC4_11 EVENT OUT PE0 TIM4_ETR TIM10_ CH1 SEG36 NBL0 TIMx_IC1_12 EVENT OUT TIM11_ CH1 SEG37 NBL1 TIMx_IC2_12 EVENT OUT PE1 Pin descriptions 47/141 PD12 STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO Doc ID 022027 Rev 5 PE2 TRACECK TIM3_ETR SEG 38 A23 TIMx_IC3_12 EVENT OUT PE3 TRACED0 TIM3_CH1 SEG 39 A19 TIMx_IC4_12 EVENT OUT PE4 TRACED1 TIM3_CH2 A20 TIMx_IC1_13 EVENT OUT PE5 TRACED2 A21 TIMx_IC2_13 EVENT OUT TIMx_IC3_13 EVENT OUT TIM9_CH1 WKUP3/ PE6TAMPER3 / WKUP3 TRACED3 TIM9_CH2 PE7 D4/DA4 COMP1_INP/ TIMx_IC4_13 EVENT OUT PE8 D5/DA5 COMP1_INP/ TIMx_IC1_14 EVENT OUT TIM2_CH1_ETR D6/DA6 COMP1_INP/ TIMx_IC2_14 EVENT OUT PE10 TIM2_CH2 D7/DA7 COMP1_INP/ TIMx_IC3_14 EVENT OUT PE11 TIM2_CH3 D8/DA8 TIMx_IC4_14 EVENT OUT PE12 TIM2_CH4 SPI1_NSS D9/DA9 TIMx_IC1_15 EVENT OUT PE13 SPI1_SCK D10/DA10 TIMx_IC2_15 EVENT OUT PE14 SPI1_MISO D11/DA11 TIMx_IC3_15 EVENT OUT PE15 SPI1_MOSI D12/DA12 TIMx_IC4_15 EVENT OUT PF0 A0 EVENT OUT STM32L151xD STM32L152xD PE9 Pin descriptions 48/ Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO Doc ID 022027 Rev 5 PF1 A1 EVENT OUT PF2 A2 EVENT OUT PF3 A3 EVENT OUT PF4 A4 EVENT OUT PF5 A5 EVENT OUT PF6 TIM5_ETR COMP1_INP G11IO1 EVENT OUT PF7 TIM5_CH2 COMP1_INP G11IO2 EVENT OUT PF8 TIM5_CH3 COMP1_INP G11IO3 EVENT OUT PF9 TIM5_CH4 COMP1_INP G11IO4 EVENT OUT PF10 COMP1_INP G11IO5 EVENT OUT PF11 COMP1_INP G3IO4 EVENT OUT A6 G3IO5 EVENT OUT PF13 A7 G9IO3 EVENT OUT PF14 A8 G9IO4 EVENT OUT PF15 A9 G2IO3 EVENT OUT Pin descriptions 49/141 PF12 STM32L151xD STM32L152xD Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO Doc ID 022027 Rev 5 PG0 A10 G2IO4 EVENT OUT PG1 A11 G2IO5 EVENT OUT PG2 A12 G7IO5 EVENT OUT PG3 A13 G7IO6 EVENT OUT PG4 A14 G7IO7 EVENT OUT PG5 A15 EVENT OUT PG6 EVENT OUT PG7 EVENT OUT PG8 EVENT OUT NE2 EVENT OUT PG10 NE3 EVENT OUT EVENT OUT PG12 NE4 EVENT OUT PG13 A24 EVENT OUT PG14 A25 EVENT OUT STM32L151xD STM32L152xD PG9 PG11 Pin descriptions 50/ Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 Port name AFIO6 AFIO7 AFIO8 .. AFIO10 AFIO11 AFIO12 .. AFIO14 AFIO15 CPRI SYSTEM Alternate function SYSTEM TIM2 TIM3/4/5 TIM9/ 10/11 I2C1/2 SPI1/2 SPI3 USART1/2/3 UART4/5 USB LCD FSMC/ SDIO EVENT OUT PG15 PH0OSC OSC_IN _IN STM32L151xD STM32L152xD Table 10. PH1OSC OSC_OUT _OUT PH2 A22 Doc ID 022027 Rev 5 Pin descriptions 51/141 Memory mapping 5 STM32L151xD STM32L152xD Memory mapping Figure 8. Memory map X && X $-! $-! X X X # X X &&&& & &&& RESERVED &LASH )NTERF ACE 2## RESERVED X X X% X% #2# RESERVED X X # #ORTEX - )NTERNAL 0ERIPHERALS X X X X # X X X# X X # X 0ORT ' 0ORT & 0ORT ( 0ORT % 0ORT $ 0ORT # 0ORT " 0ORT ! RESERVED 53!24 RESERVED X 30) X! X &3-# REGISTERS X # 3$)/ RESERVED X X !$# RESE RVE D X 4)- X X X && & X && X && & &3-# EXTERNAL MEMORY /PTION "YTES "ANK %84) X && &&& 0ERIPHERALS X X && X X # 3YSTEM RESEMEMORY RVED "ANK X X 3YSTEM MEMORY "ANK #/-0 2) RESERVED X X X X # 393#&' RESERVED RESE RVED 4)- 4)- X X && X && &&& X X RESE RVED X X /PTION "YTES "ANK X # RESERVED X $!# 072 RESERVED BYTE 53" 53" 2EG ISTERS )# )# X X 32!- X X &&& .ON VOLATILE X && MEMORY X $ATA %%02/"ANK $ATA %%02/"ANK 53!24 X X # X &&&& &LASH MEMORY "ANK 2ESERVE D X X !LIASED TO &LASH OR SYSTEM MEMORY DEPENDING ON "//4 PINS RESERVED 30) X 30) X RESERVED X &&&& &LASH MEMORY "ANK 5!24 53!24 X X RESE RVED X X # 5!24 X X # X X X # X )7$' 77$' 24# ,#$ RESERVED 4)- X # 4)- 4)- X 4)- X 4)- X X 4)- -36 52/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.6 V (for the 1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 9. Pin loading conditions Figure 10. Pin input voltage 34-,XXX PIN 34-,XXX PIN # P& 6). AI Doc ID 022027 Rev 5 AI 53/141 Electrical characteristics 6.1.6 STM32L151xD STM32L152xD Power supply scheme Figure 11. Power supply scheme OUT GP I/Os IN Level shifter Standby-power circuitry (OSC32K,RTC, Wake-up logic RTC backup registers) IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD1/2/.../N Regulator N x 100 nF + 1 x 4.7 F VSS1/2/.../N VDD VDDA VREF 10 nF + 1 F 10 nF + 1 F VREF+ ADC VREF- Analog: RCs, PLL, ... VSSA MS18291V2 6.1.7 Current consumption measurement Figure 12. Current consumption measurement scheme IDD VDD VDDA ai14126b 54/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 11. Symbol VDD-VSS VIN(2) Voltage characteristics Ratings Min Max -0.3 4.0 Input voltage on five-volt tolerant pin VSS 0.3 VDD+4.0 Input voltage on any other pin VSS 0.3 4.0 External main supply voltage (including VDDA and VDD)(1) |VDDx| Variations between different VDD power pins 50 |VSSX VSS| Variations between all different ground pins 50 VESD(HBM) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.11 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values. Table 12. Symbol IVDD IVSS Current characteristics Ratings Max. Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink)(1) Output current sunk by any I/O and control pin IIO IINJ(PIN) (2) IINJ(PIN) Output current sourced by any I/O and control pin Injected current on five-volt tolerant Injected current on any other pin I/O(3) (4) Total injected current (sum of all I/O and control pins)(5) Unit 80 80 25 - 25 mA +0 /-5 5 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note in Section 6.3.19. 3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 11 for maximum allowed input voltage values. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values. 5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Doc ID 022027 Rev 5 55/141 Electrical characteristics Table 13. STM32L151xD STM32L152xD Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 6.3 Operating conditions 6.3.1 General operating conditions Table 14. Value Unit -65 to +150 C 150 C General operating conditions Symbol Parameter fHCLK Min Max Internal AHB clock frequency 0 32 fPCLK1 Internal APB1 clock frequency 0 32 fPCLK2 Internal APB2 clock frequency 0 32 BOR detector disabled 1.65 3.6 BOR detector enabled, at power on 1.8 3.6 BOR detector disabled, after power on 1.65 3.6 1.65 3.6 VDD VDDA(1) Standard operating voltage Analog operating voltage (ADC and DAC not used) Analog operating voltage (ADC or DAC used) PD Power dissipation at TA = 85 C(3) TA Temperature range TJ Junction temperature range Conditions Must be the same voltage as VDD(2) Unit MHz V V 1.8 UFBGA132 package 3.6 333 Maximum power dissipation -40 85 Low power dissipation(4) -40 105 -40 C TA 105 C -40 105 mW C C 1. When the ADC is used, refer to Table 64: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see ). 4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJ max (see ). 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in Table 14. 56/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 15. Symbol Electrical characteristics Embedded reset and power control block characteristics Parameter Conditions VDD rise time rate tVDD(1) VDD fall time rate Min 0 BOR detector disabled 0 1000 BOR detector enabled 20 BOR detector disabled 0 1000 2 3.3 0.4 0.7 1.6 Falling edge 1 1.5 1.65 Rising edge 1.3 1.5 1.65 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 Falling edge 2.45 2.55 2.60 Rising edge 2.54 2.66 2.7 Falling edge 2.68 2.8 2.85 Rising edge 2.78 2.9 2.95 Falling edge 1.8 1.85 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 VDD rising, BOR disabled(2) VPOR/PDR Power on/power down reset threshold VBOR0 Brown-out reset threshold 0 VBOR1 Brown-out reset threshold 1 VBOR2 Brown-out reset threshold 2 VBOR3 Brown-out reset threshold 3 VBOR4 Brown-out reset threshold 4 VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Max BOR detector enabled VDD rising, BOR enabled TRSTTEMPO(1) Reset temporization Typ Unit s/V ms V Doc ID 022027 Rev 5 57/141 Electrical characteristics Table 15. Symbol Vhyst STM32L151xD STM32L152xD Embedded reset and power control block characteristics (continued) Parameter Hysteresis voltage Conditions Min Typ Max BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit mV 1. Guaranteed by characterisation, not tested in production. 2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details. 58/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.3 Electrical characteristics Embedded internal reference voltage The parameters given in Table 16 are based on characterization results, unless otherwise specified. Table 16. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit - 40 C < TJ < +105 C 1.202 1.224 1.242 V VREFINT out(1) Internal reference voltage IREFINT Internal reference current consumption - 1.4 2.3 A TVREFINT Internal reference startup time - 2 3 ms VVREF_MEAS VDDA and VREF+ voltage during VREFINT factory measure 2.99 3 3.01 V AVREF_MEAS Accuracy of factory-measured VREF value(2) Including uncertainties due to ADC and VDDA/VREF+ values - - 5 mV -40 C < TJ < +105 C - 20 50 0 C < TJ < +50 C - - 20 TCoeff(3) Temperature coefficient ACoeff(3) Long-term stability 1000 hours, T= 25 C - - 1000 ppm VDDCoeff(3) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V TS_vrefint(3)(4) ADC sampling time when reading the internal reference voltage - 5 10 s TADC_BUF(3) Startup time of reference voltage buffer for ADC - - 10 s IBUF_ADC(3) Consumption of reference voltage buffer for ADC - 13.5 25 A IVREF_OUT(3) VREF_OUT output current(5) - - 1 A CVREF_OUT(3) VREF_OUT output load - - 50 pF Consumption of reference voltage buffer for VREF_OUT and COMP - 730 1200 nA ILPBUF(3) ppm/C VREFINT_DIV1(3) 1/4 reference voltage 24 25 26 VREFINT_DIV2(3) 1/2 reference voltage 49 50 51 VREFINT_DIV3(3) 3/4 reference voltage 74 75 76 % VREFINT 1. Tested in production. 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 5. To guarantee less than 1% VREF_OUT deviation. Doc ID 022027 Rev 5 59/141 Electrical characteristics 6.3.4 STM32L151xD STM32L152xD Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 12: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: VDD = 3.6 V All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted depending on fHCLK frequency and voltage range Prefetch and 64-bit access are enabled in configurations with 1 wait state The parameters given in Table 17, Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 17. Current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 IDD (Run from Flash) Supply current in Run mode, code executed from Flash fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 2, VCORE=1.5 V VOS[1:0] = 10 fHCLK Typ 1 MHz 360 500 500 500 2 MHz 620 750 750 750 4 MHz 1070 1200 1200 1200 4 MHz 1.30 1.6 1.6 1.6 8 MHz 2.4 2.9 2.9 2.9 16 MHz 4.6 5.2 5.2 5.2 Range 1, VCORE=1.8 V VOS[1:0] = 01 8 MHz 2.9 3.5 3.5 3.5 16 MHz 5.7 6.5 6.5 6.5 32 MHz 10.4 12 12 12 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 4.5 5.2 5.2 5.2 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 10.9 12.3 12.3 12.3 65 kHz 0.05 0.079 0.092 0.13 524 kHz 0.17 0.2 0.21 0.25 4.2 MHz 1.0 1.1 1.1 1.2 Range 3, VCORE=1.2 V VOS[1:0] = 11 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 60/141 Unit 55 C 85 C 105 C Doc ID 022027 Rev 5 A mA STM32L151xD STM32L152xD Table 18. Electrical characteristics Current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 IDD (Run from RAM) Supply current in Run mode, code executed from RAM, Flash switched off fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Typ 1 MHz 310 470 470 470 2 MHz 590 780 780 780 1200 1200(3) 4 MHz Unit 55 C 85 C 1030 1200 105 C 4 MHz 1.2 1.5 1.5 1.5 8 MHz 2.3 3 3 3 16 MHz 4.3 5 5 5 8 MHz 2.7 3.5 3.5 3.5 16 MHz 5.0 5.55 5.55 5.55 32 MHz 9.8 10.9 10.9 10.9 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 4.3 4.8 4.8 4.8 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 10.1 11.7 11.7 11.7 65 kHz 40 48.5 63 100 524 kHz 148 175 183 215 4.2 MHz 990 1032 1034 1100 Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 HSI clock source (16 MHz) fHCLK MSI clock, 65 kHz Range 3, MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz A mA A 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 3. Tested in production. Doc ID 022027 Rev 5 61/141 Electrical characteristics Table 19. STM32L151xD STM32L152xD Current consumption in Sleep mode Max(1) Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) Supply current in Sleep mode, code executed from RAM, Flash switched HSI clock source OFF (16 MHz) Range 2, VCORE=1.5 V VOS[1:0] = 10 HSI clock source (16 MHz) IDD (Sleep) 62/141 1 MHz 180 220 220 220 2 MHz 225 300 300 300 4 MHz 300 380 380 380(3) 4 MHz 360 500 500 500 8 MHz 570 700 700 700 16 MHz 990 1100 1100 1100 8 MHz 675 800 800 16 MHz 1150 1250 1250 1250 32 MHz 2300 2700 2700 2700 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 1025 1100 1100 1100 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 2460 2700 2700 2700 Range 3, VCORE=1.2 V VOS[1:0] = 11 Supply current in Sleep mode, code executed from Flash Unit 55 C 85 C 105 C 800 Range 3, MSI clock, 524 kHz VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz) Typ Range 1, VCORE=1.8 V VOS[1:0] = 01 MSI clock, 65 kHz IDD (Sleep) fHCLK Range 2, VCORE=1.5 V VOS[1:0] = 10 65 kHz 30 36 46 72 524 kHz 50 58 67 92 4.2 MHz 210 245 251 273 1 MHz 190 250 250 250 2 MHz 235 300 300 300 4 MHz 315 380 380 380 4 MHz 390 500 500 500 8 MHz 600 700 700 700 16 MHz 1000 1120 1120 1120 8 MHz Range 1, VCORE=1.8 V VOS[1:0] = 01 800 800 800 16 MHz 1160 1300 1300 1300 32 MHz 2310 2700 2700 2700 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 1040 1160 1160 1160 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 2500 2800 2800 2800 Supply MSI clock, 65 kHz current in MSI clock, 524 kHz Sleep Range 3, mode, VCORE=1.2V VOS[1:0] = 11 code MSI clock, 4.2 MHz executed from Flash 690 65 kHz 42 50 60 90 524 kHz 63 72 82 110 A A A 4.2 MHz Doc ID 022027 Rev 5 230 263 265 290 STM32L151xD STM32L152xD Electrical characteristics 1. Based on characterization, not tested in production, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) 3. Tested in production. Table 20. Symbol Current consumption in Low power run mode Parameter Conditions All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.65 V to 3.6 V IDD (LP Run) Supply current in Low power run mode Max allowed current in Low power run mode MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz MSI clock, 65 kHz fHCLK = 32 kHz All peripherals OFF, code executed from Flash, VDD from 1.65 V to 3.6 V IDD max (LP Run) MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz Typ Max (1) TA = -40 C to 25 C 11 14 TA = 85 C 26 32 TA = 105 C 53 72 TA =-40 C to 25 C 18 21 TA = 85 C 33 40 TA = 105 C 60 78 TA = -40 C to 25 C 36 41 TA = 55 C 39 44 TA = 85 C 50 58 TA = 105 C 78 95 TA = -40 C to 25 C 36 40.5 TA = 85 C 53 60 TA = 105 C 81 100 TA = -40 C to 25 C 44 49 TA = 85 C 61 67 TA = 105 C 89 107 TA = -40 C to 25 C 64 71 TA = 55 C 68 73 TA = 85 C 80 88 TA = 105 C 101 110 - 200 VDD from 1.65 V to 3.6 V Unit A 1. Based on characterization, not tested in production, unless otherwise specified. Doc ID 022027 Rev 5 63/141 Electrical characteristics Table 21. Symbol STM32L151xD STM32L152xD Current consumption in Low power sleep mode Parameter Conditions MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF MSI clock, 65 kHz fHCLK = 32 kHz Flash ON All peripherals MSI clock, 65 kHz OFF, VDD from 1.65 V fHCLK = 65 kHz, Flash ON to 3.6 V Typ MSI clock, 65 kHz fHCLK = 32 kHz TIM9 and USART1 enabled, Flash ON, VDD from 1.65 V to 3.6 V MSI clock, 65 kHz fHCLK = 65 kHz 4.4 - TA = -40 C to 25 C 18 21 TA = 85 C 24 27 TA = 105 C 35 43 TA = -40 C to 25 C 18.6 21 TA = 85 C 24.5 28 TA = 105 C 35 42 31 45 20.5 TA = 85 C 24 27 TA = 105 C 35 43 TA = -40 C to 25 C 18.6 21 TA = 85 C 24.5 28 TA = 105 C 35 42 TA = -40 C to 25 C 22 25 23.5 26 28.5 31 39 45 - 200 Max allowed VDD from current in IDD max 1.65 V to (LP Sleep) Low power 3.6 V Sleep mode 1. Based on characterization, not tested in production, unless otherwise specified. Doc ID 022027 Rev 5 26 18 MSI clock, 131 kHz TA = 55 C fHCLK = 131 kHz TA = 85 C Unit 25 TA = -40 C to 25 C TA = 105 C 64/141 (1) TA = -40 C to 25 C TA = -40 C to 25 C 22 MSI clock, 131 kHz T = 55 C 23.5 A fHCLK = 131 kHz, TA = 85 C 28.5 Flash ON TA = 105 C 39 Supply current in IDD Low power (LP Sleep) sleep mode Max A STM32L151xD STM32L152xD Table 22. Symbol Electrical characteristics Typical and maximum current consumptions in Stop mode Parameter Typ Max(1) Unit Conditions TA = -40C to 25C VDD = 1.8 V 1.5 TA = -40C to 25C 1.7 4 TA = 55C 2.4 6 TA= 85C 5.4 10 TA = 105C 11.0 23 TA = -40C to 25C 3.8 6 TA = 55C 4.4 7 TA= 85C 7.4 12 TA = 105C 14.4 27 TA = -40C to 25C 7.8 10 8.3 11 11.4 16 TA = 105C 20.5 44 TA = -40C to 25C 2.1 - TA = 55C 2.8 - TA= 85C 3.8 - TA = 105C 11.1 - TA = -40C to 25C 4.2 - 4.8 - 7.9 - TA = 105C 15.0 - TA = -40C to 25C 8.2 - 8.7 - 11.9 - TA = 105C 21.4 - TA = -40C to 25C VDD = 1.8V 1.6 - T = -40C to 25C LCD OFF A VDD = 3.0V 1.9 - TA = -40C to 25C VDD = 3.6V 2.1 - LCD OFF RTC clocked by LSI or LSE external clock (32.768kHz), regulator LCD ON in LP mode,HSI and (static HSE OFF (no (2) independent watchdog) duty) LCD ON T = 55C A (1/8 (3) TA= 85C duty) IDD (Stop Supply current in Stop with RTC) mode with RTC enabled LCD OFF RTC clocked by LSE external quartz (32.768kHz), regulator in LP mode, HSI and HSE OFF (no independent watchdog(4) LCD ON T = 55C A (static duty)(2) TA= 85C LCD ON T = 55C A (1/8 (3) T A= 85C duty) Doc ID 022027 Rev 5 A 65/141 Electrical characteristics Table 22. Symbol STM32L151xD STM32L152xD Typical and maximum current consumptions in Stop mode (continued) Parameter Typ Max(1) Unit Conditions Regulator in LP mode, HSI and HSE OFF, independent watchdog TA = -40C to 25C and LSI enabled IDD (Stop) Supply current in Stop mode (RTC disabled) IDD Supply current during (WU from wakeup from Stop mode Stop) Regulator in LP mode, LSI, HSI and HSE OFF (no independent watchdog) 1.6 TA = -40C to 25C 0.65 1 TA = 55C 1.3 3 TA= 85C 4.4 9 TA = 105C 10.0 22(5) 2 - 1.45 - 1.45 - MSI = 4.2 MHz MSI = 1.05 MHz MSI = 65 kHz 2.2 TA = -40C to 25C (6) A mA 1. Based on characterization, not tested in production, unless otherwise specified. 2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. 3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF loading capacitors. 5. Tested in production. 6. When MSI = 64 kHz, the RMS current is measured over the first 15 s following the wakeup event. For the remaining part of the wakeup period, the current corresponds the Run mode current. Table 23. Symbol Typical and maximum current consumptions in Standby mode Parameter Conditions RTC clocked by LSI (no independent watchdog) IDD Supply current in Standby (Standby mode with RTC enabled with RTC) RTC clocked by LSE external quartz(no independent watchdog)(3) Typ TA = -40 C to 25 C 1.3 1.9 TA = 55 C 1.44 2.2 TA= 85 C 1.90 4 TA = 105 C 3.05 8.3(2) TA = -40 C to 25 C 1.7 - TA = 55 C 1.84 - TA= 85 C 2.33 - TA = 105 C 3.59 - Independent watchdog and TA = -40 C to 25 C LSI enabled IDD Supply current in Standby (Standby) mode (RTC disabled) TA = -40 C to 25 C Independent watchdog and TA = 55 C LSI OFF TA = 85 C TA = 105 C IDD Supply current during wakeup (WU from time from Standby mode Standby) TA = -40 C to 25 C 1. Based on characterization, not tested in production, unless otherwise specified 66/141 Doc ID 022027 Rev 5 Max(1) Unit A 1 1.7 0.35 0.6 0.47 0.9 1.2 2.75 2.9 7(2) 1 - STM32L151xD STM32L152xD Electrical characteristics 2. Tested in production. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. Doc ID 022027 Rev 5 67/141 Electrical characteristics STM32L151xD STM32L152xD Wakeup time from low-power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: Sleep mode: the clock source is the clock that was set before entering Sleep mode Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 24. Typical and maximum timings in Low power modes Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEP_LP Wakeup from Low power sleep mode fHCLK = 262 kHz tWUSTDBY Max(1) Unit 0.4 - fHCLK = 262 kHz Flash enabled 46 - fHCLK = 262 kHz Flash switched OFF 46 - fHCLK = fMSI = 4.2 MHz 8.2 - fHCLK = fMSI = 4.2 MHz Voltage range 1 and 2 7.7 8.9 fHCLK = fMSI = 4.2 MHz Voltage range 3 8.2 13.1 10.2 13.4 16 20 fHCLK = fMSI = 524 kHz 31 37 fHCLK = fMSI = 262 kHz 57 66 fHCLK = fMSI = 131 kHz 112 123 fHCLK = MSI = 65 kHz 221 236 Wakeup from Standby mode fHCLK = MSI = 2.1 MHz FWU bit = 1 58 104 Wakeup from Standby mode fHCLK = MSI = 2.1 MHz FWU bit = 0 2.6 3.25 fHCLK = fMSI = 2.1 MHz Wakeup from Stop mode, regulator in low power mode fHCLK = fMSI = 1.05 MHz 1. Based on characterization, not tested in production, unless otherwise specified 68/141 Typ fHCLK = 32 MHz Wakeup from Stop mode, regulator in Run mode tWUSTOP Conditions Doc ID 022027 Rev 5 s ms STM32L151xD STM32L152xD Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on Table 25. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run TIM2 13 11 9 11 TIM3 12 10 9 11 TIM4 12 10 9 11 TIM5 16 13 11 14 TIM6 4 4 4 4 TIM7 4 4 4 4 LCD 4 3 3 4 WWDG 3 2.5 2.5 3 SPI2 8 7 9 7.5 SPI3 7 6 7 6 USART2 8 7 7 7 USART3 8 7 7 7 USART4 8 7 7 7 USART5 8 7 7 7 I2C1 8 7 6 7 I2C2 7 6 5 6 USB 15 7 7 7 PWR 3 3 3 3 DAC 6 5 4.5 5 COMP 4 3.5 3.5 4 Peripheral APB1 Doc ID 022027 Rev 5 Unit A/MHz (fHCLK) 69/141 Electrical characteristics Table 25. STM32L151xD STM32L152xD Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 Low power sleep and run SYSCFG & RI 3 2 2 3 TIM9 8 7 6 7 TIM10 6 5 5 5 TIM11 6 5 5 5 ADC 10 8 7 8 SDIO 20 6 5 6 SPI1 4 4 4 4 USART1 8 7 6 7 GPIOA 7 6 5 6 GPIOB 7 6 5 6 GPIOC 7 6 5 6 GPIOD 7 6 5 6 GPIOE 7 6 5 6 GPIOF 7 6 5 6 GPIOG 7 6 5 6 GPIOH 2 2 1 2 CRC 0.5 0.5 0.5 1 FLASH 26 26 29 -(3) DMA1 18 15 13 18 DMA2 16 14 12 16 FSMC 15 12 10 12 279 221 219 215 Peripheral APB2 (2) AHB All enabled 70/141 Doc ID 022027 Rev 5 Unit A/MHz (fHCLK) STM32L151xD STM32L152xD Table 25. Electrical characteristics Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Range 1, VCORE= 1.8 V VOS[1:0] = 01 Peripheral Range 2, VCORE= 1.5 V VOS[1:0] = 10 Range 3, VCORE= 1.2 V VOS[1:0] = 11 IDD (RTC) 0.4 IDD (LCD) 3.1 IDD (ADC)(4) 1450 IDD (DAC)(5) 340 IDD (COMP1) 0.16 IDD (COMP2) IDD (PVD / BOR) Slow mode 2 Fast mode 5 (6) Low power sleep and run Unit A 2.6 IDD (IWDG) 0.25 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz (range 3), fHCLK = 64kHz (Low power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production. 2. HSI oscillator is OFF for this measure. 3. In low power sleep and run mode, the Flash memory must always be in power-down mode. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 6. Including supply current of internal reference voltage. 6.3.5 External clock source characteristics High-speed external user clock generated from an external source Table 26. Symbol High-speed external user clock characteristics(1) Parameter Conditions Min Typ Max Unit 1 8 32 MHz fHSE_ext User external clock source frequency VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time 12 - - tr(HSE) tf(HSE) OSC_IN rise or fall time - - 20 OSC_IN input capacitance - 2.6 - Cin(HSE) V ns Doc ID 022027 Rev 5 pF 71/141 Electrical characteristics Table 26. STM32L151xD STM32L152xD High-speed external user clock characteristics(1) Symbol Parameter Conditions DuCy(HSE) Duty cycle IL OSC_IN Input leakage current VSS VIN VDD 1. Guaranteed by design, not tested in production. 72/141 Doc ID 022027 Rev 5 Min Typ Max Unit 45 - 55 % - - 1 A STM32L151xD STM32L152xD Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 27. Low-speed external user clock characteristics(1) Symbol Parameter Conditions Min Typ Max Unit 1 32.768 1000 kHz 0.7VDD - VDD fLSE_ext User external clock source frequency VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time 465 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time - - 10 OSC32_IN input capacitance - 0.6 - pF 45 - 55 % - - 1 A V CIN(LSE) ns DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current VSS VIN VDD 1. Guaranteed by design, not tested in production Figure 13. Low-speed external clock source AC timing diagram 6,3%( 6,3%, TR,3% TF,3% T7,3% T7,3% T 4,3% %84%2 .!, #,/#+ 3/52# % F,3%?EXT /3#?). ), 34-,XX AI Doc ID 022027 Rev 5 73/141 Electrical characteristics STM32L151xD STM32L152xD Figure 14. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR(3% TF(3% T7(3% /3# ?). ), T7(3% T 4(3% %84%2 .!, #,/#+ 3/52# % F(3%?EXT 34-,XX AI High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 28. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). 74/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 28. Symbol Electrical characteristics HSE 1-24 MHz oscillator characteristics(1)(2) Parameter Conditions fOSC_IN Oscillator frequency 1 RF Feedback resistor C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) IHSE HSE driving current HSE oscillator power IDD(HSE) consumption gm tSU(HSE) (4) Oscillator transconductance Startup time Min Typ Max Unit 24 MHz - 200 - k RS = 30 - 20 - pF VDD= 3.3 V, VIN = VSS with 30 pF load - - 3 mA C = 20 pF fOSC = 16 MHz - - 2.5 (startup) 0.7 (stabilized) C = 10 pF fOSC = 16 MHz - - 2.5 (startup) 0.46 (stabilized) Startup 3.5 - - mA /V VDD is stabilized - 1 - ms mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Doc ID 022027 Rev 5 75/141 Electrical characteristics STM32L151xD STM32L152xD Figure 15. HSE oscillator circuit diagram F(3% TO CORE 2M ,M 2& #/ #, /3#?). #M GM 2ESONATOR #ONSUMPTION CONTROL 2ESONATOR 34- /3#?/54 #, AI 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 29. Symbol LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency - 32.768 - kHz RF Feedback resistor - 1.2 - M C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 k - 8 - pF ILSE LSE driving current VDD = 3.3 V, VIN = VSS - - 1.1 A VDD = 1.8 V - 450 - VDD = 3.0 V - 600 - VDD = 3.6V - 750 - IDD (LSE) Oscillator transconductance gm tSU(LSE) LSE oscillator current consumption (4) Startup time 3 VDD is stabilized - 1 nA - A/V - s 1. Based on characterization, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details. 4. 76/141 tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 16). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 16. Typical application with a 32.768 kHz crystal 2ESONATOR WITH INTEGRATED CAPACITORS #, F,3% /3#?). K( Z RESONATOR #, 2& "IAS CONTROLLED GAIN /3#?/5 4 34-,XXX AI Doc ID 022027 Rev 5 77/141 Electrical characteristics 6.3.6 STM32L151xD STM32L152xD Internal clock source characteristics The parameters given in Table 30 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 30. Symbol fHSI TRIM (1)(2) HSI oscillator characteristics Parameter Conditions Min Typ Max Unit Frequency VDD = 3.0 V - 16 - MHz HSI user-trimmed resolution Trimming code is not a multiple of 16 - 0.4 0.7 % Trimming code is a multiple of 16 - Accuracy of the ACCHSI(2) factory-calibrated HSI oscillator - 1.5 % VDDA = 3.0 V, TA = 25 C -1(3) - 1(3) % VDDA = 3.0 V, TA = 0 to 55 C -1.5 - 1.5 % VDDA = 3.0 V, TA = -10 to 70 C -2 - 2 % VDDA = 3.0 V, TA = -10 to 85 C -2.5 - 2 % VDDA = 3.0 V, TA = -10 to 105 C -4 - 2 % VDDA = 1.65 V to 3.6 V TA = -40 to 105 C -4 - 3 % tSU(HSI)(2) HSI oscillator startup time - 3.7 6 s IDD(HSI)(2) HSI oscillator power consumption - 100 140 A 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Based on characterization, not tested in production. 3. Tested in production. Low-speed internal (LSI) RC oscillator Table 31. LSI oscillator characteristics Symbol fLSI(1) DLSI(2) tsu(LSI)(3) IDD(LSI) (3) Parameter Min Typ Max Unit LSI frequency 26 38 56 kHz LSI oscillator frequency drift 0C TA 85C -10 - 4 % LSI oscillator startup time - - 200 s LSI oscillator power consumption - 400 510 nA 1. Tested in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design, not tested in production. 78/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Multi-speed internal (MSI) RC oscillator Table 32. MSI oscillator characteristics Symbol Parameter Condition Typ Max Unit MSI range 0 65.5 - MSI range 1 131 - MSI range 2 262 - MSI range 3 524 - MSI range 4 1.05 - MSI range 5 2.1 - MSI range 6 4.2 - 0.5 - % 3 - % - 2.5 %/V MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - MSI range 3 2.5 - MSI range 4 4.5 - MSI range 5 8 - MSI range 6 15 - kHz fMSI ACCMSI Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 C Frequency error after factory calibration DTEMP(MSI)(1) MSI oscillator frequency drift 0 C TA 85 C DVOLT(MSI)(1) MSI oscillator frequency drift 1.65 V VDD 3.6 V, TA = 25 C IDD(MSI)(2) MSI oscillator power consumption Doc ID 022027 Rev 5 MHz A 79/141 Electrical characteristics Table 32. Symbol tSU(MSI) STM32L151xD STM32L152xD MSI oscillator characteristics (continued) Parameter MSI oscillator startup time Condition Typ Max MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6 - MSI range 5 5 - MSI range 6, Voltage range 1 and 2 3.5 - MSI range 6, Voltage range 3 5 - MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 and 2 - 2 MSI range 3, Voltage range 3 - 3 Any range to range 5 - 4 Any range to range 6 - 6 Unit s tSTAB(MSI)(2) fOVER(MSI) MSI oscillator stabilization time MHz MSI oscillator frequency overshoot 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Based on characterization, not tested in production. 80/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.7 Electrical characteristics PLL characteristics The parameters given in Table 33 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 33. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 2 - 24 MHz PLL input clock duty cycle 45 - 55 % fPLL_OUT PLL output clock 2 - 32 MHz tLOCK Worst case PLL lock time PLL input = 2 MHz PLL VCO = 96 MHz - 100 130 s Jitter Cycle-to-cycle jitter - 600 ps IDDA(PLL) Current consumption on VDDA - 220 450 IDD(PLL) Current consumption on VDD - 120 150 fPLL_IN A 1. Based on characterization, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 6.3.8 Memory characteristics The characteristics are given at TA = -40 to 105 C unless otherwise specified. RAM memory Table 34. Symbol VRM RAM and hardware registers Parameter Conditions Data retention mode(1) STOP mode (or RESET) Min Typ Max Unit 1.65 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Doc ID 022027 Rev 5 81/141 Electrical characteristics STM32L151xD STM32L152xD Flash memory and data EEPROM Table 35. Symbol Flash memory and data EEPROM characteristics Min Typ Max(1) Unit 1.65 - 3.6 V Erasing - 3.28 3.94 Programming - 3.28 3.94 Average current during the whole programming / erase operation - 600 900 A Maximum current (peak) TA25 C, VDD = 3.6 V during the whole programming / erase operation - 1.5 2.5 mA Parameter VDD Operating voltage Read / Write / Erase tprog Programming time for word or half-page IDD Conditions ms 1. Guaranteed by design, not tested in production. Table 36. Flash memory and data EEPROM endurance and retention Value Symbol NCYC(2) Parameter Cycling (erase / write) Program memory Cycling (erase / write) EEPROM data memory Data retention (program memory) after 10 kcycles at TA = 85 C tRET(2) Data retention (EEPROM data memory) after 300 kcycles at TA = 85 C Data retention (program memory) after 10 kcycles at TA = 105 C Data retention (EEPROM data memory) after 300 kcycles at TA = 105 C Conditions TA-40C to 105 C 10 - Unit kcycles 300 - - 30 - - 30 - - TRET = +85 C years 10 - - 10 - - TRET = +105 C 1. Based on characterization not tested in production. 2. Characterization is done according to JEDEC JESD22-A117. 82/141 Min(1) Typ Max Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.9 Electrical characteristics FSMC characteristics Asynchronous waveforms and timings Figure 17 through Figure 20 represent asynchronous waveforms and Table 37 through Table 40 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: AddressSetupTime = 0 (AddressSetupTime = 1, for asynchronous multiplexed modes) AddressHoldTime = 1 DataSetupTime = 1 Figure 17. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW.% &3-#?.% T V./%?.% T W./% T H.%?./% &3-#?./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &3-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &3-#?$;= T V.!$6?.% TW.!$6 &3-#?.!$6 -36 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Doc ID 022027 Rev 5 83/141 Electrical characteristics STM32L151xD STM32L152xD Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Table 37. Symbol Parameter Min Max Unit THCLK -2 THCLK ns 0 2 ns THCLK THCLK - 1 ns tw(NE) FSMC_NE low time tv(NOE_NE) FSMC_NEx low to FSMC_NOE low tw(NOE) FSMC_NOE low time th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 4 ns th(A_NOE) Address hold time after FSMC_NOE high THCLK + 1.5 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 2*THCLK - 0.5 - ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK - ns THCLK - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 2 ns tw(NADV) FSMC_NADV low time - THCLK ns 1. CL = 30 pF. Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[1:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. 84/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Table 38. Symbol Parameter tw(NE) FSMC_NE low time tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tw(NWE) FSMC_NWE low time th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NE) FSMC_NEx low to Data valid th(Data_NWE) Data hold time after FSMC_NWE high Min Max Unit 2*THCLK -3 2*THCLK +2 ns 0.5 1 ns THCLK - 2 THCLK + 3 ns THCLK - 2.5 - ns - 0 ns THCLK - 2.5 - ns - 0 ns THCLK - 4 - ns - THCLK ns THCLK - 2.5 - ns 1. CL = 30 pF. Figure 19. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) FSMC_AD[15:0] tsu(Data_NOE) Address t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Doc ID 022027 Rev 5 85/141 Electrical characteristics STM32L151xD STM32L152xD Asynchronous multiplexed PSRAM/NOR read timings(1) Table 39. Symbol Parameter Min Max 3*THCLK - 1.5 3*THCLK + 1 Unit tw(NE) FSMC_NE low time ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 2*THCLK - 1 2*THCLK ns tw(NOE) FSMC_NOE low time THCLK - 0.5 THCLK + 0.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time 0 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 5 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1.5 2 ns tw(NADV) FSMC_NADV low time THCLK - 0.5 THCLK ns th(AD_NADV) FSMC_AD(address) valid hold time after FSMC_NADV high THCLK - 6 - ns th(A_NOE) Address hold time after FSMC_NOE high 2*THCLK - 1 - ns th(BL_NOE) FSMC_BL time after FSMC_NOE high 1.5 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time THCLK - ns tsu(Data_NOE) Data to FSMC_NOE high setup time THCLK - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 30 pF. Figure 20. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) FSMC_AD[15:0] t v(Data_NADV) Address t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B 86/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 40. Symbol Electrical characteristics Asynchronous multiplexed PSRAM/NOR write timings(1) Parameter Min Max Unit 4*THCLK - 3 4*THCLK + 2 ns THCLK THCLK + 1 ns tw(NE) FSMC_NE low time tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tw(NWE) FSMC_NWE low time 2*THCLK - 2 2*THCLK + 4 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time THCLK - 2.5 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 6 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 1.5 2 ns tw(NADV) FSMC_NADV low time THCLK - 4 THCLK + 4 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high THCLK - 5 - ns th(A_NWE) Address hold time after FSMC_NWE high THCLK - 2.5 - ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high THCLK - 3 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns - THCLK + 6 ns THCLK - 2.5 - ns tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 30 pF. Doc ID 022027 Rev 5 87/141 Electrical characteristics STM32L151xD STM32L152xD Synchronous waveforms and timings Figure 21 through Figure 24 represent synchronous waveforms and Table 42 through Table 44 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: BurstAccessMode = FSMC_BurstAccessMode_Enable; MemoryType = FSMC_MemoryType_CRAM; WriteBurst = FSMC_WriteBurst_Enable; CLKDivision = 1; DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 21. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, T D#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%( TD#,+, ./%, &3-#?./% TD#,+, !$)6 TSU!$6 #,+( TD#,+, !$6 &3-#?!$;= !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( TH#,+( !$6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIG 88/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 41. Electrical characteristics Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Min Max Unit 2*THCLK 0.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) THCLK + 1.5 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 3 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2.5 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 4 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 4 - ns TBD - ns TBD - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high THCLK - 1 ns 1. CL = 30 pF. Doc ID 022027 Rev 5 89/141 Electrical characteristics STM32L151xD STM32L152xD Figure 22. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, $ATA TD#,+, $ATA TD#,+, !$6 &3-#?!$;= !$;= $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIF 90/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 42. Electrical characteristics Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Min Max Unit 2*THCLK - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 0 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) THCLK + 4 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 0 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 5 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high TBD - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high TBD - ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns 1. CL = 30 pF. Doc ID 022027 Rev 5 91/141 Electrical characteristics STM32L151xD STM32L152xD Figure 23. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+, ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 AIF Table 43. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol Parameter Max Unit 2*THCLK 0.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 0 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 3 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 3.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 0 - ns td(CLKL-NOEL) FSMC_CLK low to FSMC_NOE low - THCLK + 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 2.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 4 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 4 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high TBD - ns th(CLKH-NWAITV) TBD - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 30 pF. 92/141 Min Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 24. Synchronous non-multiplexed PSRAM write timings TW#,+ "53452. TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATA LATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, $ATA &3-#?$;= TD#,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+, .",( TH#,+( .7!)46 &3-#?.", AIG Table 44. Synchronous non-multiplexed PSRAM write timings(1) Symbol Parameter Min Max Unit 2*THCLK -3 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 5 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 7 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) THCLK + 4 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 2 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 5 - ns td(CLKL-DATA) FSMC_D[15:0] valid data after FSMC_CLK low - 7 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 3 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high TBD - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high TBD - ns 1. CL = 30 pF. Doc ID 022027 Rev 5 93/141 Electrical characteristics 6.3.10 STM32L151xD STM32L152xD EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 45. They are based on the EMS levels and classes defined in application note AN1709. Table 45. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD 3.3 V, LQFP100, TA +25 C, Voltage limits to be applied on any I/O pin to fHCLK 32 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3.3 V, LQFP100, TA +25 C, fHCLK 32 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: 94/141 Corrupted program counter Unexpected reset Critical data corruption (control registers...) Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 46. EMI characteristics Max vs. frequency range Symbol Parameter SEMI 6.3.11 Conditions VDD 3.3 V, TA 25 C, Peak level LQFP100 package compliant with IEC 61967-2 Monitored frequency band 4 MHz 16 MHz 32 MHz voltage voltage voltage range 3 range 2 range 1 0.1 to 30 MHz 3 -6 -5 30 to 130 MHz 18 4 -7 130 MHz to 1GHz 15 5 -7 SAE EMI Level 2.5 2 1 Unit dBV - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Table 47. Symbol ESD absolute maximum ratings Ratings Conditions Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge TA +25 C, conforming voltage (human body model) to JESD22-A114 2 2000 VESD(CDM) Electrostatic discharge TA +25 C, conforming voltage (charge device model) to JESD22-C101 II 500 V 1. Based on characterization results, not tested in production. Doc ID 022027 Rev 5 95/141 Electrical characteristics STM32L151xD STM32L152xD Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: A supply overvoltage is applied to each power supply pin A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 48. Symbol LU 6.3.12 Electrical sensitivities Parameter Conditions Static latch-up class Class TA +105 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, LCD levels, etc.). The test results are given in the following table. Table 49. I/O current injection susceptibility Functional susceptibility Symbol IINJ 96/141 Description Negative injection Positive injection Injected current on true open-drain pins -5 +0 Injected current on all 5 V tolerant (FT) pins -5 +0 Injected current on any other pin -5 +5 Doc ID 022027 Rev 5 Unit mA STM32L151xD STM32L152xD 6.3.13 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 50. I/O static characteristics Symbol VIL Parameter Conditions VIL Typ Max VSS - 0.3 - 0.8 - VDD+0.3 - 5.5V - 0.3VDD(3) - VDD+0.3 - 5.25 - 5.5 10% VDD(7) - - VSS VIN VDD I/Os with LCD - - 50 VSS VIN VDD I/Os with analog switches - - 50 VSS VIN VDD I/Os with analog switches and LCD - - 50 VSS VIN VDD I/Os with USB - - TBD VSS VIN VDD Standard I/Os - - 50 VIN VSS 30 45 60 k VIN VDD 30 45 60 k - 5 - pF Input low level voltage TTL ports 2.7 V VDD 3.6 V Standard I/O input high level voltage VIH Min FT (2) I/O input high level voltage Input low level voltage CMOS ports 1.65 V VDD 3.6 V Standard I/O Input high level voltage CMOS ports 1.65 V VDD 3.6 V CMOS ports 1.65 V VDD 2.0 V VIH FT (5) 2(1) I/O input high level voltage -0.3 0.7 VDD(3)(4) CMOS ports 2.0 V VDD 3.6 V Vhys Ilkg RPU Standard I/O Schmitt trigger voltage hysteresis(6) Input leakage current (8)(3) Weak pull-up equivalent resistor(9)(3) RPD Weak pull-down equivalent CIO I/O pin capacitance resistor(9)(3) Unit V nA 1. Guaranteed by design. 2. FT = 5V tolerant. To sustain a voltage higher than VDD +0.5 the internal pull-up/pull-down resistors must be disabled. 3. Tested in production 4. 0.7VDD for 5V-tolerant receiver 5. FT = Five-volt tolerant. 6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 7. With a minimum of 200 mV. Based on characterization, not tested in production. Doc ID 022027 Rev 5 97/141 Electrical characteristics STM32L151xD STM32L152xD 8. The max. value may be exceeded if negative current is injected on adjacent pins. 9. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA with the non-standard VOL/VOH specifications given in Table 51. in the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 51. Output voltage characteristics Symbol Parameter VOL(1)(2) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(3)(2) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL (1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH (3)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 4 pins are sunk at same time VOH(3)(4) Output high level voltage for an I/O pin when 4 pins are sourced at same time Conditions IIO = +8 mA 2.7 V < VDD < 3.6 V IIO =+ 4 mA 1.65 V < VDD < 2.7 V IIO = +20 mA 2.7 V < VDD < 3.6 V Min Max - 0.4 2.4 - - 0.45 VDD-0.45 - - 1.3 VDD-1.3 - Unit V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. Tested in production. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Based on characterization data, not tested in production. 98/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 25 and Table 52, respectively. Unless otherwise specified, the parameters given in Table 52 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 52. OSPEEDRx [1:0] bit value(1) I/O AC characteristics(1) Symbol Parameter fmax(IO)out Maximum frequency(3) 00 tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) 01 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 10 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 11 - tf(IO)out tr(IO)out Output rise and fall time tEXTIpw Pulse width of external signals detected by the EXTI controller Min Max(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400 CL = 50 pF, VDD = 1.65 V to 2.7 V - 400 CL = 50 pF, VDD = 2.7 V to 3.6 V - 625 CL = 50 pF, VDD = 1.65 V to 2.7 V - 625 CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 CL = 50 pF, VDD = 1.65 V to 2.7 V - 1 CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 CL = 50 pF, VDD = 1.65 V to 2.7 V - 250 CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 CL = 50 pF, VDD = 1.65 V to 2.7 V - 2 CL = 50 pF, VDD = 2.7 V to 3.6 V - 25 CL = 50 pF, VDD = 1.65 V to 2.7 V - 125 CL = 30 pF, VDD = 2.7 V to 3.6 V - 50 CL = 50 pF, VDD = 1.65 V to 2.7 V - 8 CL = 30 pF, VDD = 2.7 V to 3.6 V - 5 CL = 50 pF, VDD = 1.65 V to 2.7 V - 30 Conditions Unit kHz ns MHz ns MHz ns MHz ns 8 - 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. Not tested in production. 3. The maximum frequency is defined in Figure 25. Doc ID 022027 Rev 5 99/141 Electrical characteristics STM32L151xD STM32L152xD Figure 25. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% External Output on 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50 pF ai14131 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. Unless otherwise specified, the parameters given in Table 53 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 53. Symbol NRST pin characteristics Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST input low level voltage VSS - 0.8 VIH(NRST)(1) NRST input high level voltage 1.4 - VDD IOL = 2 mA 2.7 V < VDD < 3.6 V - - IOL = 1.5 mA 1.65 V < VDD < 2.7 V - - 10%VDD(2) - - mV 30 45 60 k - - 50 ns 350 - - ns NRST output low level VOL(NRST)(1) voltage Vhys(NRST)(1) NRST Schmitt trigger voltage hysteresis RPU Weak pull-up equivalent resistor(3) VF(NRST)(1) NRST input filtered pulse VNF(NRST)(1) NRST input not filtered pulse VIN VSS V 0.4 1. Guaranteed by design, not tested in production. 2. 200 mV minimum value 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. 100/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 26. Recommended NRST pin protection 6$$ %XTERNAL RESET CIRCUIT .234 205 )NTERNAL RESET &ILTER & 34-,XXX AI 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 53. Otherwise the reset will not be taken into account by the device. 6.3.15 TIM timer characteristics The parameters given in the following table are guaranteed by design. Refer to Section 6.3.12: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 54. Symbol tres(TIM) fEXT ResTIM tCOUNTER TIMx(1) characteristics Parameter Conditions Min Max Unit 1 - tTIMxCLK 31.25 - ns 0 fTIMxCLK/2 MHz 0 16 MHz 16 bit 65536 tTIMxCLK 2048 s - 65536 x 65536 tTIMxCLK - 134.2 s Timer resolution time fTIMxCLK = 32 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 32 MHz Timer resolution 16-bit counter clock period 1 when internal clock is selected (timer's prescaler f TIMxCLK = 32 MHz 0.0312 disabled) tMAX_COUNT Maximum possible count fTIMxCLK = 32 MHz 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. Doc ID 022027 Rev 5 101/141 Electrical characteristics 6.3.16 STM32L151xD STM32L152xD Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 14. The STM32L151xD and STM32L152xD product line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not "true" open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 55. Refer also to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 55. I2C characteristics Standard mode I2C(1) Symbol Fast mode I2C(1)(2) Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time 0 - 0 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 20 + 0.1Cb 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF s ns s 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode IC frequencies. It must be at least 4 MHz to achieve fast mode IC frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum IC fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 102/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 27. I2C bus AC waveforms and measurement circuit 6$$ 6$$ K K 34-,XXX 3$! )# BUS 3#, 3 4!24 2%0%!4%$ 3 4!24 3 4!24 TSU34! 3$! TF3$! TR3$! TH34! TSU3$! TW3#+, 3#, TW3#+( TR3#+ TSU34!34/ 3 4/0 TH3$! TSU34/ TF3#+ AI 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 56. SCL frequency (fPCLK1= 32 MHz, VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 2 1. RP = External pull-up resistance, fSCL = I C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. Doc ID 022027 Rev 5 103/141 Electrical characteristics STM32L151xD STM32L152xD SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 57. SPI characteristics(1) Symbol fSCK 1/tc(SCK) Min Max(2) Master mode - 16 Slave mode - 16 Parameter Conditions SPI clock frequency MHz (3) Slave transmitter - SPI clock rise and fall time Capacitive load: C = 30 pF - 6 ns SPI slave input clock duty cycle Slave mode 30 70 % tsu(NSS) NSS setup time Slave mode 4tHCLK - th(NSS) NSS hold time Slave mode 2tHCLK - SCK high and low time Master mode tSCK/25 tSCK/2+3 Master mode 5 - Slave mode 6 - Master mode 5 - Slave mode 5 - tr(SCK)(2) tf(SCK)(2) DuCy(SCK) tw(SCKH)(2) tw(SCKL)(2) tsu(MI)(2) tsu(SI)(2) Data input setup time (2) th(MI) th(SI) (2) 12 Unit Data input hold time ta(SO)(4) Data output access time Slave mode 0 3tHCLK tv(SO) (2) Data output valid time Slave mode - 33 tv(MO)(2) Data output valid time Master mode - 6.5 Slave mode 17 - Master mode 0.5 - th(SO) (2) th(MO) (2) ns Data output hold time 1. The characteristics above are given for voltage range 1. 2. Based on characterization, not tested in production. 3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%. 4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 104/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 28. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 29. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) B I T1 IN M SB IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 022027 Rev 5 105/141 Electrical characteristics STM32L151xD STM32L152xD Figure 30. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) MS BIN BI T6 IN LSB IN th(MI) MOSI OUTPUT M SB OUT B I T1 OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 106/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.17 Electrical characteristics I2S characteristics Table 58. Symbol fMCK I2S characteristics Parameter Conditions Min Max 256 x 8K 256xFs (1) I2S Main Clock Output Master data: 32 bits - 64xFs Slave data: 32 bits - 64xFs 30 70 fCK I2S clock frequency DCK I2S clock frequency duty cycle Slave receiver, 48KHz tr(CK) I2S clock rise time tf(CK) I2S clock fall time tv(WS) WS valid time Master mode 4 24 th(WS) WS hold time Master mode 0 - tsu(WS) WS setup time Slave mode 15 - th(WS) WS hold time Slave mode 0 - tsu(SD_MR) Data input setup time Master receiver 8 - tsu(SD_SR) Data input setup time Slave receiver 9 - th(SD_MR) Master receiver 5 - Slave receiver 4 - Unit MHz MHz % 8 Capacitive load CL=30pF 8 ns Data input hold time th(SD_SR) tv(SD_ST) Data output valid time Slave transmitter (after enable edge) - 64 th(SD_ST) Data output hold time Slave transmitter (after enable edge) 22 - tv(SD_MT) Data output valid time Master transmitter (after enable edge) - 12 th(SD_MT) Data output hold time Master transmitter (after enable edge) 8 - 1. The maximum for 256xFs is 8 MHz Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition. Doc ID 022027 Rev 5 107/141 Electrical characteristics STM32L151xD STM32L152xD Figure 31. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB transmit th(SD_SR) LSB receive(2) SDreceive th(SD_ST) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 32. I2S master timing diagram (Philips protocol)(1) tf(CK) tr(CK) CK output tc(CK) CPOL = 0 tw(CKH) CPOL = 1 tv(WS) th(WS) tw(CKL) WS output tv(SD_MT) SDtransmit LSB transmit(2) MSB transmit LSB receive(2) LSB transmit th(SD_MR) tsu(SD_MR) SDreceive Bitn transmit th(SD_MT) MSB receive Bitn receive LSB receive ai14884b 1. Based on characterization, not tested in production. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 108/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.18 Electrical characteristics SDIO characteristics Table 59. SDIO characteristics(1) Symbol Conditions Min Max Unit Clock frequency in data transfer mode CL 30 pF 0 24 MHz Clock low time, fPP = 24 MHz CL 30 pF 20(2) - tW(CKH) Clock high time, fPP = 24 MHz CL 30 pF (2) 18 - tr Clock rise time, fPP = 24 MHz CL 30 pF - 5 tf Clock fall time, fPP = 24 MHz CL 30 pF - 5 fPP tW(CKL) Parameter ns CMD, D inputs (referenced to CK) in SD default mode From 2.8 to 3.6 V tISU Input setup time, fPP = 24 MHz CL 30 pF 2 - tIH Input hold time, fPP = 24 MHz CL 30 pF 1.6 - ns CMD, D outputs (referenced to CK) in SD default mode tOVD Output valid default time, fPP = 24 MHz CL 30 pF 0 14 tOHD Output hold default time, fPP = 24 MHz CL 30 pF 0 - ns 1. Based on characterization, not tested in production. 2. Values measured with a threshold level equal to VDD/2. Figure 33. SDIO timings tf tr tC tW(CKH) tW(CKL) CK tOHD tOVD D, CMD(output) tISU tIH D, CMD(input) -36 Doc ID 022027 Rev 5 109/141 Electrical characteristics STM32L151xD STM32L152xD USB characteristics The USB interface is USB-IF certified (full speed). Table 60. USB startup time Symbol tSTARTUP(1) Parameter Max Unit 1 s USB transceiver startup time 1. Guaranteed by design, not tested in production. Table 61. USB DC electrical characteristics Min.(1) Max.(1) Unit 3.0 3.6 V 0.2 - Differential common mode range Includes VDI range 0.8 2.5 Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 Symbol Parameter Conditions Input levels VDD VDI(2) VCM (2) VSE(2) USB operating voltage Differential input sensitivity I(USB_DP, USB_DM) V Output levels VOL(3) VOH (3) RL of 1.5 k to 3.6 V(4) Static output level low Static output level high RL of 15 k to V VSS(4) 1. All the voltages are measured from the local ground potential. 2. Guaranteed by characterization, not tested in production. 3. Tested in production. 4. RL is the load connected on the USB drivers. Figure 34. USB timings: definition of data signal rise and fall time Crossover points Differen tial Data L ines VCRS VS S Table 62. tr tf ai14137 USB: full speed electrical characteristics Driver characteristics(1) Symbol Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf Time(2) CL = 50 pF 4 20 ns tr/tf 90 110 % 1.3 2.0 V trfm VCRS 110/141 Parameter Fall Rise/ fall time matching Output signal crossover voltage Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). 6.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 64 are guaranteed by design. Table 63. Symbol fADC ADC clock frequency Parameter ADC clock frequency Conditions Min Max VREF+ = VDDA 16 VREF+ VDDA 2.4 V VDDA 3.6 V VREF+ > 2.4 V 8 Voltage range 1 & 2 VREF+ VDDA VREF+ 2.4 V 1.8 V VDDA 2.4 V 4 0.480 VREF+ = VDDA 8 VREF+ VDDA 4 Voltage range 3 Table 64. Symbol MHz 4 ADC characteristics Parameter Conditions Min Typ Max 1.8 - 3.6 1.8(1) - VDDA VDDA Power supply VREF+ Positive reference voltage VREF- Negative reference voltage - VSSA - IVDDA Current on the VDDA input pin - 1000 1450 IVREF(2) Current on the VREF input pin VAIN Unit 2.4 V VDDA 3.6 V VREF+ must be below or equal to VDDA V A Peak - 700 400 Average Conversion voltage range(3) - 450 0(4) - VREF+ Direct channels 0.03 - 1 Multiplexed channels 0.03 - 0.76 Direct channels 0.03 - 1.07 Multiplexed channels 0.03 - 0.8 Direct channels 0.03 - 1.23 Multiplexed channels 0.03 - 0.89 Direct channels 0.03 - 1.54 Multiplexed channels 0.03 - 1 12-bit sampling rate V Msps 10-bit sampling rate fS Unit Msps 8-bit sampling rate Msps 6-bit sampling rate Msps Doc ID 022027 Rev 5 111/141 Electrical characteristics Table 64. Symbol tS STM32L151xD STM32L152xD ADC characteristics (continued) Parameter Sampling time Conditions Min Typ Max Direct channels 2.4 V VDDA 3.6 V 0.25(5) - - Multiplexed channels 2.4 V VDDA 3.6 V 0.56(5) - - Direct channels 1.8 V VDDA 2.4 V 0.56 (5) Multiplexed channels 1.8 V VDDA 2.4 V s fADC = 16 MHz tCONV Total conversion time (including sampling time) CADC Internal sample and hold capacitor fTRIG External trigger frequency Regular sequencer fTRIG External trigger frequency Injected sequencer RAIN(6) External input impedance tlat Injection trigger conversion latency fADC = 16 MHz tlatr Regular trigger conversion latency fADC = 16 MHz tSTAB Unit - - 1(5) - - 4 - 384 1/fADC 1 - 24.75 s 4 to 384 (sampling phase) +12 (successive approximation) Direct channels - 1/fADC 16 pF Multiplexed channels - - 12-bit conversions - - 6/8/10-bit conversions - - 12-bit conversions - - Tconv+2 1/fADC 6/8/10-bit conversions - - Tconv+1 1/fADC - - 50 - - 0.5 219 - 281 ns 3.5 - 4.5 1/fADC 156 - 219 ns 2.5 - 3.5 1/fADC - - 3.5 s Tconv+1 1/fADC Tconv 1/fADC k Power-up time 1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage reference). 2. The current consumption through VREF is composed of two parameters: - one constant (max 300 A) - one variable (max 400 A), only during sampling time + 2 first conversion pulses So, peak consumption is 300+400 = 700 A and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 A at 1Msps 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pin descriptions for further details. 4. VSSA or VREF- must be tied to ground. 5. Minimum sampling and conversion time is reached for maximum Rext = 0.5 k 6. For 1 Msps, maximum Rext is 0.5 k. 112/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 65. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion Electrical characteristics Test conditions 2.4 V VDDA 3.6 V 2.4 V VREF+ 3.6 V fADC = 8 MHz, RAIN = 50 TA = -40 to 105 C 2.4 V VDDA 3.6 V VDDA = VREF+ fADC = 16 MHz, RAIN = 50 TA = -40 to 105 C 1 kHz Finput 100 kHz Min(3) Typ Max(3) - 2 4 - 1 2 - 1.5 3.5 - 1 2 - 1.7 3 9.2 10 - 57.5 62 - 57.5 62 - -74 -75 - - 4 6.5 - 2 4 - 4 6 - 1 2 ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error - 1.5 3 ET Total unadjusted error - 2 3 EO Offset error - 1 1.5 EG Gain error - 1.5 2 ED Differential linearity error - 1 2 EL Integral linearity error - 1 1.5 2.4 V VDDA 3.6 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C 1.8 V VDDA 2.4 V 1.8 V VREF+ 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 105 C Unit LSB bits dB LSB LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Based on characterization, not tested in production. Doc ID 022027 Rev 5 113/141 Electrical characteristics STM32L151xD STM32L152xD Figure 35. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 4095 4094 4093 (2) ET ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. EO=Offset Error: deviation between the first actual transition and the first ideal one. EG=Gain Error: deviation between the last ideal transition and the last actual one. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. (3) 7 (1) 6 5 EO 4 EL 3 ED 2 1 LSBIDEAL 1 0 1 VSSA 2 3 4 5 6 7 4093 4094 4095 4096 VDDA ai14395b Figure 36. Typical connection diagram using the ADC 6$$ 2!). 6!). 64 6 !).X #PARASITIC 64 6 ), N! 34-,XXX 3AMPLE AND HOLD !$# CONVERTER 2!$# BIT CONVERTER #!$# AIB 1. Refer to Table 64 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. 114/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics Figure 37. Maximum dynamic current consumption on VREF+ supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock Iref+ 700A 300A Table 66. RAIN max for fADC = 16 MHz(1) RAIN max (k) Ts (cycles) Ts (s) Multiplexed channels Direct channels 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.3 V 1.8 V < VDDA < 2.4 V 4 0.25 Not allowed Not allowed 0.7 Not allowed 9 0.5625 0.8 Not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 1. Guaranteed by design, not tested in production. Doc ID 022027 Rev 5 115/141 Electrical characteristics STM32L151xD STM32L152xD General PCB design guidelines Power supply decoupling should be performed as shown in Figure 38 or Figure 39, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. Figure 38. Power supply and reference decoupling (VREF+ not connected to VDDA) 34-,XXX 62%& SEE NOTE & N& 6$$! & N& 633! 62%&n SEE NOTE AIB 1. VREF+ and VREF- inputs are available only on 100-pin packages. Figure 39. Power supply and reference decoupling (VREF+ connected to VDDA) 34-,XXX 62%& 6$$! 3EE NOTE & N& 62%&n633! 3EE NOTE AIA 1. VREF+ and VREF- inputs are available only on 100-pin packages. 116/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.20 Electrical characteristics DAC electrical specifications Data guaranteed by design, not tested in production, unless otherwise specified. Table 67. Symbol DAC characteristics Parameter Conditions Min Typ Max 1.8 - 3.6 1.8 - 3.6 Unit VDDA Analog supply voltage VREF+ Reference supply voltage VREF- Lower reference voltage Current consumption on VREF+ supply VREF+ = 3.3 V No load, middle code (0x800) - 130 220 IDDVREF+(1) No load, worst code (0x000) - 220 350 No load, middle code (0x800) - 210 320 IDDA(1) Current consumption on VDDA supply VDDA = 3.3 V No load, worst code (0xF1C) - 320 520 RL(2) Resistive load 5 - - k - - 50 pF DAC output buffer OFF 6 8 10 k DAC output buffer ON 0.2 - VDDA - 0.2 V DAC output buffer OFF 0.5 - VREF+ - 1LSB mV CL 50 pF, RL 5 k DAC output buffer ON - 1.5 3 No RLOAD, CL 50 pF DAC output buffer OFF - 1.5 3 CL 50 pF, RL 5 k DAC output buffer ON - 2 4 No RLOAD, CL 50 pF DAC output buffer OFF - 2 4 CL 50 pF, RL 5 k DAC output buffer ON - 10 25 No RLOAD, CL 50 pF DAC output buffer OFF - 5 8 No RLOAD, CL 50 pF DAC output buffer OFF - 1.5 5 CL (2) VDAC_OUT DNL INL (1) (1) Offset(1) Offset1(1) V VSSA A DAC output buffer ON Capacitive load Output impedance RO VREF+ must always be below VDDA Voltage on DAC_OUT output Differential non Integral non linearity(3) linearity(4) Offset error at code 0x800 (5) Offset error at code 0x001(6) Doc ID 022027 Rev 5 LSB 117/141 Electrical characteristics Table 67. Symbol dOffset/dT(1) Gain(1) dGain/dT(1) TUE(1) STM32L151xD STM32L152xD DAC characteristics (continued) Parameter Offset error temperature coefficient (code 0x800) Gain error(7) Gain error temperature coefficient Total unadjusted error Conditions VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer OFF Min Typ Max -20 -10 0 Unit V/C VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer ON 0 CL 50 pF, RL 5 k DAC output buffer ON - 20 50 +0.1 / -0.2% +0.2 / -0.5% % No RLOAD, CL 50 pF DAC output buffer OFF - +0 / -0.2% +0 / -0.4% VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer OFF -10 -2 0 V/C VDDA 3.3V VREF+ 3.0V TA = 0 to 50 C DAC output buffer ON -40 -8 0 CL 50 pF, RL 5 k DAC output buffer ON - 12 30 LSB No RLOAD, CL 50 pF DAC output buffer OFF - 8 12 Settling time (full scale: for a 12-bit code transition between the lowest and C 50 pF, RL 5 k the highest input codes till L DAC_OUT reaches final value 1LSB - 7 12 s Max frequency for a correct DAC_OUT change Update rate (95% of final value) with 1 CL 50 pF, RL 5 k LSB variation in the input code - 1 Msps tSETTLING tWAKEUP Wakeup time from off state (setting the ENx bit in the DAC Control register)(8) CL 50 pF, RL 5 k - 9 15 s PSRR+ VDDA supply rejection ratio CL 50 pF, RL 5 k (static DC measurement) - -60 -35 dB 1. Data based on characterization results. 2. Connected between DAC_OUT and VSSA. 3. Difference between two consecutive codes - 1 LSB. 4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2. 118/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Electrical characteristics 6. Difference between the value measured at Code (0x001) and the ideal value. 7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA - 0.2) V when buffer is ON. 8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). Figure 40. 12-bit buffered /non-buffered DAC Buffered/Non-buffered DAC Buffer(1) R LOAD DAC_OUTx 12-bit digital to analog converter C LOAD ai17157V2 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.21 Operational amplifier characteristics Table 68. Operational amplifier characteristics Symbol CMIR Condition(1) Parameter Common mode input range Maximum calibration range VIOFFSET Min(2) Typ Max(2) 0 - VDD - - 15 Input offset voltage mV After offset calibration - - 1.5 - - 40 - - 80 - - 1 - - 10 Normal mode - - 500 Low power mode - - 100 - 100 220 - 30 60 VIOFFSET Input offset voltage Normal mode drift Low power mode IIB Input current bias ILOAD Drive current IDD Consumption Common mode rejection ration Normal mode - -85 - CMRR Low power mode - -90 - Power supply rejection ratio Normal mode - -85 - - -90 - Dedicated input General purpose input 75 C V/C nA A Normal mode PSRR Unit Low power mode No load, quiescent mode A dB DC Low power mode Doc ID 022027 Rev 5 dB 119/141 Electrical characteristics Table 68. STM32L151xD STM32L152xD Operational amplifier characteristics (continued) Symbol Condition(1) Parameter Normal mode Low power mode GBW VDD>2.4 V Max(2) 400 1000 3000 150 300 800 200 500 2200 70 150 800 Slew rate VDD<2.4 V Normal mode VDD>2.4 V (between 0.1 V and VDD-0.1 V) - 700 - Low power mode VDD>2.4 V - 100 - - 300 - - 50 - Normal mode 55 100 - Low power mode 65 110 - 4 - - 20 - - - - 50 VDD100 - - VDD-50 - - - - 100 - - 50 Normal mode Low power mode VDD<2.4 V Open loop gain Resistive load CLOAD Capacitive load VOHSAT High saturation voltage V/ms dB Normal mode RLOAD Unit kHZ Low power mode AO Typ Bandwidth Normal mode SR Min(2) Low power mode VDD<2.4 V Normal mode Low power mode Normal mode ILOAD = max or RLOAD = min k pF mV VOLSAT Low saturation voltage m Phase margin - 60 - GM Gain margin - -12 - dB tOFFTRIM Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - 1 - ms tWAKEUP low power mode Normal mode CLOAD 50 pf, RLOAD 4 k - 10 - Low power mode CLOAD 50 pf, RLOAD 20 k - 30 - Wakeup time s 1. Operating conditions are limited to junction temperature (0 C to 105 C) when VDD is below 2 V. Otherwise, the operating temperature range is 105 C to -40 C. 2. Data based on characterization results, not tested in production. 120/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.22 Electrical characteristics Temperature sensor characteristics Table 69. Temperature sensor characteristics Symbol Parameter TL(1) VSENSE linearity with temperature Avg_Slope (1) Average slope (2) Min Typ Max Unit - 1 2 C 1.48 1.61 1.75 mV/C 612 626.8 641.5 mV A V110 Voltage at 110C 5C IDDA(TEMP)(3) Current consumption - 3.4 6 tSTART(3) Startup time - - 10 TS_temp(4)(3) ADC sampling time when reading the temperature 10 - - s 1. Guaranteed by characterization, not tested in production. 2. Measured at VDD = 3 V 10 mV. V110 ADC conversion result is stored in the TSENSE_CAL2 byte. 3. Guaranteed by design, not tested in production. 4. Shortest sampling time can be determined in the application by multiple iterations. 6.3.23 Comparator Table 70. Symbol Comparator 1 characteristics Parameter Conditions Min(1) Typ Max(1) Unit 3.6 V VDDA Analog supply voltage R400K R400K value - 400 - R10K R10K value - 10 - 0.6 - VDDA - 7 10 - 3 10 - 3 10 mV 0 1.5 10 mV/1000 h - 160 260 nA VIN tSTART Comparator startup time Propagation delay Voffset Comparator offset ICOMP1 k Comparator 1 input voltage range td dVoffset/dt 1.65 s (2) Comparator offset variation in worst voltage stress conditions V VDDA 3.6 V VIN+ 0 V VIN- VREFINT TA = 25 C Current consumption(3) 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. Doc ID 022027 Rev 5 121/141 Electrical characteristics Table 71. Symbol VDDA VIN STM32L151xD STM32L152xD Comparator 2 characteristics Parameter Analog supply voltage Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ Threshold voltage temperature dt coefficient Current consumption(3) Min Typ Max(1) Unit 1.65 - 3.6 V 0 - VDDA V Fast mode - 15 20 Slow mode - 20 25 1.65 V VDDA 2.7 V - 1.8 3.5 2.7 V VDDA 3.6 V - 2.5 6 1.65 V VDDA 2.7 V - 0.8 2 2.7 V VDDA 3.6 V - 1.2 4 - 4 20 mV VDDA 3.3V TA = 0 to 50 C V- = VREF+, 3/4 VREF+, 1/2 VREF+, 1/4 VREF+. - 15 30 ppm /C Fast mode - 3.5 5 Slow mode - 0.5 2 Comparator 2 input voltage range tSTART ICOMP2 Conditions s A 1. Based on characterization, not tested in production. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 122/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 6.3.24 Electrical characteristics LCD controller (STM32L152xD only) The STM32L152xD embeds a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 72. Symbol LCD controller characteristics Parameter Min Typ Max VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.6 - VLCD1 LCD internal reference voltage 1 - 2.73 - VLCD2 LCD internal reference voltage 2 - 2.86 - VLCD3 LCD internal reference voltage 3 - 2.98 - VLCD4 LCD internal reference voltage 4 - 3.12 - VLCD5 LCD internal reference voltage 5 - 3.26 - VLCD6 LCD internal reference voltage 6 - 3.4 - VLCD7 LCD internal reference voltage 7 - 3.55 - Cext VLCD external capacitance 0.1 2 Unit V F Supply current at VDD = 2.2 V - 3.3 - Supply current at VDD = 3.0 V - 3.1 - Low drive resistive network overall value 5.28 6.6 7.92 M High drive resistive network total value 192 240 288 k V44 Segment/Common highest level voltage - - VLCD V V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage 0 - - Segment/Common level voltage error TA = -40 to 85 C - - 50 ILCD(1) RHtot(2) RL (2) Vxx(3) A V mV 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected. 2. Guaranteed by design, not tested in production. 3. Based on characterization, not tested in production. Doc ID 022027 Rev 5 123/141 Package characteristics STM32L151xD STM32L152xD 7 Package characteristics 7.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 124/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 41. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline Seating plane C A A2 A1 c b ccc 0.25 mm gage plane C D k D1 A1 D3 108 73 L L1 72 109 E1 E E3 144 Pin 1 identification 37 1 36 e ME_1A 1. Drawing is not to scale. Doc ID 022027 Rev 5 125/141 Package characteristics Table 73. STM32L151xD STM32L152xD LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0059 0.0079 D 21.80 22.00 22.20 0.8583 0.8661 0.874 D1 19.80 20.00 20.20 0.7795 0.7874 0.7953 D3 17.50 0.689 E 21.80 22.00 22.20 0.8583 0.8661 0.874 E1 19.80 20.00 20.20 0.7795 0.7874 0.7953 E3 17.50 0.689 e 0.50 0.0197 L 0.45 0.60 L1 k 0.75 0.0177 7 0 0.0236 1.00 0 3.5 ccc 3.5 0.08 0.0031 Figure 42. Recommended footprint 108 109 0.0295 0.0394 1. Values in inches are converted from mm and rounded to 4 decimal digits. 73 1.35 72 0.35 0.5 17.85 19.9 144 22.6 37 1 36 19.9 22.6 ai14905c 1. Dimensions are in millimeters. 126/141 Max Doc ID 022027 Rev 5 7 STM32L151xD STM32L152xD Package characteristics Figure 43. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline 0.25 mm 0.10 inch GAGE PLANE k D L D1 L1 D3 51 75 C 76 50 b E3 E1 E 100 26 Pin 1 1 identification 25 ccc C e A1 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. Doc ID 022027 Rev 5 127/141 Package characteristics Table 74. STM32L151xD STM32L152xD LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max A Min Typ 1.6 A1 0.05 A2 1.35 b 0.17 c 0.09 D 15.8 D1 13.8 Max 0.063 0.15 0.002 1.4 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.2 0.0035 16 16.2 0.622 0.6299 0.6378 14 14.2 0.5433 0.5512 0.5591 D3 0.0059 0.0079 12 0.4724 E 15.8 16 16.2 0.622 0.6299 0.6378 E1 13.8 14 14.2 0.5433 0.5512 0.5591 E3 12 0.4724 e 0.5 0.0197 L 0.45 0.6 L1 k ccc 0.75 0.0177 0.0236 1 0.0 0.0394 3.5 7.0 0.0 3.5 0.08 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 44. Recommended footprint 75 76 51 50 0.5 0.3 16.7 14.3 100 26 1.2 1 25 12.3 16.7 ai14906 1. Dimensions are in millimeters. 128/141 0.0295 Doc ID 022027 Rev 5 7.0 STM32L151xD STM32L152xD Package characteristics Figure 45. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline A A2 A1 E b E1 e D1 c L1 D L ai14398b 1. Drawing is not to scale. Table 75. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.09 Max 0.0630 0.15 0.0020 0.0059 1.40 1.45 0.0531 0.0551 0.0571 0.22 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 0 3.5 7 0 3.5 7 L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 Number of pins N 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022027 Rev 5 129/141 Package characteristics STM32L151xD STM32L152xD Figure 46. Recommended footprint 48 33 0.3 49 12.7 32 0.5 10.3 10.3 64 17 1.2 1 16 7.8 12.7 ai14909 1. Dimensions are in millimeters. 130/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Package characteristics Figure 47. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline A1 Ball Pad Corner Detail A 2 Top view A1 Ball Pad Corner Side view 1 Detail A rotated 90 Seating plane Bottom view A0G8_ME 1. Primary datum C and seating plane are defined by the spherical crowns of the solder balls. 2. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C. Table 76. UFBGA132 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.46 0.53 0.60 0.0181 0.0209 0.0236 A1 0.05 0.08 0.11 0.0020 0.0032 0.0043 A2 0.40 0.45 0.50 0.0157 0.0177 0.0197 b 0.17 0.28 0.33 0.0067 0.0110 0.0130 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022027 Rev 5 131/141 Package characteristics STM32L151xD STM32L152xD Figure 48. WLCSP64, 0.400 mm pitch wafer level chip size package outline $ ! CORNER $ETAIL ! % ! ! 3IDE VIEW 7AFER BACK SIDE $ETAIL ! ROTATED "UMP ! EEE B 3EATING PLANE E & ' ! E E ( ' E "UMP SIDE & !*6?-% 1. Drawing is not to scale. 132/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 77. Package characteristics WLCSP64, 0.400 mm pitch wafer level chip size package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.520 0.570 0.620 0.0205 0.0224 0.0244 A1 0.170 0.190 0.210 0.0067 0.0075 0.0083 A2 0.350 0.380 0.410 0.0138 0.0150 0.0161 b 0.240 0.270 0.300 0.0094 0.0106 0.0118 D 4.519 4.539 4.559 0.1779 0.1787 0.1795 E 4.891 4.911 4.931 0.1926 0.1933 0.1941 e 0.400 0.0157 e1 2.800 0.1102 F 0.870 0.0343 G 1.056 0.0416 eee 0.050 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 022027 Rev 5 133/141 Package characteristics 7.2 STM32L151xD STM32L152xD Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: TA max is the maximum ambient temperature in C, JA is the package junction-to-ambient thermal resistance, in C/W, PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 78. Symbol JA 134/141 Thermal characteristics Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 40 Thermal resistance junction-ambient BGA132 - 7 x 7 mm 60 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 43 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient WLCSP64 - 0.400 mm pitch 46 Doc ID 022027 Rev 5 Unit C/W STM32L151xD STM32L152xD Package characteristics Figure 49. Thermal resistance 3000.00 2500.00 'PSCJEEFOBSFB 5+5+NBY 2000.00 PD (mW) ,1&0 XMM 1500.00 7,#30 5&"'! XMM ,1&0 X XMM 1000.00 500.00 0.00 100 75 50 25 Temperature(C) 7.2.1 0 -36 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Doc ID 022027 Rev 5 135/141 Ordering information scheme 8 STM32L151xD STM32L152xD Ordering information scheme Table 79. STM32L15xxD ordering information scheme Example: STM32 L 151 R C T 6 D xxx Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low power Device subfamily 151: Devices without LCD 152: Devices with LCD Pin count R = 64 pins V = 100 pins Z = 144 pins Q = 132 pins Flash memory size D = 384 Kbytes of Flash memory Package H = BGA T = LQFP Y = WLCSP64 Temperature range 6 = Industrial temperature range, -40 to 85 C Options No character = VDD range: 1.8 to 3.6 V and BOR enabled D = VDD range: 1.65 to 3.6 V and BOR disabled Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 136/141 Doc ID 022027 Rev 5 STM32L151xD STM32L152xD 9 Revision history Revision history Table 80. Document revision history Date Revision 03-Oct-2011 1 Initial release. 2 Status of the document changed (datasheet instead of preliminary data). Updated low power features on page 1. Removed references to devices with 256 KB of Flash memory. GPIOF replaced with GIOPH. Added SDIO in Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts on page 11 and in Table 10: Alternate function input/output on page 43 (FSMC/SDIO instead of FSMC). Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts: replaced STM32L15xWx with STM32L15xQx. Figure 1: Ultra-low-power STM32L15xxD block diagram: updated legend. Modified Section 3.4: Clock management on page 21. Table 4: STM32L15xQD BGA132 ballout: replaced STM32L15xWC/D with STM32L15xQD. Figure 5, Figure 5, Figure 6: updated titles. Table 9: STM32L15xxD pin definitions: updated title, updated pins PF0, PF1, PH2, PF12, PF13, PF14, PF15, PG0, PG1, PG12, PG15, PD0, and PD1. Table 10: Alternate function input/output: Modified alternate function for PA13 and PA14; removed EVENT OUT for PH2. Figure 8: Memory map: removed the text "APB memory space". Modified Figure 11: Power supply scheme on page 54. Modified Table 3: Functionalities depending on the operating power supply range on page 16. Table 18: Current consumption in Run mode, code with data processing running from RAM: added footnote 3. Table 19: Current consumption in Sleep mode: updated condition for fHSE; added footnote 3. Table 23: Typical and maximum current consumptions in Standby mode: modified max values. Table 61: USB DC electrical characteristics: removed two footnotes. Modified Table 35: Flash memory and data EEPROM characteristics on page 82. Table 78: Thermal characteristics: updated "TBDs" with values. Modified tables in Section 6.3.4: Supply current characteristics on page 60. 03-Feb-2012 Changes Doc ID 022027 Rev 5 137/141 Revision history STM32L151xD STM32L152xD Table 80. Document revision history (continued) Date 18-Apr-2012 15-Jun-2012 138/141 Revision Changes 3 Added WLCSP64 package. Section 3.1: Low power modes: changed `128 kHz' to `131 kHz' in section "Low power run mode". Section 3.17.1: General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11): changed `six' to `seven' synchronizable general-purpose timers. Table 9: STM32L15xxD pin definitions on page 37: updated name of reference manual in footnote 5. I2C updated: footnote 3. from Table 55 Note about I2C clock updated: footnote 2. from Table 55 modified. Note [non-robust] updated: footnote 2. from Table 65 modified. GPIOs high current capability updated: Section 3.6: GPIOs (generalpurpose inputs/outputs) `except for analog inputs' was removed. 4 Changed maximum number of touch sensing channels to 34, and updated Table 2: Ultra-low-power STM32L15xxD device features and peripheral counts. Updated Section 3.11: ADC (analog-to-digital converter) to add Section 3.11.1: Temperature sensor and Section 3.11.2: Internal voltage reference (VREFINT). Removed caution note below Figure 11: Power supply scheme. Added note below Table 4: STM32L15xQD BGA132 ballout. Modified Table 7: STM32L15xRD WLCSP64 ballout to match top view. Changed FSMC_LBAR into FSMC_NADV, and I2C1_SMBAI into I2C1_SMBA in Table 9: STM32L15xxD pin definitions. Modified PB10/11/12 for AFIO4 alternate function, and replaced LBAR by NADV for AFIO12 in Table 10: Alternate function input/output. Updated Table 22: Typical and maximum current consumptions in Stop mode and added Note 6. Updated Table 23: Typical and maximum current consumptions in Standby mode. Updated tWUSTOP in Table 24: Typical and maximum timings in Low power modes. Updated Table 25: Peripheral current consumption. Updated Table 57: SPI characteristics, added Note 1 and Note 3, and applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI), th(MI), and th(SI). Updated IDD maximum value in Table 35: Flash memory and data EEPROM characteristics. Doc ID 022027 Rev 5 STM32L151xD STM32L152xD Table 80. Revision history Document revision history (continued) Date 25-Oct-2012 Revision Changes 5 Updated Features Updated Figure 1: Ultra-low-power STM32L15xxD block diagram Added Table 5: Functionalities depending on the working mode (from Run/active down to standby), and Table 9: CPU frequency range depending on dynamic voltage scaling Updated Figure 5: STM32L15xVD LQFP100 pinout Updated Table 9: STM32L15xxD pin definitions Added Note 2 in Table 15: Embedded reset and power control block characteristics Replaced TBD values in Table 27: Low-speed external user clock characteristics, Table 35: Flash memory and data EEPROM characteristics and Table 52: I/O AC characteristics Added Table 58: I2S characteristics, Figure 31: I2S slave timing diagram (Philips protocol)(1) and Figure 32: I2S master timing diagram (Philips protocol)(1) Added Table 59: SDIO characteristics Added Figure 33: SDIO timings Updated Section 6.3.9: FSMC characteristics Updated Table 69: Temperature sensor characteristics Added Figure 49: Thermal resistance Doc ID 022027 Rev 5 139/141 STM32L151xD STM32L152xD Please Read Carefully: Information in this document is provided solely in connection with ST products. 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