LM1877
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
LM1877 Dual Audio Power Amplifier
Check for Samples: LM1877
1FEATURES DESCRIPTION
The LM1877 is a monolithic dual power amplifier
2• 2W/Channel designed to deliver 2W/channel continuous into 8Ω
•−65 dB Ripple Rejection, Output Referred loads. The LM1877 is designed to operate with a low
•−65 dB Channel Separation, Output Referred number of external components, and still provide
flexibility for use in stereo phonographs, tape
• Wide Supply Range, 6V–24V recorders and AM-FM stereo receivers. Each power
• Very Low Cross-Over Distortion amplifier is biased from a common internal regulator
• Low Audio Band Noise to provide high power supply rejection, and output Q
point centering. The LM1877 is internally
• AC Short Circuit Protected compensated for all gains greater than 10.
• Internal Thermal Shutdown
APPLICATIONS
• Multi-Channel Audio Systems
• Stereo Phonographs
• Tape Recorders and Players
• AM-FM Radio Receivers
• Servo Amplifiers
• Intercom Systems
• Automotive Products
Connection Diagram
Figure 1. 14-Pin SOIC or PDIP (Top View)
See NPA0014B or NFF0014A Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1995–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM1877
SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
www.ti.com
Equivalent Schematic Diagram
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage 26V
Input Voltage ±0.7V
Operating Temperature 0°C to +70°C
Storage Temperature −65°C to +150°C
Junction Temperature 150°C
Lead Temperature PDIP Package Soldering (10 sec.) 260°C
SOIC Package Infrared (15 sec.) 220°C
SOIC Package Vapor Phase (60 sec.) 215°C
Thermal Resistance θJC (PDIP Package) 30°C/W
θJA (PDIP Package) 79°C/W
θJC (SOIC Package) 27°C/W
θJA (SOIC Package) 114°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
2Submit Documentation Feedback Copyright © 1995–2013, Texas Instruments Incorporated
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LM1877
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
Electrical Characteristics
VS= 20V, TA= 25°C(1) RL= 8Ω, AV= 50 (34 dB) unless otherwise specified
Parameter Conditions Min Typ Max Units
Total Supply Current PO= 0W 25 50 mA
Output Power THD = 10%
LM1877 VS= 20V, RL= 8Ω2.0 W/Ch
VS= 12V, RL= 8Ω1.3 W/Ch
Total Harmonic Distortion f = 1 kHz, VS= 14V
LM1877 PO= 50 mW/Channel 0.075 %
PO= 500 mW/Channel 0.045 %
PO= 1 W/Channel 0.055 %
Output Swing RL= 8ΩVS−6 Vp-p
Channel Separation CF= 50 μF, CIN = 0.1 μF,
f = 1 kHz, Output Referred
VS= 20V, VO= 4 Vrms −50 −70 dB
VS= 7V, VO= 0.5 Vrms −60 dB
PSRR Power Supply CF= 50 μF, CIN = 0.1 μF,
Rejection Ratio f = 120 Hz, Output Referred
VS= 20V, VRIPPLE = 1 Vrms −50 −65 dB
VS= 7V, VRIPPLE = 0.5 Vrms −40 dB
Noise Equivalent Input Noise
RS= 0, CIN = 0.1 μF, 2.5 μV
BW = 20 Hz–20 kHz, Output Noise Wideband
RS= 0, CN= 0.1 μF, AV200 0.80 mV
Open Loop Gain RS= 0, f = 100 kHz, RL= 8Ω70 dB
Input Offset Voltage 15 mV
Input Bias Current 50 nA
Input Impedance Open Loop 4 MΩ
DC Output Level VS= 20V 9 10 11 V
Slew Rate 2.0 V/μs
Power Bandwidth 65 kHz
Current Limit 1.0 A
(1) For operation at ambient temperature greater than 25°C, the LM1877 must be derated based on a maximum 150°C junction
temperature.
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
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Typical Performance Characteristics
Power Supply Rejection Ratio (Referred to the Output) vs
Device Dissipation vs Ambient Temperature Frequency
Figure 2. Figure 3.
Power Supply Rejection Ratio (Referred to the Output) vs Power Supply Rejection Ratio (Referred to the Output) vs
Frequency Supply Voltage
Figure 4. Figure 5.
Channel Separation (Referred to the Output) vs Frequency Channel Separation (Referred to the Output) vs Frequency
Figure 6. Figure 7.
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
Typical Performance Characteristics (continued)
Average Supply Current vs POUT Total Harmonic Distortion vs Frequency
Figure 8. Figure 9.
Total Harmonic Distortion vs Frequency Power Dissipation (W) Both Channels Operating
Figure 10. Figure 11.
Open Loop Gain vs Frequency Output Swing vs Supply Voltage
Figure 12. Figure 13.
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LM1877
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
Figure 15. Frequency Response of Bass Tone Figure 16. Inverting Unity Gain Amplifier
Control
Figure 17. Stereo Amplifier with AV= 200
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SNAS550B –FEBRUARY 1995–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision A (April 2013) to Revision B Page
• Changed layout of National Data Sheet to TI format ............................................................................................................ 7
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PACKAGE OPTION ADDENDUM
www.ti.com 27-Oct-2016
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM1877MX-9/NOPB ACTIVE SOIC NPA 14 1000 Green (RoHS
& no Sb/Br) CU SN Level-3-260C-168 HR 0 to 70 LM1877M
-9
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 27-Oct-2016
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM1877MX-9/NOPB SOIC NPA 14 1000 330.0 16.4 10.9 9.5 3.2 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM1877MX-9/NOPB SOIC NPA 14 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
NPA0014B
www.ti.com
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