HN58X2408SI/HN58X2416SI Two-wire serial interface 8k EEPROM (1-kword x 8-bit) 16k EEPROM (2-kword x 8-bit) REJ03C0097-0100Z Rev. 1.00 Oct. 21, 2003 Description HN58X24xxSI series are two-wire serial interface EEPROM (Electrically Erasable and Programmable ROM). They realize high speed, low power consumption and a high level of reliability by employing advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also have a 32-byte page programming function to make their write operation faster. Note: Renesas Technology's serial EEPROM are authorized for using consumer applications such as cellular phone, camcorders, audio equipment. Therefore, please contact Renesas Technology's sales office before using industrial applications such as automotive systems, embedded controllers, and meters. Features * Single supply: 1.8 V to 5.5 V * Two-wire serial interface (I C 2 TM 1 serial bus* ) * Clock frequency: 400 kHz * Power dissipation: Standby: 3 A (max) Active (Read): 1 mA (max) Active (Write): 3 mA (max) * Automatic page write: 32-byte/page * Write cycle time: 10 ms (2.7 V to 5.5 V)/15ms (1.8 V to 2.7 V) * Endurance: 10 Cycles (Page write mode) 5 * Data retention: 10 Years * Small size packages: TSSOP-8pin, SOP-8pin and SON 8-pin * Shipping tape and reel TSSOP 8-pin: 3,000 IC/reel SOP 8-pin: 2,500 IC/reel SON 8-pin: 3,000 IC/reel * Temperature range: -40 to +85C * There are also lead free products. 2 Note: 1. I C is a trademark of Philips Corporation. Rev.1.00, Oct. 21. 2003, page 1 of 21 HN58X2408SI/HN58X2416SI Ordering Information Type No. Internal organization Operating voltage Frequency Package HN58X2408SFPI 8k bit (1024 x 8-bit) 400 kHz HN58X2416SFPI 16k bit (2048 x 8-bit) HN58X2408STI 8k bit (1024 x 8-bit) 1.8 V to 5.5 V 150 mil 8-pin plastic SOP (FP-8DB) 1.8 V to 5.5 V 400 kHz 8-pin plastic TSSOP (TTP-8DA) HN58X2416STI 16k bit (2048 x 8-bit) HN58X2408SNI 8k bit (1024 x 8-bit) HN58X2416SNI 16k bit (2048 x 8-bit) HN58X2408SFPIE 8k bit (1024 x 8-bit) HN58X2416SFPIE 16k bit (2048 x 8-bit) HN58X2408STIE 8k bit (1024 x 8-bit) HN58X2416STIE 16k bit (2048 x 8-bit) HN58X2408SNIE 8k bit (1024 x 8-bit) HN58X2416SNIE 16k bit (2048 x 8-bit) 1.8 V to 5.5 V 400 kHz 8-pin plastic SON (TNP-8DA) 1.8 V to 5.5 V 400 kHz Lead Free 1.8 V to 5.5 V 400 kHz 8-pin plastic TSSOP (TTP-8DAV) Lead Free 1.8 V to 5.5 V 400 kHz 8-pin plastic SON (TNP-8DAV) Lead Free Pin Arrangement 8-pin TSSOP 8-pin SOP 8-pin SON A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA (Top view) Rev.1.00, Oct. 21, 2003, page 2 of 21 150 mil 8-pin plastic SOP (FP-8DBV) HN58X2408SI/HN58X2416SI Pin Description Pin name Function A0 to A2 Device address SCL Serial clock input SDA Serial data input/output WP Write protect VCC Power supply VSS Ground Block Diagram High voltage generator Control logic A0, A1, A2 SCL X decoder WP Address generator VSS Memory array Y decoder VCC Y-select & Sense amp. SDA Serial-parallel converter Absolute Maximum Ratings Parameter Symbol Value Supply voltage relative to VSS VCC -0.6 to +7.0 Vin -0.5* to +7.0* Topr -40 to +85 C Tstg -65 to +125 C Input voltage relative to VSS Operating temperature range* 1 Storage temperature range 2 Notes: 1. Including electrical characteristics and data retention. 2. Vin (min): -3.0 V for pulse width 50 ns. 3. Should not exceed VCC + 1.0 V. Rev.1.00, Oct. 21, 2003, page 3 of 21 Unit V 3 V HN58X2408SI/HN58X2416SI DC Operating Conditions Parameter Symbol Min Typ Max Unit Supply voltage VCC 1.8 5.5 V VSS 0 0 0 V VIH VCC x 0.7 VCC + 1.0 V Input low voltage VIL -0.3* VCC x 0.3 V Operating temperature Topr -40 +85 C Input high voltage Note: 1 1. VIL (min): -1.0 V for pulse width 50 ns. DC Characteristics (Ta = -40 to +85C, VCC = 1.8 V to 5.5 V) Parameter Symbol Min Typ Max Unit Test conditions Input leakage current ILI 2.0 A VCC = 5.5 V, Vin = 0 to 5.5 V Output leakage current ILO 2.0 A VCC = 5.5 V, Vout = 0 to 5.5 V Standby VCC current ISB 1.0 3.0 A Vin = VSS or VCC Read VCC current ICC1 1.0 mA VCC = 5.5 V, Read at 400 kHz Write VCC current ICC2 3.0 mA VCC = 5.5 V, Write at 400 kHz Output low voltage VOL2 0.4 V VCC = 4.5 to 5.5 V, IOL = 1.6 mA VCC = 2.7 to 4.5 V, IOL = 0.8 mA VCC = 1.8 to 2.7 V, IOL = 0.4 mA VOL1 0.2 V VCC = 1.8 to 2.7 V, IOL = 0.2 mA Capacitance (Ta = +25C, f = 1 MHz) Parameter Min Typ Max Unit Test conditions 1 6.0 pF Vin = 0 V 1 6.0 pF Vout = 0 V Symbol Input capacitance (A0 to A2, SCL, WP) Cin* Output capacitance (SDA) Note: CI/O* 1. This parameter is sampled and not 100% tested. Rev.1.00, Oct. 21, 2003, page 4 of 21 HN58X2408SI/HN58X2416SI AC Characteristics (Ta = -40 to +85C, VCC = 1.8 to 5.5 V) Test Conditions * Input pulse levels: VIL = 0.2 x VCC VIH = 0.8 x VCC * Input rise and fall time: 20 ns * Input and output timing reference levels: 0.5 x VCC * Output load: TTL Gate + 100 pF Parameter Symbol Min Typ Max Unit Clock frequency fSCL 400 kHz Clock pulse width low tLOW 1200 ns Clock pulse width high tHIGH 600 ns Noise suppression time tI 50 ns Access time tAA 100 900 ns Bus free time for next mode tBUF 1200 ns Start hold time tHD.STA 600 ns Start setup time tSU.STA 600 ns Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 100 ns Input rise time tR 300 ns 1 Input fall time tF 300 ns 1 Stop setup time tSU.STO 600 ns Data out hold time tDH 50 ns Write protect hold time tHD.WP 1200 ns Write protect setup time tSU.WP 0 ns Write cycle time VCC = 2.7 V to 5.5 V tWC 10 ms 2 VCC = 1.8 V to 2.7 V tWC 15 ms 2 Notes: 1. This parameter is sampled and not 100% tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. Rev.1.00, Oct. 21, 2003, page 5 of 21 Notes 1 HN58X2408SI/HN58X2416SI Timing Waveforms Bus Timing tF tHIGH 1/fSCL tLOW tR SCL tSU.STA tHD.DAT tSU.DAT tHD.STA tSU.STO SDA (in) tBUF tAA tDH SDA (out) tSU.WP tHD.WP WP Write Cycle Timing Stop condition Start condition SCL SDA D0 in Write data (Address (n)) ACK Rev.1.00, Oct. 21, 2003, page 6 of 21 tWC (Internally controlled) HN58X2408SI/HN58X2416SI Pin Function Serial Clock (SCL) The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz. Serial Input/Output Data (SDA) The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance. Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed during the SCL low period. Data Validity (SDA data change timing waveform) SCL SDA Data change Note: Data change High-to-low and low-to-high change of SDA should be done during the SCL low period. Rev.1.00, Oct. 21, 2003, page 7 of 21 HN58X2408SI/HN58X2416SI Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. As for 8k to 16k EEPROM, whole or some device address pins don't need to be fixed since device address code provided from the SDA pin is used as memory address signal. Pin Connections for A0 to A2 Pin connection Max connect Memory size number A2 8k bit 2 VCC/VSS* x* 16k bit 1 x A1 1 2 x A0 Notes x Use A0, A1 for memory address a8 and a9 x Use A0, A1, A2 for memory address a8, a9 and a10 Notes: 1. "VCC/VSS" means that device address pin should be connected to VCC or VSS. 2. x = Don't care (Open is also approval.) Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated irrespective of the WP pin status. WP pin should be fixed high or low status from start condition input to stop condition input. When left unconnected, write operation for all memory arrays are allowed because the WP pin is internally pulled down to VSS. The read operation is always activated irrespective of the WP pin status. Write Protect Area WP pin status Write protect area VIH All memory VIL Normal read/write operation Rev.1.00, Oct. 21, 2003, page 8 of 21 HN58X2408SI/HN58X2416SI Functional Description Start Condition A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation. (See start condition and stop condition) Stop Condition A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in an internally-timed write cycle to the memories. After the internally-timed write cycle which is specified as tWC, the device enters a standby mode. (See write cycle timing) Start Condition and Stop Condition SCL SDA (in) Start condition Rev.1.00, Oct. 21, 2003, page 9 of 21 Stop condition HN58X2408SI/HN58X2416SI Acknowledge All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a zero to acknowledge that it has received each word. This happens during ninth clock cycle. The transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation, EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data, the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open without sending read data. Acknowledge Timing Waveform SCL 1 SDA IN SDA OUT Rev.1.00, Oct. 21, 2003, page 10 of 21 2 8 9 Acknowledge out HN58X2408SI/HN58X2416SI Device Addressing The EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to distinguish device type and this EEPROM uses "1010" fixed code. The device address word is followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of all devices which are connected to the bus. This means that the device is selected if the inputted 3bit device address code is equal to the corresponding hard-wired A2-A0 pin status. As for the 8kbit and 16kbit EEPROMs, whole or some bits of their device address code may be used as the memory address bits. For example, A0 and A1 are used as a8 and a9 for the 8kbit. The 16kbit doesn't use the device address code instead all 3 bits are used as the memory address bits a8, a9 and a10. The eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by state if the device code is not "1010" or device address code doesn't coincide with status of the correspond hard-wired device address pins A0 to A2. Device Address Word Device address word (8-bit) Device code (fixed) Device address code* 1 R/W code* 8k 1 0 1 0 A2 a9 a8 R/W 16k 1 0 1 0 a10 a9 a8 R/W Notes: 1. A2 to A0 are device address and a10 to a8 are memory address. 2. R/W="1" is read and R/W = "0" is write. Rev.1.00, Oct. 21, 2003, page 11 of 21 2 HN58X2408SI/HN58X2416SI Write Operations Byte Write: A write operation requires an 8-bit device address word with R/W = "0". Then the EEPROM sends acknowledgment "0" at the ninth clock cycle. After these, the 8kbit to 16kbit EEPROMs receive 8-bit memory address word. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM returns to a standby mode after completion of the write cycle. 8k to 16k 1010 Start Rev.1.00, Oct. 21, 2003, page 12 of 21 W Memory address (n) Write data (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Byte Write Operation ACK R/W ACK ACK Stop HN58X2408SI/HN58X2416SI Page Write: The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to be written in a single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The page write is initiated by a start condition, device address word, memory address(n) and write data(Dn) with every ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data(Dn+1) instead of receiving a stop condition. The a0 to a4 address bits are automatically incremented upon receiving write data(Dn+1). The EEPROM can continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the last address of the page, the a0 to a4 address bits will roll over to the first address of the same page and previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters internally-timed write cycle. Start 1010 W Write data (n) ACK R/W Rev.1.00, Oct. 21, 2003, page 13 of 21 ACK ACK Write data (n+m) D5 D4 D3 D2 D1 D0 8k to 16k Memory address (n) D7 D6 D5 D4 D3 D2 D1 D0 Device address a7 a6 a5 a4 a3 a2 a1 a0 Page Write Operation Stop ACK HN58X2408SI/HN58X2416SI Acknowledge Polling: Acknowledge polling feature is used to show if the EEPROM is in an internally-timed write cycle or not. This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device address word following the start condition during an internally-timed write cycle. Acknowledge polling will operate when the R/W code = "0". Acknowledgment "1" (no acknowledgment) shows the EEPROM is in an internally-timed write cycle and acknowledgment "0" shows that the internally-timed write cycle has completed. See Write Cycle Polling using ACK. Write Cycle Polling Using ACK Send write command Send stop condition to initiate write cycle Send start condition Send device address word with R/W = 0 ACK returned No Yes Next operation is addressing the memory No Yes Proceed write operation Send memory address Send start condition Proceed random address read operation Send stop condition Rev.1.00, Oct. 21, 2003, page 14 of 21 Send stop condition HN58X2408SI/HN58X2416SI Read Operation There are three read operations: current address read, random read, and sequential read. Read operations are initiated the same way as write operations with the exception of R/W = "1". Current Address Read: The internal address counter maintains the last address accessed during the last read or write operation, with incremented by one. Current address read accesses the address kept by the internal address counter. After receiving a start condition and the device address word(R/W is "1"), the EEPROM outputs the 8-bit current address data from the most significant bit following acknowledgment "0". If the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition, the EEPROM stops the read operation and is turned to a standby state. In case the EEPROM has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. In case the EEPROM has accessed the last address of the page at previous write operation, the current address will roll over within page addressing and returns to the first address in the same page. The current address is valid while power is on. The current address after power on will be indefinite. The random read operation described below is necessary to define the memory address. Current Address Read Operation Device address Read data (n+1) 1010 Start R D7 D6 D5 D4 D3 D2 D1 D0 *1 *2 *3 8k to 16k ACK R/W No ACK Notes: 1. Don`t care bit for 16k. 2. Don`t care bits for 8k and 16k. 3. Don`t care bits for 8k and 16k. Rev.1.00, Oct. 21, 2003, page 15 of 21 Stop HN58X2408SI/HN58X2416SI Random Read: This is a read operation with defined read address. A random read requires a dummy write to set read address. The EEPROM receives a start condition, device address word(R/W=0) and memory address (8-bit for 8kbit to 16kbit EEPROMs) sequentially. The EEPROM outputs acknowledgment "0" after receiving memory address then enters a current address read with receiving a start condition. The EEPROM outputs the read data of the address which was defined in the dummy write operation. After receiving acknowledgment "1"(no acknowledgment) and a following stop condition, the EEPROM stops the random read operation and returns to a standby state. Random Read Operation Start 1010 @@@ W ACK R/W Dummy write Device address 1010 Start ACK Read data (n) # # # R D7 D6 D5 D4 D3 D2 D1 D0 8k to 16k Memory address (n) a7 a6 a5 a4 a3 a2 a1 a0 Device address ACK No ACK Stop R/W Currect address read Note: 1. 2nd device address code (#) should be same as 1st (@). Rev.1.00, Oct. 21, 2003, page 16 of 21 HN58X2408SI/HN58X2416SI Sequential Read: Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives acknowledgment "0" after 8-bit read data, the read address is incremented and the next 8-bit read data are coming out. This operation can be continued as long as the EEPROM receives acknowledgment "0". The address will roll over and returns address zero if it reaches the last address of the last page. The sequential read can be continued after roll over. The sequential read is terminated if the EEPROM receives acknowledgment "1" (no acknowledgment) and a following stop condition. Sequential Read Operation ACK R/W Rev.1.00, Oct. 21, 2003, page 17 of 21 ACK ACK ACK D5 D4 D3 D2 D1 D0 R Read data (n+1) Read data (n+2) Read data (n+m) D7 D6 D5 D4 D3 D2 D1 D0 Start 1010 Read data (n) D7 D6 D5 D4 D3 D2 D1 D0 8k to 16k D7 D6 D5 D4 D3 D2 D1 D0 Device address No ACK Stop HN58X2408SI/HN58X2416SI Notes Data Protection at VCC On/Off When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc) may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional programming, this EEPROM has a power on reset function. Be careful of the notices described below in order for the power on reset function to operate correctly. * SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition during VCC on/off may cause the trigger for the unintentional programming. * VCC should be turned off after the EEPROM is placed in a standby state. * VCC should be turned on from the ground level(VSS) in order for the EEPROM not to enter the unintentional programming mode. * VCC turn on speed should be longer than 10 s. Write/Erase Endurance and Data Retention Time 5 4 The endurance is 10 cycles in case of page programming and 10 cycles in case of byte programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is page-programmed 4 less than 10 cycles. Noise Suppression Time This EEPROM have a noise suppression function at SCL and SDA inputs, that cut noise of width less than 50 ns. Be careful not to allow noise of width more than 50 ns. Rev.1.00, Oct. 21, 2003, page 18 of 21 HN58X2408SI/HN58X2416SI Package Dimensions HN58X2408SFPI/HN58X2416SFPI (FP-8DB) HN58X2408SFPIE/HN58X2416SFPIE (FP-8DBV) Unit: mm 3.90 4.89 5.15 Max 5 8 0.69 Max 0.034 *0.22 +- 0.017 0.20 0.03 4 1.73 Max 1 6.02 0.18 1.06 *0.42 +0.063 -0.064 0.40 0.06 0.114 0.14 +- 0.038 0 - 8 1.27 + 0.289 0.60 - 0.194 0.10 0.25 M *Dimension including the plating thickness Base material dimension Rev.1.00, Oct. 21, 2003, page 19 of 21 Package Code JEDEC JEITA Mass (reference value) FP-8DB, FP-8DBV -- -- 0.08 g HN58X2408SI/HN58X2416SI HN58X2408STI/HN58X2416STI (TTP-8DA) HN58X2408STIE/HN58X2416STIE (TTP-8DAV) Unit: mm 4.40 3.00 3.30 Max 8 5 1 4 0.65 *0.22 +0.08 -0.07 0.20 0.06 1.00 0.13 M 6.40 0.20 *Dimension including the plating thickness Base material dimension Rev.1.00, Oct. 21, 2003, page 20 of 21 0.07 +0.03 -0.04 0.10 *0.17 0.05 0.15 0.04 1.10 Max 0.805 Max 0 - 8 0.50 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-8DA, TTP-8DAV -- -- 0.034 g HN58X2408SI/HN58X2416SI HN58X2408SNI/HN58X2416SNI (TNP-8DA) HN58X2408SNIE/HN58X2416SNIE (TNP-8DAV) Unit: mm 3.00 3.10 Max 5 *0.18 0.05 0.16 0.025 3.60 8 + 0.08 0.22 - 0.07 4 0.65 4.06 0.1 + 0.055 *0.145 - 0.045 0.125 0.02 0.675 Max 0.80 Max 1 0.23 0.10 0.08 M *Dimension including the plating thickness Base material dimension Rev.1.00, Oct. 21, 2003, page 21 of 21 Package Code JEDEC JEITA Mass (reference value) TNP-8DA, TNP-8DAV -- -- 0.022 g Revision History Rev. Date HN58X2408SI/HN58X2416SI Data Sheet Contents of Modification Page Description 0.01 Sep. 30, 2003 Initial issue 1.00 Oct. 21, 2003 2 Deletion of Preliminary Ordering Information Addition of HN58X2408SFPIE, HN58X2416SFPIE, HN58X2408STIE, HN58X2416STIE, HN58X2408SNIE, HN58X2416SNIE Package Dimensions FP-8DB to FP-8DB, FP-8DBV TTP-8DA to TTP-8DA, TTP-8DAV TNP-8DA to TNP-8DA, TNP-8DAV 19 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 (c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 1.0