HUF76121S3S - Intersil Corporation

CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.

UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

HUF76121P3, HUF76121S3S

47A, 30V, 0.021 Ohm, N-Channel, Logic

Level UltraFET Power MOSFETs

These N-Channel power MOSFETs

are manufactured using the

innovative UltraFET™ process.

This advanced process technology

achieves the lowest possible on-resistance per silicon area,

resulting in outstanding performance. This device is capable

of withstanding high energy in the avalanche mode and the

diode exhibits very low reverse recovery time and stored

charge. It was designed for use in applications where power

efﬁciency is important, such as switching regulators,

switching converters, motor drivers, relay drivers, low-

voltage bus switches, and power management in portable

and battery-operated products.

Formerly developmental type TA76121.

Features

• Logic Level Gate Drive

• 47A, 30V

• Ultra Low On-Resistance, rDS(ON) = 0.021Ω

• Temperature Compensating PSPICE® Model

• Temperature Compensating SABER© Model

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount

Components to PC Boards”

Symbol

Packaging

JEDEC TO-220AB JEDEC TO-263AB

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76121P3 TO-220AB 76121P

HUF76121S3S TO-263AB 76121S

NOTE: When ordering, use the entire part number. Add the suffix T to

obtain the TO-263AB variant in tape and reel, e.g., HUF76121S3ST.

DRAIN

SOURCE

GATE

DRAIN

(FLANGE)

GATE

SOURCE

DRAIN

(FLANGE)

Data Sheet September 1999 File Number

4392.8

Absolute Maximum Ratings TC= 25oC, Unless Otherwise Specified UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS 30 V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR 30 V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V

Drain Current

Continuous (TC = 25oC, VGS = 10V) (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuous (TC = 100oC, VGS = 5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM

Figure 4

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Figures 6, 17,18

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

0.6 W

W/oC

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -40 to 150 oC

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300

260

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. TJ = 25oC to 150oC.

Electrical Speciﬁcations TA= 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 30 - - V

Zero Gate Voltage Drain Current IDSS VDS = 25V, VGS = 0V - - 1 µA

VDS = 25V, VGS = 0V, TC = 150oC - - 250 µA

Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V

Drain to Source On Resistance rDS(ON) ID = 47A, VGS = 10V (Figures 9, 10) - 0.015 0.021 Ω

ID = 25A, VGS = 5V (Figure 9) - 0.019 0.028 Ω

ID = 24A, VGS = 4.5V (Figure 9) - 0.021 0.031 Ω

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.66 oC/W

Thermal Resistance Junction to Ambient RθJA TO-220 and TO-263 - - 62 oC/W

SWITCHING SPECIFICATIONS (VGS = 4.5V)

Turn-On Time tON VDD = 15V, ID≅ 24A, RL = 0.63Ω,

VGS =4.5V, RGS = 10.0Ω

(Figures 15, 21, 22)

- - 265 ns

Turn-On Delay Time td(ON) -15-ns

Rise Time tr- 160 - ns

Turn-Off Delay Time td(OFF) -14-ns

Fall Time tf-31-ns

Turn-Off Time tOFF - - 70 ns

HUF76121P3, HUF76121S3S

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time tON VDD = 15V, ID≅ 47A, RL = 0.32Ω,

VGS = 10V, RGS = 12.5Ω

(Figures 16, 21, 22)

- - 80 ns

Turn-On Delay Time td(ON) -6-ns

Rise Time tr-47-ns

Turn-Off Delay Time td(OFF) -47-ns

Fall Time tf-42-ns

Turn-Off Time tOFF - - 135 ns

GATE CHARGE SPECIFICATIONS

Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 15V, ID≅ 25A,

RL = 0.6Ω

Ig(REF) = 1.0mA

(Figures 14, 19, 20)

-2430nC

Gate Charge at 5V Qg(5) VGS = 0V to 5V - 13 16 nC

Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 1.0 1.2 nC

Gate to Source Gate Charge Qgs - 2.50 - nC

Gate to Drain “Miller” Charge Qgd - 7.80 - nC

CAPACITANCE SPECIFICATIONS

Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz

(Figure 13) - 850 - pF

Output Capacitance COSS - 465 - pF

Reverse Transfer Capacitance CRSS - 100 - pF

Electrical Speciﬁcations TA= 25oC, Unless Otherwise Specified (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Speciﬁcations

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage VSD ISD = 25A - - 1.25 V

Reverse Recovery Time trr ISD = 25A, dISD/dt = 100A/µs--65ns

Reverse Recovered Charge QRR ISD = 25A, dISD/dt = 100A/µs - - 100 nC

Typical Performance Curves

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE

TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

TA, AMBIENT TEMPERATURE (oC)

POWER DISSIPATION MULTIPLIER

00 25 50 75 100 150

0.2

0.4

0.6

0.8

1.0

1.2

125 0

ID, DRAIN CURRENT (A)

TC, CASE TEMPERATURE (oC)

VGS = 10V

VGS = 4.5V

50 75 100 125 150

HUF76121P3, HUF76121S3S

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

FIGURE 4. PEAK CURRENT CAPABILITY

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

Typical Performance Curves

(Continued)

0.01

0.1

10-5 10-4 10-3 10-2 10-1 100101

ZθJC, NORMALIZED

THERMAL IMPEDANCE

SINGLE PULSE NOTES:

DUTY FACTOR: D = t1/t2

PEAK TJ = PDM x ZθJC x RθJC + TC

PDM

t1t2

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.01

0.02

t, RECTANGULAR PULSE DURATION (s)

TC = 25oC

I = I25 150 - TC

125

FOR TEMPERATURES

ABOVE 25oC DERATE PEAK

CURRENT AS FOLLOWS:

VGS = 10V

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

VGS = 5V

100

1000

10-5 10-4 10-3 10-2 10-1 100101

IDM, PEAK CURRENT (A)

t, PULSE WIDTH (s)

100

1000

1 10 100

TJ = MAX RATED

TC = 25oC

100µs

10ms

1ms

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

LIMITED BY rDS(ON)

AREA MAY BE

OPERATION IN THIS

BVDSS MAX = 30V 1

100

0.001 0.01 0.1 1 10 100

500

IAS, AVALANCHE CURRENT (A)

tAV, TIME IN AVALANCHE (ms)

tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)

If R = 0

If R ≠ 0

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

STARTING TJ = 25oC

STARTING TJ = 150oC

HUF76121P3, HUF76121S3S

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

FIGURE 9. SOURCE TO DRAIN ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs

JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

Typical Performance Curves

(Continued)

100

012345

, DRAIN CURRENT (A)

VGS, GATE TO SOURCE VOLTAGE (V)

150oC

-40oC

25oC

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VDD = 15V 0

100

012345

, DRAIN CURRENT (A)

VDS, DRAIN TO SOURCE VOLTAGE (V)

VGS = 4V

VGS = 3V

VGS = 3.5V

VGS = 4.5V

VGS = 10V

VGS = 5V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

246810

GS, GATE TO SOURCE VOLTAGE (V)

ID = 47A

ID = 28A

ID = 15A

rDS(ON), DRAIN TO SOURCE

ON RESISTANCE (mΩ)

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

1.0

1.2

1.4

1.6

-60 0 60 120 180

0.8

NORMALIZED DRAIN TO SOURCE

TJ, JUNCTION TEMPERATURE (oC)

ON RESISTANCE

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

VGS = 10V, ID = 47A

0.8

1.0

1.2

-60 0 60 120 180

0.6

NORMALIZED GATE

TJ, JUNCTION TEMPERATURE (oC)

THRESHOLD VOLTAGE

VGS = VDS, ID = 250µA

1.0

1.1

1.2

-60.0 0.0 60.0 120 180

0.9

TJ, JUNCTION TEMPERATURE (oC)

ID = 250µA

NORMALIZED DRAIN TO SOURCE

BREAKOWN VOLTAGE

HUF76121P3, HUF76121S3S

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

Typical Performance Curves

(Continued)

300

600

900

1200

0 5 10 15 20 25 30

C, CAPACITANCE (pF)

VDS, DRAIN TO SOURCE VOLTAGE (V)

CISS

COSS

CRSS

VGS = 0V, f = 1MHz

CISS = CGS + CGD

CRSS = CGD

COSS ≈ CDS + CGD

0 5 10 15 20 25

VGS, GATE TO SOURCE VOLTAGE (V)

VDD = 15V

Qg, GATE CHARGE (nC)

ID = 47A

ID = 28A

ID = 15A

WAVEFORMS IN

DESCENDING ORDER:

100

200

300

400

500

10 20 30 40 50

00RGS, GATE TO SOURCE RESISTANCE (Ω)

VGS = 4.5V, VDD = 15V, ID = 24A, RL = 0.63Ω

td(OFF) tf

td(ON)

SWITCHING TIME (ns)

100

150

200

10 20 30 40 50

SWITCHING TIME (ns)

RGS, GATE TO SOURCE RESISTANCE (Ω)

td(OFF)

td(ON)

VGS = 10V, VDD = 15V, ID = 47A, RL = 0.32Ω

VGS

0.01Ω

IAS

VDS

VDD

DUT

VARY tP TO OBTAIN

REQUIRED PEAK IAS

VDD

VDS

BVDSS

IAS

tAV

HUF76121P3, HUF76121S3S

100

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM

Test Circuits and Waveforms

(Continued)

VGS +

VDS

VDD

DUT

Ig(REF)

VDD

Qg(TH)

VGS = 1V

Qg(5)

VGS = 5V

Qg(TOT)

VGS = 10V

VDS

VGS

IgREF)

VGS

RGS DUT

-VDD

VDS

VGS

tON

td(ON)

90%

10%

VDS 90%

10%

td(OFF)

tOFF

90%

50%

10% PULSE WIDTH

VGS

HUF76121P3, HUF76121S3S

101

PSPICE Electrical Model

.SUBCKT HUF76121 2 1 3 ; rev March 1998

CA 12 8 1.2e-9

CB 15 14 1.23e-9

CIN 6 8 7.6e-10

DBODY 7 5 DBODYMOD

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 33.4

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRAIN 2 5 1e-9

LGATE 1 9 3.57e-9

LSOURCE 3 7 4.25e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 2.5e-3

RGATE 9 20 4

RLDRAIN 2 5 10

RLGATE 1 9 35.7

RLSOURCE 3 7 42.5

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 10e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*181),4))}

.MODEL DBODYMOD D (IS = 4e-13 RS = 6.3e-3 TRS1 = 1e-3 TRS2 = 3e-6 CJO = 1.33e-9 TT = 2.8e-8 M = 0.4 XTI = 4.3 N = 0.95 IKF = 5)

.MODEL DBREAKMOD D (RS = 1.05e-1 TRS1 = 0 TRS2 = 2.5e-5)

.MODEL DPLCAPMOD D (CJO = 7.8e-10 IS = 1e-30 N = 10 M = 0.63)

.MODEL MMEDMOD NMOS (VTO = 1.8 KP = 3.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 4)

.MODEL MSTROMOD NMOS (VTO = 2.08 KP = 65 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 1.54 KP = 0.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 40 RS = 0.1)

.MODEL RBREAKMOD RES (TC1 = 9.7e-4 TC2 = 7e-7)

.MODEL RDRAINMOD RES (TC1 = 1.6e-2 TC2 = 4e-5)

.MODEL RSLCMOD RES (TC1 = 5e-3 TC2 = 8e-6)

.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)

.MODEL RVTHRESMOD RES (TC = -1.7e-3 TC2 = -4e-6)

.MODEL RVTEMPMOD RES (TC1 = -1.2e-3 TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 2)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2 VOFF= -0.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

HUF76121P3, HUF76121S3S

102

SABER Electrical Model

REVMarch1998

template huf76121 n2, n1, n3

electrical n2, n1, n3

{

var i iscl

d..model dbodymod = (is = 4e-13, xti = 4.3, cjo = 1.33e-9, tt = 2.8e-8, n = 0.95, m = 0.4)

d..model dbreakmod = ()

d..model dplcapmod = (cjo = 7.8e-10, is = 1e-30, n = 10, m = 0.63)

m..model mmedmod = (type=_n, vto = 1.8, kp = 3.5, is = 1e-30, tox = 1)

m..model mstrongmod = (type=_n, vto = 2.08, kp = 65, is = 1e-30, tox = 1)

m..model mweakmod = (type=_n, vto = 1.54, kp = 0.1, is = 1e-30, tox = 1)

sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3)

sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3, voff = -5)

sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 2)

sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2, voff = -0.5)

c.ca n12 n8 = 1.2e-9

c.cb n15 n14 = 1.23e-9

c.cin n6 n8 = 7.6e-10

d.dbody n7 n71 = model=dbodymod

d.dbreak n72 n11 = model=dbreakmod

d.dplcap n10 n5 = model=dplcapmod

i.it n8 n17 = 1

l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 3.57e-9

l.lsource n3 n7 = 4.25e-9

m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u

res.rbreak n17 n18 = 1, tc1 = 9.7e-4, tc2 = 7e-7

res.rdbody n71 n5 = 6.3e-3, tc1 = 1e-3, tc2 = 3e-6

res.rdbreak n72 n5 = 1.05e-1, tc1 = 0, tc2 = 2.5e-5

res.rdrain n50 n16 = 2.5e-3, tc1 = 1.6e-2, tc2 = 4e-5

res.rgate n9 n20 = 4

res.rldrain n2 n5 = 10

res.rlgate n1 n9 = 35.7

res.rlsource n3 n7 = 42.5

res.rslc1 n5 n51 = 1e-6, tc1 = 5e-3, tc2 = 8e-6

res.rslc2 n5 n50 = 1e3

res.rsource n8 n7 = 10e-3, tc1 = 0, tc2 = 0

res.rvtemp n18 n19 = 1, tc1 = -1.2e-3, tc2 = 1e-6

res.rvthres n22 n8 = 1, tc1 = -1.7e-3, tc2 = -4e-6

spe.ebreak n11 n7 n17 n18 = 33.4

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc = 1

equations {

i (n51->n50) + = iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/181))** 4))

}

RBREAK

RVTEMP

VBAT

RVTHRES

17 18

S1A

S1B

S2A

S2B

CA CB

EGS EDS

814

MWEAK

EBREAK DBODY

RSOURCE

SOURCE

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES 16

MMED

MSTRO

DRAIN

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ISCL

RSLC1

RSLC2

GATE RGATE EVTEMP

ESG

LGATE

RLGATE 20

RDBODY

RDBREAK

HUF76121P3, HUF76121S3S

103

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

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from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com

SPICE Thermal Model

REV March 1998

HUF76121

CTHERM1 th 6 1.1e-3

CTHERM2 6 5 2.9e-3

CTHERM3 5 4 3.2e-3

CTHERM4 4 3 1.5e-2

CTHERM5 3 2 3.9e-1

CTHERM6 2 tl 2.2

RTHERM1 th 6 1.0e-4

RTHERM2 6 5 2.0e-3

RTHERM3 5 4 3.4e-1

RTHERM4 4 3 4.6e-1

RTHERM5 3 2 1.8e-1

RTHERM6 2 tl 7.0e-2

SABER Thermal Model

Saber thermal model HUF76121

template thermal_model th tl

thermal_c th, tl

{

ctherm.ctherm1 th 6 = 1.1e-3

ctherm.ctherm2 6 5 = 2.9e-3

ctherm.ctherm3 5 4 = 3.2e-3

ctherm.ctherm4 4 3 = 1.5e-2

ctherm.ctherm5 3 2 = 3.9e-1

ctherm.ctherm6 2 tl = 2.2

rtherm.rtherm1 th 6 = 1.0e-4

rtherm.rtherm2 6 5 = 2.0e-3

rtherm.rtherm3 5 4 = 3.4e-1

rtherm.rtherm4 4 3 = 4.6e-1

rtherm.rtherm5 3 2 = 1.8e-1

rtherm.rtherm6 2 tl = 7.0e-2

}

RTHERM4

RTHERM6

RTHERM5

RTHERM3

RTHERM2

RTHERM1

CTHERM4

CTHERM6

CTHERM5

CTHERM3

CTHERM2

CTHERM1

th JUNCTION

CASE

HUF76121P3, HUF76121S3S