MC100ES7014DTR2 - Integrated Device Technology

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Order number: MC100ES7014

Rev 1, 05/2004

This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

Low Voltage 1:5 Differential LVDS

The MC100ES7014 is a LVDS differential clock fanout buffer. Designed for

the most demanding clock distribution systems, the MC100ES7014 supports

various applications that require the distribution of precisely aligned differential

clock signals. Using SiGe technology and a fully differential architecture, the

device offers very low skew outputs and superior digital signal characteristics.

Target applications for this clock driver are in high performance clock

distribution in computing, networking and telecommunication systems.

The MC100ES7014 is designed for low skew clock distribution systems and

supports clock frequencies up to 1000MHz. The device accepts two clock

sources. The CLK0 input accepts LVDS or HSTL compatible signals and CLK1

accepts PECL compatible signals. The selected input signal is distributed to 5

identical, differential LVDS compatible outputs.

Features

• 1:5 differential clock fanout buffer

• 50 ps maximum device skew

• SiGe Technology

• Supports DC to 1000 MHz operation

• LVDS compatible differential clock outputs

• PECL and HSTL/LVDS compatible differential clock inputs

• 3.3V power supply

• Supports industrial temperature range

• Standard 20 lead TSSOP package

Figure 1. 20-Lead Pinout (Top View) and Logic Diagram

VCC NC VEE CLK1 CLK1 EN CLK0 CLK0 CLK_SEL VCC

20 19 18 17 16 15 14 13 12 11

1 2 345678 910

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4

MC100ES7014

DT SUFFIX

20 LEAD TSSOP PACKAGE

CASE 948E

1:5 DIFFERENTIAL LVDS

CLOCK FANOUT DRIVER

ORDERING INFORMATION

Device Package

MC100ES7014DT TSSOP-20

MC100ES7014DTR2 TSSOP-20

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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DATA SHEET

MC100ES7014

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

Low Voltage 1:5 Differential LVDS

Clock Fanout Buffer

MC100ES7014

MOTOROLA 2 TIMING SOLUTIONS

Table 1. Pin Description

Pin Function

CLK0, CLK0 HSTL/LVDS Data Inputs

CLK1, CLK1 PECL Data Inputs

Q[0:4], Q[0:4] LVDS Data Outputs

CLK_SEL LVCMOS Active Clock Select Input

EN LVCMOS Sync Enable

VCC Positive Supply

VEE Negative Supply

nc no connect

Table 2. Function Table

Control Default 0 1

CLK_SEL 0 CLK0, CLK0 (HSTL/LVDS) is the active differential

clock input

CLK1, CLK1 (PECL) is the active differential clock

input

EN 0 Q[0:4], Q[0:4] are active. Deassertion of EN can be

asynchronous to the reference clock without

generation of output runt pulses.

Q[0:4] = L, Q[0:4] = H (outputs disabled). Assertion of

EN can be asynchronous to the reference clock

without generation of output runt pulses.

Table 3. General Specifications

Characteristics Value

Internal Input Pulldown Resistor TBD

Internal Input Pullup Resistor TBD

ESD Protection Human Body Model

Machine Model

TBD

θJA Thermal Resistance (Junction to Ambient) 0 LFPM, 8 SOIC

500 LFPM, 8 SOIC

TBD

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

Table 4. Absolute Maximum Ratings1

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not

implied.

Symbol Parameter Conditions Rating Unit

VSUPPLY Power Supply Voltage Difference between VCC & VEE 3.9 V

VIN Input Voltage VCC – VEE ≤ 3.6V VCC + 0.3

VEE – 0.3

IOUT Output Current Continuous

Surge

100

TAOperating Temperature Range –40 to +85 °C

TSTG Storage Temperature Range –65 to +150 °C

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Freescale Semiconductor, Inc.

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MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

TIMING SOLUTIONS 3 MOTOROLA

Table 5. DC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1

1. DC characteristics are design targets and pending characterization.

Symbol Characteristic Min Typ Max Unit Condition

HSTL/LVDS differential input signals (CLK0, CLK0)

VDIF Differential input voltage2

2. VDIF (DC) is the minimum differential HSTL/LVDS input voltage swing required for device functionality.

0.2 V

VX, IN Differential cross point voltage3

3. VX (DC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (DC)

range and the input swing lies within the VPP (DC) specification.

0.25 0.68 – 0.9 VCC – 1.3 V

VIH Input high voltage VX + 0.1 V

VIL Input low voltage VX – 0.1 V

IIN Input current ±150 mA VIN = VX ± 0.1V

PECL differential input signals (CLK1, CLK1)

VPP Differential input voltage4

4. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.

0.15 1.0 V Differential Operation

VCMR Differential cross point voltage5

5. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range

and the input swing lies within the VPP (DC) specification.

1.0 VCC – 0.6 V Differential Operation

VIH Input high voltage VCC – 1.165 VCC – 0.880 V

VIL Input low voltage VCC – 1.810 VCC – 1.475 V

IIN Input current ±150 mA VIN = VIH or VIN

LVCMOS control inputs EN, CLK_SEL

VIL Input low voltage 0.8 V

VIH Input high voltage 2.0 V

IIN Input current ±150 mA VIN = VIH or VIN

LVDS clock outputs (Q[0:4], Q[0:4])

VPP Output differential voltage (peak-to-peak) 250 mV LVDS

VOS Output offset voltage 1125 1275 mV LVDS

Supply Current

ICC Maximum Quiescent Supply Current without

output termination current

TBD TBD mA VCC pin (core)

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MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

MOTOROLA 4 TIMING SOLUTIONS

Table 6. AC Characteristics (VCC = 3.3V±5%; TJ = 0°C to 110°C)1 2

1. AC characteristics are design targets and pending characterization.

2. AC characteristics apply for parallel output termination of 50Ω to VTT.

Symbol Characteristic Min Typ Max Unit Condition

HSTL/LVDS differential input signals (CLK0, CLK0)

VDIF Differential input voltage (peak-to-peak)3

3. VDIF (AC) is the minimum differential HSTL/LVDS input voltage swing required to maintain AC characteristics including tpd and device-to-device

skew.

0.4 V

VX, IN Differential cross point voltage4

4. VX (AC) is the crosspoint of the differential HSTL/LVDS input signal. Functional operation is obtained when the crosspoint is within the VX (AC)

range and the input swing lies within the VDIF (AC) specification. Violation of VX (AC) or VDIF(AC) impacts the device propagation delay, device

and part-to-part skew.

0.68 1.275 V

fCLK Input Frequency 1000 TBD MHz Differential

tPD Propagation Delay TBD ps Differential

PECL differential input signals (CLK1, CLK1)

VPP Differential input voltage (peak-to-peak)5

5. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device skew.

0.2 1.0 V

VCMR Differential cross point voltage6

6. VCMR (AC) is the crosspoint of the differential PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)

range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP(AC) impacts the device propagation delay, device

and part-to-part skew.

CC – 0.6 V

fCLK Input Frequency 1000 MHz Differential

tPD Propagation Delay TBD ps Differential

LVDS clock outputs (Q[0:4], Q[0:4])

tSK(O) Output-to-output skew 50 ps Differential

tSK(PP) Output-to-output skew (part-to-part) TBD ps Differential

tJIT(CC) Output cycle-to-cycle jitter TBD

DCOOutput duty cycle TBD 50 TBD % DCfref = 50%

tr / tfOutput Rise/Fall Times 0.05 TBD ns 20% to 80%

tPDL Output disable time7

7. Propagation delay EN deassertion to differential output disabled (differential low: true output low, complementary output high).

2.5*T +tPD 3.5*T +tPD ns T = CLK period

tPLD Output enable time8

8. Propagation delay EN assertion to output enabled (active).

3*T +tPD 4*T +tPD ns T = CLK period

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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nc...

MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

TIMING SOLUTIONS 5 MOTOROLA

Figure 2. MC100ES7014 AC Test Reference

CLKx

tPDL (EN to Qx[])

50%

tPLD (EN to Qx[])

CLKx

Qx[]

Qx[] Outputs disabled

Figure 3. MC100ES7014 AC Test Reference

Differential Pulse

Generator

Z = 50Ω

RT = 50Ω

ZO = 50Ω

DUT

MC100ES7014

VTT=GND

RT = 50Ω

ZO = 50Ω

VTT=GND

Figure 5. MC100ES7014 AC Reference

Measurement Waveform (PECL Input)

CLK1

tPD (CLK1 to Q[0–4])

VCMR=VCC–1.3V

VDIF=0.8V

CLK1

Q[0–4]

Figure 4. MC100ES7014 AC Reference

Measurement Waveform (HSTL Input)

CLK0

tPD (CLK0 to Q[0–4])

VX=0.75V

VDIF=0.6V

CLK0

Q[0–4]

Figure 6. MC100ES7014 AC Reference

Measurement Waveform (LVDS Input)

CLK0

tPD (CLK0 to Q[0–4])

VX=1.2V

VDIF=0.6V

CLK0

Q[0–4]

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

MOTOROLA 6 TIMING SOLUTIONS

PACKAGE DIMENSIONS

DT SUFFIX

20 LEAD TSSOP PACKAGE

CASE 948E-02

ISSUE A

1120

PIN 1

IDENT

-V-

-U-

0.10 (0.004) V S

20X REFK

L/2

U0.15 (0.006) T

DGH

SEATING

PLANE

-W-

DETAIL E

0.25 (0.010)

DETAIL E

SECTION N-N

JJ1

0.100 (0.004)

–T–

PIN 1

IDENT

-V-

-U-

0.10 (0.004) VT

20X REFK

L/2

U0.15 (0.006) T

CASE 948E-02

ISSUE A

DATE 12/04/

INCHESMILLIMETERS

0.65 BSC 0.026 BSC

6.40 BSC 0.252 BSC

DIM

MAX

6.60

4.50

1.20

0.15

0.75

0.37

0.20

0.16

0.30

0.25

8˚

MAX

0.260

0.177

0.047

0.006

0.030

0.015

0.008

0.006

0.012

0.010

8˚

MIN

4.30

0.05

0.50

0.27

0.09

0.19

0˚

6.40

---

MIN

0.169

0.002

0.020

0.011

0.004

0.007

0˚

0.252

---

NOTES:

DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

CONTROLLING DIMENSION: MILLIMETER.

DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS. MOLD

FLASH OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH

OR PROTRUSION SHALL NOT EXCEED 0.25

(0.010) PER SIDE.

DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

DIMENSION A AND BE ARE TO BE DETERMINED

AT DATUM PLANE -W-.

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

nc...

MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM

IDT™ Low Voltage 1:5 Differential LVDS Clock Fanout Buffer

Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc

MC100ES7014

Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered

trademarks used to identify products or services of their respective owners.

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For Sales

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Fax: 408-284-2775

For Tech Support

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480-763-2056

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PART NUMBERS

INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM

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900 MHz Low Voltage LVDS Clock Synthesizer NETCOM

MC100ES7014

Low Voltage 1:5 Differential LVDS Clock Fanout Buffer NETCOM