5962-8956101EA - QP Semiconductor

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A

Add vendor CAGE F8859. Add device Class V criteria. Add delta

limits, table III. Add case outline X. Update boilerplate to

MIL-PRF-38535 requirements. – lgt

01-02-26 Raymond Monnin

B

Add radiation features in section 1.5. Correct the waveforms in

figure 5. Update the boilerplate to include radiation hardness assured

requirements. Editorial changes throughout. - jak

04-12-14

Thomas M. Hess

THE FRONT PAGE OF THIS DRAWING HAS BEEN REPLACED.

REV

SHEET

REV B B B B B B B

SHEET 15 16 17 18 19 20 21

REV STATUS REV B B B B B B B B B B A A B A

OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A PREPARED BY

Marcia B. Kelleher

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Ray Monnin

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 43218-3990

http://www.dscc.dla.mil

APPROVED BY

Michael A. Frye

THIS DRAWING IS

AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

DRAWING APPROVAL DATE

89-06-07

MICROCIRCUIT, DIGITAL, ADVANCED CMOS,

SYNCHRONOUS PRESETTABLE BINARY

COUNTER, MONOLITHIC SILICON

AMSC N/A

REVISION LEVEL

B SIZE

A CAGE CODE

67268 5962-89561

SHEET

1 OF

21

DSCC FORM 2233

APR 97 5962-E365-04

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APR 97

1. SCOPE

1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)

and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or

Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

1.2 PIN. The PIN is as shown in the following example:

For device classes M and Q:

5962 - 89561 01 E A

Federal RHA Device Case Lead

stock class designator type outline finish

designator (see 1.2.1) (see 1.2.2) (see 1.2.4) (see 1.2.5)

\ /

\/

Drawing number

For device class V:

5962 F 89561 01 V X A

Federal RHA Device Device Case Lead

stock class designator type class outline finish

designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)

\ / (see 1.2.3)

\/

Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are

marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A

specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.

1.2.2 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit function

01 54AC161 Synchronous presettable binary counter

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as listed

below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q

designators will not be included in the PIN and will not be marked on the device.

Device class Device requirements documentation

M Vendor self-certification to the requirements for MIL-STD-883 compliant,

non-JAN class level B microcircuits in accordance with MIL-PRF-38535,

appendix A

Q or V Certification and qualification to MIL-PRF-38535

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1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

E GDIP1-T16 or CDIP2-T16 16 Dual-in-line

F GDFP2-F16 or CDFP3-F16 16 Flat pack

2 CQCC1-N20 20 Square leadless chip carrier

X CDFP4-F16 16 Flat pack

1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,

appendix A for device class M.

1.3 Absolute maximum ratings. 1/ 2/ 3/

Supply voltage range (VCC).................................................................................. -0.5 V dc to +7.0 V dc

DC input voltage range (VIN)................................................................................ -0.5 V dc to VCC + 0.5 V dc

DC output voltage range (VOUT)........................................................................... -0.5 V dc to VCC + 0.5 V dc

Clamp diode current (IIK, IOK)................................................................................ ±20 mA

DC output current................................................................................................. ±50 mA

DC VCC or GND current (per pin)......................................................................... ±50 mA

Storage temperature range (TSTG) ....................................................................... -65°C to +150°C

Maximum power dissipation (PD)........................................................................ 500 mW

Lead temperature (soldering, 10 seconds):

Case outline X.................................................................................................... +260°C

All other case outlines except case X ................................................................ +245°C

Thermal resistance, junction-to-case (θJC)........................................................... See MIL-STD-1835

Junction temperature (TJ) ................................................................................... +175°C 4/

1.4 Recommended operating conditions. 2/ 3/ 5/

Supply voltage range (VCC).................................................................................. +2.0 V dc to +6.0 V dc

Input voltage range (VIN)...................................................................................... +0.0 V dc to VCC

Output voltage range (VOUT)................................................................................. +0.0 V dc to VCC

Case operating temperature range (TC)............................................................... -55°C to +125°C

Input rise or fall times:

V

CC = 3.6 V to 5.5 V.........................................................................................0 to 8 ns/V

Minimum setup time, Pn to CP (ts):

T

C = +25°C, VCC = 3.0 V..................................................................................11.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................7.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................16.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................10.5 ns

Minimum hold time, Pn to CP (th):

T

C = +25°C, VCC = 3.0 V..................................................................................0.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................1.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................0.5 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................1.5 ns

1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the

maximum levels may degrade performance and affect reliability.

2/ Unless otherwise noted, all voltages are referenced to GND.

3/ T he limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -

55°C to +125°C.

4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in

accordance with method 5004 of MIL-STD-883.

5/ Operation from 2.0 V dc to 3.0 V dc is provided for compatibility with data retention and battery back-up systems. Data

retention implies no input transition and no stored data loss with the following conditions: VIH ≥ 70% VCC, VIL ≤ 30% VCC,

V

OH ≥ 70% VCC @ -20µA, VOL ≤ 30% VCC @ 20 µA.

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APR 97

1.4 Recommended operating conditions – Continued.

Minimum setup time, PE to CP (ts):

T

C = +25°C, VCC = 3.0 V..................................................................................11.5 ns

T

C = +25°C, VCC = 4.5 V..................................................................................7.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................15.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................10.5 ns

Minimum hold time, PE to CP (th):

T

C = +25°C, VCC = 3.0 V..................................................................................-1.5 ns

T

C = +25°C, VCC = 4.5 V..................................................................................-0.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................-1.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................0.0 ns

Minimum setup time, CEP or CET to CP (ts):

T

C = +25°C, VCC = 3.0 V..................................................................................6.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................4.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................7.5 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................5.5 ns

Minimum hold time, CEP or CET to CP (th):

T

C = +25°C, VCC = 3.0 V..................................................................................1.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................2.0 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................2.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................2.0 ns

Minimum pulse width, CP (tw):

T

C = +25°C, VCC = 3.0 V..................................................................................5.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................5.0 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................5.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................5.0 ns

Minimum pulse width, MR (tw):

T

C = +25°C, VCC = 3.0 V..................................................................................5.0 ns

T

C = +25°C, VCC = 4.5 V..................................................................................5.0 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................5.0 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................5.0 ns

Minimum recovery time, MR to CP(trec):

T

C = +25°C, VCC = 3.0 V..................................................................................1.5 ns

T

C = +25°C, VCC = 4.5 V..................................................................................1.5 ns

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................1.5 ns

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................2.0 ns

Maximum frequency, CP (fmax):

T

C = +25°C, VCC = 3.0 V..................................................................................70 MHz

T

C = +25°C, VCC = 4.5 V..................................................................................95 MHz

T

C = -55°C to 125°C, VCC = 3.0 V....................................................................55 MHz

T

C = -55°C to 125°C, VCC = 4.5 V....................................................................80 MHz

1.5 Radiation features.

Device type 01:

Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) .................. 300 krads (Si)

Single Event Latchup (SEL)........................................................................... ≥ 93 MeV-cm2/mg

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2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICAT ION

MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE ST ANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from

the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.

Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract.

ELECTRONIC INDUSTRIES ALLIANCE (EIA)

JEDEC Standar d No. 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed

CMOS Devices

(Copies of these documents are available on line at http://www/jedec.org or from Electronic Industries Alliance, 2500 Wilson

Boulevard, Arlington, VA 22201-3834).

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a

specific exemption has been obtained.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with

MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified

herein.

3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

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3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.5 Counting sequence. The counting sequence shall be as specified on figure 4.

3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.

3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document

revision level control and shall be made available to the preparing or acquiring activity upon request.

3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the

electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full

case operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be

in accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.

3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or

for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2

herein) involving devices acquired to this drawing is required for any change that affects this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the option of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 40 (see MIL-PRF-38535, appendix A).

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TABLE I. Electrical performance characteristics.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+3.0 V ≤ VCC ≤ +5.5 V

Device

type

and 4/

VCC Group A

subgroups Limits 5/ Unit

unless otherwise specified device

class Min Max

Positive input

clamp voltage

3022

VIC+ For input under test, IIN = 1.0 mA All

V 0.0 V 1 0.4 1.5 V

Negative input

clamp voltage

3022

VIC- For input under test, IIN = -1.0 mA All

V Open 1 -0.4 -1.5 V

All

All 3.0 V 2.9

All

All 4.5 V 4.4

VIN = VIH minimum or VIL maximum

IOH = -50 µA

All

All 5.5 V 5.4

All

All 3.0 V 2.4 VIN = VIH minimum or VIL maximum

IOH = -4 mA

All 4.5 V 3.7

All

All 5.5 V 4.7

VIN = VIH minimum or VIL maximum

IOH = -24 mA

All

High level output

voltage

3006

VOH

6/

VIN = VIH minimum or VIL maximum

IOH = -50 mA All

All 5.5 V

1, 2, 3

3.85

V

VIN = VIH minimum or VIL maximum

IOL = 50 µA All

All 3.0 V 1, 2, 3 0.1 V

All

All 4.5 V 0.1

All

All 5.5 V 0.1

VIN = VIH minimum or VIL maximum

IOL = 12 mA All

All 3.0 V 0.5

VIN = VIH minimum or VIL maximum All 4.5 V 0.5

IOL = 24 mA All

All 5.5 V 0.5

All

Low level output

voltage

3007

VOL

6/

VIN = VIH minimum or VIL maximum

IOL = 50 mA All

All 5.5 V 1.65

High level input

voltage VIH All

All 3.0 V 1, 2, 3 2.1 V

7/ All

All 4.5 V 3.15

All

All 5.5 V

3.85

Low level input

voltage VIL All

All 3.0 V 1, 2, 3 0.9 V

7/ All

All 4.5 V 1.35

All

All 5.5 V 1.65

See footnotes at end of table.

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TABLE I. Electrical performance characteristics – Continued.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+3.0 V ≤ VCC ≤ +5.5 V

Device

type

and 4/

VCC Group A

subgroups Limits 5/ Unit

unless otherwise specified device

class Min Max

Input leakage

current low IIL V

IN = 0.0 V All

All 5.5 V 1 -0.1 µA

3009

2, 3 -1.0

Input leakage

current high IIH V

IN = 5.5 V All

All 5.5 V 1 0.1 µA

3010

2, 3 1.0

Quiescent supply

current, output ICCH V

IN = VCC or GND

IO = 0 A All

All 5.5 V 1 4 µA

high

3005 2, 3 80

M, D, P, L, R, F 8/ 01 1 50

Quiescent supply

current, output ICCL V

IN = VCC or GND

IO = 0 A All

All 5.5 V 1 4 µA

low

3005 2,3 80

M, D, P, L, R, F 8/ 01 1 50

Input capacitance

3012 CIN See 4.4.1c

TC = +25°C All

All 5.0 V 4 8.0 pF

Power dissipation

capacitance CPD

9/ See 4.4.1c

TC = +25°C, f = 1 MHz All

All 5.0 V 4 60.0 pF

Functional tests

3014

10/ See 4.4.1b

VIN = VIH or VIL

Verify output VOUT

All

All 3.0 V

7, 8 L H

5.5 V 7, 8 L H

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5

All

All 3.0 V 9 1.0

12.0

ns

All

All 4.5 V 1.5

8.5

All

All 3.0 V 10, 11 1.0

14.0

Propagation delay

time, high to low

low to high,

CP to Qn

(PE= HIGH)

3003

tPHL1,

tPLH1

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

10.0

All

All 3.0 V 9 1.0

12.0

ns

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

8.5

All

All 3.0 V 10, 11 1.0

14.0

Propagation delay

time, high to low

low to high,

CP to Qn

(PE= LOW)

3003

tPHL2,

tPLH2

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

10.0

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+3.0 V ≤ VCC ≤ +5.5 V

Device

type

and 4/

VCC Group A

subgroups Limits 5/ Unit

unless otherwise specified device

class Min Max

Propagation delay

time, high to low

low to high,

CP to TC

tPHL3

11/

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5

All

All 3.0 V 9 3.0

14.0

ns

3003 All

All 4.5 V 3.0

10.5

t

PLH3 All

All 3.0 V 3.0

14.0

11/ All

All 4.5 V 3.0

10.0

t

PHL3

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5

All

All 3.0 V 10, 11 3.0

17.5

ns

All

All 4.5 V 3.0

13.0

t

PLH3 All

All 3.0 V 3.0

18.0

11/ All

All 4.5 V 3.0

13.0

Propagation delay

time, high to low

low to high,

CET to TC

tPHL4

11/

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5

All

All 3.0 V 9 1.0

11.5

ns

3003 All

All 4.5 V 1.5

8.5

t

PLH4 All

All 3.0 V 1.0

10.0

11/ All

All 4.5 V 1.5

6.5

t

PHL4

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5

All

All 3.0 V 10, 11 1.0

13.5

ns

All

All 4.5 V 1.5

10.5

t

PLH4 All

All 3.0 V 1.0

13.0

11/ All

All 4.5 V 1.5

8.5

All

All 3.0 V 9 1.0

11.5

ns

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

8.5

All

All 3.0 V 10, 11 1.0

14.5

ns

Propagation delay

time, high to low

MR to Qn

3003

tPHL5

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

10.5

See footnotes at end of table.

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TABLE I. Electrical performance characteristics - Continued.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+3.0 V ≤ VCC ≤ +5.5 V

Device

type

and 4/

VCC Group A

subgroups Limits 5/ Unit

unless otherwise specified device

class Min Max

All

All 3.0 V 9 1.0

15.0

ns

TC = +25°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

11.5

All

All 3.0 V 10, 11 1.0

18.5

ns

Propagation delay

time, high to low,

MR to TC

3003

tPHL6

11/

TC = -55°C and +125°C

CL = 50 pF minimum

RL = 500Ω

See figure 5 All

All 4.5 V 1.5

14.0

1/ For tests not listed in the referenced MIL-STD-883 (e.g. VIH,VIL) utilize the general test procedure under the conditions

listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table I herein.

2/ Each input/output, as applicable shall be tested at the specified temperature for the specified limits. Output terminals not

designated shall be high level logic, low level logic, or open, except as follows:

a. VIC (pos) tests, the GND terminal can be open. TC = +25°C.

b. VIC (neg) tests, the VCC terminal shall be open. TC = +25°C.

c. All ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be

placed in the circuit such that all current flows through the meter.

3/ RHA parts for device type 01 meet all levels M, D, P, L, R, and F of irradiation. Pre and post irradiation values are

identical unless otherwise specified in table I. When performing post irradiation electrical measurements for any RHA

level for any device, TA = +25 °C.

4/ The word "All" in the device type and device class column, means limits for all device types and classes.

5/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND

and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the

minimum and maximum limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I,

as applicable, at 3.0 V ≤ VCC ≤ 3.6 V and 4.5 V ≤ VCC ≤ 5.5 V.

6/ The VOH and VOL tests shall be tested at VCC = 3.0 V and 4.5 V. The VOH and VOL tests are guaranteed, if not tested, for

other values of VCC. Limits shown apply to operation at VCC = 3.3 V ±0.3 V and VCC = 5.0 V ±0.5 V. Tests with input

current at +50 mA or -50 mA are performed on only one input at a time with duration not to exceed 10 ms. Transmission

driving tests may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for

V

IN = VIH minimum and VIL maximum.

7/ The VIH and VIL tests are not required if applied as forcing functions for VOH and VOL tests.

8/ The maximum limit for this parameter at 100 krads (Si) is 4 µA.

9/ Power dissipation capacitance (CPD) determines both the power consumption (PD) and dynamic current consumption (IS).

Where:

P

D = (CPD + CL) (VCC x VCC)f + (ICC x VCC)

I

S = (CPD + CL) VCCf + ICC

f is the frequency of the input signal and CL is the external output load capacitance.

10/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic

patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of

each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the

truth table in figure 2 herein. Functional tests shall be performed in sequence as approved by the qualifying activity on

qualified devices. Allowable tolerances in accordance with MIL-STD-883 for the input voltage levels may be

incorporated. F or VOUT measurements, L ≤ 0.3VCC and H ≥ 0.7VCC.

11/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. AC limits at

VCC = 3.6 V are equal to limits at VCC = 3.0 V and guaranteed by testing at VCC = 3.0 V. Minimum ac limits for VCC = 5.5 V

are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all

paths must be tested.

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Device type

01

Case outlines

E, F, and X 2

Terminal

number Terminal symbol

1 MR NC

2 CP

MR

3 P0 CP

4 P1 P0

5 P2 P1

6 P3 NC

7 CEP P2

8 GND P3

9 PE CEP

10 CET GND

11 Q3 NC

12 Q2 PE

13 Q1 CET

14 Q0 Q3

15 TC Q2

16 VCC NC

17 - - - - Q1

18 - - - - Q0

19 - - - - TC

20 - - - - VCC

NC = No connection

FIGURE 1. Terminal connections.

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Inputs

MR PE CET CEP

Action on rising

clock edge

L

H

X

L

H

X

H

L

X

H

X

L

Reset (clear)

Load (Pn to Qn)

Count (increment)

No change (hold)

H = High voltage level

L = Low voltage level

X = Irrelevant

FIGURE 2. Truth table.

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FIGURE 3. Logic diagram.

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Sequence illustrated in waveforms:

1. Reset outputs to zero.

2. Preset to binary twelve.

3. Count to thirteen, fourteen, f ifteen, zero, one, and two.

4. Inhibit.

FIGURE 4. Counting sequence.

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FIGURE 5. Switching waveforms and test circuit.

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FIGURE 5. Switching waveforms and test circuit - Continued.

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NOTES :

1. CL = 50 pF or equivalent, (includes probe and jig capacitance).

2. RT = 50Ω or equivalent. RL = 500Ω or equivalent.

3. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 1 MHz; ZO = 50Ω; tr ≤ 3.0 ns; tf ≤ 3.0 ns;

t

r and tf shall be measured from 10% of VCC to 90% of VCC and from 90% of VCC to 10% of VCC, respectively;

duty cycle = 50 percent.

4. Timing parameters shall be tested at a minimum input frequency of 1 MHz.

5. The outputs are measured one at a time with one transition per measurement.

FIGURE 5. Switching waveforms and test circuit - Continued.

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4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on

all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance

with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.

4.2.1 Additional criteria for device class M.

a. Burn-in test, method 1015 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision

level control and shall be made available to the preparing or acquiring act ivity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015 of MIL-STD-883.

(2) TA = +125°C, minimum.

b. Interim and final electrical test parameters shall be as specified in table II herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained

under document revision level control of the device manuf acturer's Technology Review Board (TRB) in accordance

with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit

shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified

in method 1015 of MIL-STD-883.

b. Interim and final electrical test parameters shall be as specified in table II herein.

c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in

MIL-PRF-38535, appendix B.

4.3 Qualification inspection f or device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspections to be performed shall be those specif ied in MIL-PRF-38535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for

device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed

for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections

(see 4.4.1 through 4.4.4).

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TABLE II. Electrical test requirements.

Test requirements Subgroups

(in accordance with

MIL-STD-883,

method 5005, table I)

Subgroups

(in accordance with

MIL-PRF-38535, table III)

Device

class M

Device

class Q

Device

class V

Interim electrical

parameters (see 4.2)

- - - - - - 1

Final electrical

parameters (see 4.2)

1/ 1, 2, 3, 7,

8, 9

1/ 1, 2, 3, 7,

8, 9

2/, 3/ 1, 2, 3, 7,

8, 9, 10, 11

Group A test

requirements (see 4.4)

1, 2, 3, 4, 7,

8, 9, 10, 11

1, 2, 3, 4, 7,

8, 9, 10, 11

1, 2, 3, 4, 7,

8, 9, 10, 11

Group C end-point electrical

parameters (see 4.4)

1, 2, 3 1, 2, 3

3/ 1, 2, 3, 7,8,

9, 10, 11

Group D end-point electrical

parameters (see 4.4)

1, 2, 3 1, 2, 3 1, 2, 3

Group E end-point electrical

parameters (see 4.4)

1, 7, 9 1, 7, 9 1, 7, 9

1/ PDA applies to subgroup 1.

2/ PDA applies to subgroups 1, 7, and deltas.

3/ Delta limits, as specified in table III, shall be required where specified, and the delta

limits shall be completed with reference to the zero hour electrical parameters.

TABLE III. Burn-in and operating life test, delta parameters (+25°C).

Parameter 1/ Symbol Delta Limits

Quiescent supply current ICCH, ICCL ±300 nA

Input current low level IIL ±20 nA

Input current high level IIH ±20 nA

Output voltage low level

VCC = 5.5 V

IOL = 24 mA

VOL ±0.04 V

Output voltage high level

VCC = 5.5 V

IOH = -24 mA

VOH ±0.2 V

1/ These parameters shall be recorded before and after the required

burn-in and life tests to determine the delta limits.

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4.4.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test

vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input

to output logic patterns per function shall be guaranteed, if not tested, to the t ruth table in figure 2, herein. For device

classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.

c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect

capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall

be tested in accordance with the latest revision of JEDEC Standard No. 20 and table I herein. For CIN and CPD, test all

applicable pins on five devices with zero failures.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.

4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:

a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify

the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method

1005 of MIL-STD-883.

b. TA = +125°C, minimum.

c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,

or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The

test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of

MIL-STD-883.

4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.

4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured

(see 3.5 herein).

a. End-point electrical parameters shall be as specified in table II herein.

b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as

specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to

radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All

device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at

TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein.

c. RHA tests for device classes M, Q, and V for levels M, D, P, L, R, and F shall be performed through each level to

determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial

qualification and after design or process changes which may affect the RHA performance of the device.

d. Prior to irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified

group A electrical parameters in table I for subgroups specified in table II herein.

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4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883,

method 1019, condition A and as specified herein. Prior to and during total dose irradiation characterization and testing, the

devices for characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the

devices for testing shall be biased to the worst case condition established during characterizat ion. Devices shall be biased as

follows:

a. Inputs tested high, VCC = 5.5 V dc ±5%, VIN = 5.0 V dc +10%, RIN = 1 kΩ ±20%, and all outputs are open.

b. Inputs tested low, VCC = 5.5 V dc ±5%, VIN = 0.0 V dc, RIN = 1 kΩ ±20%, and all outputs are open.

4.4.4.1.1 Accelerated aging test. Accelerated aging shall be performed on classes M, Q, and V devices requiring an RHA

level greater than 5K rads (Si). The post-anneal end-point electrical parameter limit s shall be as specified in table I herein and

shall be the preirradiation end-point electrical parameter limit at 25°C ± 5°C. Testing shall be performed at initial qualification

and after any design or process changes which may affect the RHA response of the device.

4.5 Methods of inspection . Methods of inspection shall be specified as follows:

4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.

Currents given are conventional current and positive when flowing into the referenced terminal.

5. PACKAGING

5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes

Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOTES

6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications

(original equipment), design applications, and logistics purposes.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-

prepared specification or drawing.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.

6.3 Record of users. Milit ary and industrial users should inform Defense Supply Center Columbus (DSCC) when a system

application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users

and this list will be used for coordination and distribution of changes to t he drawings. Users of drawings covering microelectronic

devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.

6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone

(614) 692-0547.

6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in

MIL-PRF-38535 and MIL-HDBK-1331.

6.6 Sources of supply.

6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.

The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to

this drawing.

6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.

The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been

submitted to and accepted by DSCC-VA.

STANDARD MICROCIRCUIT DRAWING BULLETIN

DATE: 04-12-14

Approved sources of supply for SMD 5962-89561 are listed below for immediate acquisition information only and shall

be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised

to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate

of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next

dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of

supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-8956101EA 27014 54AC161DMQB

5962-8956101FA 27014 54AC161FMQB

5962-89561012A 27014 54AC161LMQB

5962-8956101XA F8859 54AC161K02Q

5962-8956101VXA F8859 54AC161K02V

5962-8956101XC F8859 54AC161K01Q

5962-8956101VXC F8859 54AC161K01V

5962F8956101XA F8859 RHFAC161K02Q

5962F8956101VXA F8859 RHFAC161K02V

5962F8956101XC F8859 RHFAC161K01Q

5962F8956101VXC F8859 RHFAC161K01V

1

/ The lead finish shown for each PIN representing a hermetic package is the

most readily available from the manufacturer listed for that part. If the

desired lead finish is not listed contact the vendor to determine its availability.

2

/ Caution. Do not use this number for item acquisition. Items acquired to this

number may not satisfy the performance requirements of this drawing.

Vendor CAGE Vendor name

number and address

27014 National Semiconductor

2900 Semiconductor Drive

P. O. Box 58090

Santa Clara, CA 95052-8090

F8859 ST Microelectronics

3 rue de Suisse

BP4199

35041 RENNES cedex2-FRANCE

The information contained herein is disseminated for convenience only and the

Government assumes no liability whatsoever for any inaccuracies in the

information bulletin.