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FM28V020
256-Kbit (32K × 8) F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-86204 Rev. *H Revised November 20, 2018
256-Kbit (32K × 8) F-RAM M emory
Features
■256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32K × 8
❐High-endurance 100 trillion (1014) read/writes
❐151-year data retention (see Data Retention and Endurance
on page 8)
❐NoDelay™ writes
❐Page mode operation
❐Advanced high-reliability ferroelectric process
■SRAM compatible
❐Industry-standard 32K × 8 SRAM pinout
❐70-ns access time, 140-ns cycle time
■Superior to battery-backed SRAM modules
❐No battery concerns
❐Monolithic reliability
❐True surface mount solution, no rework steps
❐Superior for moisture, shock, and vibration
❐Resistant to negative voltage undershoots
■Low power consumption
❐Active current 5 mA (typ)
❐Standby current 90 A (typ)
■Low-voltage operation: VDD = 2.0 V to 3.6 V
■Industrial temperature: –40 C to +85 C
■Packages:
❐28-pin small outline integrated circuit (SOIC) package
❐28-pin thin small outline package (TSOP) Type I
❐32-pin thin small outline package (TSOP) Type I
■Restriction of hazardous substances (RoHS) compliant
Functional Description
The FM28V020 is a 32K × 8 nonvolatile memory that reads and
writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V020 operation is similar to that of other RAM devices
and therefore, it can be used as a drop-in replacement for a
standard SRAM in a system. Read and write cycles may be
triggered by CE or simply by changing the address. The F-RAM
memory is nonvolatile due to its unique ferroelectric memory
process. These features make the FM28V020 ideal for
nonvolatile memory applications requiring frequent or rapid
writes.
The device is available in a 28-pin SOIC, 28-pin TSOP I and
32-pin TSOP I surface mount packages. Device specifications
are guaranteed over the industrial temperature range –40 °C to
+85 °C.
For a complete list of related documentation, click here.
Address Latch
CE
Control
Logic
WE
Row Decoder
A
I/O Latch & Bus DriverOE
DQ
32 K x 8
F-RAM Array
. . .
Column Decoder
. . .
14-3
A2-0
7-0
A14-0
Logic Block Diagram
FM28V020
Document Number: 001-86204 Rev. *H Page 2 of 22
Contents
Pinouts ..............................................................................3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
Memory Operation ....................................................... 5
Read Operation ........................................................... 5
Write Operation ........................................................... 5
Page Mode Operation ................................................. 5
Pre-charge Operation .................................................. 5
SRAM Drop-In Replacement .......................................6
Endurance ................................................................... 6
Maximum Ratings ............................................................. 7
Operating Range ............................................................... 7
DC Electrical Characteristics .......................................... 7
Data Retention and Endurance ....................................... 8
Capacitance ...................................................................... 8
Thermal Resistance .......................................................... 8
AC Test Conditions .......................................................... 8
AC Switching Characteristics ......................................... 9
SRAM Read Cycle ...................................................... 9
SRAM Write Cycle ..................................................... 10
Power Cycle Timing ....................................................... 13
Functional Truth Table ................................................... 14
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
FM28V020
Document Number: 001-86204 Rev. *H Page 3 of 22
Pinouts
Figure 1. 28-pin SOIC pinout
Figure 2. 28-pin TSOP I pinout
Figure 3. 32-pin TSOP I pinout
DQ4
DQ5
DQ6
DQ7
OE
A8
A13
WE
A9
A10
A11
VDD
CE
DQ3
A14
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
A12
A7
A6
A5
A428-pin SOIC
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
16
15
19
18
17
21
20
24
23
22
26
25
28
27
A0
DQ0
DQ1
DQ2
DQ7
A10
CE
DQ6
DQ3
DQ5
A1
WE
VDD
A14
A12
A7
A6
A5
A4
OE
A11
A9
A8
A13 28-pin TSOP I
(x 8)
Top view
(not to scale)
22
23
24
5
6
25
26
27
28
1
2
3
4
10
9
13
12
11
15
14
18
17
16
20
19
21
78
A3A2
VSS
DQ4
A0
DQ0
DQ1
DQ2
DQ7
A10
CE
DQ6
DQ3
DQ5
NC
A1
NC
WE
VDD
A14
A12
A7
A6
A5
A4
OE
A11
A9
A8
A13 32-pin TSOP I
(x 8)
Top view
(not to scale)
1
2
3
4
13
14
5
6
7
8
9
10
11
12
20
19
23
22
21
25
24
28
27
26
30
29
32
31
15
16
18
17
A3
NC
A2
NC
VSS
DQ4
FM28V020
Document Number: 001-86204 Rev. *H Page 4 of 22
Pin Definitions
Pin Name I/O Type Description
A14–A0Input Address inputs: The 15 address lines select one of 32,768 bytes in the F-RAM array. The lowest two
address lines A2–A0 may be used for page mode read and write operations.
DQ7–DQ0Input/Output Data I/O Lines: 8-bit bidirectional data bus for accessing the F-RAM array.
WE Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V020 to write
the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address for
page mode write cycles.
CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A2–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the FM28V020 drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
FM28V020
Document Number: 001-86204 Rev. *H Page 5 of 22
Device Operation
The FM28V020 is a bytewide F-RAM memory logically
organized as 32,768 × 8 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE transitions LOW or the upper address
(A14–A3) changes. See the Functional Truth Table on page 14
for a complete description of read and write modes.
Memory Operation
Users access 32,768 memory locations, each with 8 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 512 rows. Each row has eight column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE,
subsequent column locations may be accessed without the need
to toggle CE. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE is still LOW. The minimum
cycle time for random addresses is tRC. Note that unlike SRAMs,
the FM28V020's CE-initiated access time is faster than the
address access time.
The FM28V020 will drive the data bus when OE is asserted LOW
and the memory access time is met. If OE is asserted after the
memory access time is met, the data bus will be driven with valid
data. If OE is asserted before completing the memory access,
the data bus will not be driven until valid data is available. This
feature minimizes supply current in the system by eliminating
transients caused by invalid data being driven to the bus. When
OE is deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM28V020, writes occur in the same interval as reads. The
FM28V020 supports both CE and WE controlled write cycles. In
both cases, the address is latched on the falling edge of CE.
In a CE
-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE is LOW when the
device is activated with the chip enable. In this case, the device
begins the memory cycle as a write. The FM28V020 will not drive
the data bus regardless of the state of OE as long as WE is LOW.
Input data must be valid when CE is deasserted HIGH. In a
WE-controlled write, the memory cycle begins on the falling edge
of CE. The WE signal falls some time later. Therefore, the
memory cycle begins as a read. The data bus will be driven if OE
is LOW; however, it will be HI-Z when WE is asserted LOW. The
CE and WE controlled write timing cases are shown on the
Figure 9 on page 12. In Figure 10 on page 12, the data bus is
shown as a hi-Z condition while the chip is write-enabled and
before the required setup time. Although this is drawn to look like
a mid-level voltage, it is recommended that all DQ pins comply
with the minimum VIH/VIL operating levels.
Write access to the array begins on the falling edge of WE after
the memory cycle is initiated. The write access terminates on the
rising edge of WE or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The FM28V020 provides the user fast access to any data within
a row element. Each row has eight column-address locations.
Address inputs A2–A0 define the column address to be
accessed. An access can start anywhere within a row and other
column locations may be accessed without the need to toggle
the CE pin. For fast access reads, after the first data byte is
driven to the bus, the column address inputs A2–A0 may be
changed to a new value. A new data byte is then driven to the
DQ pins. For fast access writes, the first write pulse defines the
first write access. While CE is LOW, a subsequent write pulse
along with a new column address provides a page mode write
access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, tPC.
Pre-charge is also activated by changing the upper addresses,
A14–A3. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the tAA address
access time; see Figure 6 on page 11. A similar sequence occurs
for write cycles; see Figure 11 on page 12. The rate at which
random addresses can be issued is tRC and tWC, respectively.
FM28V020
Document Number: 001-86204 Rev. *H Page 6 of 22
SRAM Drop-In Replacement
The FM28V020 is designed to be a drop-in replacement for
standard asynchronous SRAMs. The device does not require CE
to toggle for each new address. CE may remain LOW indefinitely
while VDD is applied. While CE is LOW, the device automatically
detects address changes and a new access begins. It also allows
page mode operation at speeds up to 15 MHz.
A typical application is shown in Figure 4. It shows a pull-up
resistor on CE, which will keep the pin HIGH during power
cycles, assuming the MCU / MPU pin tristates during the reset
condition.The pull-up resistor value should be chosen to ensure
the CE pin tracks VDD to a high enough value, so that the current
drawn when CE is LOW is not an issue. A 10-k resistor draws
330 µA when CE is LOW and VDD = 3.3 V.
Note that if CE is tied to ground, the user must be sure WE is not
LOW at power-up or power-down events. If CE and WE are both
LOW during power cycles, data will be corrupted. Figure 5 shows
a pull-up resistor on WE, which will keep the pin HIGH during
power cycles, assuming the MCU/MPU pin tristates during the
reset condition.The pull-up resistor value should be chosen to
ensure the WE pin tracks VDD to a high enough value, so that
the current drawn when WE is LOW is not an issue. A 10-k
resistor draws 330 µA when WE is LOW and VDD = 3.3 V.
For applications that require the lowest power consumption, the
CE signal should be active only during memory accesses. Due
to the external pull-up resistor, some supply current will be drawn
while CE is LOW. When CE is HIGH, the device draws no more
than the maximum standby current ISB.
CE toggling LOW on every address access is perfectly
acceptable in FM28V020.
Endurance
The FM28V020 is capable of being accessed at least 1014 times
– reads or writes. An F-RAM memory operates with a read and
restore mechanism. Therefore, an endurance cycle is applied on
a row basis. The F-RAM architecture is based on an array of
rows and columns. Rows are defined by A14–3 and column
addresses by A2–A0. The array is organized as 4K rows of eight
bytes each. The entire row is internally accessed once whether
a single byte or all eight bytes are read or written. Each byte in
the row is counted only once in an endurance calculation if the
addressing is contiguous in nature.
The user may choose to write CPU instructions and run them
from a certain address space. Table 1 shows endurance
calculations for a 256-byte repeating loop, which includes a
starting address, seven-page mode accesses, and a CE
pre-charge. The number of bus clock cycles needed to complete
a eight-byte read transaction is 1 + 7 + 1 or 9 clocks. The entire
loop causes each byte to experience only one endurance cycle.
The F-RAM read and write endurance is virtually unlimited.
Figure 4. Use of Pull-up Resistor on CE
Figure 5. Use of Pull-up Resistor on WE
MCU / MPU
CE
WE
OE
A14-0
DQ 7-0
FM28V020
VDD
MCU / MPU
CE
WE
OE
A14-0
DQ 7-0
FM28V020
VDD
Table 1. Time to Reach 100 Trillion Cycles for Repeating
256-byte Loop
Bus
Freq
(MHz)
Bus
Cycle
Time
(ns)
256-byte
Transaction
Time (s)
Endurance
Cycles/sec
Endurance
Cycles/yr
Years
to
Reach
1014
Cycles
10 100 28.8 34,720 1.09 × 1012 91.7
5 200 57.6 17,360 5.47 × 1011 182.8
FM28V020
Document Number: 001-86204 Rev. *H Page 7 of 22
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 °C to +125 °C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns)
on any pin to ground potential ............ –2.0 V to VCC + 2.0 V
Package power dissipation capability
(TA = 25 °C) ................................................................. 1.0 W
Surface mount Pb soldering temperature
(3 seconds) .............................................................. +260 C
DC output current
(1 output at a time, 1s duration) .................................. 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............ 2 kV
Charged Device Model (AEC-Q100-011 Rev. B) .. 1.25 kV
Machine Model (AEC-Q100-003 Rev. E) ................. 200 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temperature (TA) VDD
Industrial –40 C to +85 C 2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions Min Typ [1] Max Unit
VDD Power supply voltage 2.0 3.3 3.6 V
IDD VDD supply current VDD = 3.6 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
–58mA
ISB Standby current VDD = 3.6 V, CE at VDD, All other pins are static
and at CMOS levels (0.2 V or VDD – 0.2 V)
– 90 150 µA
ILI Input leakage current VIN between VDD and VSS ––+1µA
ILO Output leakage current VOUT between VDD and VSS ––+1µA
VIH Input HIGH voltage 0.7 × VDD –V
DD + 0.3 V
VIL Input LOW voltage – 0.3 – 0.3 × VDD V
VOH1 Output HIGH voltage IOH = –1.0 mA, VDD > 2.7 V 2.4 – – V
VOH2 Output HIGH voltage IOH = –100 µA VDD – 0.2 – – V
VOL1 Output LOW voltage IOL = 1 mA, VDD > 2.7 V – – 0.4 V
VOL2 Output LOW voltage IOL = 150 µA – – 0.2 V
Note
1. Typical values are at 25 °C, VDD = VDD(typ). Not 100% tested.
FM28V020
Document Number: 001-86204 Rev. *H Page 8 of 22
AC Test Conditions
Input pulse levels ...................................................0 V to 3 V
Input rise and fall times (10%–90%) ........................... < 3 ns
Input and output timing reference levels ....................... 1.5 V
Output load capacitance ............................................... 30 pF
Data Retention and Endurance
Parameter Description Test condition Min Max Unit
TDR Data retention At +85 C 10 – Years
At +75 C38–
At +65 C151–
NVCEndurance Over operating temperature 1014 – Cycles
Capacitance
Parameter Description Test Conditions Max Unit
CI/O Input/Output capacitance (DQ) TA = 25 C, f = 1 MHz, VDD = VDD(Typ) 8 pF
CIN Input capacitance 6pF
Thermal Resistance
Parameter Description Test Conditions 28-pin SOIC 28-pin TSOP I 32-pin TSOP I Unit
JA Thermal resistance
(junction to ambient)
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, in
accordance with
EIA/JESD51.
59 108 84 C/W
JC Thermal resistance
(junction to case)
30 29 26 C/W
FM28V020
Document Number: 001-86204 Rev. *H Page 9 of 22
AC Switching Characteristics
Over the Operating Range
Parameters [2]
Description Min Max Unit
Cypress
Parameter Alt Parameter
SRAM Read Cycle
tCE tACE Chip enable access time – 70 ns
tRC –Read cycle time 140 – ns
tAA –Address access time – 140 ns
tOH tOHA Output hold time 20 – ns
tAAP –Page mode address access time – 40 ns
tOHP –Page mode output hold time 3 – ns
tCA –Chip enable active time 70 – ns
tPC –Pre-charge time 70 – ns
tAS tSA Address setup time (to CE LOW) 0–ns
tAH tHA Address hold time (CE Controlled) 70 – ns
tOE[3] tDOE Output enable access time – 20 ns
tHZ[4, 5] tHZCE Chip Enable to output HI-Z – 10 ns
tOHZ[4, 5] tHZOE Output enable HIGH to output HI-Z – 10 ns
Notes
2. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and load capacitance shown in AC Test Conditions on page 8.
3. For VDD < 2.7 V, tOE max is 25 ns.
4. tHZ and tOHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
FM28V020
Document Number: 001-86204 Rev. *H Page 10 of 22
SRAM Write Cycle
tWC tWC Write cycle time 140 – ns
tCA –Chip enable active time 70 – ns
tCW tSCE Chip enable to write enable HIGH 70 – ns
tPC –Pre-charge time 70 – ns
tPWC –Page mode write enable cycle time 35 – ns
tWP tPWE Write enable pulse width 18 – ns
tAS tSA Address setup time (to CE LOW) 0 – ns
tAH tHA Address hold time (CE Controlled) 70 – ns
tASP –Page mode address setup time (to WE LOW) 5 – ns
tAHP –Page mode address hold time (to WE LOW) 20 – ns
tWLC tPWE Write enable LOW to chip disabled 25 – ns
tWLA –Write enable LOW to A14-3 change 25 – ns
tAWH – A14-3 change to write enable HIGH 140 – ns
tDS tSD Data input setup time 15 – ns
tDH tHD Data input hold time 0 – ns
tWZ[6, 7] tHZWE Write enable LOW to output HI-Z – 10 ns
tWX[7] –Write enable HIGH to output driven 5 – ns
tWS[7, 8] –Write enable to CE LOW setup time 0 – ns
tWH[7, 8] –Write enable to CE HIGH hold time 0 – ns
AC Switching Characteristics (continued)
Over the Operating Range
Parameters [2]
Description Min Max Unit
Cypress
Parameter Alt Parameter
Notes
6. tWZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
7. This parameter is characterized but not 100% tested.
8. The relationship between CE and WE determines if a CE or WE controlled write occurs.
FM28V020
Document Number: 001-86204 Rev. *H Page 11 of 22
Figure 6. Read Cycle Timing 1 (CE LOW, OE LOW)
Figure 7. Read Cycle Timing 2 (CE Controlled)
Figure 8. Page Mode Read Cycle Timing [9]
tOH
D out
A
OE
DQ
tAS
tCE
tCA tPC
tOE
tOHZ
tHZ
tAH
CE
14-0
7-0
A
OE
DQ
tAS
tCA
A
tOE
tCE
tOHZ
tAAP
tOHP
tHZ
tPC
Col 0
Data 0
Col 1
Data 1
Col 2
Data 2
CE
14-3
2-0
7-0
Note
9. Although sequential column addressing is shown, it is not required.
FM28V020
Document Number: 001-86204 Rev. *H Page 12 of 22
Figure 9. Write Cycle Timing 1 (WE Controlled) [10]
Figure 10. Write Cycle Timing 2 (CE Controlled)
Figure 11. Write Cycle Timing 3 (CE LOW) [10]
tHZ
tDH
D in
CE
A
WE
tCA tPC
DQ
tWP
tCW
tAS
D out D out
tDS
tWX
tWZ
tWLC
14-0
7-0
WE
DQ
tCA tPC
tWS
tAS
tWH
tDH
tDS
CE
tAH
D in
A
tCA tPC
tWS
tAS
tWH
tDH
tDS
tAH
14-0
7-0
tDH
tWZ
tWX
D in
A
WE
DQ
tWC
tWLA
tDS
tAWH
D out D out D in
14-0
7-0
Note
10. OE (not shown) is LOW only to show the effect of WE on DQ pins.
FM28V020
Document Number: 001-86204 Rev. *H Page 13 of 22
Figure 12. Page Mode Write Cycle Timing
tASP
tDH
A
WE
tCA tPC
DQ
tCW
ACol 0 Col 1
Data 0
Col 2
tAS
tDS
Data 1
tWP
Data 2
OE
tAHP
tPWC
tAH
CE
tWLC
14-3
2-0
7-0
Power Cycle Timing
Over the Operating Range
Parameter Description Min Max Unit
tPU Power-up (after VDD min. is reached) to first access time 250 –µs
tPD Last write (WE HIGH) to power down time 0 – µs
tVR[11] VDD power-up ramp rate 50 –µs/V
tVF[11] VDD power-down ramp rate 100 –µs/V
Figure 13. Power Cycle Timing
VDD tVF
1.0 V
VDD min
min
VDD
1.0 V
tVR
tPU
tPD
Access Allowed
Note
11. Slope measured at any point on the VDD waveform.
FM28V020
Document Number: 001-86204 Rev. *H Page 14 of 22
Functional Truth Table
CE WE A14–A3A2–A0Operation [12, 13]
H X X X Standby/Idle
↓
L
H
H
V
V
V
V
Read
L H No Change Change Page Mode Read
L H Change V Random Read
↓
L
L
L
V
V
V
V
CE-Controlled Write[13]
L↓VVWE-Controlled Write [13, 14]
L↓No Change V Page Mode Write [15]
↑
L
X
X
X
X
X
X
Starts pre-charge
Notes
12. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH.
13. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first.
14. WE-controlled write cycle begins as a Read cycle and then A14-A3 is latched.
15. Addresses A2-A0 must remain stable for at least 15 ns during page mode operation.
FM28V020
Document Number: 001-86204 Rev. *H Page 15 of 22
Ordering Code Definitions
Ordering Information
Access
time
(ns)
Ordering Code Package
Diagram Package Type Operating
Range
70 FM28V020-SG 51-85026 28-pin SOIC Industrial
FM28V020-SGTR 51-85026 28-pin SOIC
FM28V020-T28G 001-91155 28-pin TSOP I
FM28V020-T28GTR 001-91155 28-pin TSOP I
FM28V020-TG 001-91156 32-pin TSOP I
FM28V020-TGTR 001-91156 32-pin TSOP I
All the above parts are Pb-free.
Option: X = blank or TR
blank = Standard; TR = Tape and Reel
Package Type: XX = SG or T28G or TG
SG = 28-pin SOIC; T28G = 28-pin TSOP I; TG = 32-pin TSOP I
Density: 020 = 256-Kbit
Voltage: V = 2.0 V to 3.6 V
Parallel F-RAM
Cypress
28FM V 020 - XX X
FM28V020
Document Number: 001-86204 Rev. *H Page 16 of 22
Package Diagrams
Figure 14. 28-pin SOIC Package Outline, 51-85026
51-85026 *H
FM28V020
Document Number: 001-86204 Rev. *H Page 17 of 22
Figure 15. 28-pin TSOP I Package Outline, 001-91155
Package Diagrams (continued)
001-91155 **
FM28V020
Document Number: 001-86204 Rev. *H Page 18 of 22
Figure 16. 32-pin TSOP I Package Outline, 001-91156
Package Diagrams (continued)
001-91156 **
FM28V020
Document Number: 001-86204 Rev. *H Page 19 of 22
Acronyms Document Conventions
Units of Measure
Acronym Description
CPU Central Processing Unit
CMOS Complementary Metal Oxide Semiconductor
JEDEC Joint Electron Devices Engineering Council
JESD JEDEC Standards
EIA Electronic Industries Alliance
F-RAM Ferroelectric Random Access Memory
I/O Input/Output
MCU Microcontroller Unit
MPU Microprocessor Unit
RoHS Restriction of Hazardous Substances
RW Read and Write
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
Symbol Unit of Measure
°C degree Celsius
Hz hertz
kHz kilohertz
kkilohm
MHz megahertz
Amicroampere
Fmicrofarad
smicrosecond
mA milliampere
ms millisecond
Mmegaohm
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
FM28V020
Document Number: 001-86204 Rev. *H Page 20 of 22
Document History Page
Document Title: FM28V020, 256-Kbit (32K × 8) F-RAM Memory
Document Number: 001-86204
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3912932 GVCH 02/25/2013 New spec.
*A 3924836 GVCH 03/07/2013 Changed to Production status
Added 28-pin TSOP package related information in all instances across the
document.
Updated DC Electrical Characteristics:
Changed typical value of IDD parameter from 7 mA to 5 mA.
Changed maximum value of IDD parameter from 12 mA to 8 mA.
Updated AC Switching Characteristics:
SRAM Read Cycle:
Changed maximum value of tAAP parameter from 60 ns to 40 ns.
Changed maximum value of tOE parameter from 15 ns to 20 ns.
SRAM Write Cycle:
Changed minimum value of tPWC parameter from 30 ns to 35 ns.
Changed minimum value of tAHP parameter from 15 ns to 20 ns.
Updated Ordering Information:
Updated part numbers
*B 4000965 GVCH 05/15/2013 Added Appendix A - Errata for FM28V020.
*C 4045491 GVCH 06/30/2013 All errata items are fixed and the errata is removed.
*D 4274812 GVCH 03/11/2014 Updated Maximum Ratings:
Added “Maximum Junction Temperature” and its corresponding details.
Added “DC voltage applied to outputs in High-Z state” and its corresponding
details.
Added “Transient voltage (< 20 ns) on any pin to ground potential” and its
corresponding details.
Added “Package power dissipation capability (TA = 25 °C)” and its
corresponding details.
Added “DC output current (1 output at a time, 1s duration)” and its
corresponding details.
Added “Latch-up Current” and its corresponding details.
Removed “Package Moisture Sensitivity Level” and its corresponding
details.
Updated Data Retention and Endurance:
Removed existing details of TDR parameter.
Added details of TDR parameter corresponding to “TA = 85 °C”, “TA = 75 °C”
and “TA = 65 °C”.
Added NVC parameter and its corresponding details.
Added Thermal Resistance.
Updated Package Diagrams:
Removed Package Marking Scheme (top mark).
Removed “Ramtron Revision History”.
Updated to Cypress template.
Completing Sunset Review.
FM28V020
Document Number: 001-86204 Rev. *H Page 21 of 22
*E 4582540 GVCH 11/28/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Pinouts:
Updated Figure 3:
Fixed typo (Replaced VDD with NC for pin 32).
Updated Package Diagrams:
spec 51-85026 – Changed revision from *G to *H.
*F 4881722 ZSK / PSR 08/12/2015 Updated Maximum Ratings:
Removed “Maximum junction temperature” and its corresponding details.
Added “Maximum accumulated storage time” and its corresponding details.
Added “Ambient temperature with power applied” and its corresponding
details.
Updated to new template.
*G 5718305 AESATMP7 04/28/2017 Updated Cypress Logo and Copyright.
*H 6389368 GVCH 11/20/2018 Updated Maximum Ratings:
Replaced “–55 °C to +125 °C” with “–65 °C to +125 °C” in ratings
corresponding to “Storage temperature”.
Updated to new template.
Document History Page (continued)
Document Title: FM28V020, 256-Kbit (32K × 8) F-RAM Memory
Document Number: 001-86204
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 001-86204 Rev. *H Revised November 20, 2018 Page 22 of 22
FM28V020
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