LT4254
1
4254fb
The LT
®
4254 is a high voltage Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. An internal driver controls the high side
N-channel MOSFET gate for supply voltages ranging from
10.8V to 36V. The part features an open-circuit detect
(OPEN) output that indicates abnormally low load current
conditions.
The LT4254 features an adjustable analog foldback cur-
rent limit. If the supply remains in current limit for more
than a programmable time, the N-channel MOSFET shuts
off, the PWRGD output goes low and the LT4254 either
automatically restarts after a time-out delay or latches off
until the UV pin is cycled low. The RETRY pin sets whether
the part will automatically restart after an overcurrent fault
or if it will latch off until the UV pin is cycled low.
The PWRGD output indicates when the output voltage
rises above a programmed level. An external resistor
string from V
CC
provides programmable undervoltage and
overvoltage protection.
■
Hot Board Insertion
■
Electronic Circuit Breaker/Power Bussing
■
Industrial High Side Switch/Circuit Breaker
■
24V Industrial/Alarm Systems
■
12V and 24V Distributed Power Systems
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Controls Supply Voltage from 10.8V to 36V
■
Foldback Current Limiting
■
Open Circuit and Overcurrent Fault Detect
■
Drives an External N-Channel MOSFET
■
Automatic Retry or Latched Off Operation
After Overcurrent Fault
■
Programmable Supply Voltage Power-Up Rate
■
Undervoltage and Overvoltage Protection
■
Open MOSFET Detection
■
Available in 16-Lead SSOP Package
Positive High Voltage
Hot Swap Controller
with Open-Circuit Detect
4254 TA01
R5
0.025Ω
LT4254
SENSEV
CC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER GND
V
IN
24V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R9
40.2k
R6
10ΩR8
140k
PWRGD
V
OUT
24V
1.5A
R4
27k
C
L
C2
33nF
C3
0.1µFC1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
24V, 2A Hot Swap Controller
V
IN
20V/DIV
V
OUT
20V/DIV
INRUSH
CURRENT
500mA/DIV
PWRGD
20V/DIV 2.5ms/DIV
4245 TA02
LT4254 Start-Up Behavior
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
C
L
= 168µF
CONTACT BOUNCE
TYPICAL APPLICATIO
U
LT4254
2
4254fb
Supply Voltage (V
CC
) .................................. –0.3 to 44V
SENSE, PWRGD ......................................... –0.3 to 44V
GATE .......................................................... –0.3 to 50V
FB, UV, OPEN ............................................. –0.3 to 44V
OV .............................................................. –0.3 to 18V
RETRY ........................................................ –0.3 to 15V
TIMER ..................................................... –0.3V to 4.3V
Maximum Input Current (TIMER) ....................... 100µA
Operating Temperature
LT4254C ................................................. 0°C to 70°C
LT4254I ............................................. –40°C to 85°C
Storage Temperature Range ................ –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
(Note 1)
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 24V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Operating Voltage ●10.8 36 V
I
CC
Operating Current 1.9 3 mA
UVLH
Undervoltage Threshold V
CC
Low-to-High Transition ●3.96 4 4.04 V
V
UVHYS
Hysteresis 0.25 0.4 0.55 V
I
INUV
UV Input Current UV = 4.5V –0.1 –1 µA
UV = 0V –1.5 –3 µA
V
OVHL
Overvoltage Threshold V
CC
Low-to-High Transition ●3.96 4 4.04 V
V
OVHYS
Hysteresis 0.25 0.4 0.55 V
I
INOV
OV Input Current 0V ≤ OV < 6.5V 0.1 1 µA
V
OPEN
Open-Circuit Voltage Threshold (V
CC
– V
SENSE
)●2 3.5 5 mV
V
OLOPEN
OPEN Output Low Voltage I
O
= 2mA 0.20 0.5 V
I
O
= 5mA 0.75 1.3 V
I
INOPEN
Leakage Current V
OPEN
= 5V 0.1 1 µA
V
SENSETRIP
SENSE Pin Trip Voltage (V
CC
– V
SENSE
) FB = 0V ●5.5 12 25 mV
FB ≥ 2V ●40 50 60 mV
I
INSNS
SENSE Pin Input Current 40 70 µA
I
PU
GATE Pull-Up Current Charge Pump On, ∆V
GATE
= 7V ●–15 –35 –63 µA
I
PD
GATE Pull-Down Current Any Fault, V
GATE
= 3V 40 60 80 mA
∆V
GATE
External N-Channel Gate Drive (Note 2) V
GATE
– V
CC
, 12V ≤ V
CC
≤ 20V ●4.5 8.8 12.5 V
20V ≤ V
CC
≤ 36V ●10 11 12.5 V
V
FB
FB Voltage Threshold FB High-to-Low Transition ●3.96 4 4.04 V
FB Low-to-High Transition ●4.20 4.45 4.65 V
V
FBHYS
FB Hysteresis Voltage 0.3 0.45 0.60 V
V
OLPGD
PWRGD Output Low Voltage I
O
= 1.6mA 0.25 0.4 V
I
O
= 5mA 0.63 1.0 V
ORDER PART NUMBER
GN PART MARKING
4254
4254I
LT4254CGN
LT4254IGN
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Note: NC = No Connect
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
GN PACKAGE
16-LEAD PLASTIC TSSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
UV
OV
NC
OPEN
PWRGD
NC
RETRY
GND
VCC
SENSE
NC
GATE
NC
NC
FB
TIMER
T
JMAX
= 125°C, θ
JA
= 130°C/W
LT4254
3
4254fb
T
A
= 25°C
V
CC
(V)
10
1.0
I
CC
(mA)
1.5
2.0
2.5
3.0
15 20 25 30
4254 G03
35 40
I
PWRGD
PWRGD Pin Leakage Current V
PWRGD
= 36V 0.1 10 µA
I
INFB
FB Input Current FB = 4.5V –1 –0.1 µA
I
TIMERPU
TIMER Pull-Up Current ●– 60 – 120 –180 µA
I
TIMERPD
TIMER Pull-Down Current ●135 µA
V
THTIMER
TIMER Shut-Down Threshold Voltage C
TIMER
= 10nF ●4.3 4.65 5 V
D
TIMER
Duty Cycle (RETRY Mode) ●1.5 3 4.5 %
V
RETRY(TH)
RETRY Threshold ●0.4 0.8 1.2 V
I
INRTR
RETRY Input Current RETRY = GND –120 –85 –40 µA
t
PHLUV
UV Low to GATE Low C
GATE
= 100pF 1.7 µs
t
PLHUV
UV High to GATE High C
GATE
= 100pF 6 µs
t
PHLFB
FB Low to PWRGD Low 0.8 µs
t
PLHFB
FB High to PWRGD High 3.2 µs
t
PHLSENSE
(V
CC
– V
SENSE
) High to GATE Low V
CC
– V
SENSE
= 275mV 2.5 4 µs
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 24V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: An internal clamp limits the GATE pin to a maximum of 11V above
V
CC
(under normal operating conditions). Driving this pin to a voltage
beyond the clamp voltage may damage the part.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs VCC
SENSE Pin Regulation Voltage
vs Temperature, FB = 0V
SENSE Pin Regulation Voltage
vs Temperature, FB > 2V
TEMPERATURE (°C)
–50
SENSE REGULATION VOLTAGE (mV)
13
15
17
25 75
4254 G01
11
9
–25 0 50 100 125
7
5
TEMPERATURE (°C)
–50
40
SENSE REGULATION VOLTAGE (mV)
45
50
55
60
–25 0 25 50
4254 G02
75 100 125
LT4254
4
4254fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
FB Pin Hysteresis vs Temperature
GATE Pin Pull-Up Current
vs Temperature
GATE Pin Pull-Down Current
vs Temperature
∆VGATE vs Temperature ∆VGATE vs VCC
ICC vs Temperature
FB Pin Threshold Voltage (Low-
to-High) vs Temperature
TEMPERATURE (°C)
–50 –25
1.0
ICC (mA)
1.4
2.0
050 75
4254 G04
1.2
1.8
1.6
25 100 125
VCC = 36V
VCC = 10.8V
VCC = 24V
TEMPERATURE (°C)
–50
FB THRESHOLD VOLTAGE LOW-TO-HIGH (V)
4.42
4.44
4.46
25 75
4254 G05
4.40
4.38
–25 0 50 100 125
4.36
4.34
TEMPERATURE (°C)
–50
FB THRESHOLD VOLTAGE HIGH-TO-LOW (V)
4.00
4.01
4.02
25 75
4254 G06
3.99
3.98
–25 0 50 100 125
3.97
3.96
FB Pin Threshold Voltage (High-
to-Low) vs Temperature
TEMPERATURE (°C)
–50
300
FB HYSTERESIS (mV)
320
360
380
400
50
480
4254 G07
340
0
–25 75 100
25 125
420
440
460
TEMPERATURE (°C)
–50
–45
I
GATE
PULL-UP CURRENT (µA)
–40
–30
–25
–20
50
0
4254 G08
–35
0
–25 75 100
25 125
–15
–10
–5
TEMPERATURE (°C)
–50
I
GATE
PULL-DOWN CURRENT (mA)
75
25
4254 G09
60
50
–25 0 50
45
40
80
70
65
55
75 100 125
TEMPERATURE (°C)
–50
∆V
GATE
(V
GATE
– V
CC
) (V)
11
25
4254 G10
8
6
–25 0 50
5
4
12
10
9
7
75 100 125
V
CC
= 18V
V
CC
= 12V
V
CC
= 10.8V
∆VGATE vs Temperature
TEMPERATURE (°C)
–50
∆VGATE (VGATE – VCC) (V)
12.0
12.5
13.0
25 75
4254 G11
11.5
11.0
–25 0 50 100 125
10.5
10.0
VCC = 24V, 36V
VCC = 20V
V
CC
(V)
10
14
12
10
8
6
4
2
025 35
" #" /
15 20 30 40
∆V
GATE
(V
GATE
– V
CC
) (V)
T
A
= 25°C
LT4254
5
4254fb
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TIMER Shutdown Threshold
vs Temperature TIMER Pin Pull-Up Current vs VCC
UV Threshold Voltage (High-to-
Low) vs Temperature
TIMER Pin Pull-Up Current
vs Temperature
UV Hysteresis vs Temperature
TEMPERATURE (°C)
–50 –25
–150
–130
–140
TIMER PULL-UP CURRENT (µA)
–110
–80
050 75
4254 G13
–120
–90
–100
25 100 125
TIMER Pin Pull-Down Current
vs Temperature
TEMPERATURE (°C)
–50
TIMER PULL-DOWN CURRENT (µA)
3.5
25
4254 G14
2.0
1.0
–25 0 50
0.5
0
4.0
3.0
2.5
1.5
75 100 125
TIMER Pin Pull-Down Current
vs VCC
TEMPERATURE (°C)
–50 –25
4.0
TIMER SHUTDOWN THRESHOLD VOLTAGE (V)
4.4
5.0
050 75
4254 G16
4.2
4.8
4.6
25 100 125
TEMPERATURE (°C)
–50
UV THRESHOLD VOLTAGE HIGH-TO-LOW (V)
3.65
25
4254 G18
3.62
3.60
–25 0 50
3.59
3.58
3.66
3.64
3.63
3.61
75 100 125
UV Threshold Voltage (Low-to-
High) vs Temperature
TEMPERATURE (°C)
–50
UV THRESHOLD VOLTAGE LOW-TO-HIGH (V)
4.00
4.01
4.02
25 75
4254 G19
3.99
3.98
–25 0 50 100 125
3.97
3.96
TEMPERATURE (°C)
–50
UV HYSTERESIS (mV)
400
450
500
25 75
4254 G20
350
300
–25 0 50 100 125
250
200
OV Threshold Voltage (Low-to-
High) vs Temperature
TEMPERATURE (°C)
–50
OV THRESHOLD VOLTAGE (LOW-TO-HIGH) (V)
4.00
4.01
4.02
25 75
4257 G21
3.99
3.98
–25 0 50 100 125
3.97
3.96
VCC (V)
TA = 25°C
10
–126
TIMER PULL-UP CURRENT (µA)
–124
–122
–120
–118
–116
15 20 25 30
4254 G17
35 40
VCC (V)
10
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0 25 35
" #" /#
15 20 30 40
TIMER PULL-DOWN CURRENT (µA)
TA = 25°C
LT4254
6
4254fb
OPEN Output Voltage vs ILOAD
OPEN Pin Threshold Voltage
vs Temperature PWRGD Output Voltage vs ILOAD
TYPICAL PERFOR A CE CHARACTERISTICS
UW
OV Threshold Voltage (High-to-
Low) vs Temperature OV Hysteresis vs Temperature
PI FU CTIO S
UUU
V
CC
: Input Supply Voltage. The positive supply input
ranges from 10.8V to 36V for normal operation. I
CC
is
typically 1.9mA. An internal circuit disables the LT4254 for
inputs less than 9.8V (typ).
GND: Device Ground. This pin must be tied to a ground
plane for best performance.
FB: Power Good Comparator Input. FB monitors the
output voltage through an external resistive divider. When
the voltage on the FB pin is lower than the high-to-low
threshold of 4V, the PWRGD pin is pulled low and released
when the FB pin is pulled above the 4.45V low-to-high
threshold.
The FB pin also affects foldback current limit (see Figure 7
and related discussion). To disable PWRGD monitoring,
connect FB to the output voltage and float the PWRGD pin.
TIMER: Timing Input. An external timing capacitor from
TIMER to GND programs the maximum time the part is
allowed to remain in current limit. When the part goes into
current limit, a 120µA pull-up current starts to charge the
timing capacitor. When the voltage on the TIMER pin
TEMPERATURE (°C)
–50
3.50
OV THRESHOLD VOLTAGE (HIGH-TO-LOW) (V)
3.55
3.60
3.65
3.70
–25 0 25 50
4254 G22
75 100 125
TEMPERATURE (°C)
–50
OV HYSTERESIS (mV)
400
450
500
25 75
4254 G23
350
300
–25 0 50 100 125
250
200
ILOAD (mA)
0
0
OPEN VOL (V)
2
4
6
8
10
2468
4254 G24
10 12
TA = 25°C
TEMPERATURE (°C)
–50
3.0
OPEN THRESHOLD VOLTAGE (mV)
3.5
4.0
4.5
5.0
–25 0 25 50
4254 G25
75 100 125
ILOAD (mA)
0
0
PWRGD VOL (V)
1
2
3
4
6
2468
4254 G26
10 12
5
TA = 25°C
LT4254
7
4254fb
reaches 4.65V (typ), the GATE pin is pulled low; the TIMER
pull-up current will be turned off and the capacitor is dis-
charged by a 3µA pull-down current. When the TIMER pin
falls below 0.65V (typ), the GATE pin turns on again if the
RETRY pin is high (if the RETRY pin is low, the UV pin must
be pulsed low to reset the internal fault latch before the
GATE pin will turn on). If the RETRY pin is grounded and
the UV pin is not cycled low, the GATE pin remains latched
off and the TIMER pin will be discharged near ground. The
UV pin must be cycled low after the TIMER pin has dis-
charged below 0.65V (typ) to reset the part.
If the RETRY pin is floating or connected to a voltage above
its 1.2V threshold, the LT4254 automatically restarts after
a current fault. Under an output short-circuit condition, the
LT4254 cycles on and off with a 3% on-time duty cycle.
RETRY: Current Fault Retry. RETRY commands the opera-
tional mode of the current limit. If the RETRY pin is
floating, the LT4254 automatically restarts after a current
fault. If it is connected to a voltage below 0.4V, the part
latches off after a current fault (which requires that the UV
pin be cycled low in order to start normal operation again).
GATE: High Side Gate Drive for the External N-Channel
MOSFET. An internal charge pump guarantees at least 10V
of gate drive for V
CC
supply voltages above 20V and 4.5V
gate drive for V
CC
supply voltages between 10.8V and 20V.
The rising slope of the voltage on GATE is set by an external
capacitor connected from the GATE pin to GND and an
internal 35µA pull-up current source from the charge
pump output.
If the current limit is reached, the GATE pin voltage is
adjusted to maintain a constant voltage across the sense
resistor while the timing capacitor starts to charge. If the
TIMER pin voltage ever exceeds 4.65V, the GATE pin is
pulled low.
The GATE pin is also pulled to GND whenever the UV pin
is pulled low, or the V
CC
supply voltage drops below the
externally programmed undervoltage threshold or above
the overvoltage threshold.
The GATE pin is clamped internally to a maximum voltage
of 11V (typ) above VCC under normal operating conditions.
PI FU CTIO S
UUU
Driving this pin beyond the clamp voltage may damage the
part. A zener diode is needed between the gate and source
of the external MOSFET to protect its gate oxide under in-
stantaneous short-circuit conditions. See Applications
Information.
SENSE: Current Limit Sense. A sense resistor is placed in
the supply path between V
CC
and SENSE. The current limit
circuit regulates the voltage across the sense resistor (V
CC
– SENSE) to 50mV while in current limit when FB is 2V or
higher. If FB drops below 2V, the regulated voltage across
the sense resistor decreases linearly and stops at 15mV
when FB is 0V. The OPEN output also uses SENSE to detect
when the output current is less than (3.5mV)/R5. To defeat
current limit, connect SENSE to V
CC
.
PWRGD: Open Collector Output to GND. PWRGD is pulled
low whenever the voltage on FB falls below the high-to-low
threshold voltage. It goes into a high impedance state
when the voltage on FB exceeds the low-to-high threshold
voltage. An external pull-up resistor can pull PWRGD to a
voltage higher or lower than V
CC
. To disable PWRGD, float
this pin and connect FB to the output voltage.
UV: Undervoltage Sense. UV is an input that enables the
output voltage. When the UV pin is driven above 4V, the
GATE pin starts charging and the output turns on. When
the UV pin goes below 3.6V, the GATE pin discharges and
the output shuts off.
Pulsing the UV pin to ground after a current limit fault cycle
(TIMER pin dischaged to below 0.65V typ) resets the fault
latch (when RETRY pin is low, commanding latch off
operation) and allows the part to turn back on. To disable
UV sensing, connect the pin to V
CC
through a 10k resistor.
OV: Overvoltage Sense. OV is an input that disables the
output voltage. If OV ever goes above 4V, the GATE pin is
discharged and the output shuts off. When OV goes below
3.6V, the GATE pin starts charging and the output turns
back on. To disable OV sensing, connect pin to ground.
OPEN: Open Circuit Detect Output. This pin is an open
collector output that releases and is pulled high through an
external resistor if the load current is less than (3.5mV/R5).
If not used, leave this pin disconnected.
LT4254
8
4254fb
BLOCK DIAGRA
W
+
–
–
+
–
+
123µA
VP
VP
3.5mV
LOGIC
2V
12mV ~ 50mV
9.8V 4V
4V
VCC
GND
0.65V
4.65V
–
+
–
+
4V4V
PWRGD
TIMER
4254 BD
V
CC
SENSE
V
P
GEN
FB
OV
3µA
UV
RETRY
GATE
OPEN
+
–
+
–
+
–
CHARGE
PUMP
AND
GATE
DRIVER
+
–
REF GEN
16
10
7
1
2
15
4
13
5
9
8
CURRENT
LIMIT
INTERNAL
UV
TIMER
LOW
TIMER
HIGH
FOLDBACK
OV
UV
OPEN-
CIRCUIT
DETECT
LT4254
9
4254fb
TEST CIRCUIT
TI I G DIAGRA S
WUW
UV
4254 F02
GATE VOUT +2V
tPLHUV
4V
VOUT +2V
tPHLUV
3.6V
FB
4254 F03
PWRGD 1V
tPLHFB
4.45V
1V
tPHLFB
4V
VCC – SENSE
4254 F04
GATE
VCC
tPHLSENSE
50mV
Figure 2. UV to GATE Timing Figure 3. VOUT to PWRGD Timing
Figure 4. SENSE to GATE Timing
Figure 1
VCC
SENSE
GATE
TIMER
RETRY
PWRGD
OPEN
FB
OV
UV
24V
GND
3V
3V
4254 TC
100pF
+–
+–
+–
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4254 is designed to turn on a board’s supply
voltage in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The
device also provides undervoltage and overvoltage as well
as overcurrent protection while a power good output
signal indicates when the output supply voltage is ready
with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
LT4254
10
4254fb
APPLICATIO S I FOR ATIO
WUUU
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
When the power pins first make contact, transistor Q1 is
held off. If the voltage on the V
CC
pin is between the
externally programmed undervoltage and overvoltage
thresholds, and the voltage on the TIMER pin is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage at the GATE pin rises with a slope equal to 35µA/
C1 and the supply inrush current is set at:
I
INRUSH
= C
L
• 35µA/C1
If the voltage across the current sense resistor R5 reaches
V
SENSETRIP
, the inrush current will be limited by the
internal current limit circuitry. The voltage on the GATE pin
is adjusted to maintain a constant voltage across the sense
resistor and the TIMER pin begins to charge.
When the FB pin voltage goes above the low-to-high V
FB
threshold, the PWRGD pin goes high.
Short-Circuit Protection
The LT4254 features a programmable foldback current
limit with an electronic circuit breaker that protects against
short circuits or excessive load currents. The current limit
is set by placing a sense resistor (R5) between V
CC
and
SENSE.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
Figure 5. 2A, 24V Application
4254 F05
R5
0.025Ω
LT4254
SENSE
13
10
5
7
8
16 15
1
2
4
9
VCC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER GND
VIN
24V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R9
40.2k
R6
10Ω
R8
140k
PWRGD
VOUT
24V
1.5A
R4
27k
CL
C2
33nF
C3
0.1µFC1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
back as a function of the output voltage, which is sensed
internally on the FB pin.
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output at the FB pin
increases, the voltage across the sense resistor increases
until the FB pin reaches 2V, at which point the voltage
across the sense resistor is held constant at 50mV (see
Figure 7). The current limit threshold is calculated as:
I
LIMIT
= 50mV/R5
where R5 is the sense resistor.
For a 0.025Ω sense resistor, the current limit is set at
2000mA and folds back to 600mA when the output is
shorted to ground. Thus, MOSFET dissipation under short-
circuit conditions is reduced from 36W to12W. See the
Figure 6. Start-Up Waveforms
2.5ms/DIV 4254 F06
I
OUT
500mA/DIV
PWRGD
20V/DIV
V
OUT
20V/DIV
GATE
20V/DIV C
L
= 185µF
LT4254
11
4254fb
Layout Considerations section for important information
about board layout to minimize current limit threshold
error.
The LT4254 also features a variable overcurrent response
time. The time required for the part to regulate the GATE
pin voltage is a function of the voltage across the sense
resistor connected between the VCC pin and the SENSE pin.
This helps to eliminate sensitivity to current spikes and tran-
sients that might otherwise unnecessarily trigger a current
limit response and increase MOSFET dissipation. Figure 8
shows the response time as a function of the overdrive at
the SENSE pin.
TIMER
The TIMER pin provides a method for programming the
maximum time the part is allowed to operate in current
limit. When the current limit circuitry is not active, the
TIMER pin is pulled to GND by a 3µA current source. When
the current limit circuitry becomes active, a 123µA pull-up
current source is added to the TIMER pin and the voltage
will rise with a slope equal to 120µA/C
TIMER
as long as the
circuitry stays active. Once the desired maximum current
limit time is known, the capacitor value is:
C(nF) = 25.8 • t(ms)
Whenever the TIMER pin reaches 4.65V (typ), the internal
fault latch is set causing the GATE to be pulled low and the
TIMER pin to be discharged to GND by the 3µA current
source. The part is not allowed to turn on again until the
voltage at the TIMER pin falls below 0.65V (typ).
The TIMER pin must never be pulled high by a low
impedance because whenever the TIMER pin voltage rises
above the upper threshold (typically 4.65V) the pin char-
acteristics change from a high impedance current source
to a low impedance. If the pin must be pulled high by a logic
signal, then a resistor must be put in series with the TIMER
pin to limit the current to approximately 100 microam-
peres. The resistance should be chosen as follows:
R
SERIES
= (V
LOGIC
– 4.65V)/100µA
Whenever the GATE pin is commanded off by any fault
condition, it is discharged with a high current, turning off
the external MOSFET. The waveform in Figure 9 shows how
the output latches off following a short-circuit. The drop
across the sense resistor is held at 12mV as the timer ramps
up. Since the output did not rise bringing FB above 2V and
the current is still 12mV/R5, the circuit latches off.
Automatic Restart
If the RETRY pin is floating, then the functionality is as
described in the previous section.
When the voltage at the TIMER pin ramps back down to
0.65V (typ), the LT4254 turns on again. If the short-circuit
condition at the output still exists, the cycle will repeat
itself indefinitely. The duty cycle under short-circuit con-
ditions is 3% which prevents Q1 from overheating.
Latch Off Operation
If the RETRY pin is grounded, the LT4254 will latch off
after a current fault. After the part latches off, it may be
APPLICATIO S I FOR ATIO
WUUU
12mV
0V 2V FB
4254 F07
50mV
V
CC
– V
SENSE
50 100 150 200
4254 F08
12
10
8
6
4
2
RESPONSE TIME (µs)
VCC – VSENSE (mV)
0
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 8. Response Time to Overcurrent
LT4254
12
4254fb
commanded to start back up. This can be commanded by
cycling the UV pin to ground and then back high (this
command can only be accepted after the TIMER pin
discharges below the 0.65V typ threshold, so as to prevent
overheating transistor Q1).
Therefore, using the RETRY pin only, the LT4254 will
either latch off after an overcurrent fault condition or it will
go into a hiccup mode.
Undervoltage and Overvoltage Detection
The LT4254 uses the UV and OV pins to monitor the V
CC
voltage and allow the user the greatest flexibility for setting
the operational thresholds. The UV and OV pins are
internally connected to an analog window comparator.
Any time that the UV pin goes below 3.6V or the OV pin
goes above 4V, the gate will be pulled low until the UV/OV
pin voltages return to the normal operation voltage win-
dow (4V and 3.65V, respectively).
Power Good Detection
The LT4254 includes a comparator for monitoring the
output voltage. The output voltage is sensed through the
FB pin via an external resistor string. The comparator’s
output (PWRGD pin) is an open collector capable of
operating from a pull-up as high as 36V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 11
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accom-
plished by transistor Q2 and R10.
Open FET Detection
The LT4254 can be used to detect the presence of an open
FET. When the voltage across the sense resistor is less
than 3.5mV, the open collector pull-down device is shut
off allowing the OPEN pin to be externally pulled high.
An open FET condition is signalled when the OPEN pin is
high and the PWRGD pin is low (after the part has
completed its start-up cycle). This open FET condition can
be falsely signalled during start-up if the load is not
activated until after PWRGD goes high. To avoid this false
indication, the OPEN and PWRGD pins should not be
polled for a period of time, t
STARTUP
, given by:
31
35
••VC
At
CC STARTUP
µ=
This can be accomplished either by a microcontroller (if
available) or by placing an RC filter as shown in Figure 12.
Once the OPEN voltage exceeds the monitoring logic thresh-
old, V
THRESH
, and PWRGD is low, an open FET condition
is signalled. In order to prevent a false indication, the RC
product should be set with the following equation:
RC VC
AV
VV
CC
LOGIC
LOGIC THRESH
>
µ⎛
⎝
⎜⎞
⎠
⎟
⎛
⎝
⎜⎞
⎠
⎟
31
35
••
ln –
Another condition that can cause a false indication is if the
LT4254 goes into current limit during start-up. This will
cause t
STARTUP
to be longer than calculated. Also, if the
APPLICATIO S I FOR ATIO
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Figure 9. Latch Off Waveforms Figure 10. RETRY Waveforms
I
OUT
500mA/DIV
2.5ms/DIV 4254 F09
V
OUT
20V/DIV
TIMER
5V/DIV
GATE
20V/DIV
Latch Off Operation
I
OUT
500mA/DIV
2.5ms/DIV 4254 F10
V
OUT
20V/DIV
TIMER
5V/DIV
GATE
1V/DIV
Automatic Restart Operation (Short-Ciruit Output)
LT4254
13
4254fb
LT4254 stays in current limit long enough for the TIMER
pin to fully charge up to its threshold, the LT4254 will
either latch off (RETRY = 0) or go into the current limit
hiccup mode (RETRY = floating). In either case, an open
FET condition will be falsely signalled. If the LT4254 does
go into current limit during start-up, C1 can be increased
(see Power-Up Sequence).
Supply Transient Protection
The LT4254 is 100% tested and guaranteed to be safe
from damage with supply voltages up to 44V. However,
voltage transients above 44V may damage the part.
During a short-circuit condition, the large change in
currents flowing through the power supply traces can
cause inductive voltage transients which could exceed
44V. To minimize the voltage transients, the power trace
parasitic inductance should be minimized by using wider
traces or heavier trace plating and a 0.1µF bypass capaci-
tor should be placed between VCC and GND. A surge
APPLICATIO S I FOR ATIO
WUUU
suppressor (Transorb) at the input can also prevent
damage from voltage transients.
GATE Pin
A curve of gate drive vs V
CC
is shown in Figure 13. The
GATE pin is clamped to a maximum voltage of 12V above
the V
CC
voltage. This clamp is designed to withstand the
internal charge pump current. An external zener diode
should be used if the possibility exists for an instanta-
neous low resistance short on V
OUT
to occur. At a mini-
mum input supply voltage of 12V, the minimum gate drive
voltage is 4.5V. When the input supply voltage is higher
than 20V, the gate drive voltage is at least 10V and a
Figure 11. Active Low Enable PWRGD Application
4254 F11
R5
100mΩ
LT4254
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER GND
V
CC
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R6
10Ω
V
OUT
V
LOGIC
R4
27k
R8
140k
C
L
R10
27k
C2
33nF
C3
0.1µFC1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
R9
40.2k
Q2
PWRGD
GND
Figure 12. Delay Circuit for OPEN FET Detection
4
R
C
4254 F12
OPEN
LT4254
TO
MONITORING
LOGIC
VLOGIC
INTERNAL
OPEN COLLECTOR
PULL-DOWN
Figure 13. ∆VGATE vs VCC
VCC (V)
10
∆VGATE (V)
8
9
10
4254 F13
7
6
420 30 40
5
12
11
∆VGATE = VGATE – VCC
LT4254
14
4254fb
APPLICATIO S I FOR ATIO
WUUU
standard threshold MOSFET can be used. In applications
from 12V to 15V range, a logic level MOSFET must be
used.
In some applications it may be possible for the V
OUT
pin to
ring below ground (due to the parasitic trace inductance).
Higher current applications, especially where the output
load is physically far away from the LT4254 will be more
susceptible to these transients. This is normal and the
LT4254 has been designed to allow for some ringing
below ground. However, if the application is such that
V
OUT
can ring more than 1V below ground, damage may
occur to the LT4254 and an external diode from ground
(anode) to V
OUT
(cathode) will have to be added to the
circuit as shown in Figure 14 (it is critical that the reverse
breakdown voltage of the diode be higher than the highest
expected V
CC
voltage). A capacitor placed from ground to
V
OUT
directly at the LT4254 pins can help reduce the
amount of ringing on V
OUT
but it may not be enough for
some applications.
During a fault condition, the LT4254 pulls down on the
GATE pin with a switch capable of sinking about 55mA.
Once the GATE voltage drops below the output voltage by
a diode forward voltage, the external zener will forward
bias and the output will also be discharged to GND. In
addition to the GATE capacitance, the output capacitance
will be discharged through the LT4254. In applications
that have very large output capacitors, this could cause
damage to the LT4254. Therefore, the maximum output
capacitance that can be used with the LT4254 is 1000µF.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
LT4254 becomes active and pulls down on GATE). This is
due to the drain to gate capacitance forcing current into R7
and C1 when the drain voltage steps up from ground to V
CC
with an extremely fast rise time. To alleviate this situation,
a Schottky diode should be put across R7 with the cathode
connected to C1 as shown in Figure 16.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. The minimum trace width for
1oz copper foil is 0.02" per amp to make sure the trace
stays at a reasonable temperature. 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/. Small resistances can cause
large errors in high current applications. Noise immunity
will be improved significantly by locating resistor dividers
close to the pins with short V
CC
and GND traces. A 0.1µF
decoupling capacitor from UV to GND is also required.
Figure 15 shows a layout that meets these requirements.
Figure 14. Negative Output Voltage Protection Diode Application
4254 F14
R5
0.033Ω
LT4254
SENSE
13
10
5
7
8
16 15
1
2
4
9
V
CC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER GND
V
CC
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
MRA4003T3
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R9
40.2k
R6
10ΩR8
140k
V
OUT
R4
27k
C
L
100µF
C2
33nF
C3
0.1µFC1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
GND
LT4254
15
4254fb
APPLICATIO S I FOR ATIO
WUUU
Figure 15. Recommended Component Placement
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
UV
OV
NC
OPEN
PWRGD
NC
RETRY
GND
V
CC
SENSE
NC
GATE
NC
NC
FB
TIMER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R6
Q1
V
OUT
R7
R5
R
SENSE
R4
PWRGD
OPEN
GND
4254 F15
GND
R8 D1
R3
LT4254
R2
R1
V
CC
C2
C1
R9
V
CC
SHORT
PIN
VIA
2ND LAYER METAL
GN16 (SSOP) 0204
12
345678
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
16 15 14 13
.189 – .196*
(4.801 – 4.978)
12 11 10 9
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.007 – .0098
(0.178 – 0.249)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.009
(0.229)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
LT4254
16
4254fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
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© LINEAR TECHNOLOGY CORPORATION 2003
LT 1205 REV B • PRINTED IN USA
Figure 16. High dV/dT MOSFET Turn-On Protection Circuit
TYPICAL APPLICATIO
U
4254 F16
R5
0.033Ω
LT4254
SENSEVCC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER GND
VCC
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100Ω
R9
40.2k
R6
10ΩR8
140k
VOUT
IN4148W
R4
27k
CL
100µF
C2
33nF
C3
0.1µF
C1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
GND
