UltraLogic™ 64-Macrocell Flash CPLD
CY7C372i
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 38-03033 Rev. *A Revised April 16, 2004
Features
• 64 macrocells in four logic blocks
• 32 I/O pins
• Five dedi ca te d inp uts including two cl oc k pins
• In-System Reprogrammable (ISR™) Flash technology
— JTAG interface
• Bus Hold capabilities on all I/Os an d de di cated inputs
• No hidden delays
•High speed
—f
MAX = 125 MHz
—t
PD = 10 ns
—t
S = 5.5 ns
—t
CO = 6.5 ns
• Fully PCI compliant
• 3.3V or 5.0V I/O operation
• Available in 44-pin PLCC, TQFP, and CLCC packages
• Pin-compatible with the CY7C371i
Functional Description
The CY7C372i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C372i is
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C372i
is electrically erasable and ISR, which simpli fies both design
and manufacturing flows, thereby reducing costs. The
Cypress ISR function is implemented through a JTAG serial
interface. Data is shifted in and out through the SDI and SDO
pins. The ISR interface is enabled using the programming
voltage pin (ISREN). Additionally, because of the superior
routab ilit y of th e FLASH370i devices, ISR often allows users to
change existing logic designs while simultaneously fixing
pinout assignments.
The 64 macrocells in the CY7C37 2i are divid ed be tween fou r
logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
The logic blocks in the FLASH370i architecture are connected
with an extremely fast a nd predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Logic Block Diagram
PIM
INPUT
MACROCELLS
CLOCK
INPUTS
INPUTS
LOGIC LOGIC
22
36
16 16
36
8 I/Os 8 I/Os
16 16
LOGIC
36
16 16
36
8 I/Os 8 I/Os
23 INPUT/CLOCK
MACROCELLS
I/O0-I/O7LOGIC
I/O8-I/O15 I/O16-I/O23
I/O24-I/O31
BLOCK
A
BLOCK
B
BLOCK
D
BLOCK
C
CY7C372i
Document #: 38-03033 Rev. *A Page 2 of 13
Selection Guide
7C372i-125 7C372i-100 7C372i-83 7C372iL-83 7C372i-66 7C372iL-66
Maximum Propagation Delay[1], tPD (ns) 10 12 15 15 20 20
Minimum Set-up, tS (ns) 5.5 6.0 8 8 10 10
Maximum Clock to Output[1], tCO (ns) 6.5 6.5 8 8 10 10
Typical Supply Current, ICC (mA) 757575457545
Pin Configurations
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
I/O27/SDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I2
I/O23
I/O22
I/O21
I/O5/SCLK
I/O6
I/O7
I0
ISREN
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
VCCIO
VCCINT
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
6534 2
8
9
7
10
11
144
18
15
16
14
13
12
17 19 20 2221 23 24 2726 2825
31
30
29
32
33
34
39
37
38
36
35
43 42 4041
PLCC
TopView
/SMODE
/SDO
1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3 2 4443424140 I/O27/SDI
I/O26
I/O25
I/O24
CLK1/I4
GND
I3
I2
I/O23
I/O22
I/O21
I/O5/SCLK
I/O6
I/O7
I0
ISREN
GND
CLK0/I1
I/O8
I/O9
I/O10
I/O11
GND
I/O20
I/O2
GND
VCC
VCC
I/O3
I/O4
I/O1
I/O0
I/O29
I/O30
I/O31
I/O28
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
/SMODE
/SDO
CLCC
TopView
CY7C372i
Document #: 38-03033 Rev. *A Page 3 of 13
Functional Description
Like all members of the FLASH370i family , the CY7C372i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 32 I/O pins on the
CY7C372i. In addition, there are three dedicated inputs and
two input/clock pins.
Finally, the CY7C372i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used. or the type of application, the ti ming param-
eters on the CY7C372i remain the same.
Logic Block
The number of logic blocks d istinguishes the membe rs of the
FLASH370i family. The CY7C372i includes four logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 ma crocells.
Product Term Array
The product term array in the FLASH370i logic block incl udes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370 PLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Half of the macrocells on the CY7C372i have separate I/O pins
associated with them. In other words, each I/O pin is shared
by two macrocells. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The I/O macrocell also features
a separate feedback path to the PIM so that the register can
be buried if the I/O pin is used as an input.
Buried Macrocell
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a regi ster that can be configured as combi-
natorial, as a D flip-flop, a T flip-flop, or a latch. The cl ock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the
addition of input register capability. The user can program the
buried macrocell to act as an input register (D-type or latch)
whose input comes from the I/O pin associated with the neigh-
boring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable I nterconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
four logic blocks on the CY7C372i to the inputs and to each
other. All inputs (including feedbacks) travel th rough the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Speci fication publishe d by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pin s:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V powe r
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
In addition to ISR capability , a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor , is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device withou t cutting
trace connections to VCC or GND.
Design Tools
Development software for the CY7C372i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enter-
prise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
CY7C372i
Document #: 38-03033 Rev. *A Page 4 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Tem perature ................... ... ...........–65°C to +150°C
Ambient Temperature with
Power Applied...... .. ... ..................................–55°C to +125°C
Supply Voltage to Ground Potential...............–0.5V to +7.0V
DC Voltage Appli ed to Outputs
in High-Z State....... ........................................–0.5V to +7.0V
DC Input Voltage............. ... ............................–0.5V to +7.0V
DC Program Voltage............. .. ......................................12.5V
Output Current into Outputs ........................................16 mA
Static Discharge Voltage...........................................> 2001V
(per MIL–STD–883, Method 3015)
Latch-up Current.....................................................> 200 mA
Operating Range
Range Ambient
Temperature VCC
VCCINT VCCIO
Commercial 0°C to +70°C5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
Industrial −40°C to +85°C5V ± 0.5V 5V ± 0.5V
3.3V ± 0.3V
Military[2] –55°C to +125°C 5V ± 0.5V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter Description Test Conditions Min. Typ. Max. Un it
VOH Output HIGH Voltage VCC = Min. IOH = –3.2 mA (Com’l/Ind)[5] 2.4 V
IOH = –2.0 mA (Mil) 2.4 V
VOHZ Output HIGH Voltage with
Output Disabled[8] VCC = Max. IOH = 0 µA (Com’l/Ind)[5, 6] 4.0 V
IOH = –50 µA (Com’l/Ind)[5, 6] 3.6 V
VOL Output LOW Voltage VCC = Min. IOL = 16 mA (Com’l/Ind)[5] 0.5 V
IOL = 12 mA (Mil) 0.5 V
VIH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all
Inputs[7] 2.0 7.0 V
VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for all
Inputs[7] –0.5 0.8 V
IIX Input Load Current VI = Internal GND, VI = VCC –10 +10 µA
IOZ Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output
Disabled –50 +50 µA
VCC = Max., VO = 3.3V, Output Disabled[6] 0 –70 –125 µA
IOS Output Short
Circuit Current[8, 9] VCC = Max., VOUT = 0.5V –30 –160 mA
ICC Power Supply Current [10] VCC = Max., IOUT = 0 mA,
f = 1 MHz, VIN = GND, VCC Com’l/Ind. 75 125 mA
Com’l “L” –66 45 75 mA
Military 75 200 mA
IBHL Input Bus Hold LOW
Sustaining Current VCC = Min., VIL = 0.8V +75 µA
IBHH Input Bus Hold HIGH
Sustaining Current VCC = Min., VIH = 2.0V –75 µA
IBHLO Input Bus Hold LOW
Overdrive Current VCC = Max. +500 µA
IBHHO Input Bus Hold HIGH
Overdrive Current VCC = Max. −500 µA
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC = VCCINT.
5. For SDO: IOH =–2 mA, IOL = 2 mA.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-sta ted during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All ove rshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V OUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10.Measured with 16-b i t counter programmed into each logic block.
CY7C372i
Document #: 38-03033 Rev. *A Page 5 of 13
Note:
11. CI/O for dedicated Inputs, and for I/O pins wit h JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max.
12.CI/O for CLCC package is 15 pF Max.
13.tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Capacitance[9]
Parameter Description Test Conditions Min. Max. Unit
CI/O[11, 12] Input Capacitance VIN = 5.0V at f = 1 MHz 8 pF
CCLK Clock Signal Capacitance VIN = 5.0V at f = 1 MHz 5 12 pF
Inductance[9]
Parameter Description Test Conditions 44-Lead CLCC 44-Lead PLCC Unit
L Maximum Pin Inductance VIN = 5.0V at f = 1 MHz 2 5 nH
Endurance Characteristics[9]
Parameter Description Test Conditions Max. Unit
N Maximum Reprogramming Cycles Normal Programming Conditions 100 Cycles
AC Test Loads and Waveforms
Parameter[13] VxOutput Waveform Measurement Level
tER(–) 1.5V
tER(+) 2.6V
tEA(+) 1.5V
tEA(–) Vthe
(d) Test Waveforms
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
<2ns <2ns
OUTPUT
238Ω(com'l)
319Ω(mil)
170Ω(com'l)
236Ω(mil)
99Ω(com'l)
136Ω(mil)
Equivalent to: THÉ VENIN EQUIVALENT
2.08V(com'l)
2.13V(mil)
238Ω(com'l)
319Ω(mil)
170Ω(com'l)
236Ω(mil)
(c)
VOH 0.5V VX
0.5V
VOL VX
0.5V
VXVOH
0.5V
VXVOL
CY7C372i
Document #: 38-03033 Rev. *A Page 6 of 13
Switching Characteristics Over the Operating Range [14]
Parameter Description 7C372i-125 7C372i-100 7C372i-83
7C372iL-83 7C372i-66
7C372iL-66 UnitMin. Max. Min. Max. Min. Max. Min. Max.
Combinatorial Mode Parameters
tPD Input to Combinatorial Output[1] 10 12 15 20 ns
tPDL Input to Output Through Transparent Input or
Output Latch[1] 13 15 18 22 ns
tPDLL Input to Output Through T ransparent Input and
Output Latches[1] 15 16 19 24 ns
tEA Input to Output Enable[1] 14 16 19 24 ns
tER Input to Output Disable 14 16 19 24 ns
Input Registered/Latched Mode Parameters
tWL Clock or Latch Enable Input LOW Time[9] 3345ns
tWH Clock or Latch Enable Input HIGH Time[9] 3345ns
tIS Input Register or Latch Set-Up T ime 2 2 3 4 ns
tIH Input Register or Latch Hold Time 2 2 3 4 ns
tICO Input Register Clock or Latch Enable to
Combinatorial Output[1] 14 16 19 24 ns
tICOL Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1] 16 18 21 26 ns
Output Registered/Latched Mod e Parameters
tCO Clock or Latch Enable to Output[1] 6.5 6.5 8 10 ns
tSSet-Up T ime from Input to Clock or Latch Enable 5.5 6 8 10 ns
tHRegister or Latch Data Hold Time 0 0 0 0 ns
tCO2 Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1] 14 16 19 24 ns
tSCS Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array) 8101215ns
tSL Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable 10 12 15 20 ns
tHL Hold Time for Input Through Transparent Latch
from Output Regi ster Clock or Latch Enable 0000ns
fMAX1 Maximum Frequency with Internal Feedback in
Output Registered Mode (Least of 1/tSCS,
1/(tS + tH), or 1/tCO)[9]
125 100 83 66 MHz
fMAX2 Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL +
tWH), 1/(tS + tH), or 1/tCO)[9]
153.8 153.8 125 100 MHz
fMAX3 Maximum Frequency with External Feedback
(Lesser of 1/(tCO + tS) and 1/(tWL + t WH))[9] 83.3 80 62.5 50 MHz
tOH-tIH
37x Output Data Stable from Output clock Minu s
Input Register Hold Time for 7C37x[9, 15] 0000ns
Pipelined Mode Parameters
tICS Input Register Clock to Output Register Clock 8 10 12 15 ns
fMAX4 Maximum Frequency in Pipelined Mode (Least
of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or
1/tSCS)[9]
125 100 83.3 66.6 MHz
Notes:
14.All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15.This specification is intended to guara ntee interface comp atibility of the other members of th e CY7C370i fami ly with the CY7C372i. This specification is met for
the devices operating at the same ambient temperature and at the same power su pply voltage.
CY7C372i
Document #: 38-03033 Rev. *A Page 7 of 13
Reset/Preset Parameters
tRW Asynchronous Reset Width[9] 10 12 15 20 ns
tRR Asynchronous Reset Recovery Time[9] 12 14 17 22 ns
tRO Asynchronous Reset to Output[1] 16 18 21 26 ns
tPW Asynchronous Preset Width[9] 10 12 15 20 ns
tPR Asynchronous Preset Recovery Time[9] 12 14 17 22 ns
tPO Asynchronous Preset to Output[1] 16 18 21 26 ns
Tap Controller Parameter
fTAP Tap Controller Frequency 500 500 500 500 kHz
3.3V I/O Mode Parameters
t3.3IO 3.3V I/O Mode Timing Adder 1 1 1 1 ns
Switching Waveforms
Switching Characteristics Over the Operating Range (continued)[14]
Parameter Description 7C372i-125 7C372i-100 7C372i-83
7C372iL-83 7C372i-66
7C372iL-66 UnitMin. Max. Min. Max. Min. Max. Min. Max.
tPD
INPUT
COMBINATORIAL
OUTPUT
Combinatorial Output
Registered Output
tS
INPUT
CLOCK
tCO
REGISTERED
OUTPUT
tH
CLOCK
tWL
tWH
CY7C372i
Document #: 38-03033 Rev. *A Page 8 of 13
Switching Waveforms (continued)
Latched Output
tS
INPUT
LATCH ENABLE
tCO
LATCHED
OUTPUT
tH
tPDL
Registered Input
tIS
REGISTERED
INPUT
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tIH
CLOCK
tWL
tWH
Clock to Clock
REGISTERED
INPUT
INPUT REGISTER
CLOCK tICS
OUTPUT
REGISTER CLOCK
tSCS
CY7C372i
Document #: 38-03033 Rev. *A Page 9 of 13
Switching Waveforms (continued)
Latched Input and Output
tICS
LATCHED INPUT
OUTPUT LATCH
ENABLE
LATCHED
OUTPUT
tPDLL
LATCH ENABLE
tWL
tWH
tICOL
INPUT LATCH
ENABLE
tSL tHL
Asynchronous Reset
INPUT
tRO
REGISTERED
OUTPUT
CLOCK
tRR
tRW
Asynchronous Preset
INPUT
tPO
REGISTERED
OUTPUT
CLOCK
tPR
tPW
CY7C372i
Document #: 38-03033 Rev. *A Page 10 of 13
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
125 CY7C372i-125JC J67 44-Le ad Plastic Leaded Chip Carrier Commercial
100 CY7C372i-100JC J67 44-Le ad Plastic Leaded Chip Carrier Commercial
CY7C372i-100JI J67 44-Le ad Plastic Leaded Chip Carrier Industrial
83 CY7C372i-83JC J67 44-Le ad Plastic Leaded Chip Carrier Co mmercial
CY7C372i-83JI J67 44-Lead Plastic Leaded Chip Carrier Industrial
CY7C372i-83YMB Y67 44-Lead Ceramic Leaded Chip Carrier Military
83 CY7C372iL-83JC J67 44-Lead Plastic Leaded Chip Carrier Commercial
66 CY7C372i-66JC J67 44-Lead Plastic Leaded Chip Carrier Commercial
CY7C372i-66JI J67 44-Le ad Plastic Leaded Chip Carrier Ind ustrial
CY7C372i-66YMB Y67 44-Lead Ceramic Leaded Chip Carrier Military
66 CY7C372iL-66JC J67 44-Lead Plastic Leaded Chip Carrier Commercial
Switching Waveforms (continued)
INPUT
tER
OUTPUTS
tEA
Output Enable/Disable
CY7C372i
Document #: 38-03033 Rev. *A Page 11 of 13
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tPD 9, 10, 11
tCO 9, 10, 11
tICO 9, 10, 11
tS9, 10, 11
tH9, 10, 11
tIS 9, 10, 11
tIH 9, 10, 11
tICS 9, 10, 11
Package Diagrams
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
CY7C372i
Document #: 38-03033 Rev. *A Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circ uitry other than ci rcuitry embodied in a Cypress S emiconductor produc t. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor product s in life-support syste ms applicat ion implies th at th e manu fac turer assu mes all risk of such use and in doing so ind emnifie s Cypress Semicondu ctor ag ainst all charges.
ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise, are trademarks of Cypress Semiconductor
Corporation.
Package Diagrams (continued)
44-Pin Ceramic Leaded Chip Carrier Y67
51-80014-**
CY7C372i
Document #: 38-03033 Rev. *A Page 13 of 13
Document History Page
Document Title: CY7C372i UltraLogic™ 64-Macrocell Flash CPLD
Document Number: 38-03033
REV. ECN NO. Issue Date Orig. of
Change Decsription of Chang e
** 106378 06/18/01 SZV Change from Spec# 38-00498 to 38-03033
*A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs”
