MILITARY AND COMMERCIAL TEMPERATURE RANGES OCTOBER 1995
1995 Integrated Device Technology, Inc. 9.4 DSC-4646/3
Integrated Device Technology, Inc.
1
FAST CMOS
BUFFER/CLOCK DRIVER
FEATURES:
• 0.5 MICRON CMOS technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS power levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: –32mA IOH, 48mA IOL
• Two independent output banks with 3-state control
– One 1:5 Inverting bank
– One 1:5 Non-Inverting bank
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Available in DIP, SOIC, SSOP, QSOP, CERPACK and
IDT54/74FCT810BT/CT
LCC packages
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
3103 drw 02
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
DIP/SOIC/SSOP/QSOP/CERPACK
TOP VIEW
P20-1
D20-1
SO20-2
SO20-7
SO20-8
&
E20-1
OA
1
OA
3
GND
OA
4
OA
5
OA
2
OE
A
IN
A
V
CC
GND
OB
1
OB
2
OB
3
GND
OB
4
GND
IN
B
OB
5
OE
B
V
CC
OE
A
5
IN
A
IN
B
OE
B
OA
1
-OA
5
OB
1
-OB
5
5
3103 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDEX
LCC
TOP VIEW
3 2 20 19
1
4
5
6
7
8
18
17
16
15
14
910111213
L20-2
OA
3
GND
OA
4
OA
5
GND
OB
2
OB
3
GND
OB
4
OB
5
OEA
INA
INB
OEB
GND
OA2
OA1
VCC
VCC
OB1
3103 drw 03
PIN CONFIGURATIONS
DESCRIPTION:
The IDT54/74FCT810BT/CT is a dual bank inverting/ non-
inverting clock driver built using advanced dual metal CMOS
technology. It consists of two banks of drivers, one inverting
and one non-inverting. Each bank drives five output buffers
from a standard TTL-compatible input. The IDT54/
74FCT810BT/CT have low output skew, pulse skew and
package skew. Inputs are designed with hysteresis circuitry
for improved noise immunity. The outputs are designed with
TTL output levels and controlled edge rates to reduce signal
noise. The part has multiple grounds, minimizing the effects of
ground inductance.
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4 2
PIN DESCRIPTION
3103 tbl 01
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions Typ. Max. Unit
CIN Input
Capacitance VIN = 0V 4.5 6.0 pF
COUT Output
Capacitance VOUT = 0V 5.5 8.0 pF
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial Military Unit
VTERM(2) Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0 V
VTERM(3) Terminal Voltage
with Respect to
GND
–0.5 to VCC
+0.5 –0.5 to VCC
+0.5 V
TAOperating
Temperature 0 to +70 –55 to +125 °C
TBIAS Temperature
Under Bias –55 to +125 –65 to +135 °C
TSTG Storage
Temperature –55 to +125 –65 to +150 °C
IOUT DC Output
Current –60 to +120 –60 to +120 mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability. No terminal voltage may exceed
VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals.
3. Output and I/O terminals.
3103 lnk 03
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is ± 5µA at TA = –55°C.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 — — V
VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V
II H Input HIGH Current(5) VCC = Max. VI = 2.7V — — ±1µA
II L Input LOW Current(5) VCC = Max. VI = 0.5V — — ±1µA
IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA
IOZL (3-State Output pins)(5) VO = 0.5V — — ±1µA
II Input HIGH Current(5) VCC = Max., VI = VCC (Max.) — — ±1µA
VIK Clamp Diode Voltage VCC = Min., IIN= –18mA — –0.7 –1.2 V
IOS Short Circuit Current VCC = Max.(3), VO = GND –60 –120 –225 mA
VOH Output HIGH Voltage VCC = Min.
VIN = VIH or VIL IOH = –12mA MIL.
IOH = –15mA COM'L. 2.4 3.3 — V
IOH = –24mA MIL.
IOH = –32mA COM'L.(4) 2.0 3.0 —
VOL Output LOW Voltage VCC = Min.
VIN = VIH or VIL IOL = 32mA MIL.
IOL = 48mA COM'L. — 0.3 0.55 V
IOFF Input/Output Power Off Leakage(5) VCC = 0V, VIN or VO ≤ 4.5V — — ±1µA
VHInput Hysteresis for all inputs — — 150 — mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA
3103 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested. 3103 lnk 02
Pin Names Description
OE
A,
OE
B3-State Output Enable Inputs (Active LOW)
INA, INBClock Inputs
OAn,
OB
nClock Outputs
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4 3
POWER SUPPLY CHARACTERISTICS
3103 tbl 05
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fONO)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fO= Output Frequency
NO= Number of Outputs at fO
All currents are in milliamps and all frequencies are in megahertz.
Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
∆ICC Quiescent Power Supply Current
TTL Inputs HIGH VCC = Max.
VIN = 3.4V(3) — 0.5 2.0 mA
ICCD Dynamic Power Supply Current(4) VCC = Max.
Outputs Open
OE
A =
OE
B = GND
50% Duty Cycle
VIN = VCC
VIN = GND — 60 100 µA/
MHz/bit
ICTotal Power Supply Current(6) VCC = Max.
Outputs Open
fo= 25MHz
VIN = VCC
VIN = GND — 7.5 13 mA
50% Duty Cycle
OE
A = GND,
OE
B =VCC VIN = 3.4V
VIN = GND — 7.8 14.0
VCC = Max.
Outputs Open
fo = 50MHz
VIN = VCC
VIN = GND — 30.0 50.5(5)
50% Duty Cycle
OE
A =
OE
B = GND VIN = 3.4V
VIN = GND — 30.5 52.5(5)
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4 4
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay
limits do not imply skew.
3103 tbl 06
IDT54/74FCT810BT IDT54/74FCT810CT
Com'l. Mil. Com'l. Mil.
Symbol Parameter Condition(1) Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL Propagation Delay
INA to OAn, INB to
OB
nCL = 50pF
RL = 500Ω1.5 4.5 1.5 4.9 1.5 4.3 1.5 4.6 ns
tROutput Rise Time — 1.5 — 2.0 — 1.5 — 2.0 ns
tFOutput Fall Time — 1.5 — 1.5 — 1.5 — 1.5 ns
tSK1(o) Output skew (same bank): skew between
outputs of same bank and same package
(same transition)
— 0.5 — 0.9 — 0.3 — 0.7 ns
tSK2(o) Output skew (all banks): skew between
outputs of all banks of same package
(inputs tied together)
— 0.7 — 1.1 — 0.6 — 1.0 ns
tSK(p) Pulse skew: skew between opposite
transitions of same output |(tPHL-tPLH)| — 0.7 — 1.2 — 0.7 — 1.1 ns
tSK(t) Package skew: skew between outputs of
different packages at same power supply
voltage, temperature, package type and
speed grade
— 1.2 — 1.5 — 1.0 — 1.2 ns
tPZL
tPZH Output Enable Time
OE
A to OAn,
OE
B to
OB
n1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
tPLZ
tPHZ Output Disable Time
OE
A to OAn,
OE
B to
OB
n1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4 5
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
Package 1 and Package 2 are same device type and speed grade 3103 drw 10
3103 drw 09
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
SWITCH
CLOSED
SWITCH
OPEN
V
OL
V
OH
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE DISABLE
t
PD1a
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
t
SK2(o)
t
PD2a
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT t
PD1b
t
PD2b
t
SK2(o)
t
SK(t)
=
|t
PD2a -
t
PD1a
|
or
|t
PD2b-
t
PD1b
|
PACKAGE SKEW - tSK(t) ENABLE AND DISABLE TIMES
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
RT =Termination resistance: should be equal to ZOUT of the Pulse
Generator.
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME
SWITCH POSITION
Test Switch
Disable LOW
Enable LOW Closed
Disable HIGH
Enable HIGH Open
3103 lnk 07
Pulse
Generator
RT
D.U.T.
VCC
VIN
CL
VOUT
50pF 500Ω
500Ω
7.0V
3103 drw 04
3103 drw 07 3103 drw 08
t
PLH
t
PHL
3V
0V
V
OH
1.5V
1.5V
V
OL
t
SK(p)
=
|t
PHL -
t
PLH
|
INPUT
OUTPUT
t
PLH1
OUTPUT 1
OUTPUT 2
t
SK2(o)
t
PHL2
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT t
PHL1
t
PLH2
t
SK2(o)
t
SK2(o)
=
|t
PHL2 -
t
PLH1
|
or
|t
PLH2 -
t
PHL1
|
3103 drw 06
3103 drw 05
TEST WAVEFORMS
PACKAGE DELAY
3V
0V
V
OH
t
PLH
t
PHL
V
OL
1.5V
1.5V
t
R
t
F
2.0V
0.8V
t
PLH1
OUTPUT 1
OUTPUT 2
t
SK1(o)
t
PLH2
3V
0V
V
OH
1.5V
1.5V
V
OL
V
OH
1.5V
V
OL
INPUT t
PHL1
t
PHL2
t
SK1(o)
t
SK1(o)
=
|t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PLH1
|
INPUT
O
UTPUT
OUTPUT SKEW (ALL BANKS) - tSK2(o) PULSE SKEW - tSK(p)
OUTPUT SKEW (SAME BANK) - tSK1(o)
IDT54/74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.4 6
ORDERING INFORMATION
XXX
Device Type XX
Package X
Process/
Blank
B
P
D
E
L
SO
PY
Q
810BT
810CT
Commercial
Military (-55°C to +125°C) Compliant to
MIL-STD-883, Class B
Plastic DIP
CERDIP
CERPACK
Leadless Chip Carrier
Small Outline IC
Shrink Small Outline IC
Quarter-size Small Outline IC
Temperature
Range
IDTXXFCT
Temp. Range
54
74 -55°C to +125°C
0°C to + 70°C
Inverting, Non-Inverting Buffer/Clock driver
3103 drw 13
