IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE FAST CMOS BUFFER/CLOCK DRIVER IDT74FCT810BT/CT FEATURES: DESCRIPTION: FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION The 74FCT810T is a dual bank inverting/ non-inverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The FCT810T has low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance. * * * * * * * * 0.5 MICRON CMOS Technology Guaranteed low skew < 600ps (max.) Very low duty cycle distortion < 700ps (max.) Low CMOS levels TTL compatible inputs and outputs TTL level output voltage swings High drive: -32mA IOH, +48mA IOL Two independent output banks with 3-state control: - One 1:5 inverting bank - One 1:5 non-inverting bank * Available in QSOP, SSOP, and SOIC packages OEA 5 IN A OA 1 -O A 5 VCC 1 20 VCC OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GND 5 16 GND OA4 6 15 OB4 OA5 7 14 OB5 GND 8 13 GND OEA 9 12 OEB INA 10 11 INB OE B 5 IN B O B 1 -O B 5 QSOP/ SOIC/ SSOP TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE APRIL 2001 1 c 2001 Integrated Device Technology, Inc. DSC-4646/1 IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE CAPACITANCE (TA = +25OC, f = 1.0MHz) ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Parameter(1) Unit Symbol Conditions Typ. Max. Unit Input Capacitance VIN = 0V 4.5 6 pF Output Capacitance VOUT = 0V 5.5 8 pF VTERM Terminal Voltage with Respect to GND -0.5 to +7 V CIN TSTG Storage Temperature -65 to +150 C C OUT IOUT DC Output Current -60 to +120 mA NOTE: 1. This parameter is measured at characterization but not tested. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. PIN DESCRIPTION Pin Names OEA, OEB Description 3-State Output-Enable Inputs (Active LOW) INA, INB Clock Inputs OAx, OBx Clock Outputs DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C, VCC = 5V 5% Parameter Test Conditions(1) VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level IIH Input HIGH Current (Input pins) VCC = Max. VI = 2.7V Symbol Min. Typ.(2) Max. Unit 2 -- -- V -- -- 0.8 V -- -- 1 A IIL Input LOW Current (Input pins) VCC = Max. VI = 0.5V -- -- 1 A IOZH High Impedance Output Current VCC = Max. VO = 2.7V -- -- 1 A IOZL (3-State Output pins) VO = 0.5V -- -- 1 II Input HIGH Current VCC = Max., VI = VCC (Max.) -- -- 1 A VIK Clamp Diode Voltage VCC = Min., IIN = -18mA -- -0.7 -1.2 V -60 -120 -225 mA 2.4 3.3 -- V GND(3) IOS Short Circuit Current VCC = Max., VO = VOH Output HIGH Voltage VCC = Min. IOH = -15mA VIN = VIH or VIL IOH = -32mA(4) 2 3 -- VCC = Min. IOL = 48mA -- 0.3 0.55 VOL Output LOW Voltage V VIN = VIH or VIL Input/Output Power Off Leakage VCC = 0V, VIN or VO 4.5V -- -- 1 A VH Input Hysteresis for all inputs -- -- 150 -- mV ICCL ICCH ICCZ Quiescent Power Supply Current VCC = Max., VIN = GND or VCC -- 5 500 A I OFF NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition should not exceed one second. 2 IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Symbol ICC ICCD Test Conditions(1) Parameter Quiescent Power Supply Current VCC = Max. TTL Inputs HIGH VIN = 3.4V(3) Dynamic Power Supply Current(4) VCC = Max. VIN = VCC Outputs Open VIN = GND Min. Typ.(2) Max. Unit -- 0.5 2 mA -- 60 100 A/MHz -- 7.5 13 mA -- 7.8 14 -- 30 50.5(5) -- 30.5 52.5(5) OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. VIN = VCC Outputs Open VIN = GND fO = 25MHz 50% Duty Cycle VIN = 3.4V OEA = GND, OEB = VCC VIN = GND VCC = Max. VIN = VCC Outputs Open VIN = GND fO = 50MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = GND VIN = GND NOTES: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at VCC = 5V, +25C ambient. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 3 IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4) FCT810BT Symbol tPLH tPHL tR Parameter Propagation Delay INA to OAx, INA to OBx Output Rise Time Conditions(1) CL = 50pF FCT810CT Min.(2) 1.5 Max. 4.5 Min.(2) 1.5 Max. 4.3 Unit ns -- 1.5 -- 1.5 ns RL = 500 tF tSK1(O) Output Fall Time Output skew (same bank): skew between outputs of -- -- 1.5 0.5 -- -- 1.5 0.3 ns ns tSK2(O) same bank and same package (same transition) Output skew (all banks): skew between outputs of -- 0.7 -- 0.6 ns tSK(P) all banks of same package (inputs tied together) Pulse skew: skew between opposite transitions -- 0.7 -- 0.7 ns -- 1.2 -- 1 ns of same output (|tPHL -- tPLH|) tSK(T) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade tPZL tPZH Output Enable Time OEA to OAx, OEB to OBx 1.5 6 1.5 5 ns tPLZ tPHZ Output Disable Time OEA to OAx, OEB to OBx 1.5 6 1.5 5 ns NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 4 IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500 V OUT V IN Pulse Generator D.U.T. 50pF R T C 500 Test Switch Disable LOW Enable LOW Closed Disable HIGH Enable HIGH GND DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. L Test Circuit for All Outputs 3V 1.5V 0V 3V INPUT t PLH1 1.5V INPUT tPHL1 V OH 0V tPLH tPH L 1.5V VOL OUTPUT 1 0.8V OUTPUT 1.5V VOL OUTPUT 2 V OL t PLH2 t PLH1 t PH L2 tSK(o) = |t PLH2 - tPLH1 | or |tPHL2 - t PHL1 | Output Skew (Same Bank) - tSK1(O) Package Delay INPUT V OH 1.5V tF tR tSK(o) t SK(o) V OH 2.0V 3V 1.5V 0V tPH L1 3V 1.5V VOH INPUT 1.5V VOL OUTPUT 1 0V t PH L tPLH V OH t SK(o) tSK(o) 1.5V VOH OUTPUT 2 VOL OUTPUT 1.5V VOL tPLH2 t SK(o) = |t PLH2 - t SK(p) = |tPHL - tPLH | t PH L2 tPLH1 | or |t PHL2 - tPHL1 | Pulse Skew - tSK(P) Output Skew (All Banks) - tSK2(O) ENABLE 3V INPUT t PD 1a tPD 1b CONTROL INPUT VOH 1.5V tSK2(o) PACKAGE 2 OUTPUT tPD2a tSK2(o) tPD2b t SK(t) = |t PD2a - tPD1a | or 1.5V 0V t OUTPUT NORMA LLY LOW V OL PACKAGE 1 OUTPUT DISABLE 3V 1.5V 0V VOH 1.5V VOL SW ITCH CLOSE D t OUTPUT NORMA LLY HIGH |tPD 2b - t PD1b | Package Skew - tSK(T) t PZL 3.5V 1.5V 3.5V t PZH SW ITCH OPEN PLZ 0.3V V OL 0.3V VOH PHZ 1.5V 0V 0V Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns NOTE: 1. Package 1 and Package 2 are same device type and speed grade. 5 IDT74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT FCT XX XXX Temp. Range Device Type XX Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 SO PY Q Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC 810BT 810CT Inverting, Non-Inverting Buffer/Clock Driver 74 0C to + 70C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: logichelp@idt.com (408) 654-6459