IDT74FCT810CTQG8 - Integrated Device Technology

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

APRIL 2001

2001 Integrated Device Technology, Inc. DSC-4646/1c

IDT74FCT810BT/CT

COMMERCIAL TEMPERATURE RANGE

FAST CMOS

BUFFER/CLOCK DRIVER

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

• 0.5 MICRON CMOS Technology

• Guaranteed low skew < 600ps (max.)

• Very low duty cycle distortion < 700ps (max.)

• Low CMOS levels

• TTL compatible inputs and outputs

• TTL level output voltage swings

• High drive: -32mA IOH, +48mA IOL

• Two independent output banks with 3-state control:

– One 1:5 inverting bank

– One 1:5 non-inverting bank

• Available in QSOP, SSOP, and SOIC packages

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

PIN CONFIGURATION

QSOP/ SOIC/ SSOP

TOP VIEW

DESCRIPTION:

The 74FCT810T is a dual bank inverting/ non-inverting clock driver

built using advanced dual metal CMOS technology. It consists of two banks

of drivers, one inverting and one non-inverting. Each bank drives five output

buffers from a standard TTL-compatible input. The FCT810T has low output

skew, pulse skew and package skew. Inputs are designed with hysteresis

circuitry for improved noise immunity. The outputs are designed with TTL

output levels and controlled edge rates to reduce signal noise. The part has

multiple grounds, minimizing the effects of ground inductance.

OEA

INAOA1 -OA5

OEB

INBOB1 -OB5

10 11

OA1

OA3

GND

OA4

OA5

OA2

OEA

INA

VCC

GND

OB1

OB2

OB3

GND

OB4

GND

INB

OB5

OEB

VCC

COMMERCIAL TEMPERATURE RANGE

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

VTERM Terminal Voltage with Respect to GND –0.5 to +7 V

TSTG Storage Temperature –65 to +150 °C

IOUT DC Output Current –60 to +120 mA

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability. PIN DESCRIPTION

Pin Names Description

OEA, OEB3-State Output-Enable Inputs (Active LOW)

INA, INBClock Inputs

OAx, OBx Clock Outputs

CAPACITANCE (TA = +25OC, f = 1.0MHz)

Symbol Parameter(1) Conditions Typ. Max. Unit

CIN Input Capacitance VIN = 0V 4.5 6 pF

COUT Output Capacitance VOUT = 0V 5.5 8 pF

NOTE:

1. This parameter is measured at characterization but not tested.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Commercial: TA = 0°C to +70°C, VCC = 5V ± 5%

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

VIH Input HIGH Level (Input pins) Guaranteed Logic HIGH Level 2 — — V

VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V

IIH Input HIGH Current (Input pins) VCC = Max. VI = 2.7V — — ±1µA

IIL Input LOW Current (Input pins) VCC = Max. VI = 0.5V — — ±1µA

IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1µA

IOZL (3-State Output pins) VO = 0.5V — — ±1

IIInput HIGH Current VCC = Max., VI = VCC (Max.) — — ±1µA

VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V

IOS Short Circuit Current VCC = Max., VO = GND(3) –60 –120 –225 mA

VOH Output HIGH Voltage VCC = Min. IOH = –15mA 2 . 4 3 . 3 — V

VIN = VIH or VIL IOH = –32mA(4) 23—

VOL Output LOW Voltage VCC = Min. IOL = 48mA — 0.3 0.55 V

VIN = VIH or VIL

IOFF Input/Output Power Off Leakage VCC = 0V, VIN or VO ≤ 4.5V — — ±1µA

VHInput Hysteresis for all inputs — — 150 — mV

ICCL Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA

ICCH

ICCZ

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at Vcc = 5V, +25°C ambient.

3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.

4. Duration of the condition should not exceed one second.

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

NOTES:

1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 5V, +25°C ambient.

3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

5. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fONO)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fO = Output Frequency

NO = Number of Outputs at fO

All currents are in milliamps and all frequencies are in megahertz.

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Min. Typ.(2) Max. Unit

∆ICC Quiescent Power Supply Current VCC = Max. — 0.5 2 mA

TTL Inputs HIGH VIN = 3.4V(3)

ICCD Dynamic Power Supply Current(4) VCC = Max. VIN = VCC — 60 100 µA/MHz

Outputs Open VIN = GND

OEA = OEB = GND

50% Duty Cycle

ICTotal Power Supply Current(6) VCC = Max. VIN = VCC — 7.5 13 mA

Outputs Open VIN = GND

fO = 25MHz

50% Duty Cycle VIN = 3.4V — 7.8 14

OEA = GND, OEB = VCC VIN = GND

VCC = Max. VIN = VCC — 30 50.5(5)

Outputs Open VIN = GND

fO = 50MHz

50% Duty Cycle VIN = 3.4V — 30.5 52.5(5)

OEA = OEB = GND VIN = GND

COMMERCIAL TEMPERATURE RANGE

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER

NOTES:

1. See test circuits and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.

4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4)

FCT810BT FCT810CT

Symbol Parameter Conditions(1) Min.(2) Max.Min.(2) Max.Unit

tPLH Propagation Delay CL = 50pF 1.5 4.5 1.5 4.3 ns

tPHL INA to OAx, INA to OBxRL = 500Ω

tROutput Rise Time — 1.5 — 1.5 ns

tFOutput Fall Time — 1.5 — 1.5 ns

tSK1(O) Output skew (same bank): skew between outputs of — 0.5 — 0.3 ns

same bank and same package (same transition)

tSK2(O) Output skew (all banks): skew between outputs of — 0.7 — 0.6 ns

all banks of same package (inputs tied together)

tSK(P) Pulse skew: skew between opposite transitions — 0.7 — 0.7 ns

of same output (|tPHL -– tPLH|)

tSK(T) Package skew: skew between outputs of different — 1.2 — 1 ns

packages at same power supply voltage,

temperature, package type and speed grade

tPZL Output Enable Time 1.5 6 1.5 5 ns

tPZH OEA to OAx, OEB to OBx

tPLZ Output Disable Time 1.5 6 1.5 5 ns

tPHZ OEA to OAx, OEB to OBx

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

tPLH1

OUTPUT 1

OUTPUT 2

tSK(o)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

INPUT tPHL1

tPHL2

tSK(o)

tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

1.5V

3.5V

SWITCH

CLOSED

SWITCH

OPEN

VOL

VOH

0.3V

tPLZ

tPZL

tPZH tPHZ

3.5V

1.5V

ENABLE DISABLE

VOH

tPLH tPHL

VOL

1.5V

tRtF

2.0V

0.8V

INPUT

OUTPUT

tPLH tPHL

VOH

1.5V

VOL

tSK(p) = |tPHL - tPLH|

INPUT

OUTPUT

Pulse

Generator

D.U.T.

VCC

VIN

VOUT

50pF 500Ω

500Ω

7.0V

tPLH1

OUTPUT 1

OUTPUT 2

tSK(o)

tPLH2

VOH

1.5V

VOL

VOH

1.5V

VOL

INPUT tPHL1

tPHL2

tSK(o)

tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|

IN PUT tPD1a

PACKAGE 1 OUTPUT

PACKAGE 2 OUTPUT

tSK2(o)

tPD2a

VOH

1.5V

VOL

VOH

1.5V

VOL

tPD1b

tPD2b

tSK2(o)

tSK(t) = |tPD2a - tPD1a| or |tPD2b - tPD1b|

TEST CIRCUITS AND WAVEFORMS

Package Delay

Pulse Skew - tSK(P)

Enable and Disable Times

Output Skew (Same Bank) - tSK1(O)

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns

NOTE:

1. Package 1 and Package 2 are same device type and speed grade.

Test Circuit for All Outputs

Package Skew - tSK(T)

Output Skew (All Banks) - tSK2(O)

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Test Switch

Disable LOW Closed

Enable LOW

Disable HIGH G ND

Enable HIGH

SWITCH POSITION

COMMERCIAL TEMPERATURE RANGE

IDT74FCT810BT/CT

FAST CMOS BUFFER/CLOCK DRIVER

ORDERING INFORMATION

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459

www.idt.com

XXX

Device Type XX

Package

810BT

810CT

Small Outline IC

Shrink Small Outline IC

Quarter-size Small Outline IC

Temp. Range

74 0°C to + 70°C

Inverting, Non-Inverting B uff er/ Clock Dr iver

IDT FCT