TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 D D D D D D Complete Discrete Multitone (DMT)-Based Asymmetric Digital Subscriber Line (ADSL) Coder/Decoder (Codec) Solution Complies With ANSI Std T1.413, Issue 2 and ITU Std G.992.1 Supports up to 8-Mbit/s Downstream and 800-kbit/s Upstream Duplex Integrated 14-Bit Converters for Transmitter/Echo-Canceller/Receiver (TX/EC/RX) Integrated 12-Bit Digital-to-Analog Converter (DAC) for Voltage-Controlled Oscillator (VCXO) Control Integrated TX/EC/RX Channel Filters D D D D D D D D D Integrated TX/EC/RX Attenuation/Gain Integrated Voltage Reference Selectable 2.2-Mega Samples Per Second (MSPS) or 4.4-MSPS Parallel Data Transfer Rate Serial-Configuration Port Eight General-Purpose (GP) Output Terminals Single 3.3-V 10% Supply Operation Hardware/Software Power Down -40C to 85C Operation Packaged in 100-Pin Plastic Quad Flatpack description The TLV320AD13A is a high-speed coder/decoder (codec) for remote terminal (RT)-side modems that supports ADSL over integrated services digital network (ISDN) solution. The TLV320AD13A is a low-power device composed of five major functional groups for transmit (TX), receive (RX), clock, reference, and host interface. It is designed to work with the Texas Instruments (TI) TNETD2022D central office (CO)-side codec for ISDN. The TX channel consists of a 138-kHz to 276-kHz digital bandpass filter, a 14-bit high-speed digital-to-analog converter (DAC), a 276-kHz analog low-pass filter (LPF), a TX attenuator, and an echo-cancellation (EC) channel. The RX channel consists of a 1.104-MHz digital LPF, a 1.104-MHz analog LPF, a frequency equalizer, and a programmable-gain amplifier (PGA). The clock circuit divides a 35.328-MHz frequency from an external voltage-controlled oscillator (VCXO) down to the necessary frequencies used throughout the device. The frequency of the external VCXO is controlled by a 12-bit onboard voltage-output DAC. An onboard reference circuit generates a 1.5-V reference for the converters. The device has a parallel port for data transfer and a serial port for control. The parallel port is 16 bits wide and is reserved for moving data between the codec and a host transceiver such as the TI C6x DSP. Configuration is done via a serial port. The device can be powered down via a dedicated pin, or through software control, to reduce heat dissipation. Additionally, there is a general-purpose (GP) port consisting of eight output terminals for control of external circuitry. The TLV320AD13A codec is characterized for operation in the temperature range of -40C to 85C and is available in a 100-pin PQFP (PZ) package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI is a trademark of Texas Instruments. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 CONFIG2 NC NC ENISDN RXM RXP AVSSFILRX AVDDFILRX VSS NC VMIDREF REFM REFP AVSSREF AVDDREF NC AVSSFILTX AVDDFILTX TXM TXP NC ECM ECP NC NC PZ PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC - No internal connection 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 47 48 49 50 WETX WEEC OE 36 37 38 39 40 41 42 43 44 45 46 32 33 34 35 30 31 DVDDBF DVSSBF D9 D10 D11 D12 D13 D14 D15 SDO SDI SCLK/READY FS OSEN INT CLKOUT/INT CLKIN DVSSCLK DV DDCLK SYNC DVSSLG DVDDLG 28 29 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7 TEST2 NC VMIDADC AVDDADC AVSSADC NC DVDDRX DVSSRX D0 D1 D2 D3 D4 D5 D6 D7 D8 NC NC AVDDFILEC AVSSFILEC AVSS2TX AVDD2TX COMPBTX COMPATX AVSS1TX AVDD1TX AVSS2EC AVDD2EC COMPAEC COMPBEC AVSS1EC AVDD1EC VCXOCNTL TEST DVDDDAC DVSSDAC ADR1 ADR0 PWDN RESET CS TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ADR0 ADR1 54 55 I Serial-port chip ID address. ADR0 is the least significant bit. AVDDADC AVDDFILEC 12 I RX-channel analog power supply 73 I EC-channel filter analog power-supply return AVDDFILRX AVDDFILTX 93 I RX-channel filter analog power supply 83 I TX-channel filter analog power supply AVDDREF AVDD1EC 86 I Reference analog power supply 60 I EC-channel analog power-supply 1 AVDD2EC AVDD1TX 64 I EC-channel analog power-supply 2 66 I TX-channel analog power-supply 1 AVDD2TX AVSSADC 70 I TX-channel analog power-supply 2 13 I RX-channel analog power-supply return AVSSFILEC AVSSFILRX 72 I EC-channel filter analog power-supply return 94 I RX-channel filter analog power-supply return AVSSFILTX AVSSREF 84 I TX-channel filter analog power-supply return 87 I Reference analog power-supply return AVSS1EC AVSS2EC 61 I EC-channel analog power-supply return 1 65 I EC-channel analog power-supply return 2 AVSS1TX AVSS2TX 67 I TX-channel analog power-supply return 1 71 I TX-channel analog power-supply return 2 CLKIN 42 I 35.328-MHz VCXO clock input CLKOUT/INT 41 O If CONFIG2 is low, this terminal is 4.416-MHz clock output. If CONFIG2 is high, this terminal functions as INT. COMPAEC 63 O EC-channel decoupling cap input A (add 500-pF ceramic capacitor between this terminal and AVDD1EC) COMPATX 68 O TX-channel decoupling cap input A (add 500-pF ceramic capacitor between this terminal and AVDD1TX) COMPBEC 62 O EC-channel decoupling cap input B (add 1-F ceramic capacitor between this terminal and AVDD1EC) COMPBTX 69 O TX-channel decoupling cap input B (add 1-F ceramic capacitor between this terminal and AVDD1TX) CONFIG2 100 I I/O configuration. A high on this terminal redefines the function of terminals 37 and 41. The default state of this terminal is low. Refer to Figure 2 for details. CS 51 I Parallel-port chip select D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) 34 33 32 31 30 29 28 25 24 23 22 21 20 19 18 17 (LSB) I/O Parallel-port data. D0 is the least significant bit (LSB) (drive up to 50 pF). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION DVDDBF 26 I Digital I/O buffer power supply DVDDCLK 44 I Digital-clock power supply DVDDDAC 57 I Digital power supply for TX channel DVDDLG 47 I Digital-logic power supply DVDDRX 15 I RX-channel digital power supply DVSSBF 27 I Digital I/O buffer power-supply return DVSSCLK 43 I Digital clock power-supply return DVSSDAC 56 I Digital power-supply return for TX channel DVSSLG 46 I Digital logic power-supply return DVSSRX 16 I RX-channel digital power-supply return ECM 79 O EC output minus ECP 78 O EC output plus ENISDN 97 I ISDN configuration input. This terminal must be tied high for ISDN operation. The terminal setting should be done before the chip is reset. The default of the terminal is low. FS 38 I Frame synchronization input GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 8 7 6 5 4 3 2 1 O General-purpose output port INT 40 O Data-rate clock (INT is 4.4 MHz when OSEN = 1, 2.2 MHz when OSEN = 0) NC 10, 14, 74, 75, 76, 77, 80, 85, 91, 98, 99 OE 50 I Parallel-port output enable OSEN 39 I Oversampling enable. OSEN = 1 enables oversampling mode (INT = 4.4 MHz). PWDN 53 I Power down. When PWDN = 0, the device is in normal operating mode. When PWDN = 1, the device is in power-down mode. REFM 89 O Decoupling reference voltage minus (add 10-F tantalum and 0.1-F ceramic capacitors between this terminal and AVSSREF). The nominal dc voltage at this terminal is 0.5 V. REFP 88 O Decoupling reference voltage plus (add 10-F tantalum and 0.1-F ceramic capacitors between this terminal and AVSSREF). The nominal dc voltage at this terminal is 2.5 V. RESET 52 I Hardware system reset. An active low level resets the device. RXM 96 I RX input minus. RXM is self biased to AVDDFILRX/2. RXP 95 I RX input plus. RXP is self biased to AVDDFILRX/2. SCLK/READY 37 O If CONFIG2 is low, this terminal is serial clock output. If CONFIG2 is high, it indicates the period in which parallel data can be transferred. SDI 36 I Serial data input SDO 35 O Serial data output SYNC 45 I Synchronization pulse for clock synchronization (see Figure 3). A high pulse to this terminal synchronizes the clock operation. Tie SYNC to DVSSLG for auto-synchronization. TEST 58 I Test mode terminal. Tie this terminal low for normal operation. No connection. All NC terminals should be left open. TEST2 9 I Test mode terminal. Tie this terminal low for normal operation. TXM 82 O TX output minus 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION TXP 81 O TX output plus VCXOCNTL 59 O VCXO DAC control output VMIDADC 11 O Decoupling 1.5 V for analog-to-digital converter (ADC) (add 10-F tantalum and 0.1-F ceramic capacitors between this terminal and AVSSADC). VMIDREF 90 O Decoupling 1.5-V reference voltage (add 10-F tantalum and 0.1-F ceramic capacitors between this terminal and AVSSREF). VSS WEEC 92 I Substrate. Connect VSS to analog ground. 49 I Write enable for EC channel WETX 48 I Write enable for TX channel functional block diagram Codec Interface FS SDI SDO SCLK Digital LPF TX DAC 276 kHz TX LPF TXP PAA TXM Parallel Bus 138 kHz 276 kHz 14 Bit 4.416 MSPS 276 kHz Digital HPF Digital LPF TX DAC TX LPF 0 to -24 dB (-1 dB/step) EC PAA ECP PAA ECM SCR14[2] Control 1.104 MHz 14 Bit 4.416 MSPS Digital LPF RX ADC 0 to 11.5 dB (0.25 dB/step) PGA 25-dB Shape 1.104 MHz (5 dB/step) RX LPF RX EQ Serial Interface VCXO DAC OSEN Clock Generator VCXOCNTL CLKIN Internal Reference 0 to 6 dB (1 dB/step) RXP PGA RXM GP7-GP0 SYNC RESET PWDN ADR1 ADR0 276 kHz Digital HPF 0 to -24 dB (-1 dB/step) TX PAA SCR7[0] Oversampling CS D15-D0 WETX OE INT WEEC 138 kHz 14 Bit 4.416 MSPS GP7-GP0 CLKOUT 4.416 MHz VCXO 35.328 MHz POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 functional description TX channel/EC channel The TX channel is powered by a high-performance DAC. This is a 4.416-MHz, 14-bit DAC that provides 16x oversampling to reduce DAC noise so that it does not contribute to the receive noise. An LPF limits its output to 276 kHz. A programmable attenuator (PAA), with a range of 24 dB in 1-dB steps, drives the output into the external ADSL line driver. The TX high-pass filter (HPF) can be bypassed. A second transmitter is used to perform pre-EC. This analog EC helps reduce the dynamic-range requirements of the RT receiver. It has the same function as the first transmitter channel. It drives a separate external line driver to perform the cancellation. RX channel The RX channel has two PGAs and an equalizer to match the loop loss and flatten signal-to-noise ratio (SNR). This results in a reduction in the dynamic-range requirement for the high-resolution ADC. The RX channel also has a 1.104-MHz LPF with a 4.416-mega samples per second (MSPS) 14-bit ADC to provide a 2x oversampling (OSEN = 1). VCXO-control DAC A 12-bit serial DAC is used to control the external 35.328-MHz VCXO that provides the system clock to the codec. In a typical application, the update rate of the DAC is about 4 kHz, depending on the ADSL frame rate. The host transceiver initiates the update through the serial interface. The two 8-bit registers, SCR4 and SCR5 (each 2s complement), are used to generate the 12-bit code for the DAC. This requires the use of 16 bits to obtain a 12-bit number. The lower four bits of the most significant bit register (SCR5[3:0]) are added (2s complement) to the higher four bits of the least significant bit register (SCR4[7:4]). Refer to Figure 1 for code generation. The updated code is sent to the DAC two SCLKs after the SCR4 register is received. If SCR5 does not need to be updated, only one write cycle to SCR4 is needed to update the VCXO DAC. In this case, the lower eight bits of the 12-bit word are updated. SCR4 D7 D7 D7 D7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 D6 D5 D4 D3 D2 D1 D0 + SCR5 D11 D10 D9 D8 D7 12-Bit Code for VCXO DAC Figure 1. 12-Bit Code Generation for VCXO DAC clock generation The clock-generation block provides the necessary clock signals for the device, with minimum skew and jitter. This is closely dependent on the performance of the external VCXO. The external VCXO specifications are: D D D 6 3.3-V supply 35.328 MHz, 50 PPM Minimum duty cycle is 60/40 (50/50 is optimum). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 clock generation (continued) Table 1 describes the major clocks generated internally. Table 1. Clock Description CLOCK FREQUENCY (MHz) OSEN = 0 OSEN = 1 INT 2.208 4.416 CLKOUT 4.416 4.416 SCLK 4.416 4.416 interrupt (INT) INT to the host processor is 4.416 MHz when OSEN = 1 and 2.208 MHz when OSEN = 0. serial clock (SCLK) SCLK used in the serial codec interface has a fixed frequency of 4.416 MHz and is synchronous with the master clock (35.328 MHz). clock output (CLKOUT) CLKOUT is 4.416 MHz and is synchronous with the master clock (35.328 MHz). interface parallel interface The device has a 16-bit parallel interface for transmitter and receiver data. Strobes OE, WETX, WEEC, and CS from the host are edge-triggered signals. Incoming data is registered on the rising edge of WETX/WEEC as long as it meets the minimum setup and hold times. Output data from the codec is enabled with delay after the falling edge of the OE strobe, and disabled after the rising edge of the OE strobe. Two kinds of interrupt (INT and INT) to the host controller are generated onboard. The INT cycle time is hardware configurable for either 4.416 MHz (2x oversampling mode, OSEN = 1) or 2.208 MHz (1x oversampling mode, OSEN = 0). SYNC is used to synchronize the operation between the codec and the host transceiver. SCLK/READY is used to indicate the parallel data transfer period in configuration mode 2 (see Figure 2). The 16-bit data is left justified, i.e., D15 is the most significant bit (MSB) and D0 is the least significant bit (LSB). The TX and RX data contains 16 valid bits. All 16 bits are used in the digital filtering. keep-out zones (KOZs) The last CLKIN cycle before a transition of CLKOUT is defined as a KOZ. These zones are reserved for the sampling of analog signals. All digital I/O (except CLKIN) should be quiet during these KOZs. oversampling mode OSEN selects 2x oversampling mode (INT running at 4.416 MHz), or 1x oversampling mode (INT running at 2.208 MHz) for receive-channel ADC. serial interface The serial port is used for codec configuration and register reading. The word length is 16 bits. Two hardware configuration terminals, ADR[1:0] are used to configure the device ID. Up to four codecs can be identified for each host transceiver peripherals port. The master codec (ADR[1:0] = [0,0]) provides the SCLK to the host processor. The SCLK terminals on the other codecs are left unconnected. All the codecs in a multicodec system should be synchronized so that their SCLK signals are in phase - even though the signals themselves are not being used. This ensures that, even though the individual SCLK signals of each codec are not being used, the data is being latched into the codec properly. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 serial interface (continued) The SCLK is a continuously running 4.416-MHz fixed-frequency clock, synchronized to the codec internal events and CLKOUT (to the host) so that the KOZs can be monitored. A host transceiver can drive the frame synchronization (FS) (synchronized to the CLKOUT from the codec) into the codec to initiate a 16-bit serial I/O frame. If SCR5 needs to be updated, the host controller must first write the SCR5 register of the VCXO DAC data and then the SCR4 register of the VCXO DAC data. The VCXO DAC gets updated only after the SCR4 register is written. GP port The GP port provides eight outputs, each capable of delivering 0.5 mA, for control of external circuitry such as LEDs, gain control, and power down. voltage reference The built-in reference provides the needed reference voltage and current to individual analog blocks. It also is brought out to external terminals for noise decoupling. register programming See Figure 4 for timing and format details. 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System Control Registers (SCRs) REGISTER NAME ADDRESS S3, S2, S1, S0 MODE DEFAULT VALUE R 00000000 FUNCTION SCR0 0000 SCR1 0001 R/W 00000000 D[4:0] = TX channel PAA gain select. D[4:0] = 00000 for 0 dB, D[4:0] = 11000 for -24 dB. SCR2 0010 R/W 00000000 D[5:0] = RX PGA2. D[5:0] = 000000 for 0 dB, D[5:0] = 101110 for 11.5 dB. SCR3 0011 R/W 00000000 D[2:0] = RX EQ slope select. D[2:0] = 000 for 0 dB/MHz, D[2:0] = 001 for 5 dB/MHz, D[2:0] = 101 for 25 dB/MHz SCR4 0100 R/W 00000000 D[7:0] = VCXODAC (low 8 bits of 12-bit DAC code) SCR5 0101 R/W 00000000 D[7:0] = VCXODAC (high 8 bits of 12-bit DAC code) SCR6 0110 R/W 00000000 D[7:0] = GP[7:0] W D0: Software reset (self clearing) SCR7 0111 R/W 00000000 Miscellaneous control (set to 1 to enable) D0: Bypass TX ISDN HPF (138 kHz) D1: Software power-down RX channel D2: Software power-down TX channel D3: Analog loopback (TX channel) D4: Digital loopback (TX and EC channel) D5: Parallel interface (read back) test-mode enable D6: EC channel power down D7: EC analog loopback SCR8 1000 R/W 00000000 D[4:0] = EC channel PAA gain select. D[4:0] = 00000 for 0 dB. D[4:0] = 11000 for -24 dB. SCR9 1001 R/W 00000000 D[7:0] = RX offset low SCR10 1010 R/W 00000000 D[7:0] = RX offset high SCR11 1011 R/W 00000000 D[4:0] = TX digital gain select. The gain range is -1 dB to 1 dB in 0.1-dB steps. D[4:0] = 00000 for 0 dB D[4:0] = 00001 for 0.1 dB. D[4:0] = 01010 for 1 dB. D[4:0] = 10000 for -1 dB. D[4:0] = 11001 for -0.1 dB. SCR12 1100 R/W 00000000 D[2:0] = RX PGA1. D[2:0] = 000 for 0 dB. D[2:0] = 110 for 6 dB. SCR13 1101 R/W 00000000 D[4:0] = EC digital gain select. The gain range is -1 dB to 1 dB in 0.1-dB steps. D[4:0] = 00000 for 0 dB. D[4:0] = 00001 for 0.1 dB D[4:0] = 01010 for 1 dB. D[4:0] = 10000 for -1 dB. D[4:0] = 11001 for -0.1 dB. 00000000 D0: Reserved D1: enable FIFO (first in, first out) (see Note 1) D2: bypass EC ISDN HPF (138 kHz) D3: ECNULL. When D3 is set to 1, ECP and ECM are connected to weakly driven mid supply. It can be used only during EC power-down mode. SCR14 1110 R/W NOTE 1: It is a two-stage FIFO buffer, and can store up to two write samples if asynchronous write operation is required. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) SCR0 - SYSTEM CONTROL (address: 0000b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) 0 0 0 0 0 0 0 1 01 DESCRIPTION Software reset (self clearing). All control registers are set to reset content. SCR1 - TX PAA CONTROL (address: 0001b, contents at reset: 00000000b) 10 D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) DESCRIPTION 0 0 0 0 0 0 0 0 00 TX PAA gain = 0 dB 0 0 0 0 0 0 0 1 01 TX PAA gain = -1 dB 0 0 0 0 0 0 1 0 02 TX PAA gain = -2 dB 0 0 0 0 0 0 1 1 03 TX PAA gain = -3 dB 0 0 0 0 0 1 0 0 04 TX PAA gain = -4 dB 0 0 0 0 0 1 0 1 05 TX PAA gain = -5 dB 0 0 0 0 0 1 1 0 06 TX PAA gain = -6 dB 0 0 0 0 0 1 1 1 07 TX PAA gain = -7 dB 0 0 0 0 1 0 0 0 08 TX PAA gain = -8 dB 0 0 0 0 1 0 0 1 09 TX PAA gain = -9 dB 0 0 0 0 1 0 1 0 0A TX PAA gain = -10 dB 0 0 0 0 1 0 1 1 0B TX PAA gain = -11 dB 0 0 0 0 1 1 0 0 0C TX PAA gain = -12 dB 0 0 0 0 1 1 0 1 0D TX PAA gain = -13 dB 0 0 0 0 1 1 1 0 0E TX PAA gain = -14 dB 0 0 0 0 1 1 1 1 0F TX PAA gain = -15 dB 0 0 0 1 0 0 0 0 10 TX PAA gain = -16 dB 0 0 0 1 0 0 0 1 11 TX PAA gain = -17 dB 0 0 0 1 0 0 1 0 12 TX PAA gain = -18 dB 0 0 0 1 0 0 1 1 13 TX PAA gain = -19 dB 0 0 0 1 0 1 0 0 14 TX PAA gain = -20 dB 0 0 0 1 0 1 0 1 15 TX PAA gain = -21 dB 0 0 0 1 0 1 1 0 16 TX PAA gain = -22 dB 0 0 0 1 0 1 1 1 17 TX PAA gain = -23 dB 0 0 0 1 1 0 0 0 18 TX PAA gain = -24 dB - - - - - - - - 19-FF TX PAA gain = -24 dB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) SCR2 - RX PGA2 CONTROL (address: 0010b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) 0 0 0 0 0 0 0 0 00 RX PGA2 = 0 dB 0 0 0 0 0 0 0 1 01 RX PGA2 = 0.25 dB 0 0 0 0 0 0 1 0 02 RX PGA2 = 0.5 dB 0 0 0 0 0 0 1 1 03 RX PGA2 = 0.75 dB 0 0 0 0 0 1 0 0 04 RX PGA2 = 1.0 dB 0 0 0 0 0 1 0 1 05 RX PGA2 = 1.25 dB 0 0 0 0 0 1 1 0 06 RX PGA2 = 1.5 dB 0 0 0 0 0 1 1 1 07 RX PGA2 = 1.75 dB 0 0 0 0 1 0 0 0 08 RX PGA2 = 2.0 dB 0 0 0 0 1 0 0 1 09 RX PGA2 = 2.25 dB 0 0 0 0 1 0 1 0 0A RX PGA2 = 2.5 dB 0 0 0 0 1 0 1 1 0B RX PGA2 = 2.75 dB 0 0 0 0 1 1 0 0 0C RX PGA2 = 3.0 dB 0 0 0 0 1 1 0 1 0D RX PGA2 = 3.25 dB 0 0 0 0 1 1 1 0 0E RX PGA2 = 3.5 dB 0 0 0 0 1 1 1 1 0F RX PGA2 = 3.75 dB 0 0 0 1 0 0 0 0 10 RX PGA2 = 4.0 dB 0 0 0 1 0 0 0 1 11 RX PGA2 = 4.25 dB 0 0 0 1 0 0 1 0 12 RX PGA2 = 4.5 dB 0 0 0 1 0 0 1 1 13 RX PGA2 = 4.75 dB 0 0 0 1 0 1 0 0 14 RX PGA2 = 5.0 dB 0 0 0 1 0 1 0 1 15 RX PGA2 = 5.25 dB 0 0 0 1 0 1 1 0 16 RX PGA2 = 5.5 dB 0 0 0 1 0 1 1 1 17 RX PGA2 = 5.75 dB 0 0 0 1 1 0 0 0 18 RX PGA2 = 6.0 dB 0 0 0 1 1 0 0 1 19 RX PGA2 = 6.25 dB 0 0 0 1 1 0 1 0 1A RX PGA2 = 6.5 dB 0 0 0 1 1 0 1 1 1B RX PGA2 = 6.75 dB 0 0 0 1 1 1 0 0 1C RX PGA2 = 7.0 dB 0 0 0 1 1 1 0 1 1D RX PGA2 = 7.25 dB 0 0 0 1 1 1 1 0 1E RX PGA2 = 7.5 dB 0 0 0 1 1 1 1 1 1F RX PGA2 = 7.75 dB 0 0 1 0 0 0 0 0 20 RX PGA2 = 8.0 dB 0 0 1 0 0 0 0 1 21 RX PGA2 = 8.25 dB 0 0 1 0 0 0 1 0 22 RX PGA2 = 8.5 dB 0 0 1 0 0 0 1 1 23 RX PGA2 = 8.75 dB 0 0 1 0 0 1 0 0 24 RX PGA2 = 9.0 dB 0 0 1 0 0 1 0 1 25 RX PGA2 = 9.25 dB 0 0 1 0 0 1 1 0 26 RX PGA2 = 9.5 dB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DESCRIPTION 11 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) SCR2 - RX PGA2 CONTROL (address: 0010b, contents at reset: 00000000b) (continued) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) DESCRIPTION 0 0 1 0 0 1 1 1 27 RX PGA2 = 9.75 dB 0 0 1 0 1 0 0 0 28 RX PGA2 = 10.0 dB 0 0 1 0 1 0 0 1 29 RX PGA2 = 10.25 dB 0 0 1 0 1 0 1 0 2A RX PGA2 = 10.5 dB 0 0 1 0 1 0 1 1 2B RX PGA2 = 10.75 dB 0 0 1 0 1 1 0 0 2C RX PGA2 = 11.0 dB 0 0 1 0 1 1 0 1 2D RX PGA2 = 11.25 dB 0 0 1 0 1 1 1 0 2E RX PGA2 = 11.5 dB - - - - - - - - 2F-FF RX PGA2 = 11.5 dB SCR3 - RX EQ CONTROL (address: 0011b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) DESCRIPTION 0 0 0 0 0 0 0 0 00 RX EQ = 0 dB/MHz 0 0 0 0 0 0 0 1 01 RX EQ = 5 dB/MHz 0 0 0 0 0 0 1 0 02 RX EQ = 10 dB/MHz 0 0 0 0 0 0 1 1 03 RX EQ = 15 dB/MHz 0 0 0 0 0 1 0 0 04 RX EQ = 20 dB/MHz 0 0 0 0 0 1 0 1 05 RX EQ = 25 dB/MHz - - - - - - - - 06-FF RX EQ = 25 dB/MHz SCR4 - VCXO DATA (address: 0100b, contents at reset: 00000000b) SCR5 - VCXO DATA (address: 0101b, contents at reset: 00000000b) The following page shows some representative VCXO DAC analog outputs. The read-back values of SCR4 and SCR5 are different from the values written to the registers. 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) VCXO DAC DIGITAL-ANALOG MAPPING (representative analog outputs) OPERATION SRC5[7:0] x 24 + SCR4[7:0] HEX RESULT ANALOG OUTPUT COMMENTS 0x800 0V Min scale 0x801 V Just above min * * * * * * * * * 0xFFF 2047 V Just below mid 0x000 2048 V Mid scale 0x001 2049 V Just above mid * * * * * * * * * 0x7FE 4094 V Just below max 0x7FF 4095 V Max scale NOTES: 2. = (3/4095) V 3. The analog output is computed as follows: ((SCR%[7:0] * 24 + SCR4[7:0])) + 2048(decimal) * Examples: D Positive SCR5 + positive SCR4 (0x24 * 24 + 0x42) = 0x240 + 0x42 = 0x282 = 642 decimal Analog output = (642 + 2048) V = 2690 V = 1.971 V The read-back values of SCR5 and SCR4 are 0x02 and 0x82. D Positive SCR5 + negative SCR4 (0x24 * 24 + 0xC2) = 0x240 + 0xFC2 = 0x202 = 514 decimal Analog output = (514 + 2048) V = 2562 V = 1.877 V The read-back values of SCR5 and SCR4 are 0x02 and 0x02. D Negative SCR5 + positive SCR4 (0xA2 * 24 + 0x42) = 0xA20 + 0x42 = 0xA62 = -1438 decimal Analog output = (-1438 + 2048) V = 610 V = 0.447 V The read-back values of SCR5 and SCR4 are 0x0A and 0x62 D Negative SCR5 + negative SCR4 (0xA2 * 24 + 0xC2) = 0xA20 + 0xFC2 = 0x9E2 = -1566 decimal Analog output = (-1566 + 2048) V = 482 V = 0.353 V The read-back values of SCR5 and SCR4 are 0x09 and 0xE2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) SCR6 - GP OUTPUT DATA (address: 0110b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION 0/1 - - - - - - - GP7 = low(0)/high(1) - 0/1 - - - - - - GP6 = low(0)/high(1) - - 0/1 - - - - - GP5 = low(0)/high(1) - - - 0/1 - - - - GP4 = low(0)/high(1) - - - - 0/1 - - - GP3 = low(0)/high(1) - - - - - 0/1 - - GP2 = low(0)/high(1) - - - - - - 0/1 - GP1 = low(0)/high(1) - - - - - - - 0/1 GP0 = low(0)/high(1) SCR7 - MISCELLANEOUS CONTROL 1 (address: 0111b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION - - - - - - - 1 Bypass TX digital HPF (138 kHz) - - - - - - 1 - Software power-down RX channel - - - - - 1 - - Software power-down TX channel - - - - 1 - - - Analog loopback (TX channel) (see Note 4) - - - 1 - - - - Digital loopback (TX and EC channel) (see Note 5) - - 1 - - - - - TX parallel interface (read back) test mode enable (see Note 6) - 1 - - - - - - EC channel power down 1 - - - - - - - EC analog loopback NOTES: 4. Analog loopback: Analog outputs (TXP/TXM or ECP/ECM) are internally connected to RXP/RXM. 5. Digital loopback: RX digital output buffer (16-bit word) is internally connected to the TX/EC digital input buffer. 6. The input digital data is read back from RX output buffer without going through the DAC. SCR8 - EC PAA CONTROL (address: 1000b, contents at reset: 00000000b) SCR8 has the same format as SCR1 (see SCR1 - TX PAA Control). SCR9 - RX OFFSET CONTROL [7:0] (address: 1001b, contents at reset: 00000000b) SCR10 - RX OFFSET CONTROL [15:8] (address: 1010b, contents at reset: 00000000b) Registers SCR9 and SCR10 are combined to form a 16-bit word in 2s complement data format. The 16-bit word is used to adjust the RX channel DC offset error. The 16-bit word is added to the 16-bit data from the RX digital filter before the data goes to the RX output buffer. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System-Control Registers (SCRs) (Continued) SCR11 - TX CHANNEL DIGITAL GAIN CONTROL (address: 1011b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) DESCRIPTION 0 0 0 1 1 0 0 1 19 TX digital gain = -0.1 dB 0 0 0 1 1 0 0 0 18 TX digital gain = -0.2 dB 0 0 0 1 0 1 1 1 17 TX digital gain = -0.3 dB 0 0 0 1 0 1 1 0 16 TX digital gain = -0.4 dB 0 0 0 1 0 1 0 1 15 TX digital gain = -0.5 dB 0 0 0 1 0 1 0 0 14 TX digital gain = -0.6 dB 0 0 0 1 0 0 1 1 13 TX digital gain = -0.7 dB 0 0 0 1 0 0 1 0 12 TX digital gain = -0.8 dB 0 0 0 1 0 0 0 1 11 TX digital gain = -0.9 dB 0 0 0 1 0 0 0 0 10 TX digital gain = -1 dB 0 0 0 0 0 0 0 0 00 TX digital gain = 0 dB 0 0 0 0 0 0 0 1 01 TX digital gain = 0.1 dB 0 0 0 0 0 0 1 0 02 TX digital gain = 0.2 dB 0 0 0 0 0 0 1 1 03 TX digital gain = 0.3 dB 0 0 0 0 0 1 0 0 04 TX digital gain = 0.4 dB 0 0 0 0 0 1 0 1 05 TX digital gain = 0.5 dB 0 0 0 0 0 1 1 0 06 TX digital gain = 0.6 dB 0 0 0 0 0 1 1 1 07 TX digital gain = 0.7 dB 0 0 0 0 1 0 0 0 08 TX digital gain = 0.8 dB 0 0 0 0 1 0 0 1 09 TX digital gain = 0.9 dB 0 0 0 0 1 0 1 0 0A TX digital gain = 1 dB - - - - - - - - All others Reserved (see Note 7) Digital gain is used to compensate the TX-channel gain error. NOTE 7: Performance of the codec for an invalid combination of bits is not ensured, and such combinations should not be used. The user should make no assumption that the code bits saturate to a maximum or minimum value or wrap around to a valid combination. SCR12 - RX PGA1 CONTROL (address: 1100b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 REGISTER VALUE (HEX) DESCRIPTION 0 0 0 0 0 0 0 0 00 RX PGA1 = 0 dB 0 0 0 0 0 0 0 1 01 RX PGA1 = 1 dB 0 0 0 0 0 0 1 0 02 RX PGA1 = 2 dB 0 0 0 0 0 0 1 1 03 RX PGA1 = 3 dB 0 0 0 0 0 1 0 0 04 RX PGA1 = 4 dB 0 0 0 0 0 1 0 1 05 RX PGA1 = 5 dB 0 0 0 0 0 1 1 0 06 RX PGA1 = 6 dB - - - - - - - - 07-FF RX PGA1 = 6 dB SCR13 - EC CHANNEL DIGITAL GAIN CONTROL (address: 1101b, contents at reset: 00000000b) SCR13 has the same format as SCR11 (see SCR11 - TX Channel Digital Gain Control). POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Table 2. System Control Registers (SCRs) (Continued) SCR14 - MISCELLANEOUS CONTROL 2 (address: 1110b, contents at reset: 00000000b) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 - - 1 0 Enable FIFO DESCRIPTION 0 0 0 0 - 1 - 0 Bypass EC digital HPF (138 kHz) 0 0 0 0 1 - - 0 ECP and ECM are connected to weakly driven mid supply. It can be used only during EC power-down mode. device initialization time The TLV320AD13A completes all calibration and initialization in less than 1 second. This includes reference settling time (950 s), one rest after power up (one serial frame), VCXODAC configuration (two serial frames), TX/RX gain select (four serial frames), and calibration of the DAC (256 x 113 ns). Each 16-bit frame requires up to 5 s. The host processor must initiate this process upon a successful power up. power down Both hardware and software power-down modes are provided. The serial interface is operative when the codec is in power-down mode. By sending commands through the serial interface, either the codec or part of the codec can be software powered down. All the references are kept on in the software power-down mode. The codec also can be hardware powered down by setting the PWDN terminal to high. All the references are shut off in the hardware power-down mode. The contents of the registers do not change in either power-down mode. power-supply grouping recommendation The following power-supply grouping is recommended for best performance of this device. It is recommended for each power supply group to have a separate ferrite bead. D D D D 16 Group 1: AVDDFILTX, AVDDFILEC, AVDD1TX, AVDD2TX, AVDD1EC, AVDD2EC Group 2: AVDDFILRX, AVDDADC Group 3: AVDDREF Group 4: DVDDBF, DVDDCLK, DVDDLG, DVDDRX, DVDDDAC POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage, AVDD to AVSS, DVDD to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4.5 V Analog input voltage range to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to AVDD + 0.3 V Digital input voltage range to DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to DVDD + 0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 150C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions power supply Supply voltage AVDDADC, AVDD1EC, AVDD2EC, AVDD1TX, AVDD2TX, AVDDFILEC, AVDDFILTX, AVDDFILRX, AVDDREF, DVDDBF, DVDDCLK, DVDDLG, DVDDDAC, DVDDRX MIN NOM MAX 3 3.3 3.6 PSSR UNIT V dB digital inputs MIN High-level input voltage, VIH Low-level input voltage, VIL II = 0.75 mA II = -0.75 mA NOM MAX 2 UNIT V 0.8 V analog input MIN g g g Analog-input signal range AVDDFILRX = 3.3 V, input signal is measured single ended NOM MAX AVDDFILRX/2 0.75 AVDDFILRX = 3.3 V, input signal is measured differentially UNIT V 3 VPP clock MIN Input clock frequency Input clock duty cycle DVDDCLK = 3.3 V DVDDCLK = 3.3 V POST OFFICE BOX 655303 NOM 35.328 MAX UNIT MHz 50% * DALLAS, TEXAS 75265 17 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 electrical characteristics over recommended operating free-air temperature range, typical at TA = 25C, CLKIN = 35.328 MHz, analog power supply = 3.3 V, digital power supply = 3.3 (unless otherwise noted) TX and EC channel (measured differentially unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP Signal bandwidth Conversion rate Channel gain error OSEN = 1 4.416 OSEN = 0 2.208 PAA = 0 dB, Input = 99.1875 kHz at 6 dB PAA step gain error DC offset kHz MHz 0.1 dB -0.2 0.2 dB 70 mV -70 -65 Group delay Power-supply reject ratio g Full-scale output voltage 200 mVPP at 99.1875 kHz Load = 2000 , Single-ended measured Load = 4000 , Differentially measured UNIT -0.1 RX to TX channel (43.125 kHz at -1 dB) Cross-talk PSRR MAX 138 dB 6 s 50 dB AVDD1TX/2 0.75 V 3 VPP 43.125 kHz at -1dB 43.125 kHz at -1dB 81 dB 86 dB AC Performance SNR Signal-to-noise ratio THD Total harmonic distortion ratio TSNR Signal-to-noise + harmonic distortion ratio 43.125 kHz at -1dB 80 dB MT Missing tone test 120.750 kHz (missing tone) 76 dB Channel Frequency Response Gain relative to g gain at 99.1875 kHz (25.875-kHz digital HPF is bypassed) 30 kHz -0.25 60 kHz -0.25 0.25 0.25 138 kHz -3 dB 276 kHz -55 The input signal is the digital equivalent of a sinewave (digital full scale = 0 dB). The nominal differential output with this input condition is 3 VPP. 27 tones, 25.875 kHz to 138 kHz, 4.3125 kHz/step, -1 dB reference output PARAMETER REFP REF plus voltage REFM REF minus voltage VMIDREF REF mid voltage VMIDADC RX channel mid voltage TEST CONDITIONS MIN TYP MAX UNIT AVDDREF = 3.3 V AVDDREF = 3.3 V 2.5 V 0.5 V AVDDREF = 3.3 V AVDDREF = 3.3 V 1.5 V 1.5 V digital outputs PARAMETER VOH VOL 18 TEST CONDITIONS High-level output voltage IOH = 0.5 mA IOL = -0.5 mA Low-level output voltage POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MIN TYP MAX 2.4 UNIT V 0.6 V TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 electrical characteristics over recommended operating free-air temperature range, typical at TA = 25C, CLKIN = 35.328 MHz, analog power supply = 3.3 V, digital power supply = 3.3 (unless otherwise noted) (continued) RX channel (measured differentially unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Signal bandwidth 1104 kHz Conversion rate 4.416 MHz PGA1 = 0 dB, PGA2 = 2.5 dB, Input = 99.1875 kHz at -1 dB Channel gain error -1.5 PGA1 (0 dB to 6 dB at 1 dB/step) PGA gain error PGA2 (2.5 dB to 14 dB at 0.25 dB/step) DC offset 1.5 -0.2 0.2 -0.03 0.03 PGA1 = 0 dB, PGA2 = 2.5 dB TX to RX channel (99.1875 kHz at -1 dB) Crosstalk Group delay CMRR Common-mode reject ratio 99.1875 kHz at -1 dB PSRR Power-supply reject ratio 200 mVPP at 99.1875 kHz Input impedance dB 3 mV 63 dB 8 s 70 dB 50 dB AVDDFILRX/2 0.75 Analog-input self-bias dc voltage dB V 10 k 99.1875 kHz at 0 dB 99.1875 kHz at 0 dB 68 dB 77 dB 99.1875 kHz at 0 dB 68 dB 120.750 kHz (missing tone) 66 750.375 kHz (missing tone) 66 AC Performance SNR Signal-to-noise ratio THD Total harmonic distortion ratio TSNR Signal-to-noise + harmonic distortion ratio MT Missing tone test Missing-tone dB Channel Frequency Response (EQ[2:0] = 0 dB/MHz) Gain relative to gain at 99 99.1875 1875 kHz 60 kHz -0.25 0.25 300 kHz -0.25 0.25 800 kHz 1 1000 kHz The analog input test signal is a sine wave with 0 dB = 3 VPP as the reference level. 250 tones, 25.875 kHz to 1104 kHz, 4.3125 kHz/step, 0 dB dB 0.7 VCXO DAC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 12 Bit DNL Differential nonlinearity 1 LSB INL Integral nonlinearity 4 LSB 30 mV 3 V Offset error Analog output Full-scale output voltage Load = 50 k, VDD = 3.3 V power dissipation PARAMETER TEST CONDITIONS Active mode Power dissipation Power down mode Power-down POST OFFICE BOX 655303 MIN TYP MAX 800 850 Hardware power down 65 Software power down 70 * DALLAS, TEXAS 75265 UNIT mW 19 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 timing requirements parallel port (see Figures 2 and 3) MIN NOM MAX 28.3 UNIT tc1 th1 Cycle time, CLKIN Hold time, D0-D15 valid after WETX 5 ns th2 th3 Hold time, D0-D15 valid after WEEC 5 ns Hold time, SYNC high after CLKIN 5 ns tsu1 tsu2 Setup time, D0-D15 valid before WETX 15 ns Setup time, D0-D15 valid before WEEC 15 ns tsu3 tsu4 Setup time, SYNC high before CLKIN 10 ns Setup time, WETX/WEEC high before CS ns 5 ns CLKIN cycle tw1 Pulse duration, KOZ 1 tw2 tw3 Pulse duration, OE low 20 ns Pulse duration, WETX low 28 ns tw4 tw5 Pulse duration, WEEC low 28 Pulse duration, SYNC high ns 28 ns switching characteristics over recommended operating conditions (unless otherwise noted) parallel port (see Figures 2 and 3) PARAMETER MIN TYP OSEN = 0 16 OSEN = 1 8 MAX UNIT CLKIN cycles tc2 2 Cycle time, time INT tc3 Cycle time, CLKOUT td1 td2 Delay time, KOZ end to INT Delay time, KOZ end (CLKIN) to OE/CS 0 ns td3 Delay time, KOZ end to WETX/CS or WEEC/CS 0 ns td4 td5 Delay time, from OE/CS (and READY if CONFIG2 = 1) to D0-D15 valid td6 Delay time, KOZ end to SCLK/READY 14.2 ns td7 Delay time, SCLK/READY to KOZ 14.2 ns 20 CLKIN cycles 8 5 Delay time, from OE/CS to D0-D15 Hi-Z POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ns 15 ns 5 ns TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 Keep Out Zones (KOZs) CLKIN (35.328 MHz) (input) tc1 tw1 td1 tc2 INT (OSEN = 0) (output) tc2 INT (OSEN = 1) (output) tc3 CLKOUT (CONFIG2 = 0 or floating) (output) SCLK/READY (CONFIG2 = 0 or floating) (output) td6 SCLK/READY (CONFIG2 = 1) (output) II II II II CS (input) (see Note A) OE (RXADC) (input) (see Note A) td7 tw2 WETX (TXDAC) (input) (see Note B) WEEC (TXDAC) (input) (see Note B) I I td2 II II II II tsu4 II II td3 II II tsu4 tw3 II II td5 tsu1 td4 II II II II tw4 td3 tsu2 D0-D15 (input/output) 4 Access Zone 1 1 th1 Access Zone 2 2 Access Zone 3 3 th2 Access Zone 4 4 NOTES: A. CS AND OE may fall/rise together or be skewed from each other. It does not matter which falls/rises first. However, td4 is referenced from whichever falls last, and td5 is referenced from whichever rises first. CS can be connected to low if the parallel bus is not shared. B. CS and WETX/WEEC may fall together or be skewed from each other. The rising edges of WETX and WEEC should occur prior to the rising edge of CS. C. The minimum update rate for TX and EC channel is 276 kHz in normal mode, and 552 kHz in oversampling mode. The write operation for TX and EC can occur at any place as long as they do not conflict with each other or the read cycle. D. If CONFIG2 = 1, the READY signal must be high to read or write the codec. Figure 2. Parallel Port POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 21 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 KOZ 1 CLKIN (35.328 MHz) (input) 2 3 4 5 6 7 8 tsu3 th3 SYNC (input) IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIII tw5 INT (output) CLKOUT (output) SCLK (output) Rising edge of INT and CLKOUT occurs on eighth rising edge of CLKIN after SYNC pulse is sampled high. Figure 3. SYNC Pulse 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 timing requirements serial port (see Figure 4) MIN tw Pulse duration, FS high tc(FS) NOM MAX 28 Cycle time, FS UNIT ns SCLK cycles 18 switching characteristics over recommended operating conditions serial port (see Figure 4) PARAMETER MIN TYP MAX UNIT CLKIN cycles tc Cycle time, SCLK 8 td1 td2 Delay time, SCLK to SDO valid td3 td4 Delay time, SCLK to SDI invalid Delay time, FS to SCLK td5 Delay time, SDI valid to SCLK 20 ns 15 Delay time, SCLK to FS ns 5 ns 5 ns 20 ns tc(FS) tw (see Note A) FS (input) td2 td4 tc SCLK (output) FS is latched at falling edge of SCLK. NNNNNN NNNNNN SDI (input) SDO (output) (Read: R/W = 1) SDO (output) (Write: R/W = 0) NOTES: A. B. C. D. R/W td5 td3 ADR 1 ADR 0 S3 S2 S1 S0 X D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 NNNN NNNN D0 see Note B Hi-Z Hi-Z D0 td1 Hi-Z A width of one SCLK cycle time is recommended for tw. ADR0 and ADR1 are the hardware-configurable values of ADR0 and ADR1 input terminals. Data on SDI is latched at the falling edge of SCLK. Data is sent from SDO at the rising edge of SCLK. Figure 4. Serial Port POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 23 TLV320AD13A 3.3-V INTEGRATED ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL) INTEGRATED SERVICES DIGITAL NETWORK (ISDN) CODEC SLWS109 - AUGUST 2000 MECHANICAL DATA PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0- 7 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 thermal resistance (R) characteristics NO 1 RJC Junction-to-case AIR FLOW (LFPM) 5.4 N/A 2 30.4 0 3 24.2 150 22.3 250 20.0 500 4 RJA Junction to free air Junction-to-free 5 LFPM = Linear feet per minute 24 C/W POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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