ISPLSI 1024EA-100LTN100 - LATTICE SEMICONDUCTOR

1. General description

The PCA9547 is an octal bidirectional translating multiplexer controlled by the I2C-bus.

The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one

SCx/SDx channel can be selected at a time, determined by the contents of the

programmable control re gister. Th e device powers up with Channel 0 connected, allowing

immediate communication between the master and downstream devices on that channel.

An active LOW reset input allows the PCA9547 to recover from a situation where one of

the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets

the I2C-bus st ate machine causing all the channels to be d eselected, except Channel 0 so

that the master can regain control of the bus.

The pass gates of the multiplexers are constructed such that the VDD pin can be used to

limit the maximum high voltage which will be passed by the PCA9547. This allows the use

of diff erent bus voltages on each pair , so that 1.8 V, 2.5 V, or 3.3 V parts can communicate

with 5 V parts without any additional protection. External pull-up resistors pull the bus up

to the desired voltage level for each channel. All I/O pins are 5 V tolerant.

2. Features and benefits

1-of-8 bidirectional translating multiplexer

I2C-bus interface logic; compatible with SMBus standards

Active LOW RESET input

3 address pins allowing up to 8 devices on the I2C-bus

Channel selection via I2C-bus, one channel at a time

Power-up with all channels deselected except Channel 0 which is connected

Low Ron multiplexers

Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses

No glitch on power-up

Supports hot insertion

Low standby current

Operating power supply voltage range of 2.3 V to 5.5 V

5 V tolerant inputs

0 Hz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

Packages offered: SO24, TSSOP24, HVQFN24

PCA9547

8-channel I2C-bus multiplexer with reset

Rev. 4 — 1 April 2014 Product data sheet

Product data sheet Rev. 4 — 1 April 2014 2 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

3. Ordering information

3.1 Ordering options

Table 1. Ordering information

Type number Topside

marking Package

Name Description Version

PCA9547D PCA9547D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

PCA9547PW PCA9547PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width

4.4 mm SOT355-1

PCA9547BS 9547 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 40.85 mm SOT616-1

Table 2. Ordering options

Type number Orderable part

number Package Packing method Minimum

order

quantity

Temperature range

PCA9547D PCA9547D,112 SO24 Standard marking

* IC’s tube - DSC bulk pack 1200 Tamb =40 C to +85 C

PCA9547D,118 SO24 Reel 13” Q1/T 1

*Standard mark SMD 1000 Tamb =40 C to +85 C

PCA9547PW PCA9547PW,112 TSSOP24 Standard marking

* IC’s tube - DSC bulk pack 1575 Tamb =40 C to +85 C

PCA9547PW,118 TSSOP24 Reel 13” Q1/T1

*Standard mark SMD 2500 Tamb =40 C to +85 C

PCA9547BS PCA9547BS,118 HVQFN24 Reel 13” Q1/T1

*Standard mark SMD 6000 Tamb =40 C to +85 C

Product data sheet Rev. 4 — 1 April 2014 3 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

4. Block diagram

Fig 1. Block diagram of PCA9547

SWITCH CONTROL LOGIC

PCA9547

RESET

CIRCUIT

002aaa961

SC0

SC1

SC2

SC3

SC4

SC5

SC6

SC7

SD0

SD1

SD2

SD3

SD4

SD5

SD6

SD7

RESET

C-BUS

CONTROL

INPUT

FILTER

SCL

SDA

Product data sheet Rev. 4 — 1 April 2014 4 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

5. Pinning information

5.1 Pinning

Fig 2. Pin configuration for SO24 Fig 3. Pin configuration for TSSOP24

Fig 4. Pin configuration for HVQFN24 (transparent top view)

PCA9547D

A0 VDD

A1 SDA

RESET SCL

SD0 A2

SC0 SC7

SD1 SD7

SC1 SC6

SD2 SD6

SC2 SC5

SD3 SD5

SC3 SC4

VSS SD4

002aaa958

PCA9547PW

A0 VDD

A1 SDA

RESET SCL

SD0 A2

SC0 SC7

SD1 SD7

SC1 SC6

SD2 SD6

SC2 SC5

SD3 SD5

SC3 SC4

VSS SD4

002aaa959

002aaa960

PCA9547BS

Transparent top view

SC5

SD2

SC2

SD6

SC1 SC6

SD1 SD7

SC0 SC7

SD0 A2

SD3

SC3

VSS

SD4

SC4

SD5

RESET

VDD

SDA

SCL

terminal 1

index area

613

514

4 15

3 16

2 17

118

Product data sheet Rev. 4 — 1 April 2014 5 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

5.2 Pin description

[1] HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The

VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,

and board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

Table 3. Pin description

Symbol Pin Description

SO24, TSSOP24 HVQFN24

A0 1 22 address input 0

A1 2 23 address input 1

RESET 3 24 active LOW reset input

SD0 4 1 serial data output 0

SC0 5 2 serial clock output 0

SD1 6 3 serial data output 1

SC1 7 4 serial clock output 1

SD2 8 5 serial data output 2

SC2 9 6 serial clock output 2

SD3 10 7 serial data output 3

SC3 11 8 serial clock output 3

VSS 12 9[1] supply ground

SD4 13 10 serial data output 4

SC4 14 11 serial clock output 4

SD5 15 12 serial data output 5

SC5 16 13 serial clock output 5

SD6 17 14 serial data output 6

SC6 18 15 serial clock output 6

SD7 19 16 serial data output 7

SC7 20 17 serial clock output 7

A2 21 18 address input 2

SCL 22 19 serial clock line

SDA 23 20 serial data line

VDD 24 21 supply voltage

Product data sheet Rev. 4 — 1 April 2014 6 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

6. Functional description

6.1 Device addressing

Following a START condition, the bus mast er mus t ou tpu t th e ad dress of the slave it is

accessing. The address of the PCA9547 is shown in Figure 5. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

6.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9547, which will be stored in the Control register. If multiple bytes are

received by the PCA9547, it will save the last byte received. This register can be written

and read via the I2C-bus.

6.2.1 Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the control

the control byte are used to determine which channel is to be selected. When a cha nnel is

selected, the channel will become active after a STOP condition has been placed on the

I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is

made active, so that no false conditions are generated at the time of connection.

Fig 5. Slave address

002aaa962

1 1 1 0 A2 A1 A0 R/W

fixed hardware

selectable

Fig 6. Control register

002aaa963

X X X X B3 B2 B1 B0

channel selection bits

(read/write)

76543210

enable bit

Product data sheet Rev. 4 — 1 April 2014 7 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

6.3 RESET input

The RESET input is an active LOW signal which may be used to recover from a bus fault

condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9547 will reset its

RESET input must be connected to VDD through a pull-up resistor.

6.4 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9547 in

a reset condition until VDD has reached VPOR. At this po int, the reset condition is rel eased

and the PCA9547 registe r and I2C-bus state machine are in itialized to their default st ates,

causing all the channels to be deselected except channel 0. Thereafter, VDD must be

lowered below 0.2 V for at least 5 s in order to reset the device.

Table 4. Contro l register

Write = channel selection; Read = channel status

D7 D6 D5 D4 B3 B2 B1 B0 Command

XXXX0XXXno channel selected

XXXX1000channel0 enabled

XXXX1001channel1 enabled

XXXX1010channel2 enabled

XXXX1011channel3 enabled

XXXX1100channel4 enabled

XXXX1101channel5 enabled

XXXX1110channel6 enabled

XXXX1111channel7 enabled

00001000channel 0 enabled;

power-up/reset default state

Product data sheet Rev. 4 — 1 April 2014 8 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

6.5 Voltage translation

The pass gate transistors of the PCA9547 are constructed such that the VDD voltage can

be used to limit the maximum voltage that will be passed from one I2C-bus to another.

Figure 7 shows the voltage characteristics of the pass ga te transistors (note that the

PCA9547 is only tested at the points specified in Section 11 “Static characteristics” of this

data sheet). In order for the P CA9 54 7 to act as a voltage translator, the Vo(mux) voltage

should be equal to, or lower than the lowest bus voltage. For examp le, if the main bus was

running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(mux) should be

equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at

Figure 7, we see that Vo(mux)(max) will be at 2.7 V when the PCA9547 supply voltage is

3.5 V or lower so the PCA9547 supply voltage could be set to 3.3 V. Pull-up resistors can

then be used to bring the bus voltages to their appropriate levels (see Figure 14).

More information can b e found in Application Note AN262, PCA954X family of I2C/SMBus

multiplexers and switches.

(1) maximum

(2) typical

(3) minimum

Fig 7. Pass gate voltage as a function of supply voltage

VDD (V)

2.0 5.54.53.0 4.0

002aab802

3.0

2.0

4.0

5.0

Vo(mux)

(V)

1.0 3.5 5.02.5

(1)

(2)

(3)

Product data sheet Rev. 4 — 1 April 2014 9 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

7. Characteristics of the I2C-bus

The I2C-bus is for 2 -way, 2-line communication between differe nt ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bi t is transferred durin g each clock pulse . The data o n the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 8).

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HI GH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (seeFigure 9.)

Fig 8. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 9. Definition of START and STOP conditions

mba608

SDA

SCL P

STOP condition

START condition

Product data sheet Rev. 4 — 1 April 2014 10 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

7.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The

device that controls the message is the ‘master’ and the devices which are controlled by

the master are the ‘slaves’ (see Figure 10).

7.3 Acknowledge

The number of data bytes transferred between the START and the ST OP cond itions from

transmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,

whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addresse d must gener ate an acknowledg e af ter the reception of

each byte. Also a master must generate an acknowledge after the reception of each byte

that has been clocke d ou t of th e sla ve tr an smitter. The device that acknowledges has to

pull down the SDA line during the acknowledge cl ock pulse , so that the SDA line is st able

LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold

times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event, the

transmitter mus t leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 10. System configuratio n

002aaa966

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER MASTER

TRANSMITTER/

RECEIVER

SDA

SCL

I2C-BUS

MULTIPLEXER

SLAVE

Fig 11 . Acknowledgement on the I2C-bus

002aaa987

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from master

Product data sheet Rev. 4 — 1 April 2014 11 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

7.4 Bus transactions

Data is transmitted to the PCA9547 control register using the Write mode as shown in

Figure 12.

Data is read from PCA9547 using the Read mode as shown in Figure 13.

Fig 12. Write control register

Fig 13. Read co ntrol register

002aaa988

XXXXB3B2B1B01 1 0 A2 A1 A0 0 AS 1 A P

slave address

START condition R/W acknowledge

from slave acknowledge

from slave

control register

SDA

STOP condition

002aaa989

XXXXB3B2B1B01 1 0 A2 A1 A0 1 AS 1 NA P

slave address

START condition R/W acknowledge

from slave no acknowledge

from master

control register

SDA

STOP condition

last byte

Product data sheet Rev. 4 — 1 April 2014 12 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

8. Application design-in information

Fig 14. Typical application

PCA9547

SD0

SC0

SD1

SC1

VSS

SDA

SCL

RESET

VDD = 3.3 V

VDD = 2.7 V to 5.5 V

I2C-bus/SMBus

master

002aaa965

SDA

SCL channel 0

channel 1

SD2

SC2 channel 2

SD3

SC3 channel 3

SD4

SC4

V = 2.7 V to 5.5 V

SD5

SC5

channel 4

channel 5

SD6

SC6 channel 6

V = 2.7 V to 5.5 V

SD7

SC7 channel 7

V = 2.7 V to 5.5 V

Product data sheet Rev. 4 — 1 April 2014 13 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

9. Limiting values

[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which ar e detrimental to reliability. The maximum junction

temperature of this integrated circuit should not exceed 125 C.

10. Thermal characteristics

Table 5. Limiting valu es

In accordance with the Absolute Maximum Rating System (IEC 60134).[1]

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +7.0 V

VIinput voltage 0.5 +7.0 V

IIinput current 20 +20 mA

IOoutput current 25 +25 mA

IDD supply current 100 +100 mA

ISS ground supply current 100 +100 mA

Ptot total power dissipation - 400 mW

Tj(max) maximum junction

temperature [1] -+125C

Tstg storage temperature 60 +150 C

Tamb ambient temperature 40 +85 C

Table 6. Therm al char acteristics

Symbol Parameter Conditions Typ Unit

Rth(j-a) thermal resistance from junction

to ambient HVQFN24 package 40 C/W

SO24 package 77 C/W

TSSOP24 package 128 C/W

Product data sheet Rev. 4 — 1 April 2014 14 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

11. Static characteristics

[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.

[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.

Table 7. Static characteristics at VDD =2.3V to 3.6V

VSS = 0 V; Tamb =





C to +85



C; unless otherwise specified. See Table 8 on page 15 for VDD = 4.5 V to 5.5 V.[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 2.3 - 3.6 V

IDD supply current operating mode; VDD = 3.6 V; no load;

VI=V

DD or VSS; fSCL = 100 kHz -2050A

Istb standby current Standby mode; VDD = 3.6 V; no load;

VI=V

DD or VSS

-0.12 A

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] -1.62.1V

Input SCL; input/outpu t S DA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW- l e vel output curren t VOL =0.4V 3 - - mA

VOL =0.6V 6 - - mA

ILleakage current VI=V

DD or VSS 1-+1 A

Ciinput capacitance VI=V

SS -1419pF

Select inputs A0, A1, A2, RESET

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

ILI input leakage current pin at VDD or VSS 1-+1 A

Ciinput capacitance VI=V

SS -25 pF

Pass gate

Ron ON-state resistance multiplexer; VDD = 3.6 V; VO=0.4V;

IO=15mA 51130

multiplexer; VDD = 2.3 V to 2.7 V;

VO=0.4V; I

O=10mA 71655

Vo(mux) multiplexer output voltage Vi(mux) =V

DD =3.3V; I

o(mux) =100 A- 1.9- V

Vi(mux) =V

DD = 3.0 V to 3.6 V;

Io(mux) =100 A1.6 - 2.8 V

Vo(mux) =V

DD =2.5V;

Io(mux) =100 A-1.5- V

Vo(mux) =V

DD = 2.3 V to 2.7 V;

Io(mux) =100 A0.9 - 2.0 V

ILleakage current VI=V

DD or VSS 1-+1 A

Cio input/output capacitance VI=V

SS -35 pF

Product data sheet Rev. 4 — 1 April 2014 15 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.

[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.

Table 8. Static characteristics at VDD =4.5V to 5.5V

VSS = 0 V; Tamb =





C to +85



C; unless otherwise specified. See Table 7 on page 14 for VDD = 2.3 V to 3.6 V.[1]

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD supply voltage 4.5 - 5.5 V

IDD supply current operating mode; VDD =5.5V;

no load; VI=V

DD or VSS;

fSCL = 100 kHz

- 65 100 A

Istb standby current Standby mode; VDD =5.5V;

no load; VI=V

DD or VSS

-0.62 A

VPOR power-on reset voltage no load; VI=V

DD or VSS [2] -1.72.1V

Input SCL; input/outpu t S DA

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

IOL LOW-level output current VOL =0.4V 3 - - mA

VOL =0.6V 6 - - mA

IIL LOW-level input current VI=V

SS 1- +1 A

IIH HIGH-level input current VI=V

SS 1- +1 A

Ciinput capacitance VI=V

SS -1419pF

Select inputs A0, A1, A2, RESET

VIL LOW-level input voltage 0.5 - +0.3VDD V

VIH HIGH-level input voltage 0.7VDD -6 V

ILI input leakage current pin at VDD or VSS 1- +1 A

Ciinput capacitance VI=V

SS -25 pF

Pass gate

Ron ON-state resistance multiplexer; VDD = 4.5 V to 5.5 V;

VO=0.4V; I

O=15mA 4924

Vo(mux) multiplexer output voltage Vi(mux) =V

DD =5.0V;

Io(mux) =100 A-3.6- V

Vi(mux) =V

DD = 4.5 V to 5.5 V;

Io(mux) =100 A2.6 - 4.5 V

ILleakage current VI=V

DD or VSS 1- +1 A

Cio input/output capacitance VI=V

SS -35 pF

Product data sheet Rev. 4 — 1 April 2014 16 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

12. Dynamic characteristics

[1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance.

[2] After this period, the first clock pulse is generated.

[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to

bridge the undefined region of the falling edge of SCL.

[4] Cb= total capacitance of one bus line in pF.

[5] Measurements taken with 1 k pull-up resistor and 50 pF load.

Table 9. Dynamic characteristics

Symbol Parameter Conditions Standard-mode

I2C-bus Fast-mode I2C-bus Unit

Min Max Min Max

tPD propagation delay from SDA to SDx,

or SCL to SCx -0.3

[1] -0.3

[1] ns

fSCL SCL clock frequency 0 100 0 40 0 kHz

tBUF bus free time between a STOP and

START condition 4.7 - 1.3 - s

tHD;STA hold time (repeated) START condition [2] 4.0 - 0.6 - s

tLOW LOW period of the SCL clock 4.7 - 1.3 - s

tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s

tSU;STA set-up time for a repeated START

condition 4.7 - 0.6 - s

tSU;STO set-up time for STOP condition 4.0 - 0.6 - s

tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s

tSU;DAT data set-up time 250 - 100 - ns

trrise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns

tffall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns

Cbcapacitive load for each bus line - 400 - 400 pF

tSP pulse width of spikes that must be

suppressed by the input filter - 50 - 50 ns

tVD;DAT data valid time HIGH-to-LOW [5] -1 - 1s

LOW-to-HIGH [5] - 0.6 - 0.6 s

tVD;ACK data valid acknowledge time - 1 - 1 s

RESET

tw(rst)L LOW-level reset time 4 - 4 - ns

trst reset time SDA clear 500 - 500 - ns

trec(rst) reset recovery time 0 - 0 - ns

Product data sheet Rev. 4 — 1 April 2014 17 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Fig 15. Definition of timing on the I2C-bus

BUF

HD;STA

PP S

LOW

HD;DAT

HIGH

SU;DAT

SU;STA

HD;STA

SU;STO

SDA

SCL

002aaa986

0.7 × V

0.3 × V

0.7 × V

0.3 × V

Fig 16. Definitio n of RESET timing

SDA

SCL

002aac314

50 %

70 %

50 % 50 %

trec(rst) tw(rst)L

RESET

START

trst

ACK or read cycle

Product data sheet Rev. 4 — 1 April 2014 18 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

13. Package outline

Fig 17. SO24 package outline (SOT137-1)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZ

ywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

2.65 0.3

0.1 2.45

2.25 0.49

0.36 0.32

0.23 15.6

15.2 7.6

7.4 1.27 10.65

10.00 1.1

1.0 0.9

0.4 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.1

0.4

SOT137-1

detail X

vMA

(A )

0.25

075E05 MS-013

pin 1 index

0.1 0.012

0.004 0.096

0.089 0.019

0.014 0.013

0.009 0.61

0.60 0.30

0.29 0.05

1.4

0.055

0.419

0.394 0.043

0.039 0.035

0.016

0.01

0.25

0.01 0.004

0.043

0.016

0.01

0 5 10 mm

scale

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

99-12-27

03-02-19

Product data sheet Rev. 4 — 1 April 2014 19 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Fig 18. TSSOP24 package outline (SOT355-1)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 7.9

7.7 4.5

4.3 0.65 6.6

6.2 0.4

0.3 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT355-1 MO-153 99-12-27

03-02-19

0.25 0.5

0.2

112

24 13

pin 1 index

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

max.

1.1

Product data sheet Rev. 4 — 1 April 2014 20 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Fig 19. HVQFN24 package outline (SOT616-1)

0.51 0.2

A1Eh

UNIT ye

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 4.1

3.9

2.25

1.95

4.1

3.9 2.25

1.95

2.5

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT616-1 MO-220 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT616-1

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

712

24 19

01-08-08

02-10-22

terminal 1

index area

terminal 1

index area

1/2 e

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 4 — 1 April 2014 21 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesi ve and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 4 — 1 April 2014 22 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 20) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 20.

Table 10. SnPb eutec t ic process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 11. Lead-free process (from J-STD-020D)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 4 — 1 April 2014 23 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

MSL: Moisture Sensitivity Level

Fig 20. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Product data sheet Rev. 4 — 1 April 2014 24 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

15. Soldering: PCB footprints

Fig 21. PCB footprint for SOT137-1 (SO24); reflow soldering

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  

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Product data sheet Rev. 4 — 1 April 2014 25 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Fig 22. PCB footprint for SOT355-1 (TSSOP24); reflow soldering

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Product data sheet Rev. 4 — 1 April 2014 26 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Fig 23. PCB footprint for SOT616-1; reflow soldering

627)RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH

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Product data sheet Rev. 4 — 1 April 2014 27 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

16. Abbreviations

17. Revision history

Table 12. Abbreviations

Acronym Description

CDM Charged Device Model

ESD ElectroStatic Discharge

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LSB Least Significant Bit

PCB Printed-Circuit Board

SMBus System Management Bus

Table 13. Revision history

Document ID Release date Data sheet statu s Change notice Supersedes

PCA9547 v.4 20140401 Product data sheet - PCA9547 v.3

Modifications: •Section 2 “Features and benefits”, 15th bullet item: deleted phrase “200 V MM per JESD22-A115”

•Table 1 “Ordering information”:

–added column “Topside marking” (moved from Table 2)

–Type number PCA9547PW: Topside mark corrected from “PCA9547” to “PCA9547PW” (this is a

correction to documentation only, no change to device)

•Table 2 “Ordering options”:

–added columns “Orderable part number”, “Package”, “Packing method”, “Minimum order quantity”

–deleted column “Topside mark” (moved to Table 1)

•Section 6.4 “Power-on reset”, first paragraph, third sentence: corrected from “VDD must be lowered

below 0.2 V to reset the device” to “VDD must be lowered below 0.2 V for at least 5 s in order to reset

the device”

•Table 5 “Limiting values ”: added limiting valu e “T j(max)”

•Added Section 10 “Thermal characteristics”

•Table 7 “Static characteristics at VDD = 2.3 V to 3.6 V”:

–sub-section “Select inputs A0, A1, A2, RESET”: Max value for VIH corrected from “VDD +0.5V”

to “6 V”

–Table note [2]: inserted phrase “for at least 5 s”

•Table 8 “Static characteristics at VDD = 4.5 V to 5.5 V”:

–sub-section “Select inputs A0, A1, A2, RESET”: Max value for VIH corrected from “VDD +0.5V”

to “6 V”

–Table note [2]: inserted phrase “for at least 5 s”

•Added Section 15 “Soldering: PCB footprints”

PCA9547 v.3 20090710 Product data sheet - PCA9547 v.2

PCA9547 v.2 20060912 Product data sheet - PCA9547 v.1

PCA9547 v.1 20051005 Product data sheet - -

Product data sheet Rev. 4 — 1 April 2014 28 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incident al,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whethe r or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggreg ate and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors product s are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applicat ions where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or cu stomer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by custo mer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and product s using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third p arty

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specif ication for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 4 — 1 April 2014 29 of 30

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is a utomotive qualified,

the product is not suitable for automotive use. It i s neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applicat ions, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y

liability, damages or failed product cl aims resulting fr om customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-En glish (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

I2C-bus — logo is a trademark of NXP Semi conductors N.V.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors PCA9547

8-channel I2C-bus multiplexer with reset

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 1 April 2014

Document identifier: PCA9547

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

6 Functional description . . . . . . . . . . . . . . . . . . . 6

6.1 Device addressing . . . . . . . . . . . . . . . . . . . . . . 6

6.2 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 6

6.2.1 Control register definition . . . . . . . . . . . . . . . . . 6

6.3 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.4 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7

6.5 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8

7 Characteristics of the I2C-bus . . . . . . . . . . . . . 9

7.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.1.1 START and STOP conditions. . . . . . . . . . . . . . 9

7.2 System configuration . . . . . . . . . . . . . . . . . . . 10

7.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10

7.4 Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 11

8 Application design-in inform ation . . . . . . . . . 12

9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13

10 Thermal characteristics . . . . . . . . . . . . . . . . . 13

11 Static characteristics. . . . . . . . . . . . . . . . . . . . 14

12 Dynamic characteristics . . . . . . . . . . . . . . . . . 16

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18

14 Soldering of SMD packages . . . . . . . . . . . . . . 21

14.1 Introduction to soldering . . . . . . . . . . . . . . . . . 21

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 21

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 21

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 22

15 Soldering: PCB footprints. . . . . . . . . . . . . . . . 24

16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 27

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 27

18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28

18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 28

18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

19 Contact information. . . . . . . . . . . . . . . . . . . . . 29

20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30