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FEATURES APPLICATIONS
DESCRIPTION
TLK4201EA
SLLS719 – APRIL 2006
4.25-GBPS CABLE AND PC BOARD EQUALIZER
•1.0625-Gbps, 2.125-Gbps, and 4.25-Gbps•Multirate Operation up to 4.25 Gbps
Fibre Channel Systems•Compensates up to 12 dB Loss at 2.1 GHz
•High-Speed Links in Communication and•Suitable to Receive 4.25 Gbps Data Over up
Data Systemsto 36 Inches (0.91 Meters) of FR4 PC Boards
•Backplane Interconnect•Suitable to Receive 4.25 Gbps Data Over up
•Rack-to-Rack Interconnectto 30 Feet (9.1 Meters) of CX4 Cable
A
•Ultralow Power Consumption
A
A•Input Offset Cancellation
A•High-Input Dynamic Range
A•Output Disable
A
A•Output Polarity Select
A•Selectable Loss-of-Signal (LOS) Detection
A•Selectable Squelch Function
A
•CML Data Outputs•Single 3.3-V Supply•Surface-Mount, Small-Footprint,3-mm × 3-mm, 16-Pin QFN Package
The TLK4201EA is a versatile, high-speed limiting equalizer for applications in digital high-speed links with datarates up to 4.25 Gbps.
This device provides a high-frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fullydifferential output swing for input signals as low as 100 mV
P-P
(at the input of the interconnect line or cable).
The high input signal dynamic range ensures low-jitter output signals even when overdriven with input signalswings as high as 2000 mV
P-P
.
The TLK4201EA includes fixed loss-of-signal (LOS) detection, which can be used to implement a squelchfunction by connecting the LOS output to the adjacent DISABLE input. The LOS function can be disabled bypulling LOSDIS to high level.
The TLK4201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package. It requires a single 3.3-Vsupply.
This very power-efficient equalizer is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
DOUT+
DOUT−
DIN+
DIN−
+
Gain Stage
++ +
COC2 COC1
DISABLE
LOS
VCC
GND
OUTPOL
Bandgap Voltage
Reference and
Bias Current
Generation
Gain Stage Gain Stage
Loss of
Signal Detection
Offset
Cancellation
−
LOSDIS
CML
Output
Buffer
Stage
− − −
B0052-03
Fixed Equalizer
Stage
HIGH-SPEED DATA PATH
LOSS OF SIGNAL DETECTION
BAND-GAP VOLTAGE AND BIAS GENERATION
TLK4201EA
SLLS719 – APRIL 2006
A simplified block diagram of the TLK4201EA is shown in Figure 1 . This compact, low-power, 4.25-Gbpsequalizer consists of a high-speed data path with an offset cancellation circuitry, a loss-of-signal detection block,and a band-gap voltage reference and bias current generation block.
The equalizer requires a single 3.3-V supply voltage. All circuit parts are described in detail as follows.
Figure 1. Simplified Block Diagram of the TLK4201EA
The high-speed data signal with frequency dependent loss is applied to the data path by means of the inputsignal pins DIN+/DIN–. The data path consists of the fixed equalizer input stage with 100- Ωon-chip differentialline termination, three gain stages, which provide the required gain to ensure a limited output signal, and a CMLoutput stage. The equalized and amplified data output signal is available at the output pins DOUT+/DOUT–,which provide 2 × 50- Ωback-termination to VCC. The output stage also includes a data polarity switchingfunction, which is controlled by the OUTPOL input, and a disable function, controlled by the signal applied to theDISABLE input pin. An offset cancellation circuit compensates for inevitable internal offset voltages and thusensures proper operation even for very small input data signals.
The low-frequency cutoff is as low as 10 kHz with the built-in filter capacitor. For applications which require evenlower cutoff frequencies, an additional external filter capacitor can be connected to the COC1/COC2 pins.
The output signal of the second gain stage is monitored by the loss-of-signal detection circuitry. In this block, theinput signal is compared to a fixed threshold. If the low-frequency components of the input signal fall below thisthreshold, a loss of signal is indicated at the LOS pin.
A squelch function can be easily implemented by connecting the LOS output to the adjacent DISABLE input.This measure avoids chattering of the output when no input signal is present. The LOS function can be disabledby pulling LOSDIS to high level.
The TLK4201EA equalizer is supplied by a single 3.3V ±10% supply voltage connected to the VCC pins. Thisvoltage is referred to ground (GND).
An on-chip band-gap voltage circuit generates a supply-voltage-independent reference from which all internallyrequired voltages and bias currents are derived.
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DEVICE INFORMATION
GND
COC2
COC1
NC
1
2
3
4
VCC
DIN+
DIN−
VCC
RGT PACKAGE
(TOP VIEW)
12
11
10
9
16
VCC
DOUT+
DOUT−
OUTPOL
15 14 13
5 6 7 8
LOSDIS
DISABLE
LOS
GND
P0019-03
EP
TLK4201EA
SLLS719 – APRIL 2006
The TLK4201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN Package.
This quad package has a lead pitch of 0.5 mm. The pinout is shown in Figure 2 .
Figure 2. Pinout of TLK4201EA
TERMINAL FUNCTIONS
TERMINAL
TYPE DESCRIPTIONNAME NO.
VCC 1, 4, 12 Supply 3.3V ± 10% supply voltage.DIN+ 2 Analog In Noninverted data input. On-chip 100- Ωterminated to DIN–.DIN– 3 Analog In Inverted data input. On-chip 100- Ωterminated to DIN+.LOS disable input. High level disables LOS circuitry and sets LOS pin to low level. Low levelLOSDIS 5 CMOS In enables LOS function. This pin has approximately 825-k Ωinternal electronic pulldownresistor.DISABLE 6 CMOS In Disables CML output stage when set to high level. 400-k Ωon-chip pulldown resistor.LOS 7 CMOS Out High level indicates that the input signal amplitude is below the fixed threshold level.GND 8, 16 Supply Circuit groundOutput data signal polarity select with approximately 715-k Ωinternal electronic pullupresistor:OUTPOL 9 CMOS In
Setting to high-level or leaving pin open selects normal polarity. Low-level selects invertedpolarity.DOUT– 10 CML Out Inverted data output. On-chip 50- Ωback-terminated to VCC.DOUT+ 11 CML Out Noninverted data output. On-chip 50- Ωback-terminated to VCC.NC 13 — Not connected
Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor betweenCOC1 14 Analog this pin and COC2 (pin 15).To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor betweenCOC2 15 Analog this pin and COC1 (pin 14).To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).EP EP Exposed die pad (EP) must be grounded.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
TLK4201EA
SLLS719 – APRIL 2006
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
(1)
UNIT
V
CC
Supply voltage at VCC
(2)
–0.3 to 4 VV
DIN+
, V
DIN–
Input voltage at DIN+, DIN–
(2)
0.5 to 4 VV
LOSDIS
, V
DISABLE
, Input voltage at LOSDIS, DISABLE, OUTPOL, COC1, COC2
(2)
–0.3 to 4 VV
OUTPOL
, V
COC1
,V
COC2
V
COC,DIFF
Differential input voltage between COC1 and COC2 ±1 VV
DIN,DIFF
Differential input voltage between DIN+ and DIN– ±2.5 vI
DIN+
, I
DIN–
Continuous input current at input pins DIN+ and DIN– –25 to 25 mAESD ESD ratings at all pins, human body model (HBM) 2.5 kVT
J,max
Maximum junction temperature 125 °CT
stg
Storage temperature range –65 to 85 °CT
A
Free-air operating temperature –40 to 85 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values are with respect to network ground terminal.
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage, CMOS 2.1 VV
IL
Low-level input voltage, CMOS 0.6 VT
A
Free-air operating temperature –40 85 °C
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VLOSDIS = low, DISABLE = low,I
CC
Supply current 32 38 mAincluding CML output currentR
I
Input resistance, data Differential 100 ΩR
O
Output resistance, data Single-ended to V
CC
50 ΩV
OH
High-level output voltage, LOS I
source
= 30 µA 2.4 VV
OL
Low-level output voltage, LOS I
sink
= 1 mA 0.4 V
(1) Typical values are measured at V
CC
= 3.3 V and T
A
= 25°C
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AC ELECTRICAL CHARACTERISTICS
TLK4201EA
SLLS719 – APRIL 2006
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
C
OC
= open 10 50Low frequency –3dB bandwidth kHzC
OC
= 0.1 µF 0.8Maximum data rate 4.25 GbpsV
IN,MIN
Data input voltage sensitivity
(2)
BER < 10
-12
, input signal applied 100 120 mV
P-Pover 36 inches of 7-mil-wide striplineinterconnect on standard FR4,voltage at the input of theinterconnect line, K28.5 pattern at4.25 Gbps.V
IN,MAX
Data input voltage overload Voltage at the interconnect input 2000 mV
P-P
High-frequency boost f = 2.1 GHz 9 12 16 dBDISABLE = high 0.25 10Data differential output voltageV
OD
mV
P-Pswing
DISABLE = low 600 780 1200No board or cable 2024 inches of 257-mil-widef = 4.25 GHz,
stripline onK28.5 pattern,
standard FR4V
IN
= 200 mV
P-PDJ Deterministic jitter (differential 36 inches of 20 ps
P-Pvoltage at the 7-mil-wideinterconnect stripline oninput) standard FR430 feet CX4 cable 2050 feet CX4 cable 35RJ Random jitter V
IN
= 200 mV
P-P
(differential voltage 4 ps
RMSat the interconnect input)Latency From DIN+/DIN– to DOUT+/DOUT– 250 pst
r
Output rise time 20% to 80%, 4.25 Gbps, no board or 55 85 pscablet
f
Output fall time 20% to 80%, 4.25 Gbps, no board or 55 85 pscablet
DIS
Disable response time 20 nsInput signal applied over 36 inches of7-mil-wide stripline interconnect onV
AS
LOS assert threshold voltage standard FR4, voltage at the input of 40 80 mV
P-Pthe interconnect line, K28.5 pattern at4.25 Gbps.
(3)
Input signal applied over 36 inches of7-mil-wide stripline interconnect onV
DAS
LOS de-assert threshold voltage standard FR4, voltage at the input of 130 200 mV
P-Pthe interconnect line, K28.5 pattern at4.25 Gbps.
(3)
K28.5 at 4.25 Gbps over 36 inches ofLOS hysteresis 3 4.5 dB7-mil-wide stripline on standard FR4K28.5 at 4.25 Gbps over 36 inches oft
AS/DAS
LOS assert/de-assert time 2 100 µs7-mil-wide stripline on standard FR4
(1) Typical values are measured at V
CC
= 3.3 V and T
A
= 25°C.(2) The given differential input signal swing is measured at the input of the interconnect. The high-frequency components of the signal at theoutput of the interconnect (connected to input pins DIN+/DIN– of the TLK4201EA) may be attenuated by as much as 12 dB at 2.1 GHzdepending on the interconnect length and attenuation characteristics of the interconnect.(3) Depending on the interconnect line length and performance, the bit pattern, and the data rate, the assert and de-assert thresholdvoltage levels vary. For more information, see the Typical Characteristics section.
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TYPICAL CHARACTERISTICS
DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
36 Inches x 7 mil Stripline
G001
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 1 ns/Div
36 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 100 ps/Div
48 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 1 ns/Div
48 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 100 ps/Div
TLK4201EA
SLLS719 – APRIL 2006
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25°C, and V
IN
= 200 mV
P-P
(unless otherwise noted)
4.25 GBPS USING A PRBS 2
31
– 1 PATTERN
Figure 3. Equalizer Input And Output Signals With Different Interconnect Lines at 4.25 GHz
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DIFFERENTIAL EQUALIZER INPUT SIGNAL (TOP) AND OUTPUT SIGNAL (BOTTOM) AT
36 Inches x 7 mil Stripline
G002
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 1 ns/Div
36 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 100 ps/Div
48 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 1 ns/Div
48 Inches x 7 mil Stripline
Input Voltage
75 mV/Div
Output Voltage
250 mV/Div
Time − 100 ps/Div
TLK4201EA
SLLS719 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25°C, and V
IN
= 200 mV
P-P
(unless otherwise noted)
2.125 GBPS USING A PRBS 2
31
– 1 PATTERN
Figure 4. Equalizer Input And Output Signals With Different Interconnect Lines at 2.125 GHz
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Stripline Length − Inches
0
5
10
15
20
25
0 5 10 15 20 25 30 35 40 45 50
Deterministic Jitter Including PWD − psP−P
G003
4.25 Gbps
K28.5 Pattern
VID − Differential Input Voltage − VP−P
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.5 1.0 1.5 2.0
Random Jitter − psRMS
G004
No Interconnect Line Loss
VID − Differential Input Voltage − VP−P
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0
Deterministic Jitter Including PWD − psP−P
G005
No Interconnect Line Loss
4.25 Gbps
K28.5 Pattern
VID − Differential Input Voltage − VP−P
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0
Deterministic Jitter Including PWD − psP−P
G006
36−Inch 7−mil Stripline
4.25 Gbps
K28.5 Pattern
TLK4201EA
SLLS719 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25°C, and V
IN
= 200 mV
P-P
(unless otherwise noted)
DETERMINISTIC JITTER RANDOM JITTERvs vsSTRIPLINE LENGTH INPUT VOLTAGE
Figure 5. Figure 6.
DETERMINISTIC JITTER DETERMINISTIC JITTERvs vsINPUT VOLTAGE INPUT VOLTAGE
Figure 7. Figure 8.
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f − Frequency − GHz
−35
−30
−25
−20
−15
−10
−5
0
0123456
Differential S11 − dB
G007
f − Frequency − GHz
−35
−30
−25
−20
−15
−10
−5
0
0123456
Differential S22 − dB
G008
Data Rate − Gbps
0
20
40
60
80
100
120
140
160
180
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
LOS Assert Threshold Voltage − mVP−P
G009
K28.5 Pattern
48 Inch
36 Inch 24 Inch
12 Inch
No line
Data Rate − Gbps
0
20
40
60
80
100
120
140
160
180
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
LOS De-assert Threshold Voltage − mVP−P
G010
K28.5 Pattern
48 Inch 36 Inch
24 Inch 12 Inch No line
TLK4201EA
SLLS719 – APRIL 2006
TYPICAL CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25°C, and V
IN
= 200 mV
P-P
(unless otherwise noted)
DIFFERENTIAL INPUT RETURN LOSS DIFFERENTIAL OUTPUT RETURN LOSSvs vsFREQUENCY FREQUENCY
Figure 9. Figure 10.
LOS ASSERT THRESHOLD VOLTAGE LOS DE-ASSERT THRESHOLD VOLTAGEvs vsDATA RATE (K28.5 PATTERN) DATA RATE (K28.5 PATTERN)
Figure 11. Figure 12.
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APPLICATION INFORMATION
VCC
DIN+
DIN−
LOSDIS
DOUT−
DOUT+
GND
DIN+
DIN− DOUT−
DOUT+
GND
VCC
OUTPOL
VCC
VCC
NC
LOS
DISABLE
TLK4201EA
16-Pin QFN
COC2
COC1
OUTPOL
LOSDIS
COC
Optional
C1
C2
C3
C4
S0072-03
0 Inch to 36 Inches
Stripline on FR4
DISABLE LOS
Optional Connection
for Squelch Function
f − Frequency − GHz
−60
−55
−50
−45
−40
−35
−30
−25
−20
−15
−10
−5
0
0123456
Differential Stripline Attenuation − dB
G011
12” Stripline
24” Stripline
36” Stripline
48” Stripline
TLK4201EA
SLLS719 – APRIL 2006
Figure 13 shows the TLK4201EA connected with an ac-coupled interface to the data signal source via a striplineinterconnect line. The output load is ac-coupled as well.
The ac-coupling capacitors C
1
through C
4
in the input and output data signal lines are the only required externalcomponents. In addition, if a very low cutoff frequency is required, as an option, an external filter capacitor C
OCmay be used.
Figure 13. Basic Application Circuit with AC-Coupled I/Os
Figure 14. Attenuation Characteristics of Stripline Interconnect Lines
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLK4201EARGTR ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLK4201EARGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLK4201EARGTT ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLK4201EARGTTG4 ACTIVE QFN RGT 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLK4201EARGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TLK4201EARGTT QFN RGT 16 250 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLK4201EARGTR QFN RGT 16 3000 338.1 338.1 20.6
TLK4201EARGTT QFN RGT 16 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Feb-2012
Pack Materials-Page 2
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