REJ03C0109-0201 Rev.2.01 Page 1 of 11
Jun 16, 2010
Datasheet
R1RW0416DI Series
Wide Temperature Range Version
4M High Speed SRAM (256-kword × 16-bit)
Description
The R1RW0416DI is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access
time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. The R1RW0416DI is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin
plastic TSOPII for high density surface mounting.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 10ns/12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 145/130 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current: 5 mA (max)
• Center V
CC
and V
SS
type pin out
• Temperature range: −40 to +85°C
Ordering Information
Type No. Access time Package
R1RW0416DGE-0PI 10ns
R1RW0416DGE-2PI 12 ns
400-mil 44-pin plastic SOJ (44P0K)
R1RW0416DSB-0PI 10 ns
R1RW0416DSB-2PI 12 ns
400-mil 44-pin plastic TSOPII (44P3W-H)
REJ03C0109-0201
Rev.2.01
Jun 16, 2010
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 2 of 11
Jun 16, 2010
Pin Arrangement
Pin Description
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS# Chip select
OE# Output enable
WE# Write enable
UB# Upper byte select
LB# Lower byte select
V
CC
Power supply
V
SS
Ground
NC No connection
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 3 of 11
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Block Diagram
R1RW0416DI Series
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Operation Table
CS#
OE#
WE#
LB#
UB#
Mode V
CC
current
I/O1−
−−
−I/O8 I/O9−
−−
−I/O16
Ref. Cycle
H × × × × Standby I
SB
, I
SB1
High-Z High-Z
L H H × × Output disable I
CC
High-Z High-Z
L L H L L Read I
CC
Output Output Read cycle
L L H L H Lower byte read
I
CC
Output High-Z Read cycle
L L H H L Upper byte read
I
CC
High-Z Output Read cycle
L L H H H I
CC
High-Z High-Z
L × L L L Write I
CC
Input Input Write cycle
L × L L H Lower byte write
I
CC
Input High-Z Write cycle
L × L H L Upper byte write
I
CC
High-Z Input Write cycle
L × L H H I
CC
High-Z High-Z
Note: H: V
IH
, L: V
IL
, ×: V
IH
or V
IL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to V
SS
V
CC
−0.5 to +4.6 V
Voltage on any pin relative to V
SS
V
T
−0.5*
1
to V
CC
+ 0.5*
2
V
Power dissipation P
T
1.0 W
Operating temperature Topr −40 to +85 °C
Storage temperature Tstg −55 to +125 °C
Storage temperature under bias Tbias −40 to +85 °C
Notes: 1. V
T
(min) = −2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
T
(max) = V
CC
+ 2.0 V for pulse width (over shoot) ≤ 6 ns
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 5 of 11
Jun 16, 2010
Recommended DC Operating Conditions
(Ta = −40 to +85°C)
Parameter Symbol Min Typ Max Unit
Supply voltage V
CC
*
3
3.0 3.3 3.6 V
V
SS
*
4
0 0 0 V
Input voltage V
IH
2.0 V
CC
+ 0.5*
2
V
V
IL
−0.5*
1
0.8 V
Notes: 1. V
IL
(min) = −2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
IH
(max) = V
CC
+ 2.0 V for pulse width (over shoot) ≤ 6 ns
3. The supply voltage with all V
CC
pins must be on the same level.
4. The supply voltage with all V
SS
pins must be on the same level.
DC Characteristics
(Ta = −40 to +85°C, V
CC
= 3.3 V ± 0.3 V, V
SS
= 0 V)
Parameter Symbol
Min Max Unit Test conditions
Input leakage current |I
LI
| 2 µA V
IN
= V
SS
to V
CC
Output leakage current |I
LO
| 2 µA V
IN
= V
SS
to V
CC
Operating power supply current I
CC
130 mA Min cycle
CS# = V
IL
, I
OUT
= 0 mA
Other inputs = V
IH
/V
IL
Standby power supply current I
SB
40 mA Min cycle, CS# = V
IH
,
Other inputs = V
IH
/V
IL
I
SB1
5 mA f = 0 MHz
V
CC
≥ CS# ≥ V
CC
− 0.2 V,
(1) 0 V ≤ V
IN
≤ 0.2 V or
(2) V
CC
≥ V
IN
≥ V
CC
− 0.2 V
Output voltage V
OL
0.4 V I
OL
= 8 mA
V
OH
2.4 V I
OH
= −4 mA
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Max Unit Test conditions
Input capacitance*
1
C
IN
6 pF V
IN
= 0 V
Input/output capacitance*
1
C
I/O
8 pF V
I/O
= 0 V
Note: 1. This parameter is sampled and not 100% tested.
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 6 of 11
Jun 16, 2010
AC Characteristics
(Ta = −40 to +85°C, V
CC
= 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
Read Cycle
R1RW0416DI
10ns Version 12ns Version
Parameter Symbol
Min Max Min Max Unit Notes
Read cycle time t
RC
10 12 ns
Address access time t
AA
10 12 ns
Chip select access time t
ACS
10 12 ns
Output enable to output valid t
OE
5 6 ns
Byte select to output valid t
BA
5 6 ns
Output hold from address change t
OH
3 3 ns
Chip select to output in low-Z t
CLZ
3 3 ns 1
Output enable to output in low-Z t
OLZ
0 0 ns 1
Byte select to output in low-Z t
BLZ
0 0 ns 1
Chip deselect to output in high-Z t
CHZ
5 6 ns 1
Output disable to output in high-Z t
OHZ
5 6 ns 1
Byte deselect to output in high-Z t
BHZ
5 6 ns 1
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 7 of 11
Jun 16, 2010
Write Cycle
R1RW0416DI
10ns Version 12ns Version
Parameter Symbol
Min Max Min Max Unit Notes
Write cycle time t
WC
10 12 ns
Address valid to end of write t
AW
7 8 ns
Chip select to end of write t
CW
7 8 ns 8
Write pulse width t
WP
7 8 ns 7
Byte select to end of write t
BW
7 8 ns
Address setup time t
AS
0 0 ns 5
Write recovery time t
WR
0 0 ns 6
Data to write time overlap t
DW
5 6 ns
Data hold from write time t
DH
0 0 ns
Write disable to output in low-Z t
OW
3 3 ns 1
Output disable to output in high-Z t
OHZ
5 6 ns 1
Write enable to output in high-Z t
WHZ
5 6 ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is sampled and
not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
5. t
AS
is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going low.
6. t
WR
is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (t
WP
). A write begins
at the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write
ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high.
8. t
CW
is measured from the later of CS# going low to the end of write.
R1RW0416DI Series
REJ03C0109-0201 Rev.2.01 Page 8 of 11
Jun 16, 2010
Timing Waveforms
Read Timing Waveform (1) (WE# = V
IH
)
Read Timing Waveform (2) (WE# = V
IH
, LB# = V
IL
, UB# = V
IL
)
R1RW0416DI Series
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Write Timing Waveform (1) (WE# Controlled)
R1RW0416DI Series
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Write Timing Waveform (2) (CS# Controlled)
R1RW0416DI Series
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Write Timing Waveform (3) (LB#, UB# Controlled, OE# = V
IH
)
All trademarks and registered trademarks are the property of their respective owners.
C - 1
Revision History R1RW0416DI Series data sheet
Description
Rev. Date Page Summary
0.01 Sep. 30, 2003 − Initial issue
1.00 Mar. 12, 2004 −- Deletion of Preliminary
2.00 May. 01, 2009 −
P1
P5
P6/P7
Addition of access grade 10ns version.
The product lineup :R1RW0416DSB-0PI/DGE-0PI is added.
Operating power supply current of 10ns cycle version is described to the
DC characteristic.
The timing standard of 10ns version is described at the read cycle
The timing standard of 10ns version is described at the write cycle
2.01 Jun. 16, 2010 − Change the format, ‘Renesas Electronics Corporation’,
All documents should contain the following section break and paragraph as the last item. The footers of this document
refer to the paragraph in order to reference the last page of the document.
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