128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. History Draft Date 1.0 First Version Release Feb. 2005 1.1 Changed tOH(Only Symbol `H'): 2.5ns -> 2.7ns Apr. 2005 Remark This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Apr. 2005 1 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series DESCRIPTION The Hynix HY5V26E(L)F(P) series is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY5V26E(L)F(P) series is organized as 4banks of 2,097,152 x 16. HY5V26E(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a '2N' rule) FEATURES * Programmable Burst Length and Burst Type * Voltage: VDD and VDDQ 3.3V supply voltage * All device pins are compatible with LVTTL interface - 1, 2, 4, 8 or full page for Sequential Burst * 54 Ball FBGA (Lead or Lead Free Package) - 1, 2, 4 or 8 for Interleave Burst * All inputs and outputs referenced to positive edge of system clock * Data mask function by UDQM, LDQM * Internal four banks operation * Auto refresh and self refresh * 4096 Refresh cycles / 64ms * Programmable CAS Latency; 2, 3 Clocks * Burst Read Single Write operation ORDERING INFORMATION Part No. Clock Frequency HY5V26E(L)F(P)-5 200MHz HY5V26E(L)F(P)-6 166MHz HY5V26E(L)F(P)-7 143MHz HY5V26E(L)F(P)-H 133MHz Organization Interface Package 4Banks x 2Mbits x16 LVTTL 54 Ball FBGA Note: 1. HY5V26EF Series: Normal power, Leaded. 2. HY5V26ELF Series: Low power, Leaded. 3. HY5V26EFP Series: Normal power, Lead Free. 4. HY5V26ELFP Series: Low power, Lead Free. 5. HY5V26ESF(P) Series: Super Low power; Contact Hynix Office for product availability. Rev. 1.1 / Apr. 2005 2 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series BALL CONFIGURATION 9 8 3 7 2 1 A B C 54 Ball D FBGA E 0.8mm Ball Pitch F G H J <Bottom View> 1 2 3 7 8 9 VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 NC VSS E VDD LDQM DQ7 UDQM CLK CKE F /CAS /RAS /WE NC A11 A9 G BA0 BA1 /CS A8 A7 A6 H A0 A1 A10 VSS A5 A4 J A3 A2 VDD < Top View > Rev. 1.1 / Apr. 2005 3 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series FUNCTIONAL BLOCK DIAGRAM 2Mbit x 4banks x 16 I/O Synchronous DRAM Internal Row Counter Self refresh logic & timer 2Mx16 BANK 3 CLK CAS Column Active U/LDQM A0 Address Buffers BA1 DQ0 DQ15 Y-Decoder Column Add Counter Bank Select A11 Memory Cell Array Column Pre Decoder WE A1 2Mx16 BANK 0 I/O Buffer & Logic Refresh 2Mx16 BANK 1 Sense AMP & I/O Gate State Machine RAS 2Mx16 BANK 2 X-Decoder X-Decoder X-Decoder X-Decoder CKE CS Row Pre Decoder Row Active Address Register Mode Register Burst Counter CAS Latency Data Out Control Pipe Line Control BA0 Rev. 1.1 / Apr. 2005 4 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A11 A10 A9 A8 A7 0 0 0 0 OP Code 0 0 A6 A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length OP Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency Burst Type A3 Burst Type 0 Sequential 1 Interleave Burst Length A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 0 1 0 1 1 0 1 0 Burst Length A2 A1 A0 1 0 0 0 2 0 0 1 3 0 1 0 4 4 0 Reserved 0 1 1 8 8 1 Reserved 1 0 0 Reserved Reserved Reserved A3 = 0 A3=1 0 1 1 1 2 2 1 1 0 Reserved 1 0 1 Reserved 1 1 1 Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Rev. 1.1 / Apr. 2005 5 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series ABSOLUTE MAXIMUM RATING Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 oC Storage Temperature TSTG -55 ~ 125 oC Voltage on Any Pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD relative to VSS VDD, VDDQ -1.0 ~ 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD 1 TSOLDER 260 / 10 Soldering Temperature / Time W o C / Sec DC OPERATING CONDITION (TA = 0oC to 70oC) Parameter Power Supply Voltage Symbol Min. Typ Max Unit Note VDD, VDDQ 3.0 3.3 3.6 V 1 Input High Voltage VIH 2.0 3.0 VDDQ + 0.3 V 1, 2 Input Low Voltage VIL -0.3 - 0.8 V 1, 3 Note: 1. All voltages are referenced to VSS = 0V 2. VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration. 3. VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration AC OPERATING TEST CONDITION (TA = 0oC to 70oC, VDD=3.30.3V, VSS=0V) Parameter Symbol Value VIH / VIL 2.4 / 0.4 V Vtrip 1.4 V Input Rise / Fall Time tR / tF 1 ns Output Timing Measurement Reference Level Voltage Voutref 1.4 V CL 50 pF AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement Unit Note 1 Note: 1. Vtt = 1.4V Vtt = 1.4V RT = 50 RT = 500 Output Output Z0 = 50 50pF 50pF DC Output Load Circuit Rev. 1.1 / Apr. 2005 AC Output Load Circuit 6 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series CAPACITANCE (TA = 0oC to 70oC, f=1MHz, VDD=3.3V) Parameter Pin Symbol Min Max Unit CLK CI1 2.0 4.0 pF Input capacitance A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS, WE, LDQM, UDQM CI2 2.0 4.0 pF Data input / output capacitance DQ0 ~ DQ15 CI/O 3.0 5.5 pF DC CHARACTERISTICS I (TA = 0oC to 70oC) Parameter Symbol Min Max Unit Note Input Leakage Current ILI -1 1 uA 1 Output Leakage Current ILO -1 1 uA 2 Output High Voltage VOH 2.4 - V IOH = -2mA Output Low Voltage VOL - 0.4 V IOL = +2mA Note: 1. VIN = 0 to 3.3V, All other balls are not tested under VIN =0V 2. DOUT is disabled, VOUT=0 to 3.6 Rev. 1.1 / Apr. 2005 7 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series DC CHARACTERISTICS II (TA = 0oC to 70oC) Parameter Symbol Speed Test Condition 5 6 7 H 120 110 100 100 Unit Note Operating Current IDD1 Burst length=1, One bank active tRC tRC(min), IOL=0mA Precharge Standby Current in Power Down Mode IDD2P CKE VIL(max), tCK = 15ns 2 mA IDD2PS CKE VIL(max), tCK = 2 mA IDD2N CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V 18 IDD2NS CKE VIH(min), tCK = Input signals are stable. 15 IDD3P CKE VIL(max), tCK = 15ns 5 IDD3PS CKE VIL(max), tCK = 5 IDD3N CKE VIH(min), CS VIH(min), tCK = 15ns Input signals are changed one time during 2clks. All other pins VDD-0.2V or 0.2V 40 IDD3NS CKE VIH(min), tCK = Input signals are stable. 35 Burst Mode Operating Current IDD4 tCK tCK(min), IOL=0mA All banks active 120 110 100 100 mA 1 Auto Refresh Current IDD5 tRC tRC(min), All banks active 210 200 190 190 mA 2 Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Self Refresh Current IDD6 CKE 0.2V mA 1 mA mA mA Normal 2 mA Low power 800 uA 3 Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open 2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3. HY5V26EF(P) Series: Normal Power HY5V26ELF(P) Series: Low Power Rev. 1.1 / Apr. 2005 8 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series AC CHARACTERISTICS I (AC operating conditions unless otherwise noted) Symbol Parameter 5 6 7 Min Max Min Max Min 7.0 H Max Min Max Unit Note CL = 3 tCK3 5.0 CL = 2 tCK2 10 Clock High Pulse Width tCHW 1.75 - 2.0 - 2.0 - 2.5 - ns 1 Clock Low Pulse Width tCLW 1.75 - 2.0 - 2.0 - 2.5 - ns 1 CL = 3 tAC3 - 4.5 - 5.4 - 5.4 - 5.4 ns CL = 2 tAC2 - 6.0 - 6.0 - 6.0 - 6.0 ns Data-out Hold Time tOH 2.0 - 2.0 - 2.5 - 2.7 - ns Data-Input Setup Time tDS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Data-Input Hold Time tDH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 Address Setup Time tAS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Address Hold Time tAH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CKE Setup Time tCKS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 CKE Hold Time tCKH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 Command Setup Time tCS 1.5 - 1.5 - 1.5 - 1.5 - ns 1 Command Hold Time tCH 0.8 - 0.8 - 0.8 - 0.8 - ns 1 CLK to Data Output in Low-Z Time tOLZ 1.0 - 1.0 - 1.5 - 1.5 - ns System Clock Cycle Time Access Time From Clock CLK to Data Output in High-Z Time 1000 6.0 10 1000 10 1000 7.5 10 1000 ns ns CL = 3 tOHZ3 - 4.5 - 5.4 - 5.4 - 5.4 ns CL = 2 tOHZ2 - 6.0 - 6.0 - 6.0 - 6.0 ns 2 Note: 1. Assume tR / tF (input rise and fall time) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter. 2. Access time to be measured with input signals of 1V/ns edge rate, from 0.8V to 0.2V. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter. Rev. 1.1 / Apr. 2005 9 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series AC CHARACTERISTICS II (AC operating conditions unless otherwise noted) Parameter Symbol 5 6 7 H Min Max Min Max Min Max Min Max Uni t RAS Cycle Time Operation tRC 55 - 60 - 63 - 63 - ns RAS Cycle Time Auto Refresh tRRC 55 - 60 - 63 - 63 - ns RAS to CAS Delay tRCD 15 - 18 - 20 - 20 - ns RAS Active Time tRAS 38.7 100K 42 100K 42 100K 42 120 K ns RAS Precharge Time tRP 15 - 18 - 20 - 20 - ns RAS to RAS Bank Active Delay tRRD 10 - 12 - 14 - 15 - ns CAS to CAS Delay tCCD 1 - 1 - 1 - 1 - CLK Write Command to Data-In Delay tWTL 0 - 0 - 0 - 0 - CLK Data-in to Precharge Command tDPL 2 - 2 - 2 - 2 - CLK Data-In to Active Command tDAL DQM to Data-Out Hi-Z tDQZ 2 - 2 - 2 - 2 - CLK DQM to Data-In Mask tDQM 0 - 0 - 0 - 0 - CLK MRS to New Command tMRD 2 - 2 - 2 - 2 - CLK Precharge to Data Output High-Z CL = 3 tPROZ3 3 - 3 - 3 - 3 - CLK CL = 2 tPROZ2 2 - 2 - 2 - 2 - CLK Power Down Exit Time tDPE 1 - 1 - 1 - 1 - CLK Self Refresh Exit Time tSRE 1 - 1 - 1 - 1 - CLK Refresh Time tREF - 64 - 64 - 64 - 64 ms Not e tDPL + tRP 1 Note: 1. A new command can be given tRRC after self refresh exit. Rev. 1.1 / Apr. 2005 10 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series COMMAND TRUTH TABLE Command CKEn-1 CKEn CS RAS CAS WE DQM Mode Register Set H X L L L L X OP code No Operation H X H X X X L H H H X X Bank Active H X L L H H X H X L H L H X CA H X L H L L X CA H X L L H L X X Burst Stop H X L H H L X X DQM H V X Auto Refresh H H L L L H X X Burst-Read-Single-WRITE H X L L L L X A9 ball High (Other balls OP code) Entry H L L L L H X Exit L H H X X X L H H H Entry H L H X X X L H H H H X X X L H H H H X X X L V V V Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Self Refresh1 X Precharge power down Clock Suspend Exit L H Entry H L Exit L H Rev. 1.1 / Apr. 2005 X X ADDR A10/AP BA RA Note V L H L H V V H X L V MRS Mode X X X X X X X 11 Synchronous DRAM Memory 128Mbit (8Mx16bit) HY5V26E(L)F(P) Series PACKAGE INFORMATION 54 Ball FBGA 8.0mm x 8.0mm Unit [mm] 8.0 6.40 BSC 0.80(Typ) 0.8 A1 INDEX MARK 0.80(Typ) 0.450 0.05 View 3.20 0.05 8.00 6.40 Bottom 0.340 0.05 4.00 0.05 1.20 max Rev. 1.1 / Apr. 2005 12