LTC2171CUKG-14#PBF - LINEAR TECHNOLOGY

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Typical applicaTion

DescripTion

14-Bit, 65Msps/40Msps/

25Msps Low Power Quad ADCs

The LTC

2172-14/LTC2171-14/LTC2170-14 are 4-channel,

simultaneous sampling 14-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals. They

are perfect for demanding communications applications

with AC performance that includes 73.7dB SNR and 90dB

spurious free dynamic range (SFDR). An ultralow jitter of

0.15psRMS allows undersampling of IF frequencies with

excellent noise performance.

DC specifications include ±1LSB INL (typ), ±0.3LSB DNL

(typ) and no missing codes over temperature. The transi-

tion noise is a low 1.2LSBRMS.

The digital outputs are serial LVDS to minimize the num-

ber of data lines. Each channel outputs two bits at a time

(2-lane mode) or one bit at a time (1-lane mode). The LVDS

drivers have optional internal termination and adjustable

output levels to ensure clean signal integrity.

The ENC+ and ENC– inputs may be driven differentially

or single-ended with a sine wave, PECL, LVDS, TTL or

CMOS inputs. An internal clock duty cycle stabilizer al-

lows high performance at full speed for a wide range of

clock duty cycles.

LTC2172-14, 65Msps,

2-Tone FFT, fIN = 70MHz and 75MHz

FeaTures

applicaTions

n 4-Channel Simultaneous Sampling ADC

n 73.7dB SNR

n 90dB SFDR

n Low Power: 311mW/202mW/162mW Total,

78mW/51mW/41mW per Channel

n Single 1.8V Supply

n Serial LVDS Outputs: One or Tw o Bits per Channel

n Selectable Input Ranges: 1VP-P to 2VP-P

n 800MHz Full Power Bandwidth Sample-and-Hold

n Shutdown and Nap Modes

n Serial SPI Port for Configuration

n Pin-Compatible 14-Bit and 12-Bit Versions

n 52-Pin (7mm × 8mm) QFN Package

n Communications

n Cellular Base Stations

n Software Defined Radios

n Portable Medical Imaging

n Multichannel Data Acquisition

n Nondestructive Testing

L, LT, LT C, LT M , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

DATA

SERIALIZER

ENCODE

INPUT

SERIALIZED

LVDS

OUTPUTS

1.8V

VDD

1.8V

OVDD

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

DATA

CLOCK

OUT

FRAME

OGND

GND

217214 TA01

S/H

CHANNEL 1

ANALOG

INPUT

14-BIT

ADC CORE

S/H

CHANNEL 2

ANALOG

INPUT

14-BIT

ADC CORE

S/H

CHANNEL 3

ANALOG

INPUT

14-BIT

ADC CORE

S/H

CHANNEL 4

ANALOG

INPUT

14-BIT

ADC CORE

PLL

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

217214 TA01b

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

pin conFiguraTionabsoluTe MaxiMuM raTings

Supply Voltages

VDD , OVDD............................................... –0.3V to 2V

Analog Input Voltage (AIN+, AIN–,

PAR/SER, SENSE) (Note 3) .......... –0.3V to (VDD + 0.2V)

Digital Input Voltage (ENC+, ENC–, CS,

SDI, SCK) (Note 4) .................................... –0.3V to 3.9V

SDO (Note 4) ............................................. –0.3V to 3.9V

Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)

Operating Temperature Range

LTC2172C, LTC2171C, LTC2170C ............. 0°C to 70°C

LTC2172I, LTC2171I, LTC2170I ............–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1 and 2)

1615 17 18 19

TOP VIEW

GND

UKG PACKAGE

52-LEAD (7mm × 8mm) PLASTIC QFN

20 21 22 23 24 25 26

5152 50 49 48 47 46 45 44 43 42 41

1AIN1+

AIN1–

VCM12

AIN2+

AIN2–

REFH

REFL

AIN3+

AIN3–

VCM34

AIN4+

AIN4–

OUT2A+

OUT2A–

OUT2B+

OUT2B–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT3A+

OUT3A–

OUT3B+

OUT3B–

VDD

SENSE

GND

VREF

PAR/SER

SDO

GND

OUT1A+

OUT1A–

OUT1B+

OUT1B–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT4B–

OUT4B+

OUT4A–

OUT4A+

TJMAX = 150°C,

JA = 28°C/W

EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2172CUKG-14#PBF LTC2172CUKG-14#TRPBF LTC2172UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2172IUKG-14#PBF LTC2172IUKG-14#TRPBF LTC2172UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2171CUKG-14#PBF LTC2171CUKG-14#TRPBF LTC2171UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2171IUKG-14#PBF LTC2171IUKG-14#TRPBF LTC2171UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

LTC2170CUKG-14#PBF LTC2170CUKG-14#TRPBF LTC2170UKG-14 52-Lead (7mm × 8mm) Plastic QFN 0°C to 70°C

LTC2170IUKG-14#PBF LTC2170IUKG-14#TRPBF LTC2170UKG-14 52-Lead (7mm × 8mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

converTer characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

PARAMETER CONDITIONS

LTC2172-14 LTC2171-14 LTC2170-14

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l14 14 14 Bits

Integral Linearity Error Differential Analog Input (Note 6) l–3.25 ±1 3.25 –2.75 ±1 2.75 –2.75 ±1 2.75 LSB

Differential Linearity Error Differential Analog Input l–0.8 ±0.3 0.8 –0.8 ±0.3 0.8 –0.8 ±0.3 0.8 LSB

Offset Error (Note 7) l–12 ±3 12 –12 ±3 12 –12 ±3 12 mV

Gain Error Internal Reference

External Reference

–2.5

–1

0.5

–2.5

–1

0.5

–2.5

–1

0.5

%FS

Offset Drift ±20 ±20 ±20 µV/°C

Full-Scale Drift Internal Reference

External Reference

±35

±25

±35

±25

±35

±25

ppm/°C

Gain Matching External Reference ±0.2 ±0.2 ±0.2 %FS

Offset Matching ±3 ±3 ±3 mV

Transition Noise External Reference 1.2 1.2 1.2 LSBRMS

analog inpuT

The l denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (AIN+ – AIN–) 1.7V < VDD < 1.9V l1 to 2 VP-P

VIN(CM) Analog Input Common Mode (AIN+ + AIN–)/2 Differential Analog Input (Note 8) lVCM – 100mV VCM VCM + 100mV V

VSENSE External Voltage Reference Applied to SENSE External Reference Mode l0.625 1.250 1.300 V

IIN(CM) Analog Input Common Mode Current Per Pin, 65Msps

Per Pin, 40Msps

Per Pin, 25Msps

µA

IIN1 Analog Input Leakage Current (No Encode) 0 < AIN+, AIN– < VDD l–1 1 µA

IIN2 PAR/SER Input Leakage Current 0 < PAR/SER < VDD l–3 3 µA

IIN3 SENSE Input Leakage Current 0.625 < SENSE < 1.3V l–6 6 µA

tAP Sample-and-Hold Acquisition Delay Time 0 ns

tJITTER Sample-and-Hold Acquisition Delay Jitter 0.15 psRMS

CMRR Analog Input Common Mode Rejection Ratio 80 dB

BW-3B Full-Power Bandwidth Figure 6 Test Circuit 800 MHz

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

DynaMic accuracy

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2172-14 LTC2171-14 LTC2170-14

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

SNR Signal-to-Noise Ratio 5MHz Input

30MHz Input

70MHz Input

140MHz Input

72.0

73.7

73.5

71.7

73.5

73.4

72.8

71.1

72.9

72.8

72.3

dBFS

SFDR Spurious Free Dynamic Range

2nd or 3rd Harmonic

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

Spurious Free Dynamic Range

4th Harmonic or Higher

5MHz Input

30MHz Input

70MHz Input

140MHz Input

dBFS

S/(N+D) Signal-to-Noise Plus

Distortion Ratio

5MHz Input

30MHz Input

70MHz Input

140MHz Input

71.2

73.6

73.5

73.2

72.5

71.3

73.3

73.2

73.1

72.3

70.8

72.8

72.7

72.5

71.9

dBFS

Crosstalk, Near Channel 10MHz Input (Note 12) –90 –90 –90 dBc

Crosstalk, Far Channel 10MHz Input (Note 12) –105 –105 –105 dBc

inTernal reFerence characTerisTics

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)

PARAMETER CONDITIONS MIN TYP MAX UNITS

VCM Output Voltage IOUT = 0 0.5 • VDD – 25mV 0.5 • VDD 0.5 • VDD + 25mV V

VCM Output Temperature Drift ±25 ppm/°C

VCM Output Resistance –600µA < IOUT < 1mA 4 Ω

VREF Output Voltage IOUT = 0 1.225 1.250 1.275 V

VREF Output Temperature Drift ±25 ppm/°C

VREF Output Resistance –400µA < IOUT < 1mA 7 Ω

VREF Line Regulation 1.7V < VDD < 1.9V 0.6 mV/V

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODE INPUTS (ENC+, ENC– )

Differential Encode Mode (ENC– Not Tied to GND)

VID Differential Input Voltage (Note 8) l0.2 V

VICM Common Mode Input Voltage Internally Set

Externally Set (Note 8)

1.1

1.2

1.6

VIN Input Voltage Range ENC+, ENC– to GND l0.2 3.6 V

RIN Input Resistance (See Figure 10) 10 kΩ

CIN Input Capacitance 3.5 pF

Single-Ended Encode Mode (ENC– Tied to GND)

VIH High Level Input Voltage VDD = 1.8V l1.2 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

VIN Input Voltage Range ENC+ to GND l0 3.6 V

RIN Input Resistance (See Figure 11) 30 kΩ

CIN Input Capacitance 3.5 pF

DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)

VIH High Level Input Voltage VDD = 1.8V l1.3 V

VIL Low Level Input Voltage VDD = 1.8V l0.6 V

IIN Input Current VIN = 0V to 3.6V l–10 10 µA

CIN Input Capacitance 3 pF

SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)

ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V 200 Ω

IOH Logic High Output Leakage Current SDO = 0V to 3.6V l–10 10 µA

COUT Output Capacitance 3 pF

DIGITAL DATA OUTPUTS

VOD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

VOS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

1.375

RTERM On-Chip Termination Resistance Termination Enabled, OVDD = 1.8V 100 Ω

DigiTal inpuTs anD ouTpuTs

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 5)

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

TiMing characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

SYMBOL PARAMETER CONDITIONS

LTC2172-14 LTC2171-14 LTC2170-14

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

fSSampling Frequency (Notes 10, 11) l5 65 5 40 5 25 MHz

tENCL ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tENCH ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

7.3

7.69

100

11.88

12.5

100

tAP Sample-and-Hold

Acquisition Delay Time

0 0 0 ns

power requireMenTs

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

SYMBOL PARAMETER CONDITIONS

LTC2172-14 LTC2171-14 LTC2170-14

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

VDD Analog Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

OVDD Output Supply Voltage (Note 10) l1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V

IVDD Analog Supply Current Sine Wave Input l157 181 96 112 75 85 mA

IOVDD Digital Supply Current 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

PDISS Power Dissipation 1-Lane Mode, 1.75mA Mode

1-Lane Mode, 3.5mA Mode

2-Lane Mode, 1.75mA Mode

2-Lane Mode, 3.5mA Mode

311

337

328

367

378

419

202

225

216

256

250

293

162

185

178

216

202

243

PSLEEP Sleep Mode Power 1 1 1 mW

PNAP Nap Mode Power 75 75 75 mW

PDIFFCLK Power Increase with Differential Encode Mode Enabled

(No Increase for Sleep Mode)

20 20 20 mW

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Digital Data Outputs (RTERM = 100Ω Differential, CL = 2pF to GND on Each Output)

tSER Serial Data Bit Period 2-Lanes, 16-Bit Serialization

2-Lanes, 14-Bit Serialization

2-Lanes, 12-Bit Serialization

1-Lane, 16-Bit Serialization

1-Lane, 14-Bit Serialization

1-Lane, 12-Bit Serialization

1 / (8 • fS)

1 / (7 • fS)

1 / (6 • fS)

1 / (16 • fS)

1 / (14 • fS)

1 / (12 • fS)

tFRAME FR to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tDATA DATA to DCO Delay (Note 8) l0.35 • tSER 0.5 • tSER 0.65 • tSER s

tPD Propagation Delay (Note 8) l0.7n + 2 • tSER 1.1n + 2 • tSER 1.5n + 2 • tSER s

tROutput Rise Time Data, DCO, FR, 20% to 80% 0.17 ns

tFOutput Fall Time Data, DCO, FR, 20% to 80% 0.17 ns

DCO Cycle-to-Cycle Jitter tSER = 1ns 60 psP-P

Pipeline Latency 6 Cycles

SPI Port Timing (Note 8)

tSCK SCK Period Write Mode

Readback Mode, CSDO = 20pF, RPULLUP = 2k

250

tSCS to SCK Set-Up Time l5 ns

tHSCK to CS Set-Up Time l5 ns

tDS SDI Set-Up Time l5 ns

tDH SDI Hold Time l5 ns

tDO SCK Falling to SDO Valid Readback Mode

CSDO = 20pF, RPULLUP = 2k

l125 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND with GND and OGND

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above VDD, they

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above VDD without latchup.

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above VDD

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

Note 5: V

= OV

= 1.8V, f

SAMPLE

= 65MHz (LTC2172),

40MHz (LTC2171), or 25MHz (LTC2170), 2-lane output mode, differential

ENC+/ENC– = 2V

P-P

sine wave, input range = 2V

P-P

with differential drive,

unless otherwise noted.

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5 LSB when

the output code flickers between 00 0000 0000 0000 and 11 1111 1111

1111 in 2’s complement output mode.

Note 8: Guaranteed by design, not subject to test.

Note 9: V

= OV

= 1.8V, f

SAMPLE

= 65MHz (LTC2172), 40MHz

(LTC2171), or 25MHz (LTC2170), 2-lane output mode, ENC+ = single-

ended 1.8V square wave, ENC– = 0V, input range = 2V

P-P

with differential

drive, unless otherwise noted. The supply current and power dissipation

specifications are totals for the entire chip, not per channel.

Note 10: Recommended operating conditions.

Note 11: The maximum sampling frequency depends on the speed grade

of the part and also which serialization mode is used. The maximum serial

data rate is 1000Mbps, so tSER must be greater than or equal to 1ns.

Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4.

Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and

Ch.2 to Ch.4.

TiMing characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 5)

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

TiMing DiagraMs

2-Lane Output Mode, 16-Bit Serialization*

2-Lane Output Mode, 14-Bit Serialization

217214 TD01

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

*SEE THE DIGITAL OUTPUTS SECTION

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D5 D3 D1 0 D13 D11 D9 D7 D5 D3 D1 0 D13 D11 D9

D4 D2 D0 0 D12 D10 D8 D6 D4 D2 D0 0 D12 D10 D8

tENCH tENCL

tSER

217214 TD02

tAP

N + 2

N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

NOTE THAT IN THIS MODE, FR+/FR– HAS TWO TIMES THE PERIOD OF ENC+/ENC–

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-3SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9

D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8

tENCH tENCL

tSER

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

TiMing DiagraMs

2-Lane Output Mode, 12-Bit Serialization

1-Lane Output Mode, 16-Bit Serialization

217214 TD04

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

OUT#B+, OUT#B– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUT#A–

tFRAME tDATA tSER

tSER

tPD

D1 D0 0 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 D13 D12 D11 D10

tENCH tENCL

tSER

217214 TD03

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR+

ENC+

DCO+

FR–

OUT#A+

SAMPLE N-6 SAMPLE N-5

OUT#A–

OUT#B+

OUT#B–

SAMPLE N-4

tFRAME

tDATA tSER

tSER

tPD

D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9

D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8

tENCH tENCL

tSER

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

217214 TD05

tAP N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

OUT#B+, OUT#B– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUT#A–

tFRAME tDATA tSER

tSER

tPD

D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10

tENCH tENCL

tSER

TiMing DiagraMs

1-Lane Output Mode, 14-Bit Serialization

1-Lane Output Mode, 12-Bit Serialization

217214 TD06

tAP

N + 1

ANALOG

INPUT

ENC–

DCO–

FR–

ENC+

DCO+

FR+

OUT#A+

OUT#B+, OUT#B– ARE DISABLED

SAMPLE N-6 SAMPLE N-5 SAMPLE N-4

OUT#A–

tFRAME tDATA tSER

tSER

tPD

D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11

tENCH tENCL

tSER

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

SPI Port Timing (Readback Mode)

tStDS

A5 A4 A3 A2 A1 A0 XX

D7 D6 D5 D4 D3 D2 D1 D0

XX XX XX XX XX XX XX

SCK

SDI R/W

SDO HIGH IMPEDANCE

tDH

tDO

tSCK tH

A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

217214 TD07

SCK

SDI R/W

SDO HIGH IMPEDANCE

SPI Port Timing (Write Mode)

TiMing DiagraMs

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

LTC2172-14: 8k Point FFT,

fIN = 30MHz, –1dBFS, 65Msps

LTC2172-14: 8k Point FFT,

fIN = 70MHz, –1dBFS, 65Msps

LTC2172-14: 8k Point FFT,

fIN = 140MHz, –1dBFS, 65Msps

LTC2172-14: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

65Msps

LTC2172-14: Shorted Input

Histogram

LTC2172-14: SNR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

LTC2172-14: Integral

Nonlinearity (INL)

LTC2172-14: Differential

Nonlinearity (DNL)

LTC2172-14: 8k Point FFT,

fIN = 5MHz, –1dBFS, 65Msps

Typical perForMance characTerisTics

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

217214 G03

010 20 30

OUTPUT CODE

–2.0

–0.5

–1.0

–1.5

INL ERROR (LSB)

0.5

1.0

1.5

2.0

4096 8192 12288 16384

217214 G01

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

4096 8192 12288 16384

217214 G02

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

217214 G04

10 20 30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

217214 G05

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

217214 G06

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20 30

217214 G07

OUTPUT CODE

8197

1000

3000

2000

COUNT

4000

5000

6000

8199 8201 8203 8205

217214 G08

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

217214 G09

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

IOVDD vs Sample Rate, 5MHz Sine

Wave Input, –1dBFS

LTC2172-14: SNR vs SENSE,

fIN = 5MHz, –1dBFS

LTC2171-14: Integral Nonlinearity

(INL)

LTC2171-14: Differential

Nonlinearity (DNL)

LTC2171-14: 8k Point FFT,

fIN = 5MHz –1dBFS, 40Msps

LTC2172-14: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 65Msps

LTC2172-14: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2172-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

65Msps

Typical perForMance characTerisTics

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

217214 G10

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

217214 G11

dBFS

dBc

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

217214 G14

OUTPUT CODE

–2.0

–0.5

–1.0

–1.5

INL ERROR (LSB)

0.5

1.0

1.5

2.0

4096 8192 12288 16384

217214 G15

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

4096 8192 12288 16384

217214 G16

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

217214 G17

INPUT LEVEL (dBFS)

SNR (dBc AND dBFS)

–60 –50 –40 –30 –20 –10 0

217214 G50

dBc

dBFS

SAMPLE RATE (Msps)

160

155

150

145

140

135

130

125

120

115

110

IVDD (mA)

0 10 20 30 40 50 60

217214 G53

SAMPLE RATE (Msps)

IOVDD (mA)

0 20 40 60

217214 G51

1-LANE, 1.75mA

2-LANE, 3.5mA

2-LANE, 1.75mA

1-LANE, 3.5mA

LTC2172-14: SNR vs Input Level,

fIN = 70MHz, 2V Range, 65Msps

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Typical perForMance characTerisTics

LTC2171-14: 8k Point FFT,

fIN = 69MHz, –1dBFS, 40Msps

LTC2171-14: 8k Point FFT,

fIN = 139MHz, –1dBFS, 40Msps

LTC2171-14: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

40Msps

LTC2171-14: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2171-14: Shorted Input

Histogram

LTC2171-14: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 40Msps

LTC2171-14: SNR vs Input

Frequency, –1dBFS,

2V Range, 40Msps

LTC2171-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

40Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

217214 G19

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

217214 G20

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

217214 G21

OUTPUT CODE

8198

1000

3000

2000

COUNT

4000

5000

6000

8200 8202 8204 8206

217214 G22

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

217214 G23

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

217214 G24

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

217214 G25

dBFS

dBc

SAMPLE RATE (Msps)

100

IVDD (mA)

0 10 20 30 40

217214 G54

LTC2171-14: 8k Point FFT,

fIN = 29MHz, –1dBFS, 40Msps

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

10 20

217214 G18

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

LTC2171-14: SNR vs SENSE,

fIN = 5MHz, –1dBFS

LTC2170-14: Integral Nonlinearity

(INL)

LTC2170-14: Differential

Nonlinearity (DNL)

LTC2170-14: 8k Point FFT,

fIN = 5MHz –1dBFS, 25Msps

LTC2170-14: 8k Point FFT,

fIN = 30MHz –1dBFS, 25Msps

LTC2170-14: 8k Point FFT,

fIN = 70MHz –1dBFS, 25Msps

LTC2170-14: 8k Point FFT,

fIN = 140MHz –1dBFS, 25Msps

LTC2170-14: 8k Point 2-Tone FFT,

fIN = 68MHz, 69MHz, –1dBFS,

25Msps

LTC2170-14: Shorted Input

Histogram

Typical perForMance characTerisTics

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

217214 G27

OUTPUT CODE

–2.0

–0.5

–1.0

–1.5

INL ERROR (LSB)

0.5

1.0

1.5

2.0

4096 8192 12288 16384

217214 G28

OUTPUT CODE

–1.0

–0.4

–0.2

–0.6

–0.8

DNL ERROR (LSB)

0.4

0.2

0.6

0.8

1.0

4096 8192 12288 16384

217214 G29

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

217214 G30

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

217214 G31

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

217214 G32

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

217214 G33

FREQUENCY (MHz)

–100

–110

–120

–70

–60

–80

–90

AMPLITUDE (dBFS)

–50

–30

–40

–20

–10

510

217214 G34

OUTPUT CODE

8198

1000

3000

2000

COUNT

4000

5000

6000

8200 8202 8204 8206

217214 G35

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

INPUT FREQUENCY (MHz)

SFDR (dBFS)

50 100 150 200 250 300 350

217214 G37

INPUT LEVEL (dBFS)

–80

SFDR (dBc AND dBFS)

100

110

–70 –60 –50 –40 –30 –20 –10 0

217214 G38

dBFS

dBc

SENSE PIN (V)

0.6

SNR (dBFS)

0.7 0.8 0.9 1.1 1.2 1.31

217214 G40

LTC2170-14: SFDR vs Input Level,

fIN = 70MHz, 2V Range, 25Msps

LTC2170-14: SFDR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

LTC2170-14: IVDD vs Sample Rate,

5MHz Sine Wave Input, –1dBFS

LTC2170-14: SNR vs SENSE,

fIN = 5MHz, –1dBFS

Typical perForMance characTerisTics

LTC2170-14: SNR vs Input

Frequency, –1dBFS, 2V Range,

25Msps

INPUT FREQUENCY (MHz)

SNR (dBFS)

50 100 150 200 250 300 350

217214 G36

SERIAL DATA RATE (Mbps)

350

300

250

200

150

100

PEAK-TO-PEAK JITTER (ps)

0 200 400 600 800 1000

217214 G52

SAMPLE RATE (Msps)

IVDD (mA)

0 5 10 15 2520

217214 G55

DCO Cycle-Cycle Jitter vs Serial

Data Rate

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

AIN1+ (Pin 1): Channel 1 Positive Differential Analog

Input.

AIN1– (Pin 2): Channel 1 Negative Differential Analog

Input.

VCM12 (Pin 3): Common Mode Bias Output, Nominally

Equal to VDD/2. VCM should be used to bias the common

mode of the analog inputs of channels 1 and 2. Bypass

to ground with a 0.1µF ceramic capacitor.

AIN2+ (Pin 4): Channel 2 Positive Differential Analog

Input.

AIN2– (Pin 5): Channel 2 Negative Differential Analog

Input.

REFH (Pins 6, 7): ADC High Reference. Bypass to Pin 8

and Pin 9 with a 2.2µF ceramic capacitor, and to ground

with a 0.1µF ceramic capacitor.

REFL (Pins 8, 9): ADC Low Reference. Bypass to Pin 6

and Pin 7 with a 2.2µF ceramic capacitor, and to ground

with a 0.1µF ceramic capacitor.

AIN3+ (Pin 10): Channel 3 Positive Differential Analog

Input.

AIN3– (Pin 11): Channel 3 Negative Differential Analog

Input.

VCM34 (Pin 12): Common Mode Bias Output, Nominally

Equal to VDD/2. VCM should be used to bias the common

mode of the analog inputs of channels 3 and 4. Bypass

to ground with a 0.1µF ceramic capacitor.

AIN4+ (Pin 13): Channel 4 Positive Differential Analog

Input.

AIN4– (Pin 14): Channel 4 Negative Differential Analog

Input.

VDD (Pins 15, 16, 51, 52): 1.8V Analog Power Supply.

Bypass to ground with 0.1µF ceramic capacitors. Adjacent

pins can share a bypass capacitor.

ENC+ (Pin 17): Encode Input. Conversion starts on the

rising edge.

ENC– (Pin 18): Encode Complement Input. Conversion

starts on the falling edge.

CS (Pin 19): In serial programming mode (PAR/SER = 0V),

CS is the serial interface chip select input. When CS is low,

SCK is enabled for shifting data on SDI into the mode

control registers. In parallel programming mode (PAR/SER

= VDD), CS selects two-lane or one-lane output mode. CS

can be driven with 1.8V to 3.3V logic.

SCK (Pin 20): In serial programming mode (PAR/SER

= 0V), SCK is the serial interface clock input. In parallel

programming mode (PAR/SER = VDD), SCK selects 3.5mA

or 1.75mA LVDS output currents. SCK can be driven with

1.8V to 3.3V logic.

SDI (Pin 21): In serial programming mode (PAR/SER =

0V), SDI is the serial interface data input. Data on SDI

is clocked into the mode control registers on the rising

edge of SCK. In parallel programming mode (PAR/SER =

VDD), SDI can be used to power down the part. SDI can

be driven with 1.8V to 3.3V logic.

GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power

Ground. The exposed pad must be soldered to the PCB

ground.

OGND (Pin 33): Output Driver Ground. Must be shorted

to the ground plane by a very low inductance path. Use

multiple vias close to the pin.

OVDD (Pin 34): Output Driver Supply. Bypass to ground

with a 0.1µF ceramic capacitor.

SDO (Pin 46): In serial programming mode (PAR/SER

= 0V), SDO is the optional serial interface data output.

Data on SDO is read back from the mode control registers

and can be latched on the falling edge of SCK. SDO is

an open-drain N-channel MOSFET output that requires

an external 2k pull-up resistor of 1.8V to 3.3V. If read-

back from the mode control registers is not needed,

the pull-up resistor is not necessary and SDO can be

left unconnected. In parallel programming mode (PAR/

SER = VDD), SDO is an input that enables internal 100Ω

termination resistors on the digital outputs. When used

as an input, SDO can be driven with 1.8V to 3.3V logic

through a 1k series resistor.

pin FuncTions

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

pin FuncTions

PAR/SER (Pin 47): Programming Mode Selection Pin.

Connect to ground to enable serial programming mode.

CS, SCK, SDI and SDO become a serial interface that con-

trols the A/D operating modes. Connect to VDD to enable

parallel programming mode where CS, SCK, SDI and SDO

become parallel logic inputs that control a reduced set of

the A/D operating modes. PAR/SER should be connected

directly to ground or the VDD of the part and not be driven

by a logic signal.

VREF (Pin 48): Reference Voltage Output. Bypass to ground

with a 1µF ceramic capacitor, nominally 1.25V.

SENSE (Pin 50): Reference Programming Pin. Connect-

ing SENSE to VDD selects the internal reference and a

±1V input range. Connecting SENSE to ground selects

the internal reference and a ±0.5V input range. An external

reference between 0.625V and 1.3V applied to SENSE

selects an input range of ±0.8 • VSENSE.

LVDS OUTPUTS

The following pins are differential LVDS outputs. The

output current level is programmable. There is an op-

tional internal 100Ω termination resistor between the

pins of each LVDS output pair.

OUT4B–/OUT4B+, OUT4A–/OUT4A+ (Pins 23/24,

Pins 25/ 26): Serial Data Outputs for Channel 4. In 1-lane

output mode, only OUT4A–/OUT4A+ are used.

OUT3B–/OUT3B+, OUT3A–/OUT3A+ (Pins 27/28,

Pins 29/30): Serial Data Outputs for Channel 3. In

1-lane output mode, only OUT3A–/OUT3A+ are used.

FR–/FR+ (Pin 31/Pin 32): Frame Start Output.

DCO–/DCO+ (Pin 35/Pin 36): Data Clock Output.

OUT2B–/OUT2B+, OUT2A–/OUT2A+ (Pins 37/38,

Pins 39/40): Serial Data Outputs for Channel 2. In

1-lane output mode, only OUT2A–/OUT2A+ are used.

OUT1B–/OUT1B+, OUT1A–/OUT1A+ (Pins 41/42,

Pins 43/44): Serial Data Outputs for Channel 1. In

1-lane output mode, only OUT1A–/OUT1A+ are used.

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

FuncTional block DiagraM

PLL

DATA

SERIALIZER

SAMPLE-

AND-HOLD

14-BIT

ADC CORE

CHANNEL 1

ANALOG

INPUT

14-BIT

ADC CORE

CHANNEL 2

ANALOG

INPUT

14-BIT

ADC CORE

CHANNEL 3

ANALOG

INPUT

14-BIT

ADC CORE

CHANNEL 4

ANALOG

INPUT

1.8V

VDD

1.8VENC+ENC–

OVDD

VDD/2

DIFF

REF

AMP

REF

BUF

2.2µF

0.1µF 0.1µF

0.1µF

REFH REFL

RANGE

SELECT

1.25V

REFERENCE

REFH REFL

OUT1A

OUT1B

OUT2A

OUT2B

OUT3A

OUT3B

OUT4A

OUT4B

DATA

CLOCKOUT

FRAME

OGND

VCM12

GND VCM34

0.1µF0.1µF SDOCS

SENSE

VREF

1µF

MODE

CONTROL

REGISTERS

SCKPAR/SER SDI

217214 F01

SAMPLE-

AND-HOLD

SAMPLE-

AND-HOLD

SAMPLE-

AND-HOLD

Figure 1. Functional Block Diagram

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

CONVERTER OPERATION

The LTC2172-14/LTC2171-14/LTC2170-14 are low power,

4-channel, 14-bit, 65Msps/40Msps/25Msps A/D convert-

ers that are powered by a single 1.8V supply. The analog

inputs should be driven differentially. The encode input

can be driven differentially for optimal jitter performance,

or single-ended for lower power consumption. The digital

outputs are serial LVDS to minimize the number of data

lines. Each channel outputs two bits at a time (2-lane

mode) or one bit at a time (1-lane mode). Many additional

features can be chosen by programming the mode control

registers through a serial SPI port.

ANALOG INPUT

The analog inputs are differential CMOS sample-and-hold

circuits (Figure 2). The inputs should be driven differen-

tially around a common mode voltage set by the VCM12

applicaTions inForMaTion

or VCM34 output pins, which are nominally VDD /2. For the

2V input range, the inputs should swing from VCM – 0.5V

to VCM + 0.5V. There should be a 180° phase difference

between the inputs.

The four channels are simultaneously sampled by a

shared encode circuit (Figure 2).

INPUT DRIVE CIRCUITS

Input Filtering

If possible, there should be an RC lowpass filter right

at the analog inputs. This lowpass filter isolates the

drive circuitry from the A/D sample-and-hold switch-

ing and limits wideband noise from the drive circuitry.

Figure 3 shows an example of an input RC filter. The RC

component values should be chosen based on the ap-

plication’s input frequency.

Figure 2. Equivalent Input Circuit. Only One of

the Four Analog Channels Is Shown.

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

CSAMPLE

3.5pF

RON

25Ω

RON

25Ω

VDD

LTC2172-14

AIN+

217214 F02

CSAMPLE

3.5pF

VDD

AIN–

ENC–

ENC+

1.2V

10k

1.2V

10k

CPARASITIC

1.8pF

CPARASITIC

1.8pF

10Ω

10Ω

25Ω

25Ω 25Ω

25Ω

50Ω

0.1µF

AIN+

AIN–

12pF

0.1µF

VCM

LTC2172-14

ANALOG

INPUT

0.1µF T1

1:1

T1: MA/COM MABAES0060

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

217214 F03

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Transformer Coupled Circuits

Figure 3 shows the analog input being driven by an RF

transformer with a center-tapped secondary. The center

tap is biased with VCM, setting the A/D input at its opti-

mal DC level. At higher input frequencies a transmission

line balun transformer (Figures 4 to 6) has better balance,

resulting in lower A/D distortion.

applicaTions inForMaTion

Amplifier Circuits

Figure 7 shows the analog input being driven by a high

speed differential amplifier. The output of the amplifier is

AC-coupled to the A/D so the amplifier’s output common

mode voltage can be optimally set to minimize distortion.

At very high frequencies an RF gain block will often have

lower distortion than a differential amplifier. If the gain

block is single-ended, then a transformer circuit (Figures

4 to 6) should convert the signal to differential before

driving the A/D.

Figure 5. Recommended Front-End Circuit for Input

Frequencies from 170MHz to 300MHz

Figure 6. Recommended Front-End Circuit for Input

Frequencies Above 300MHz

Figure 4. Recommended Front-End Circuit for Input

Frequencies from 70MHz to 170MHz

25Ω

50Ω

0.1µF

AIN+

AIN–

4.7pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM MABA-007159-000000

T2: MA/COM MABAES0060

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

217214 F04

LTC2172-14 25Ω

25Ω

50Ω

0.1µF

AIN+

AIN–

1.8pF

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM MABA-007159-000000

T2: COILCRAFT WBC1-1LB

RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE

217214 F05

LTC2172-14

25Ω

50Ω

0.1µF

2.7nH

AIN+

AIN–

0.1µF

VCM

ANALOG

INPUT

0.1µF

T1: MA/COM ETC1-1-13

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

217214 F06

LTC2172-14

25Ω

200Ω

0.1µF AIN+

AIN–

12pF

0.1µF

VCM

LTC2172-14

217214 F07

––

ANALOG

INPUT

HIGH SPEED

DIFFERENTIAL

AMPLIFIER

0.1µF

Figure 7. Front-End Circuit Using a High Speed

Differential Amplifier

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applicaTions inForMaTion

Reference

The LTC2172-14/LTC2171-14/LTC2170-14 has an internal

1.25V voltage reference. For a 2V input range using the

internal reference, connect SENSE to VDD. For a 1V input

range using the internal reference, connect SENSE to

ground. For a 2V input range with an external reference,

apply a 1.25V reference voltage to SENSE (Figure 9).

The input range can be adjusted by applying a voltage to

SENSE that is between 0.625V and 1.30V. The input range

will then be 1.6 • VSENSE.

The reference is shared by all four ADC channels, so it is

not possible to independently adjust the input range of

individual channels.

The VREF, REFH and REFL pins should be bypassed, as

shown in Figure 8. The 0.1µF capacitor between REFH and

REFL should be as close to the pins as possible (not on

the backside of the circuit board).

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

Figure 8. Reference Circuit

Figure 9. Using an External 1.25V Reference

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

VREF

REFH

SENSE

TIE TO VDD FOR 2V RANGE;

TIE TO GND FOR 1V RANGE;

RANGE = 1.6 • VSENSE FOR

0.625V < VSENSE < 1.300V

1.25V

REFL

0.1µF2.2µF

INTERNAL ADC

HIGH REFERENCE

BUFFER

5Ω

0.8x

DIFF AMP

INTERNAL ADC

LOW REFERENCE

1.25V BANDGAP

REFERENCE

0.625V

RANGE

DETECT

AND

CONTROL

1µF

0.1µF

LTC2172-14

217214 F08

SENSE

1.25V

EXTERNAL

REFERENCE

1µF

VREF

217214 F09

LTC2172-14

VDD

LTC2172-14

217214 F10

ENC–

ENC+

15k

VDD

DIFFERENTIAL

COMPARATOR

30k

ENC+

ENC–

217214 F11

1.8V TO 3.3V

LTC2172-14

CMOS LOGIC

BUFFER

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12 and 13).

The encode inputs are internally biased to 1.2V through

10k equivalent resistance. The encode inputs can be taken

above VDD (up to 3.6V), and the common mode range

is from 1.1V to 1.6V. In the differential encode mode,

ENC– should stay at least 200mV above ground to avoid

falsely triggering the single-ended encode mode. For

good jitter performance ENC+ should have fast rise and

fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

encode input. ENC+ can be taken above VDD (up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The

ENC+ threshold is 0.9V. For good jitter performance

ENC+ should have fast rise and fall times.

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

applicaTions inForMaTion

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

DIGITAL OUTPUTS

The digital outputs of the LTC2172-14/LTC2171-14/

LTC2170-14 are serialized LVDS signals. Each chan-

nel outputs two bits at a time (2-lane mode) or one

bit at a time (1-lane mode). The data can be serialized

with 16-, 14-, or 12-bit serialization (see the Timing

Diagrams section for details). Note that with 12-bit

serialization the two LSBs are not available—this mode

is included for compatibility with the 12-bit versions

of these parts.

The output data should be latched on the rising and

falling edges of the data clockout (DCO). A data frame

output (FR) can be used to determine when the data

from a new conversion result begins. In the 2-lane, 14-

bit serialization mode, the frequency of the FR output

is halved.

The maximum serial data rate for the data outputs is

1Gbps, so the maximum sample rate of the ADC will de-

pend on the serialization mode as well as the speed grade

of the ADC (see Table 1). The minimum sample rate for

all serialization modes is 5Msps.

Figure 12. Sinusoidal Encode Drive

Figure 13. PECL or LVDS Encode Drive

50Ω 100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2172-14

217214 F12

ENC–

ENC+ENC+

ENC–

PECL OR

LVDS

CLOCK

0.1µF

217214 F13

LTC2172-14

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applicaTions inForMaTion

By default the outputs are standard LVDS levels: a 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100Ω differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

The outputs are powered by OVDD and OGND which are

isolated from the A/D core power and ground.

Programmable LVDS Output Current

The default output driver current is 3.5mA. This current can

be adjusted by control register A2 in serial programming

mode. Available current levels are 1.75mA, 2.1mA, 2.5mA,

3mA, 3.5mA, 4mA and 4.5mA. In parallel programming

mode the SCK pin can select either 3.5mA or 1.75mA.

Optional LVDS Driver Internal Termination

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100Ω termination resistor can

be enabled by serially programming mode control register

A2. The internal termination helps absorb any reflections

caused by imperfect termination at the receiver. When the

internal termination is enabled, the output driver current

is doubled to maintain the same output voltage swing. In

parallel programming mode the SDO pin enables internal

termination. Internal termination should only be used with

1.75mA, 2.1mA or 2.5mA LVDS output current modes.

Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2172-14. The Sampling

Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2171-14) or 25MHz (LTC2170-14).

SERIALIZATION MODE

MAXIMUM SAMPLING

FREQUENCY, fS (MHz) DCO FREQUENCY FR FREQUENCY SERIAL D ATA RATE

2-Lane 16-Bit Serialization 65 4 • fSfS8 • fS

2-Lane 14-Bit Serialization 65 3.5 • fS0.5 • fS7 • fS

2-Lane 12-Bit Serialization 65 3 • fSfS6 • fS

1-Lane 16-Bit Serialization 62.5 8 • fSfS16 • fS

1-Lane 14-Bit Serialization 65 7 • fSfS14 • fS

1-Lane 12-Bit Serialization 65 6 • fSfS12 • fS

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

Table 2. Output Codes vs Input Voltage

AIN+ – AIN–

(2V RANGE)

D13-D0

(OFFSET BINARY)

D13-D0

(2’s COMPLEMENT)

>1.000000V

+0.999878V

+0.999756V

11 1111 1111 1111

11 1111 1111 1110

01 1111 1111 1111

01 1111 1111 1110

+0.000122V

+0.000000V

–0.000122V

–0.000244V

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

–0.999878V

–1.000000V

≤–1.000000V

00 0000 0000 0001

00 0000 0000 0000

10 0000 0000 0001

10 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones in

the ADC output spectrum. These unwanted tones can be

randomized by randomizing the digital output before it is

transmitted off chip, which reduces the unwanted tone

amplitude.

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The FR and DCO outputs are

not affected. The output randomizer is enabled by serially

programming mode control register A1.

Digital Output Test Pattern

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D13-D0) of all channels to known values. The digital

output test patterns are enabled by serially programming

mode control registers A3 and A4. When enabled, the test

patterns override all other formatting modes: 2’s comple-

ment and randomizer.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs, including DCO and FR, are disabled to save

power or enable in-circuit testing. When disabled, the com-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire chip is powered down,

resulting in 1mW power consumption. Sleep mode is

enabled by mode control register A1 (serial program-

ming mode), or by SDI (parallel programming mode).

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on VREF,

REFH and REFL. For the suggested values in Figure 8, the

A/D will stabilize after 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing a faster wake-up than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling, then an additional 50µs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by the mode control

applicaTions inForMaTion

DEVICE PROGRAMMING MODES

The operating modes of the LTC2172-14/LTC2171-14/

LTC2170-14 can be programmed by either a parallel

interface or a simple serial interface. The serial interface

has more flexibility and can program all available modes.

The parallel interface is more limited and can only program

some of the more commonly used modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to VDD. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to VDD or ground, or driven by 1.8V, 2.5V or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD)

PIN DESCRIPTION

CS 2-Lane/1-Lane Selection Bit

0 = 2-Lane, 16-Bit Serialization Output Mode

1 = 1-Lane, 14-Bit Serialization Output Mode

SCK LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

SDI Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO Internal 100Ω Termination Selection Bit

0 = Internal Termination Disabled

1 = Internal Termination Enabled

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first 16 rising edges of

SCK. Any SCK rising edges after the first 16 are ignored.

The data transfer ends when CS is taken high again.

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applicaTions inForMaTion

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be

written to the register set by the address bits (A6:A0).

If the R/W bit is high, data in the register set by the

address bits (A6:A0) will be read back on the SDO pin

(see the Timing Diagrams section). During a readback

command the register is not updated and data on SDI

is ignored.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and readback is not needed,

then SDO can be left floating and no pull-up resistor is

needed. Table 4 shows a map of the mode control registers.

Software Reset

If serial programming is used, the mode control registers

should be programmed as soon as possible after the power

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset, bit D7 in the

reset register is written with a logic 1. After the reset SPI

write command is complete, bit D7 is automatically set

back to zero.

Table 4. Serial Programming Mode Register Map (PAR/SER = GND)

D7 D6 D5 D4 D3 D2 D1 D0

RESET X X X X X X X

Bit 7 RESET Software Reset Bit

0 = Not Used

1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is

automatically set back to zero after the reset is complete at the end of the SPI write command. The reset register is write only.

Bits 6-0 Unused, Don’t Care Bits.

D7 D6 D5 D4 D3 D2 D1 D0

DCSOFF RAND TWOSCOMP SLEEP NAP_4 NAP_3 NAP_2 NAP_1

Bit 7 DCSOFF Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer On

1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.

Bit 6 RAND Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

Bit 5 TWOSCOMP Tw o ’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Tw o ’s Complement Data Format

Bits 4-0 SLEEP:NAP_4:NAP_1 Sleep/Nap Mode Control Bits

00000 = Normal Operation

0XXX1 = Channel 1 in Nap Mode

0XX1X = Channel 2 in Nap Mode

0X1XX = Channel 3 in Nap Mode

01XXX = Channel 4 in Nap Mode

1XXXX = Sleep Mode. All Channels Are Disabled

Note: Any Combination of Channels Can Be Placed in Nap Mode.

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applicaTions inForMaTion

D7 D6 D5 D4 D3 D2 D1 D0

ILVDS2 ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE2 OUTMODE1 OUTMODE0

Bits 7-5 ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 4 TERMON LVDS Internal Termination Bit

0 = Internal Termination Off

1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be

used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.

Bit 3 OUTOFF Output Disable Bit

0 = Digital Outputs are enabled.

1 = Digital Outputs are disabled.

Bits 2-0 OUTMODE2:OUTMODE0 Digital Output Mode Control Bits

000 = 2-Lanes, 16-Bit Serialization

001 = 2-Lanes, 14-Bit Serialization

010 = 2-Lanes, 12-Bit Serialization

011 = Not Used

100 = Not Used

101 = 1-Lane, 14-Bit Serialization

110 = 1-Lane, 12-Bit Serialization

111 = 1-Lane, 16-Bit Serialization

D7 D6 D5 D4 D3 D2 D1 D0

OUTTEST X TP13 TP12 TP11 TP10 TP9 TP8

Bit 7 OUTTEST Digital Output Test Pattern Control Bit

0 = Digital Output Test Pattern Off

1 = Digital Output Test Pattern On

Bit 6 Unused, Don’t Care Bit.

Bits 5-0 TP13:TP8 Test Pattern Data Bits (MSB)

TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.

D7 D6 D5 D4 D3 D2 D1 D0

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

Bits 7-0 TP7:TP0 Test Pattern Data Bits (LSB)

TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

applicaTions inForMaTion

GROUNDING AND BYPASSING

The LTC2172-14/LTC2171-14/LTC2170-14 requires a

printed circuit board with a clean unbroken ground plane.

A multilayer board with an internal ground plane in the

first layer beneath the ADC is recommended. Layout for

the printed circuit board should ensure that digital and

analog signal lines are separated as much as possible. In

particular, care should be taken not to run any digital track

alongside an analog signal track or underneath the ADC.

High quality ceramic bypass capacitors should be used at

the VDD, OVDD, VCM, VREF, REFH and REFL pins. Bypass

capacitors must be located as close to the pins as possible.

Of particular importance is the 0.1µF capacitor between

REFH and REFL. This capacitor should be on the same

side of the circuit board as the A/D, and as close to the

device as possible (1.5mm or less). Size 0402 ceramic

capacitors are recommended. The larger 2.2µF capacitor

between REFH and REFL can be somewhat further away.

The traces connecting the pins and bypass capacitors must

be kept short and should be made as wide as possible.

The analog inputs, encode signals and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

HEAT TRANSFER

Most of the heat generated by the LTC2172-14/LTC2171-14/

LTC2170-14 is transferred from the die through the bottom-

side exposed pad and package leads onto the printed circuit

board. For good electrical and thermal performance, the

exposed pad must be soldered to a large grounded pad

on the PC board. This pad should be connected to the

internal ground planes by an array of vias.

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Typical applicaTions

Silkscreen Top Top Side

Inner Layer 2 GND Inner Layer 3

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Typical applicaTions

Inner Layer 4 Inner Layer 5 Power

Bottom Side Silkscreen Bottom

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Typical applicaTions

LTC2172

1AIN1+

AIN1–

VCM12

AIN2+

AIN2–

REFH

REFL

AIN3+

AIN3–

VCM34

AIN4+

AIN4–

OUT2A+

OUT2A–

OUT2B+

OUT2B–

DCO+

DCO–

OVDD

OGND

FR+

FR–

OUT3A+

OUT3A–

OUT3B+

OUT3B–

VDD

ENC+

ENC–

SCK

SDI

GND

OUT4B–

OUT4B+

OUT4A–

OUT4A+

1615

VDD

17 18 19 20 21 22 23 24 25 26

VDD

SENSE

GND

VREF

PAR/SER

SDO

GND

OUT1A+

OUT1A–

OUT1B+

OUT1B–

5152 50 49 48

SDO

PAR/SER

SENSE

47 46 45 44 43 42 41

C30

0.1µF

2.2µF

C59

0.1µF

C29

0.1µF

SPI BUS

DIGITAL

OUTPUTS

OVDD

C46

0.1µF

C47

0.1µF

AIN1

AIN2

AIN3

AIN4

ENCODE

CLOCK

ENCODE

CLOCK

217214 TA02

R14

DIGITAL

OUTPUTS

C16

0.1µF

1µF

VDD

C17

1µF

LTC2172 Schematic

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

package DescripTion

UKG Package

52-Lead Plastic QFN (7mm × 8mm)

(Reference LTC DWG # 05-08-1729 Rev Ø)

7.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45°C

CHAMFER

0.40 ± 0.10

5251

BOTTOM VIEW—EXPOSED PAD

TOP VIEW

SIDE VIEW

6.50 REF

(2 SIDES)

8.00 ± 0.10

(2 SIDES)

5.50 REF

(2 SIDES)

0.75 ± 0.05

R = 0.115

TYP

R = 0.10

TYP 0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

6.45 ±0.10

5.41 ±0.10

0.00 – 0.05

(UKG52) QFN REV Ø 0306

5.50 REF

(2 SIDES)

5.41 ±0.05

6.45 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

6.10 ±0.05

7.50 ±0.05

6.50 REF

(2 SIDES) 7.10 ±0.05 8.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 03/10 Changed Sampling Frequency Max for LTC2171-14 from 45MHz to 40MHz in the Timing Characteristics section. 6

Added full part numbers to Grounding and Bypassing and Heat Transfer sections in Applications Information. 28

Revised Descriptions and Comments in the Related Parts section. 34

B 07/11 Corrected pin names for Pins 41-44 in the Pin Functions section. 18

Revised Software Reset paragraph and Table 4 in the Applications Information section. 26

LTC2172-14/

LTC2171-14/LTC2170-14

21721014fb

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0711 REV B • PRINTED IN USA

 LINEAR TECHNOLOGY CORPORATION 2010

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

ADCs

LTC2170-12/LTC2171-

12/LTC2172-12

12-Bit, 25Msps/40Msps/65Msps

1.8V Quad ADCs, Ultralow Power

160mW/198mW/306mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs,

7mm × 8mm QFN-52

LTC2173-12/LTC2174-

12/LTC2175-12

12-Bit, 80Msps/105Msps/125Msps

1.8V Quad ADCs, Ultralow Power

369mW/439mW/545mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,

7mm × 8mm QFN-52

LTC2256-14/LTC2257-

14/LTC2258-14

14-Bit, 25Msps/40Msps/65Msps

1.8V ADCs, Ultralow Power

35mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS

Outputs, 6mm × 6mm QFN-40

LTC2259-14/LTC2260-

14/LTC2261-14

14-Bit, 80Msps/105Msps/125Msps

1.8V ADCs, Ultralow Power

89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS

Outputs, 6mm × 6mm QFN-40

LTC2262-14 14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,

6mm × 6mm QFN-40

LTC2263-14/LTC2264-

14/LTC2265-14

14-Bit, 25Msps/40Msps/65Msps

1.8V Dual ADCs, Ultralow Power

94mW/113mW/171mW, 73.7dB SNR, 90dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

LTC2263-12/LTC2264-

12/LTC2265-12

12-Bit, 25Msps/40Msps/65Msps

1.8V Dual ADCs, Ultralow Power

94mW/112mW/167mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

LTC2266-14/LTC2267-

14/LTC2268-14

14-Bit, 80Msps/105Msps/125Msps

1.8V Dual ADCs, Ultralow Power

203mW/243mW/299mW, 73.1dB SNR, 88dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

LTC2266-12/LTC2267-

12/LTC2268-12

12-Bit, 80Msps/105Msps/125Msps

1.8V Dual ADCs, Ultralow Power

200mW/238mW/292mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,

6mm × 6mm QFN-40

RF Mixers/Demodulators

LTC5517 40MHz to 900MHz Direct Conversion

Quadrature Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LTC5527 400MHz to 3.7GHz High Linearity

Downconverting Mixer

24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 1900MHz, NF = 12.5dB,

50Ω Single-Ended RF and LO Ports, 5V Supply

LTC5557 400MHz to 3.8GHz High Linearity

Downconverting Mixer

24.7dBm IIP3 at 1950MHz, 23.7dBm IIP3 at 2.6GHz, NF = 13.2dB, 3.3V Supply

Operation, Integrated Transformer

LTC5575 800MHz to 2.7GHz Direct Conversion

Quadrature Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF

and LO Transformer

Amplifiers/Filters

LTC6412 800MHz, 31dB Range, Analog-Controlled

Variable Gain Amplifier

Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise

Figure, 4mm × 4mm QFN-24

LTC6420-20 Dual Low Noise, Low Distortion

Differential ADC Drivers for 300MHz IF

Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 80mA Supply Current per

Amplifier, 46dBm OIP3 at 100MHz, 3mm × 4mm QFN-20

LTC6421-20 Dual Low Noise, Low Distortion

Differential ADC Drivers for 140MHz IF

Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 40mA Supply Current per

Amplifier, 42dBm OIP3 at 100MHz, 3mm × 4mm QFN-20

LTC6605-7/ LTC6605-10/

LTC6605-14

Dual Matched 7MHz/10MHz/14MHz Filters

with ADC Drivers

Dual Matched 2nd Order Lowpass Filters with Differential Drivers,

Pin-Programmable Gain, 6mm × 3mm DFN-22

Signal Chain Receivers

LTM9002 14-Bit Dual Channel IF/Baseband Receiver

Subsystem

Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers