1
dc919af
DEMO MANUAL DC919A
DESCRIPTION
LTC2207, LTC2206, LTC2205,
LTC2204, LTC2203, LTC2202, LTC2201
16-Bit/14-Bit 10Msps to 105Msps ADCs
Demonstration circuit 919A supports members of a family
of 16-bit/14-bit 10Msps to 105Msps ADCs. Each assembly
features one of the following devices: LTC
®
2207, LTC2206,
LTC2205, LTC2204, LTC2203, LTC2202, or LTC2201 high
speed, high dynamic range ADCs.
Other members of this family include the LTC2208/
LTC2208-14 16-bit/14-bit 130Msps ADC with LVDS out-
puts. These 9mm × 9mm QFN devices are supported by
Demonstration circuit 854 (CMOS outputs) or by Dem-
onstration circuit 996 (LVDS outputs).
Several versions of the 919A demo board supporting a
single-ended clock input, specifically targeted for use
with the 25Msps LTC2203, 20Msps LTC2201 and 10Msps L, LT, LTC, LTM, μModule, Linear Technology and the Linear logo are registered trademarks
and QuikEval and PScope are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
LTC2202 A/D converters, are listed in Table 1. LTC2204,
LTC2205, LTC2206 and LTC2207 have differential clock
inputs but use a single-ended clock input for evaluation
with the DC input on the DC919A board. Depending on the
required sample rate and input frequency, the DC919A is
supplied with the appropriate ADC and with an optimized
input circuit. The circuitry on the analog inputs is optimized
for analog input frequencies from DC to 70MHz or from
1MHz to 70MHz if using the transformer coupled input. For
higher input frequencies, contact the factory for support.
Design files for this circuit board are available at
http://www.linear.com/demo
Table 1. DC919A Variants
DC919 VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY
919A-A LTC2207 16-Bit 105Msps DC - 70MHz
919A-B LTC2206 16-Bit 80Msps DC - 70MHz
919A-C LTC2205 16-Bit 65Msps DC - 70MHz
919A-D LTC2204 16-Bit 40Msps DC -70MHz
919A-E LTC2203 16-Bit 25Msps DC - 70MHz
919A-F LTC2202 16-Bit 10Msps DC - 70MHz
919A-G LTC2207-14 14-Bit 105Msps DC -70MHz
919A-H LTC2206-14 14-Bit 80Msps DC - 70MHz
919A-I LTC2205-14 14-Bit 65Msps DC - 70MHz
919A-J LTC2201 16-Bit 20Msps DC - 70MHz
PERFORMANCE SUMMARY
(TA = 25°C)
PARAMETER CONDITION VALUE
Supply Voltage Depending on Sampling Rate and the A/D Converter Provided, this
Supply Must Provide Up to 500mA.
Optimized for 3.3V
[3.15V ↔ 3.45V Min/Max]
Analog Input Range Depending on PGA Pin Voltage 1.5VP-P to 2.25VP-P
Logic Input Voltages Minimum Logic High 2.4V
Maximum Logic Low 0.8V
Logic Output Voltage
(74VCX245 Output Buffer, VCC = 2.5V)
Minimum Logic High at –1.6mA 2.3V (33Ω Series Terminations)
Maximum Logic Low at 1.6mA 0.7V (33Ω Series Terminations)
Sampling Frequency (Convert Clock Frequency) See Table 1
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dc919af
DEMO MANUAL DC919A
QUICK START PROCEDURE
Demonstration circuit 919A is easy to set up to evaluate
the performance of the LTC2207, LTC2206, LTC2205,
LTC2204, LTC2203, or LTC2202 A/D converters. Refer to
Figure 1 for proper measurement equipment setup and
follow this procedure:
Setup
If a DC718 QuikEval™ II Data Analysis and Collection
System was supplied with the DC919A demonstration
circuit, follow the DC718 Quick Start Guide to install the
required software and for connecting the DC718 to the
DC919A to a PC.
DC919A Demonstration Circuit Board Jumpers
The DC919A demonstration circuit board should have
the following jumper settings as default: (as per Figure 1)
JP1: Output clock polarity: GND
JP2: SENSE: VDD, (Internal reference)
JP3: PGA: GND 2.25V range
JP4: RAND: GND Not randomized
JP5: SHDN: GND Not shutdown
JP6: DITH: GND No internal dithering
Applying Power and Signals to the DC919A
Demonstration Circuit
If a DC718 is used to acquire data from the DC919A, the
DC718 must FIRST be connected to a powered USB port
or provided an external 6V to 9V BEFORE applying 3.3V
across the pins marked “+3.3V” and “PWR GND” on the
DC919A. The DC919A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC718 data collection board is powered by the USB
cable and does not require an external power supply unless
it must be connected to the PC through an unpowered hub
in which case it must be supplied an external 6V to 9V on
turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.
Encode Clock
NOTE: This is a logic compatible input, contrary to the
majority of Linear Technology ADC demo boards. It is not
terminated with 50Ω.
Apply an encode clock to the SMA connector on the DC919A
demonstration circuit board marked “J3 ENCODE INPUT”.
For the best noise performance, the ENCODE INPUT
must be driven with a very low jitter source. A low jitter
3.3V oscillator with direct connection through a barrel is
recommended.
If using a sinusoidal generator, the amplitude should be
as large as possible, up to 3VP-P or 13dBm, filtered and
terminated with a 50Ω thru-terminator. If a generator
with 50Ω output impedance is connected via a cable, it
is recommended that a thru-terminator be used. However,
below 15MHz, it is recommended that a square wave
drive be used.
If a sinusoidal ground referenced signal, or an AC-coupled
signal is used, 1.5V to 1.7V DC bias must be introduced
via a bias tee.
DC919A has provision for a popular surface mount oscil-
lator form and some population options to select this as
the clock source. (Please see schematic.)
If only sinusoidal or clipped sinusoid signal sources are
available as the clock source for scenarios involving sam-
pling rates less than 15Msps to 20Msps, it is recommended
PERFORMANCE SUMMARY
(TA = 25°C)
Convert Clock Level 50Ω Source Impedance, AC-Coupled or Ground Referenced (Convert
Clock Input Is Capacitor Coupled on Board and Terminated with 50Ω.)
2VP-P ↔ 2.5VP-P Sine Wave or
Square Wave
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet
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dc919af
DEMO MANUAL DC919A
QUICK START PROCEDURE
Figure 1. DC919A Setup
that a divide by 4 or divide by 8 be used. If the converter
is to be used at very low sampling rates approaching the
minimum, a higher divide ratio may be required. This is
especially important if undersampling.
If you want to use these converters at less than the minimum
sampling rate, it is recommended that you run the ADC
above the minimum rate, and decimate. If oversampling
low frequencies, the use of a sinusoid is potentially accept-
able, but it must be very clean or the low dV/dt will result
in a great sensitivity to wideband noise in the clock driver.
The use of a divider may require a bandpass filter prior to
the divider in order to achieve best SNR as the divider can
exaggerate phase noise if it is sensitive to GHz frequen-
cies. Contact Linear Technology for recommendations or
in some cases, available clock sources or dividers.
Most generators require filtering or they will compromise
both the SNR and the SFDR of the ADCs.
Generally data sheet FFT plots are taken with 10 pole LC
filters made by TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically related spurs
and broad band noise. Low phase noise Agilent 8644B
generators are used with TTE band pass filters for both
the Clock input and the Analog input. In the case of the
LTC2203/LTC2202/LTC2201 we use a divide by 4.
This demo board is, populated by default for the DC input
path. There is a transformer mounted at T1, but C4, C6,
R9 and R13 are not populated. If a single-ended AC input
is required, the DC input paths must be disconnected by
removing R26, 27, 31 and 32, and the above components
installed.
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dc919af
DEMO MANUAL DC919A
If the transformer input is required, C4 and C6 should be
0.1μF X5R 0402, R9 and R13 should be 10Ω 0402 resistors.
Note that this transformer (ETC1-1T) is poor below 1MHz.
Reduced amplitude signals can be applied to 300kHz.
Applications below 300kHz must be driven directly via
DC inputs.
As there are a significant number of these boards that
are customized, please confirm the population of your
board. The schematic below shows the default population,
the photograph shows the population of a transformer
coupled version. This board may also be populated with
LTC2204-2207 for DC drive applications, in which case,
R33 is a 0.1μF capacitor.
Apply the analog input signal of interest to the SMA con-
nector on the DC919A demonstration circuit board marked
“J2 ANALOG INPUT”. These inputs are capacitive coupled
to a Flux coupled transformers ETC1-1T. In some cases,
where these devices are to be used in undersampling
scenarios, this transformer should be replaced with an
ETC1-1-13 Balun.
The DC919A can be modified for direct DC drive from a
suitable differential signal source.
This may be done by yourself or at special request when
you order the demo board.
If the DC input paths are populated with low value (5.1Ω)
resistors at both ends of these transmission lines, you
must provide a reasonably well balanced differential drive
with 1.25V common mode.
The spacing of these SMA connectors (0.8") allows them
to be mated directly with demo boards for devices such
as the LT1993, LT1994, LT5514 and others.
It is not recommended to drive this ADC in a single-ended
fashion into a single DC input.
An internally generated conversion clock output is available
on pin 3 of J1 and the data samples are available on Pins
7 to 37 of J1 which can be collected via a logic analyzer,
cabled to a development system through a SHORT 2 to 4
inch long 40-pin ribbon cable or collected by the DC718
QuikEval II Data Acquisition Board using the PScope™
System Software provided or down loaded from the Linear
Technology website at http://www.linear.com/software/.
If a DC718 was provided, follow the DC718 Quick Start
Guide and the instructions below.
If data is to be collected by a logic analyzer, pin 40 must
be strapped to OVDD or 2.5V.
(Please see schematic.)
To start the data collection software if PScope.exe is in-
stalled (by default) in \Program Files\LTC\PScope\, double
click the PScope Icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC919A demonstration circuit is properly connected
to the DC718, PScope should automatically detect the
DC919A, and configure itself accordingly. If necessary,
the procedure below explains how to manually configure
PScope.
Under the configure menu, go to ADC Configuration.
Check the Config Manually box and use the following
configuration options:
User configure
16-Bit (or 14-Bit if using -14 versions)
Alignment: Left-16
Bipolar (2’s complement)
Positive clock edge
Type: CMOS
If everything is hooked up properly, powered and a suit-
able convert clock is present, clicking the Collect button
should result in time and frequency plots displayed in
the PScope window. Additional information and help for
PScope is available in the DC718 Quick Start Guide and in
the online help available within the PScope program itself.
Analog Input Network
For optimal distortion and noise performance the RC
network on the analog inputs should be optimized for
different analog input frequencies. At this point in time,
the circuit in Figure 3 for input frequencies below 70MHz.
For input frequencies from 70MHz to 140MHz, the circuit
in Figure 2 is used. These two input networks cover a
QUICK START PROCEDURE
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dc919af
DEMO MANUAL DC919A
broad bandwidth and are not optimized for operation at a
specific input frequency.
In almost all cases, filters will be required on both analog
input and encode clock to provide data sheet SNR.
Narrow band high-Q filters may produce poor SNR results
with Dither enabled. 10% bandpass would be preferred
over 5% bandpass on the analog input. The filters should
be located close to the inputs to avoid reflections from
impedance discontinuities at the driven end of a long
transmission line. Most filters do not present 50Ω outside
the passband.
In cases with long transmission lines, 3dB to 10dB pads
may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
QUICK START PROCEDURE
based on a Gallium Arsenide Gain block prior to the final
filter. This is particularly true at higher frequencies where
IC based operational amplifiers may be unable to deliver
the combination of low noise figure and High IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
For advice on drive circuits or for input frequencies greater
than 70MHz contact the factory for support.
For input frequencies less than 5MHz, or greater than
150MHz, other input networks may be more appropriate.
Please consult the factory for suggestions on drivers
and networks if your signal sources extend outside these
ranges, or if you experience difficulties driving these sug-
gested networks.
0.1μF
AIN+
AIN–
4.7pF
2.2μF
VCM
ANALOG
INPUT
0.1μF
0.1μF
T1
1:1
T1 = MA/COM ETC1-1-13.
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE,
EXCEPT 2.2μF
dc919a F02
25Ω
5Ω
5Ω
10Ω
50Ω
10Ω
25Ω
LTC2203/
LTC2202
Figure 2. Analog Front End Circuit For 70MHz+
Figure 3. Analog Front End Circuit for 1MHz < AIN < 70MHz
0.1μF
AIN+
AIN–
8.2pF
2.2μF
VCM
ANALOG
INPUT
0.1μF T1
1:1
T1 = COILCRAFT WBCI-IT OR
MA/COM ETC1-1T RESISTORS,
CAPACITORS ARE 0402 PACKAGE
SIZE EXCEPT 2.2μF
dc919a F03
25Ω
5Ω
5Ω
10Ω
50Ω
10Ω
25Ω
LTC2203/
LTC2202
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dc919af
DEMO MANUAL DC919A
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 5 C1, C13, C14, C25, C26 CAP., X7R, 0.1μF, 25V, 10% 0603 TDK, C1608X7R1E104K
2 0 C4, C6 (OPEN) CAP., 0603
3 2 C8, C2 CAP., X5R, 2.2μF, 6.3V, 10% 0603 TDK, C1608X5R0J225K
4 3 C3, C5, C7 CAP., C0G, 8.2pF, 50V, 5% 0402 AVX, 04025A8R2JAT
5 7 C9, C15-C19, C28 CAP., X5R, 0.1μF, 10V, 10% 0402 TDK, C1005X5R1A104K
6 1 C20 CAP., X5R, 10μF, 6.3V, 10% 0805 TDK, C2012X5R0J106K
7 1 C21 CAP., X7R, 0.01μF, 50V, 10% 0603 TDK, C1608X7R1H103K
8 1 C22 CAP., X7R, 1.0μF, 16V, 10% 0603 TDK, C1608X7R1C105K
9 1 C23 CAP., X5R, 4.7μF, 10V, 10% 0805 TDK, C2012X5R1A475K
10 0 C27 (OPT) CAP., 100μF, 6.3V 6032
11 3 E1, E3, E4 TESTPOINT, TURRET, 0.061" MILL-MAX, 2308-2-00-44
12 6 JP1-JP6 0.079 SINGLE ROW HEADER, 3-PIN SAMTEC, TMM103-02-L-S
13 6 JP1-JP6 SHUNT SAMTEC, 2SN-BK-G
14 1 J1 CON, HDR, 0.1 × 0.1 CNTRS, 40-PIN SAMTEC, TSW-120-07-L-D
15 3 J2, J3, J4 CON., SMA 50Ω EDGE-LANCH CONNEX, 132357
16 0 OSC1 (OPT)
17 4 RN1, RN2, RN3, RN4 RES ARRAY, 33Ω, 5%, 0402 VISHAY, CRA04S0803330JRT7
18 4 R1, R2, R20, R21 RES., CHIP, 10k, 1/16W, 5% 0402 AAC, CR05-103JM
19 2 R3, R7 RES., CHIP, 1k, 1/16W, 5% 0603 AAC, CR16-102JM
20 0 R4, R6, R9, R11-R13, R24, R30 (OPEN) RES., CHIP, 0603
21 2 R26, R27 RES., CHIP, 10Ω, 1/16W, 5% 0603 AAC, CR16-100JM
22 2 R5, R28 RES., CHIP, 33Ω, 1/16W, 5% 0402 VISHAY, CRCW0402330JRT6
23 1 R8 RES., CHIP, 51Ω, 1/16W, 5% 0402 AAC, CR05-510JM
24 1 R29 RES., CHIP, 1k, 1/16W, 5% 0402 AAC, CR05-102JM
25 2 R10, R14 RES., CHIP, 5.1Ω, 1/16W, 5% 0402 AAC, CR05-5R1JM
26 2 R31, R32 RES., CHIP, 0Ω, 1/16W, 0402 AAC, CJ05-000M
28 2 R12, R11 RES., CHIP, 24.9Ω, 1/16W, 1% 0603 VISHAY, CRCW060324R9FRT6
29 3 R17, R18, R19 RES., CHIP, 10k, 1/16W, 5% 0603 AAC, CR16-103JM
30 1 R22 RES., CHIP, 105k, 1/16W, 1% 0603 AAC, CR16-1053FM
31 1 R23 RES., CHIP, 100k, 1/16W, 5% 0603 AAC, CR16-104JM
32 1 R25 RES., CHIP, 1Ω, 1/8W, 5% 0805 AAC, CR10-1R0JM
33 1 T1 TRANSFORMER, 1:1, ETC1-1T M/A-COM, ETC1-1T
34 2 U3, U2 I.C., 74VCX245BQX, DQFN20 FAIRCHILD, 74VCX245BQX
35 2 U4, U5 I.C., NC7SV86 SC70-5 FAIRCHILD, NC7SV86P5X
36 1 U6 I.C., 24LC025, TSSOP-8 MICROCHIP, 24LC025 I /ST
37 1 U7 I.C., LT1763, SO8 LINEAR TECH., LT1763CS8
38 4 (STAND-OFF) STAND-OFF, NYLON 0.25" tall KEYSTONE, 8831(SNAP ON)
7
dc919af
DEMO MANUAL DC919A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM
INPUT
ANALOG
INPUT
ENCODE
+3.3V
VDD
GND
VDD
OPEN
SENSE
PGA
VDD
GND
VDD
OVP
GND
SHDN
GND
VDD VDD
GND
DITH
OGND
RAND
GND
DCIN+
40
DC919A-A
Assembly Type
DC < Ain < 70MHz
*
0.01uF
LTC2205CUK
INPUT FREQUENCY
65
LTC2204CUK
16
LTC2207CUK
VERSION TABLE
16
25
DC919A-C
DC919A-E LTC2203CUK
DC919A-B
DC919A-F
DC919A-D
16
U1
80
16
LTC2202CUK
16
Bits
105
LTC2206CUK
MspsR33
0 OHM
0 OHM
0.01uF
0.01uF
0.01uF
DC < Ain < 70MHz
DC < Ain < 70MHz
DC < Ain < 70MHz
DC < Ain < 70MHz
DC < Ain < 70MHz 16 10
14
105
DC919A-G LTC2207CUK-14
DC919A-H LTC2206CUK-14
0.01uF
0.01uF
DC < Ain < 70MHz
DC < Ain < 70MHz 14 80
14 65
DC919A-I LTC2205CUK-14
DC919A-J LTC2201CUK
0.01uF
0 OHM
DC < Ain < 70MHz
DC < Ain < 70MHz 16 20
VDD
VDD
VDD
OVP
VDD
OVP
OVP
OVP
OVP
VDD VDD
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN
CHECKED
APPROVED
ENGINEER
DESIGNER
TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
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A
DC919A
Tuesday, April 17, 2012
11
June Wu 4/14/05
D. Redmayne 4/14/05
16 BIT HIGH SPEED ADC
LTC2203 FAMILY
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN
CHECKED
APPROVED
ENGINEER
DESIGNER
TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
7+,6&,5&8,7,635235,(7$5<72/,1($57(&+12/2*<$1'
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&86720(5127,&(
A
DC919A
Tuesday, April 17, 2012
11
June Wu 4/14/05
D. Redmayne 4/14/05
16 BIT HIGH SPEED ADC
LTC2203 FAMILY
SIZE
SCALE:
CAGE CODE
DWG NO
REV
SHEET OF
FILENAME:
TITLE
CONTRACT NO.
APPROVALS
DATE
DRAWN
CHECKED
APPROVED
ENGINEER
DESIGNER
TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Phone: (408)432-1900
Fax: (408)434-0507
7+,6&,5&8,7,635235,(7$5<72/,1($57(&+12/2*<$1'
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&86720(5127,&(
A
DC919A
Tuesday, April 17, 2012
11
June Wu 4/14/05
D. Redmayne 4/14/05
16 BIT HIGH SPEED ADC
LTC2203 FAMILY
R31
0
R31
0C1
0.1uF
C1
0.1uF
RN4B 33RN4B 33
R14
5.1
R14
5.1
R6 open
R6 open
C20
10uF
6.3V
C20
10uF
6.3V
U2
74VCX245BQX
U2
74VCX245BQX
T/R 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
R2
10K
R2
10K
RN1C 33RN1C 33
C26
0.1uF
C26
0.1uF
U4
NC7SV86P5X
U4
NC7SV86P5X
1
24
53
R28
33
R28
33
C21 0.01uF
C21 0.01uF
U6
24LC025
U6
24LC025
A0
1
A1
2
A2
3
A3
4SDA 5
SCL 6
WP 7
VCC 8
+C27
100uF
6.3V
opt.
+C27
100uF
6.3V
opt.
J2J2
C13
0.1uF
C13
0.1uF
RN2A 33RN2A 33
E1E1
U7
LT1763
U7
LT1763
OUT
1
ADJ
2
GND
3
BYP
4SHDN 5
GND 6
GND 7
IN 8
R18
10K
R18
10K
RN3B 33RN3B 33
JP3JP3
1
2
3
R26
10
R26
10
C23
4.7uF
C23
4.7uF
R22
105K
R22
105K
R32
0
R32
0
RN3A 33RN3A 33
C19
0.1uF
C19
0.1uF
R13
open
R13
open U3
74VCX245BQX
U3
74VCX245BQX
T/R 1
A0 2
A1 3
A2 4
A3 5
A4 6
A5 7
A6 8
A7 9
GND 10
B7
11
B6
12
B5
13
B4
14
B3
15
B2
16
B1
17
B0
18
OE
19
VCC
20
RN2C 33RN2C 33
R25
1
R25
1
RN2D 33RN2D 33
R24
open
R24
open
C5
8.2pF
C5
8.2pF
R21 10K
R21 10K
J1
3201S-40G1
J1
3201S-40G1
1
122
3
344
5
566
7
788
9
910 10
11
11 12 12
13
13 14 14
15
15 16 16
17
17 18 18
19
19 20 20
21
21 22 22
23
23 24 24
25
25 26 26
27
27 28 28
29
29 30 30
31
31 32 32
33
33 34 34
35
35 36 36
37
37 38 38
39
39 40 40
C16
0.1uF
C16
0.1uF
JP1JP1
1
2
3
R5 33
R5 33
RN3C 33RN3C 33
C28
0.1uF
C28
0.1uF
E3E3
R8
51
R8
51
R7 1KR7 1K
C15
0.1uF
C15
0.1uF
C9
0.1uF
C9
0.1uF
R23
100K
R23
100K
R19
10K
R19
10K
RN2B 33RN2B 33
JP2JP2
1
2
3
R33
*
R33
*
OSC1
opt.
OSC1
opt.
EN
1
GND
2
Fo 3
Vdd 4
T1
ETC1-1T
T1
ETC1-1T
4
5 1
3
2
EXPOSED PAD
U1
*
EXPOSED PAD
U1
*
Sense
1
Vcm
2
Vdd
3
Vdd
4
GND
5
Ain+
6
Ain-
7
GND
8
GND/ENC+
9
GND/ENC-
10
GND
11
Vdd
12
Vdd
13
GND
15
SHDN
16
OVdd 37
D12 39
OF 43
MODE 45
RAND 46
PGA 47
GND 48
CLKOUT- 29
CLKOUT+ 30
GND
49
DITH
17
D0
18
Vdd
14
D1
19
D2
20
D3
21
D4
22
OGND
23
OVdd
24
OVdd 25
D5 26
D6 27
D7 28
OGND 31
D8 32
D9 33
D10 34
D11 35
OVdd 36
OGND 38
D13 40
D14 41
D15 42
OE 44
C8
2.2uF
C8
2.2uF
R1
10K
R1
10K
RN1D 33RN1D 33
C22
1.0uF
C22
1.0uF
C25
0.1uF
C25
0.1uF
R3 1KR3 1K
C17
0.1uF
C17
0.1uF
R12
open
R12
open
E4E4
R29
1K
R29
1K
C14
0.1uF
C14
0.1uF
RN3D 33RN3D 33
C3
8.2pF
C3
8.2pF
JP4JP4
1
2
3
R27
10
R27
10
JP5JP5
1
2
3
RN4A 33RN4A 33
U5
NC7SV86P5X
U5
NC7SV86P5X
1
2
4
53
RN4D 33RN4D 33
RN1B 33RN1B 33
J3J3
RN4C 33RN4C 33
R11
open
R11
open
C18
0.1uF
C18
0.1uF
R20 10K
R20 10K
C7
8.2pF
C7
8.2pF
J4J4
JP6JP6
1
2
3
R10
5.1
R10
5.1
R17
10K
R17
10K
RN1A 33RN1A 33
R9
open
R9
open
R30
open
R30
open
C4 open
C4 open
C6 openC6 open
R4 openR4 open
C2 2.2uF
C2 2.2uF
8
dc919af
DEMO MANUAL DC919A
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2012
LT 0512 • PRINTED IN USA
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT
OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety
measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union
directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date
of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU
OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS
FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR
ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or
agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance,
customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and
observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-
tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation