Type Package Marking
TLE4254GA PG-DSO-8 4254GA
TLE4254GS PG-DSO-8 4254GS
TLE4254EJ A PG-DSO-8 exposed pad 4254EJA
TLE4254EJ S PG-DSO-8 exposed pad 4254EJS
PG-DSO-8
PG-DSO-8 exposed pad
Data Sheet 1 Rev. 1.2, 2009-11-18
High Accuracy Low Dropout Voltage Tracking
Regulator
TLE4254
1Overview
Features
• 70 mA output current capability
• Very tight output tracking tolerance to reference
• Output voltage adjustable down to 2.0 V
• Stable operation with 1 µF ceramic output capacitor
• Flexibility of output voltage adjust higher or lower than reference,
proportional to the reference voltage (version GA / EJ A)
• Status output to indicate short circuits at the output (version GS / EJ S)
• Very low dropout voltage of typ. 0.2 V @ maximum output current
• Combined reference / enable input
• Very low current consumption in OFF mode
• Wide input voltage range -20 V ≤ VI ≤ +45 V
• Wide temperature range: -40 °C ≤ Tj ≤ 150 °C
• Output protected against short circuit to GND and battery
• Input protected against reverse polarity
• Overtemperature protection
• Green product (RoHS compliant)
• AEC qualified
Functional Description
The TLE4254 is a monolithic integrated low-dropout voltage tracking regulator with high accuracy in small PG-
DSO-8 packages. The IC is designed to supply off-board systems, e. g. sensors in powertrain management
systems under the severe conditions of automotive applications. Therefore, the IC is equipped with additional
protection functions against reverese polarity and short circuit to GND and battery.
With supply voltages up to 40 V, the output voltage follows a reference voltage applied at the adjust input with very
high accuracy. The reference voltage applied directly to the adjust input or by an e. g. external resistor divider can
be 2.0 V at minimum.
The output is able to drive loads up to 70 mA while the device follows with high accuracy the e. g. 5 V output of a
main voltage regulator acting as reference.
TLE4254
Overview
Data Sheet 2 Rev. 1.2, 2009-11-18
The TLE4254 can be set into shutdown mode in order to reduce the current consumption to a minimum. This suits
the IC for low power battery applications.
Versions “GS” and “EJ S” offer an open collector status output indicating an overvoltage and undervoltage error
condition of the output voltage.
Versions “GA” and “EJ A” allow setting the output voltage to higher value than the reference voltage by connecting
a voltage divider to the feedback pin “FB”.
Data Sheet 3 Rev. 1.2, 2009-11-18
TLE4254
Block Diagram
2 Block Diagram
Figure 1 Block Diagram TLE4254GA and TLE4254EJ A
Figure 2 Block Diagram TLE4254GS and TLE4254EJ S
Saturation
Control and
Protection
circuits
Temperature
control
+
-
I
GND
Q
FB
EN/
ADJ
TLE4254GA
TLE4254EJ A
+
-
=
typ.
1.4V
Saturation
Control and
Protection
circuits
Temperature
control
+
-
I
GND
Q
ST
EN/
ADJ
TLE4254GS
TLE4254EJ S
+
-
=
typ.
1.4V
Status
Generator
TLE4254
Pin Definitions and Functions
Data Sheet 4 Rev. 1.2, 2009-11-18
3 Pin Definitions and Functions
3.1 Pin Assignment TLE4254GA and TLE4254GS
Figure 3 Pin Configurations TLE4254GA and TLE4254GS
3.2 Pin Functions TLE4254GA and TLE4254GS
Pin Symbol Function
1Q Tracker Output.
Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR
requirements given in the table “Functional Range”.
2, 3,
6, 7
GND Ground reference.
Interconnect the pins on PCB. Connect to heatsink area.
4FB
(version GA)
Feedback input (version GA only).
Non inverting input of the internal error amplifier to control the output voltage.
Connect this pin directly to the output pin in order to obtain lower or equal output voltages
with respect to the reference voltage.
Connect a voltage divider for higher output voltages than the reference.
(See also application information.)
4ST
(version GS)
Tracking Regulator Status Output (version GS only).
Open collector output. Connect via a pull-up resistor to a positive voltage rail.
A low signal indicates fault condions at the regulator’s output.
5EN/ADJ Adjust / Enable.
Connect the reference to this pin. The active high signal of the reference turns on the device;
a low signal disables the IC. The reference voltage can be connected directly or by a voltage
divider for lower output voltages (see application information).
8I Input.
IC supply. For compensating line influences, a capacitor close to the IC terminals is
recommended.
GND
GND
GND
FB EN/ADJ
I
Q
4
3
2
1
TLE 4254
GA
GND
5
6
7
8
GND
GND
GND
ST EN/ADJ
I
Q
4
3
2
1
TLE 4254
GS
GND
5
6
7
8
Data Sheet 5 Rev. 1.2, 2009-11-18
TLE4254
Pin Definitions and Functions
3.3 Pin Assignment TLE4254EJ A and TLE4254EJ S
Figure 4 Pin Configurations TLE4254EJ A and TLE4254EJ S
3.4 Pin Functions TLE4254EJ A and TLE4254EJ S
Pin Symbol Function
1Q Tracker Output.
Block to GND with a capacitor close to the IC terminals, respecting capacitance and ESR
requirements given in the table “Functional Range”.
2, 3,
7
n.c. not connected
connect to GND
4FB
(version EJ A)
Feedback input (version EJ A only).
Non inverting input of the internal error amplifier to control the output voltage.
Connect this pin directly to the output pin in order to obtain lower or equal output voltages
with respect to the reference voltage.
Connect a voltage divider for higher output voltages than the reference.
(See also application information.)
4ST
(version EJ S)
Tracking Regulator Status Output (version GS only).
Open collector output. Connect via a pull-up resistor to a positive voltage rail.
A low signal indicates fault condions at the regulator’s output.
5EN/ADJ Adjust / Enable.
Connect the reference to this pin. The active high signal of the reference turns on the
device; a low signal disables the IC. The reference voltage can be connected directly or by
a voltage divider for lower output voltages (see application information).
6GND Ground reference.
Interconnect the pins on PCB. Connect to heatsink area.
8I Input.
IC supply. For compensating line influences, a capacitor close to the IC terminals is
recommended.
Pad – Exposed Pad
connect to GND
QF
QF
*1'
)% (1$'-
,
4
7/((-$
QF
QF
QF
*1'
67 (1$'-
,
4
7/((-6
QF
TLE4254
General Product Characteristics
Data Sheet 6 Rev. 1.2, 2009-11-18
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground (unless otherwise specified).
Not subject to production test; specified by design.
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Voltages
4.1.1 Input voltage VI-20 45 V –
4.1.2 Adjust / Enable input voltage VADJ/EN -20 45 V –
4.1.3 Output voltage VQ-5 45 V –
4.1.4 Feedback input voltage (version
GA / EJ A)
VFB -20 45 V –
4.1.5 Status output voltage (version
GS / EJ S)
VST -0.3 7 V –
Temperatures
4.1.6 Junction Temperature Tj-40 150 °C–
4.1.7 Storage Temperature Tstg -50 150 °C–
ESD Rating
4.1.8 ESD Susceptibility |VESD,HBM|4–kVHBM
2)
2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114
4.1.9 |VESD,CDM|1 – kV CDM 3)
3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1
Data Sheet 7 Rev. 1.2, 2009-11-18
TLE4254
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Input Voltage VI445VVI ≥ VQ + Vdr
4.2.1 Adjust / Enable Input Voltage
(Voltage Tracking Range)
VADJ/EN 2.0 – V –
4.2.2 Junction Temperature Tj-40 150 °C–
4.2.3 Output Capacitor CQ1– µF–
1)
1) Not subject to production test; specified by design.
4.2.4 ESRCQ –5 Ω– 1)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
PG-DSO-8:
4.3.1 Junction to Ambient RthJA – 155 – K/W Footprint only 1) 2)
1) Not subject to production test; specified by design.
2) Package mounted on PCB FR4; 80 x 80 x 1.5 mm; 35 µm Cu, 5 µm Sn; horizontal position; zero airflow.
4.3.2 – 96 – K/W 300 mm2 PCB heatsink area 1) 2)
4.3.3 – 86 – K/W 600 mm2 PCB heatsink area 2) 1)
PG-DSO-8 exposed pad:
4.3.4 Junction to Case RthJC – 15 – K/W measured to exposed pad
4.3.5 Junction to Ambient RthJA –47–K/W–
3)
3) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.6 – 159 – K/W Footprint only 2) 1)
4.3.7 – 71 – K/W 300 mm2 PCB heatsink area 2) 1)
4.3.8 – 60 – K/W 600 mm2 PCB heatsink area 2) 1)
TLE4254
Electrical Characteristics
Data Sheet 8 Rev. 1.2, 2009-11-18
5 Electrical Characteristics
5.1 Tracking Regulator
The output voltage VQ is controlled by comparing it to the voltage applied at pin ADJ/EN and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit and the load. To ensure stable operation, the
output capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” have to be maintained. For details see also the typical performance graph “Output Capacitor Series
Resistor ESRCQ vs. Output Current IQ”. Also, the output capacitor shall be sized to buffer load transients.
An input capacitor CI is strongly recommended to buffer line influences. Connect the capacitors close to the IC
terminals.
Protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events. These
safeguards contain output current limitation, reverse polarity protection as well as thermal shutdown in case of
overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at high input voltages.
The overtemperature protection circuit prevents the IC from immediate destruction under fault conditions (e. g.
output continuously short-circuited) by reducing the output current. A thermal balance below 200 °C junction
temperature is established. Please note that a junction temperature above 150 °C is outside the maximum ratings
and reduces the IC lifetime.
The TLE4254 allows a negative supply voltage. However, several small currents are flowing into the IC increasing
its junction temperature. This has to be considered for the thermal design, respecting that the thermal protection
circuit is not operating during reverse polarity condition.
Table 1 Electrical Characteristics Tracking Regulator
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ (version GA / EJ A); -40 °C ≤ Tj ≤ 150 °C; CQ = 1 µF;
all voltages with respect to ground (unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
5.1.1 Output Voltage Tracking
Accuracy
∆VQ = VEN/ADJ - VQ
∆VQ-5 – 5 mV 8 V ≤ VI ≤ 18 V;
0.1 mA ≤ IQ ≤ 60 mA;
VADJ/EN = 5 V
5.1.2 -10 – 10 mV 5.5 V ≤ VI ≤ 26 V;
0.1 mA ≤ IQ ≤ 60 mA;
VADJ/EN = 5 V
5.1.3 -10 – 10 mV 5.5 V ≤ VI ≤ 32 V;
0.1 mA ≤ IQ ≤ 30 mA;
VADJ/EN = 5 V
5.1.4 Load Regulation
steady-state
|dVQ,load|– 1 10 mV IQ = 0.1 mA to 70 mA;
VADJ/EN = 5 V
5.1.5 Line Regulation
steady-state
|dVQ,line|– 1 10 mV VI = 5.5 V to 32 V;
IQ = 5 mA
VADJ/EN = 5 V
Data Sheet 9 Rev. 1.2, 2009-11-18
TLE4254
Electrical Characteristics
5.1.6 Power Supply Ripple
Rejection
PSRR 60 – – dB fripple = 100 Hz;
Vripple = 1 Vpp
IQ = 5 mA
CQ = 10 µF, ceramic type 1)
5.1.7 Dropout Voltage
Vdr = VI - VQ
Vdr – 200 400 mV IQ = 70 mA 2)
5.1.8 Output Current Limitation IQ,max 71 100 150 mA VQ = (VADJ/EN - 0.1 V);
VADJ/EN = 5 V
5.1.9 Reverse Current IQ-4 -2 – mA VI = 0 V;
VQ = 32 V;
VADJ/EN = 5 V
5.1.10 Reverse Current
at Negative Input Voltage
II-5 -3 – mA VI = -16 V;
VQ = 0 V;
VADJ/EN = 5 V
Feedback Input FB (version GA / EJ A only):
5.1.11 Feedback Input Biasing
Current
IFB –0.10.5µAVFB = 5 V
Overtemperature Protection:
5.1.12 Junction Temperature
Equilibrium
Tj,eq 151 – 200 °C Tj increasing due to power
dissipation generated
by the IC 1)
1) Parameter not subject to production test; specified by design.
2) Measured when the output voltage VQ has dropped 100 mV from its nominal value.
Table 1 Electrical Characteristics Tracking Regulator
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ (version GA / EJ A); -40 °C ≤ Tj ≤ 150 °C; CQ = 1 µF;
all voltages with respect to ground (unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
TLE4254
Electrical Characteristics
Data Sheet 10 Rev. 1.2, 2009-11-18
Typical Performance Characteristics Tracking Regulator
Tracking Accuracy ∆VQ vs.
Junction Temperature Tj
Output Capacitor Series Resistor
ESRCQ vs. Output Current IQ
Output Capacitor Series Resistor
ESRCQ vs. Output Current IQ
Output Voltage VQ vs.
Adjust Voltage VADJ,EN
Output Voltage VQ vs.
Input Voltage VI
-40
T
j
[°C]
-20 20 40 80 100
∆
V
Q
[mV]
dVQ-Tj.vsd
-1
-2
-3
0
0 60 140120
I
Q
= 0.1 mA
I
Q
= 70 mA
-4
ESR-IQ_1u.vsd
1
0.1
0.01
ESR
CQ
[Ω]
0
I
Q[mA]
30 45
15 60
10
C
Q = 1 µF
6 V <
V
I < 28 V
-40 °C <
T
j < 150 °C
Stable
Region
E S R-IQ_470n.vs d
1
0.1
0.01
ESR
CQ
[Ω]
0
IQ
[mA]
30 45
15 60
10
C
Q
= 470 nF
6 V <
V
I
< 28 V
-40 °C <
T
j
< 150 °C
Stable
Region
V
Q
[V]
VQ-V ADJ.vsd
3
2
1
4
V
I
= 13.5 V
234
1
V
ADJ
[V]
T
j
= 25 °C
V
Q
[V]
VQ-VI.vsd
3
2
1
4
V
ADJ
= 5 V
57
3
V
I
[V]
T
j
= 25 °C
1
5
V
dr
Data Sheet 11 Rev. 1.2, 2009-11-18
TLE4254
Electrical Characteristics
Output Current Limitation IQ,max
vs. Input Voltage VI, VADJ,EN = 5V
Output Current Limitation IQ,max
vs. Input Voltage VI, VADJ,EN = 2V
Reverse Output Current IQ vs.
Output Voltage VQ
Dropout Voltage Vdr vs.
Output Current IQ
Dropout Voltage Vdr vs.
Junction Temperature Tj
Reverse Current II vs.
Input Voltage VI
Typical Performance Characteristics Tracking Regulator
0
VI
[V]
20 30
IQ
[mA]
SOA_5V.VSD
60
40
20
80
10 40
120
T
j
= 25 °C
V
ADJ
= 5 V
T
j
= 150 °C
T
j
= -40 °C
0
VI
[V]
20 30
IQ
[mA]
S OA _2V .V S D
60
40
20
80
10 40
120
T
j
= 25 °C
V
ADJ
= 2 V
T
j
= 150 °C
T
j
= -40 °C
0
VQ
[V]
16 24
IQ
[mA]
IQ-V Q.vsd
-2
-3
-4
-1
832
+1
V
I = 0 V
V
ADJ = 5 V
T
j = 150 °C
T
j = -40 °C
0
0.1
I
Q[mA]
110
V dr-IQ _lo g.v sd
100
10
1000
70
V
dr
[mV]
T
j
= 25 °C
-40
T
j
[°C]
-20 20 40 80 100
Vdr
[mV]
Vdr-Tj.vsd
250
150
300
060 140120
IQ
= 70 mA
350
100
-20
V
I
[V]
-10 -5
I
I
[mA]
II-V I.vsd
-2
-3
-4
-1
-15 0
+1
T
j
= 150 °C
T
j
= -40 °C
V
Q
= 0 V
V
ADJ
= 5 V
TLE4254
Electrical Characteristics
Data Sheet 12 Rev. 1.2, 2009-11-18
5.2 Current Consumption
Table 2 Electrical Characteristics Current Consumption
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ (version GA / EJ A); -40 °C ≤ Tj ≤ 150 °C; CQ = 1 µF
all voltages with respect to ground (unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.13 Quiescent Current
Stand-by Mode
Iq1 –15µAVADJ/EN ≤ 0.4 V;
Tj ≤ 125 °C
5.2.14 Current Consumption
Iq = II - IQ
Iq2 –5080µAIQ ≤ 100 µA;
VADJ/EN = 5 V
5.2.15 – 9 15 mA IQ ≤ 70 mA;
VADJ/EN = 5 V
Typical Performance Characteristics Current Consumption
Quiescent Current Iq1 vs.
Junction Temperature Tj
Current Consumption Iq2 vs.
Output Current IQ
Current Consumption Iq vs.
Input Voltage VI
Iq1-Tj.v sd
1
0.1
I
q1
[µA]
-40
Tj
[°C]
-20 20 40 80 100
060 140120
V
I
= 13.5V
V
EN/ADJ
= 0.2 V
0.1
I
Q
[mA]
110
Iq-IQ_l og.vs d
1
0,1
70
T
j
= -40 °C
I
q
[mA]
10
0,04
T
j
= 150 °C
0
Iq[mA]
20 30
V
I
[V]
Iq_VI.vs d
1.2
0.8
0.4
10 40
0
1.8
V
ADJ
= 5 V
I
Q
= 1 mA
T
j
= 25 °C
Data Sheet 13 Rev. 1.2, 2009-11-18
TLE4254
Electrical Characteristics
5.3 Adjust / Enable Input
In order to reduce the quiescent current to a minumum, the TLE4254 can be switched to stand-by mode by setting
the adjust/enable input “ADJ/EN” to “low”.
In case the pin “ADJ/EN is left open, an internal pull-down resistors keeps the voltage at the pin low and therefore
ensures that the regulator is switched off.
Table 3 Electrical Characteristics Adjust / Enable
VI = 13.5 V; VADJ/EN ≥ 2.0 V; VFB = VQ (version GA / EJ A); -40 °C ≤ Tj ≤ 150 °C; CQ = 1 µF
all voltages with respect to ground (unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
5.3.16 Adjust / Enable
Low Signal Valid
VADJ/EN,low ––0.4VVQ = 0 V;
IQ ≤ 5 µA @ Tj ≤ 125 °C
5.3.17 Adjust / Enable
High Signal Valid
(Tracking Region)
VADJ/EN,high 2––VVQ settled
5.3.18 Adjust / Enable
Input Current
IADJ/EN –23µAVADJ/EN = 5 V
5.3.19 Adjust / Enable
Input Current
if Input tied to GND
IADJ/EN –0.30.6mAVADJ/EN = 5 V;
VI = 0 V
5.3.20 Adjust / Enable
internal pull-down resistor
RADJ/EN 1.7 2.5 3.3 MΩ
Typical Performance Characteristics Adjust / Enable Input
Adjust / Enable Input
Current IADJ/EN vs. Tj
Adjust / Enable Input
Current IADJ/EN vs. VI
Startup Sequence
VQ vs. VADJ,EN
-50
Tj
[° C ]
50 100
IAD J
[µA ]
IADJ-Tj .vsd
2.3
2.2
2.1
2.4
0 150
2.5
VI
= 13.5 V
VADJ
= 5 V
0
V
I
[V]
10 30
IADJ_ VI.v s d
10
1
40
I
ADJ
[µA]
100
20
T
j
= -40 °C
T
j
= 150 °C
V
Q
[V]
VQ-V ADJ.vsd
3
2
1
4
V
I
= 13.5 V
234
1
V
ADJ
[V]
T
j
= 25 °C
TLE4254
Electrical Characteristics
Data Sheet 14 Rev. 1.2, 2009-11-18
5.4 Status Output (version GS / EJ S only)
The status output ST indicates an overvoltage or undervoltage situation at the regulator’s output Q. Therefore, the
output voltage VQ is compared to the reference voltage VADJ/EN. Variations of the output voltage are indicated by
a low signal at the status output ST. Transients shorter than the status reaction time tST,r will not trigger the status
output.
The status output ST is an open collector output, requiring a pull-up resisitor to a positive voltage rail.
Table 4 Electrical Characteristics Status Output ST (Version GS / EJ S only)
VI = 13.5 V; VADJ/EN ≥ 2.0 V; -40 °C ≤ Tj ≤ 150 °C; CQ = 1 µF
all voltages with respect to ground (unless otherwise specified).
Pos. Parameter Symbol Limit Values Unit Test Condition
Min. Typ. Max.
5.4.21 Status switching threshold,
undervoltage
VQ,UV VADJ/EN
- 120
VADJ/EN
- 70
VADJ/EN
- 50
mV VQ decreasing
5.4.22 Status switching threshold,
overvoltage
VQ,OV VADJ/EN
+ 50
VADJ/EN
+ 70
VADJ/EN
+ 120
mV VQ increasing
5.4.23 Status reaction time tST,r 10 15 30 µs –
5.4.24 Status output
low voltage
VST,low ––0.4VIST = 1 mA;
VI ≥ 4 V
5.4.25 Status output
sink current limitation
IST,max 1––mAIST = 1 mA;
VST = 0.8 V
5.4.26 Status output
leakage current
IST,leak –02µAVQ = VADJ/EN
VST = 5 V
Data Sheet 15 Rev. 1.2, 2009-11-18
TLE4254
Application Information
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
The application circuits shown are simplified examples. The function must be verified in the real application.
Figure 5 Application circuit: Output voltage VQ equal to reference voltage VADJ/EN
Figure 5 shows a typical schematic for applications where the tracker output voltage VQ equals the reference
voltage VREF applied to the pin “EN/ADJ”. At version GA / EJ A, the pin FB is directly connected to the output “Q”.
The reference voltage is directly applied to “EN/ADJ”.
ADJ
I
Q
EN/
GND
TLE4254GA
TLE4254EJ A
8
2, 3, 6, 7
5
1
VDD
I/O
IQ
GND
VBAT
e.g. off board
supply,
sensors
VREF
micro controller
e.g.
C167,
XC16X
TC17xx
Main µC supply
e.g.
TLE4271-2
TLE4471
TLE6368...
FB 4
EN/
ADJ
IQ
GND
TLE4254GS
TLE4254EJ S
8
5
1
micro controller
e.g.
C167,
XC16X
TC17xx
VDD
I/O
Main µC supply
e.g.
TLE4271-2
TLE4471
TLE6368...
IQ
GND
VBAT
VQ < VREF
VREF
ST
4
2, 3, 6, 7
I/O
TLE4254
Application Information
Data Sheet 16 Rev. 1.2, 2009-11-18
Figure 6 Application circuit: Output voltage VQ lower than reference voltage VREF
Status Output feedbacked to microcontroller (version GS / EJ S)
In order to obtain a lower output voltage VQ at the tracker output than the reference voltage VREF, a voltage divider
according to Application circuit: Output voltage VQ lower than reference voltage VREF Status Output
feedbacked to microcontroller (version GS / EJ S) has to be used. The output voltage VQ then calculates:
With a given reference voltage VREF, the desired output voltage VQ and the resistor value R1ADJ, the resistor value
for R2ADJ is given by:
Taking into consideration also the effect of the internal EN/ADJ pull-down resistor, the external resistor divider’s
R2ADJ has to be selected to:
EN/
ADJ
IQ
GND
TLE4254GS
TLE4254EJ S
8
5
1
micro controller
e.g.
C167,
XC16X
TC17xx
VDD
I/O
Main µC supply
e.g.
TLE4271-2
TLE4471
TLE6368...
IQ
GND
VBAT
VQ < VREF
R1 ADJ
R2 ADJ
VREF
ST
4
2, 3, 6, 7
I/O
VQVREF
R2ADJ
R1ADJ R2ADJ
+
----------------------------------------


⋅=
R2ADJ R1ADJ
VQ
VREF VQ
–
---------------------------


⋅=
R2ADJ select,
R2ADJ RPullDown min,
⋅
RPullDown min,R2ADJ
–
----------------------------------------------------------


=
Data Sheet 17 Rev. 1.2, 2009-11-18
TLE4254
Application Information
Figure 7 Application circuit: Output voltage VQ higher than reference voltage VREF (version GA / EJ A
only)
For output voltages higher than the reference voltage, the voltage divider has to be applied between the feedback
and the output according to Application circuit: Output voltage VQ higher than reference voltage VREF
(version GA / EJ A only). The equation for the output voltage with respect to the reference voltage is given by:
Keep in mind that the input voltage has to be at minimum equal to the output voltage plus the dropout voltage of
the regulator.
With a given reference voltage VREF, the desired output voltage VQ and the resistor value R1FB, the resistor value
for R2FB is given by:
4
ADJ
IFB
Q
EN/
GND
TLE4254GA
TLE4254EJ A
8
2, 3, 6, 7
5
1
VDD
I/O
IQ
GND
VBAT
VQ > VREF
VREF
R1FB
R2FB
micro controller
e.g.
C167,
XC16X
TC17xx
Main µC supply
e.g.
TLE4271-2
TLE4471
TLE6368...
VQVREF
R1FB R2FB
+
R2FB
---------------------------------


⋅=
R2FB R1FB
VREF
VQVREF
–
---------------------------


⋅=
TLE4254
Package Outlines
Data Sheet 18 Rev. 1.2, 2009-11-18
7 Package Outlines
Figure 8 Outline and footprint PG-DSO-8
Find all packages, sorts of packing and others at the Infineon Internet Page “Packages”:
http://www.infineon.com/packages.Dimensions in mm
+0.06
0.19
0.35 x 45˚
1)
-0.2
4
C
8 MAX.
0.64
±0.2
6
±0.25
0.2 8x
MC
1.27
+0.1
0.41 0.2 MA
-0.06
1.75 MAX.
(1.45)
±0.07
0.175
B
8x
B
2)
Index Marking
5-0.21)
41
85
A
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01181
0.1
HLG05506
e
A
B
L
Reflow Soldering
Dimensions:
e = 1.27
A = 5.69
L = 1.31
B = 0.65
Data Sheet 19 Rev. 1.2, 2009-11-18
TLE4254
Package Outlines
Outline and footprint PG-DSO-8 exposed pad
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
PG-DSO-8-27-PO V01
14
85
8
14
5
8x
0.41
±0.09 2)
M
0.2 DC A-B
1.27 C
Stand Off
+0
-0.1
0.1
(1.45)
1.7 MAX.
0.08
Seating Plane
C
A
B
4.9
±0.11)
A-BC0.1 2x
3
)
JEDEC reference MS-012 variation BA
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
Bottom View
±0.2
3
±0.2
2.65
0.2
±0.2
D6
M
D 8x
0.64
±0.25
3.9
±0.11)
0.1
0.35 x 45˚
CD2x
+0.06
0.19
8
˚
MAX.
Index Marking
PG-DSO-8-27-FP V01
1.27
5.69
0.65
1.31
2.65
3
TLE4254
Revision History
Data Sheet 20 Rev. 1.2, 2009-11-18
8 Revision History
Revision History: 2009-11-18 Updated Version, product versions
TLE4254EJ A and TLE4254EJ S in PG-DSO-
8 exposed pad and all related description added
Rev. 1.2
Previous Version: 2008-07-16 Rev. 1.1
typing errors corrected
Previous Version: 2006-11-22 Rev. 1.0
“Package Outlines” on Page 18 Drawing Updated
Edition 2009-11-18
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
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question, please contact the nearest Infineon Technologies Office.
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