2-41 www.adlinktech.com
CompactPCI
Introduction
ADLINK's PCI/PCIe-7300A and cPCI-7300 are ultra-highspeed digital I/O card consisting of 32 digital input/output channels. High
performance designs and state-of-the-art technology make these cards ideal for a wide range of applications, such as high-speed data
transfer, digital pattern generation and digital pattern capture applications, and logic analyzer applications. Trigger signals are available
to start the data acquisition of pattern generation.
■ Maximum Data Acquisition Rate
For sustained data transfer directly from or to host memory, the maximum data acquisition rate can be 80 MB/s. The maximum data
transfer rates between external device and onboard FIFO can be up to 80 MB/s for DO and 160 MB/s for DI. 80MB/s is achieved by
32-bit data width multiplied by an internal 20 MHz clock. 160 MB/s is achieved by 32-bit data width with an external 40 MHz clock
for digital input channels only. The PCI/PCIe-7300A, cPCI-7300 can reach 160 MB/s throughput only when the acquired data length
is less than FIFO size (16 k samples).
■ Bus Mastering DMA
The PCI/PCIe-7300A, cPCI-7300 performs high-speed data transfers between onboard FIFO and host memory using bus mastering
DMA and scatter gather. When the PCI/PCIe-7300A, cPCI-7300 becomes the bus master, it takes control of the PCI/PCIe/cPCI bus,
transfers data at burst speed, and then releases the bus. The host memory can be utilized as much as possible to store data when the
data acquisition throughput is less than the sustained PCI bus bandwidth.
■ Scatter Gather Support
For bus master devices, the hardware has the special-design built-in support for transferring data to and from non-contiguous ranges
of physical memory. The PCI/PCIe-7300A, cPCI-7300 contains multiple pairs of address and length registers, each one describing
a single contiguous buffer segment. This allows the PCI/PCIe-7300A, cPCI-7300 to perform I/O using buffers that are scattered
throughout DMA address space. These multiple address and count registers are often referred to as a scatter/gather list, and you can
also think of these bus masters as having their own built-in mapping registers. With scatter gather support, the data transfer size is no
longer a limitation, and moreover, ring buffer is easily achieved with the link list of the scattered memory.
■ I/O Port Configurations
The PCI/PCIe-7300A, cPCI-7300 is initially configured as two ports: PORT A and PORT B. Each port controls 16 digital I/O lines.
The I/O ports can be configured as either input or output. According to outside device environment, the PCI/PCIe-7300A, cPCI-7300 can
be configured to meet all high-speed digital I/O data transferring. PCI/PCIe-7300A, cPCI-7300 can support many different digital I/O
operation modes:
■
Internal clock: The digital input and output operations are handled by internal clock and data is transferred by busmastering DMA.
■
External clock: The digital input and output operations are handled by external In/Out strobe signals (DI_REQ or DO_ACK)
and data is transferred by busmastering DMA.
■
Handshaking: Through REQ and ACK signals, the digital I/O data can have simple handshaking data transfer to guarantee no data loss.
■
Pattern generation: The PCI/PCIe-7300A, cPCI-7300 reads or writes digital data at a prede termined rate. Users can control the rate
internally via by onboard counters with 50 ns timing resolution.
Features
■ x1lanePCIExpress® Interface (PCIe-7300A)
■ Supports a 32-bit 5 V PCI bus (PCI-7300A)
■ 3UEurocardformfactor,CompactPCIcompliant
(PICMG 2.0 R2.1) (cPCI-7300)
■ 32-CH 5 V/TTL digital inputs/outputs
■ 20MHz(80MB/s)maximumtransferrate
■ 8, 16, or 32-bit transfers
■ 4auxiliaryDI&4auxiliaryDO
■ Onboard 64 kB FIFO
■ Onboard programmable timer pacer clock
■ Timed digital input sampling controlled by internal
timerorexternalclock
■ Independent trigger signals to start data
acquisition and pattern generation
■ Scatter-gather DMA
■ Supports handshaking digital I/O transfer mode
■ Repeated digital pattern generation from FIFO
■ Active terminators for high-speed and longdistance
data transfer
■ Operating Systems
• Windows 7/Vista/XP/2000/2003 Server
• Linux
■ Recommended Software
• AD-Logger
• VB.NET/VC.NET/VB/VC++/BCB/Delphi
• DAQBench
■ Driver Support
• DAQPilot for LabVIEW™
• PCIS-DASK for Windows
• PCIS-DASK/X for Linux
PCI/PCIe-7300A, cPCI-7300
PCIe-7300A
PCI-7300A
cPCI-7300
Port A (16DIO)
Active
Te rminators
D31..1 6
D15..0
Port B (16DIO)
Active
Te rminators
D15..0
D31..1 6
Local Bus
PCI/PCIe
Controller
8254
Timer
D3..0
D7..4
AUX DO 3..0
AUX DI 3..0
PCI/PCIe Bus
DITRIG,DIREQ
DIACK
DOTRIG,DOACK
DOREQ
Block Diagram of PCI-7300A
REG
REG
REG
REG
16K Words
FIFO
16K Words
16K Words
FIFO
REG
REG
REG
REG
REG
REG
REG
Control
&
Timing
DO
DI
Data FIFO Scatter Gather
Fragmented
Physical Memory
Retrieves
Data
PCI Bus
Controller
Timer
CPU
Port A (16DIO)
Active
Terminators
D31..1 6
D15..0
Port B (16DIO)
Active
Terminators
D15..0
D31..1 6
Local Bus
PCI/PCIe
Controller
8254
Timer
D3..0
D7..4
AUX DO 3..0
AUX DI 3..0
PCI/PCIe Bus
DITRIG,DIREQ
DIACK
DOTRIG,DOACK
DOREQ
Block Diagram of PCI-7300A
REG
REG
REG
REG
16K Words
FIFO
16K Words
16K Words
FIFO
REG
REG
REG
REG
REG
REG
REG
Control
&
Timing
DO
DI
Data FIFO Scatter Gather
Fragmented
Physical Memory
Retrieves
Data
PCI Bus
Controller
Timer
CPU
80 MB/s High-Speed 32-CH Digital I/O Cards
2-42
www.adlinktech.com
High-Speed DIO
Pin Assignment
Specifications
Digital I/O
■
Numbers of channel (Software configurable)
• 16 DI & 16 DO
• 32 DI
• 32 DO
■
Compatibility: 5 V/TTL
■
Digital logic levels
• Input high voltage: 2-5.25 V
• Input low voltage: 0-0.8 V
• Output high voltage: 2.7 V minimum
• Output low voltage: 0.5 V maximum
■
Input load
• Terminator OFF
- Input high current: 1 mA
- Input low current: 20 mA
• Terminator ON
- Termination resistor: 111 Ω
- Termination voltage: 2.9 V
- Input high current: 1 mA
- Input low current: 22.4 mA
■
Output driving capacity
• Source current: 8 mA
• Sink current: 48 mA
Transfer Characteristics
■
Data transfers:
Bus-mastering DMA with Scatter/Gather
■
Data width: 32/16/8 bits (programmable)
Data Transfer Count
■
2 M double words (8 MB) for non-chaining
mode DMA
■
No limitation for chaining mode (scatter/gather) DMA
MaxTransferRate
■
DO: 80 MBytes/s, 32-bit output @ 20 MHz
DI: 80 MBytes/s, 32-bit input @ 20 MHz
Trigger
■
DI_TRG for digital inputs,
DO_TRG for digital outputs
■
Compatibility: 5 V/TTL
■
Trigger types: rising or falling edges
■
Minimum pulse width: 32 ns
Clocking Mode
■
Internal clock
• Internal clock sources: 20 MHz, 10 MHz, Timer#0
output (digital input pacer) and Timer #1
output (digital output pacer)
■
External clock up to 40 MHz
■
Handshaking
■
Burst handshaking
Ordering Information
■ PCI-7300A
80 MB/S High-Speed 32-CH Digital I/O Card
■ PCIe-7300A
80 MB/S High-Speed 32-CH Digital I/O PCIe Card
■ cPCI-7300
80 MB/s High-Speed 32-CH Digital I/O Module
Power
+5 V
+12 V
+3.3 V
+5 V
Device
PCI-7300A
PCIe-7300A
cPCI-7300
Onboard
terminator off
830 mA typical
119 mA typical
499 mA typical
830 mA typical
Onboard
terminator on
1.0 A typicall
287 mA typical
543 mA typical
1.0 A typical
Terminal Boards & Cables
■ DIN-100S-01
Terminal Board with One 100-pin SCSI-II Connector
and DIN-Rail Mounting (Cables are not included.)
Note:
Legacy DIN-502S can be replaced by two DIN-50S-01
and ACL-10252-1 (100-Pin to two 50-Pin Cable, 1 M)
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DO_ACK
DO_REQ
DO_TRG
AUXO3
AUXO2
AUXO1
AUXO0
TERMPWR
TERMPWR
TERMPWR
TERMPWR
AUXI3
AUXI2
AUXI1
AUXI0
DI_ACK
DI_REQ
DI_TRG
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Programmable Counter
■
Base clock: 10 MHz
■
Timer #0 as digital input pacer
■
Timer #1 as digital output pacer
■
Timer #2: as interrupt source
AuxiliaryDigitalI/O
■
Number of channels
• 4-CH digital inputs
• 4-CH digital outputs
■
Compatibility: 5 V/TTL
■
Data transfers: programmed I/O
■
I/O connector: One 100-pin SCSI-II female
■
Operating temperature: 0˚C to 60˚C
■
Storage temperature: -20˚C to 80˚C
■
Relative humidity: 5% to 95%, non-condensing
■
Power requirements
■
Dimensions (not including connectors)
• 179 mm x 106 mm (PCI-7300A)
• 168 mm x 112 mm (PCIe-7300A)
• 160 mm x 100 mm (cPCI-7300)
■ ACL-102100-1
100-pin SCSI-II cable (mating with AMP-787082-9), 1 M
* For more information on mating cables, please refer to
P2-61/62.
Updated 03-28, 2012. ©2012 ADLINK Technology, Inc. All Rights Reserved. All specications are subject to change without further notice.
