Figure 1. ADS-CCD1202 Functional Block Diagram
FLASH
ADC
REF
DAC
REGISTER
REGISTER
DIGITAL
CORRECTION
LOGIC
12 BIT 1 (MSB)
11 BIT 2
10 BIT 3
9 BIT 4
8 BIT 5
7 BIT 6
6 BIT 7
5 BIT 8
4 BIT 9
3 BIT 10
2 BIT 11
1 BIT 12 (LSB)
TIMING AND
CONTROL LOGIC
ANALOG INPUT 20
START CONVERT 16
EOC 15
13
+5V SUPPLY
17, 18
NO CONNECT
22
+12V/+15V SUPPLY
14, 19, 23
GROUND
24
–12V/–15V SUPPLY
S1 S2
S/H
BUFFER
–
+
+10V REFERENCE 21
BLOCK DIAGRAM
The functionally complete, easy-to-use ADS-
CCD1202 is a 12-bit, 2MHz Sampling A/D Con-
verter whose performance and production testing
have been optimized for use in CCD applications.
This device delivers the lowest noise (600Vrms)
and the best differential linearity error (±0.45LSB
maximum) of any commercially available 12-bit
A/D in its speed class. It can respond to full scale
input steps (from empty to full well) with less than
a single count of error, and its input is immune to
overvoltages that may occur due to blooming.
Packaged in an industry-standard, 24-pin,
ceramic DDIP, the ADS-CCD1202 requires ±15V (or
±12V) and +5V supplies and typically consumes
1.75 (1.45) Watts. The device is 100% production
tested for all critical performance parameters and
is fully specifi ed over both the 0 to +70°C and –55
to +125°C operating temperature ranges.
For those applications using correlated double
sampling, the ADS-CCD1202 can be supplied
without its internal sample-hold amplifi er and
achieve conversion rates up to 2.5MHz. DATEL
will also entertain discussions about including the
CDS circuit internal to the ADS-CCD1202. Please
contact us for more details.
PRODUCT OVERVIEW
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION PIN FUNCTION
1 BIT 12 (LSB) 24 –12V/–15V SUPPLY
2 BIT 11 23 GROUND
3 BIT 10 22 +12V/+15V SUPPLY
4 BIT 9 21 +10V REFERENCE OUT
5 BIT 8 20 ANALOG INPUT
6 BIT7 19 GROUND
7 BIT 6 18 NO CONNECT
8 BIT 5 17 NO CONNECT
9 BIT 4 16 START CONVERT
10 BIT 3 15 EOC
11 BIT 2 14 GROUND
12 BIT 1 (MSB) 13 +5V SUPPLY
FEATURES
■ Unipolar input range (0 to +10V)
■ 2MHz sampling rate
■ 4096-to-1 dynamic range (72.2dB)
■ Low noise, 600Vrms (1/4 of an LSB)
■ Outstanding differential nonlinearity error
(±0.45 LSB max.)
■ Small, 24-pin ceramic DDIP
■ Low power, 1.75 Watts
■ Operates from ±12V or ±15V supplies
■ Edge-triggered, no pipeline delay
■ Low cost
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
For full details go to
www.murata-ps.com/rohs
www.murata-ps.com
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 1 of 8
PHYSICAL/ENVIRONMENTAL
PARAMETERS MIN. TYP. MAX. UNITS
Operating Temp. Range, Case
ADS-CCD1202MC 0 — +70 °C
ADS-CCD1202MM –55 — +125 °C
Thermal Impedance
Tjc — 5 — °C/Watt
Tca — 24 — °C/Watt
Storage Temperature Range –65 — +150 °C
Package Type 24-pin, metal-sealed ceramic DDIP
Weight 0.42 ounces (12 grams)
ABSOLUTE MAXIMUM RATINGS
PARAMETERS LIMITS UNITS
+12V/+15V Supply (Pin 22) 0 to +16 Volts
–12V/–15V Supply (Pin 24) 0 to –16 Volts
+5V Supply (Pin 13) 0 to +6 Volts
Digital Input (Pin 16) –0.3 to +VDD +0.3 Volts
Analog Input (Pin 20) –5 to +14 Volts
Lead Temp. (10 seconds) +300 °C
+25°C 0 TO +70°C –55 TO +125°C
ANALOG INPUT MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS
Input Voltage Range d — 0 to +10 — — 0 to +10 — — 0 to +10 — Volts
Input Resistance 0.99 1 1.01 0.99 1 1.01 0.99 1 1.01 k:
Input Capacitance — 7 15 — 7 15 — 7 15 pF
DIGITAL INPUT
Logic Levels
Logic "1" +2.0 — — +2.0 — — +2.0 — — Volts
Logic "0" — — +0.8 — — +0.8 — — +0.8 Volts
Logic Loading "1" — — +20 — — +20 — — +20 µA
Logic Loading "0" — — –20 — — –20 — — –20 µA
Start Convert Positive Pulse Width ➂ — 200 — — 200 — — 200 — ns
STATIC PERFORMANCE
Resolution — 12 — — 12 — — 12 — Bits
Integral Nonlinearity (fi n = 10kHz) — ±0.5 — — ±0.5 — — ±1 — LSB
Differential Nonlinearity (fi n = 10kHz) — +0.25 ±0.45 — ±0.25 ±0.45 — ±0.35 ±0.75 LSB
Full Scale Absolute Accuracy — +0.1 ±0.3 — ±0.2 ±0.5 — ±0.3 ±0.8 %FSR
Offset Error (Tech Note 2) — ±0.15 ±0.3 — ±0.2 ±0.5 — ±0.5 ±1.2 %FSR
Gain Error (Tech Note 2) — ±0.1 ±0.4 — ±0.4 ±0.8 — ±0.5 ±1.4 %
No Missing Codes (fi n = 10kHz) 12 — — 12 — — 12 — — Bits
DYNAMIC PERFORMANCE
Peak Harmonics (–0.5dB)
dc to 500kHz — –80 –75 — –80 –75 — –76 –72 dB
500kHz to 1MHz — –77 –71 — –77 –71 — –73 –66 dB
Total Harmonic Distortion (–0.5dB)
dc to 500kHz — –76 –73 — –76 –73 — –74 –70 dB
500kHz to 1MHz — –75 –70 — –75 –70 — –71 –65 dB
Signal-to-Noise Ratio (w/o distortion, –0.5dB)
dc to 500kHz 71 72 — 71 72 — 71 72 — dB
500kHz to 1MHz 71 72 — 71 72 — 70 72 — dB
Signal-to-Noise Ratio f (& distortion, –0.5dB)
dc to 500kHz 70 71 — 70 71 — 68 70 — dB
500kHz to 1MHz 68 71 — 68 71 — 65 69 — dB
Two-Tone Intermodulation Distortion
(fi n = 200kHz, 500kHz, fs = 2MHz, –0.5dB) — –83 — — –82 — — –81 — dB
Noise — 600 — — 600 — — 600 — Vrms
Input Bandwidth (–3dB)
Small Signal (–20dB input) — 9 — — 9 — — 9 — MHz
Large Signal(–0.5dB input) — 8 — — 8 — — 8 — MHz
Feedthrough Rejection (fi n = 1MHz) — 82 — — 82 — — 82 — dB
Slew Rate — ±200 — — ±200 — — ±200 — V/s
Aperture Delay Time — ±20 — — ±20 — — ±20 — ns
Aperture Uncertainty — 5 — — 5 — — 5 — ps rms
S/H Acquisition Time (to ±0.01%FSR, 10V step) 150 190 230 150 190 230 150 190 230 ns
Overvoltage Recovery Time ➄ — 400 500 — 400 500 — 400 500 ns
A/D Conversion Rate 2 — — 2 — — 2 — — MHz
ANALOG OUTPUT
Internal Reference
Voltage +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 +9.95 +10.0 +10.05 Volts
Drift — ±5 — — ±5 — — ±5 — ppm/ºC
External Current — — 1.5 — — 1.5 — — 1.5 mA
FUNCTIONAL SPECIFICATIONS
(TA = +25°C, ±Vcc = ±15V (or ±12V), +VDD = +5V, 2MHz sampling rate, and a minimum 1 minute warmup ➀ unless otherwise specifi ed.)
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 2 of 8
TECHNICAL NOTES
Footnotes:
➀ All power supplies must be on before applying a start convert pulse. All supplies
and the clock (START CONVERT) must be present during warmup periods.
➁ Contact DATEL for availability of other input voltage ranges.
➂ A 200ns wide start convert pulse is used for all production testing.
➃ Effective bits is equal to:
➄ This is the time required before the A/D output data is valid after the analog input
is back within the specifi ed range.
(SNR + Distortion) – 1.76 + 20 log Full Scale Amplitude
Actual Input Amplitude
6.02
1. Obtaining fully specifi ed performance from the ADS-CCD1202 requires
careful attention to pc-card layout and power supply decoupling. The
device’s analog and digital ground systems are connected to each other
internally. For optimal performance, tie all ground pins (14, 19, and 23)
directly to a large analog ground plane beneath the package.
Bypass all power supplies, as well as the REFERENCE OUTPUT (pin 21),
to ground with 4.7F tantalum capacitors in parallel with 0.1F ceramic
capacitors. Locate the bypass capacitors as close to the unit as possible.
If the user-installed offset and gain adjusting circuit shown in Figure 2 is
used, also locate it as close to the ADS-CCD1202 as possible.
2. ADS-CCD1202 achieves its specifi ed accuracies without external calibra-
tion. If required, the device’s small initial offset and gain errors can be
reduced to zero using the input circuit of Figure 2. When using this circuit,
or any similar offset and gain-calibration hardware, make adjustments fol-
lowing warmup. To avoid interaction, always adjust offset before gain.
3. When operating the ADS-CCD1202 from ±12V supplies, do not drive
external circuitry with the REFERENCE OUTPUT (pin 21). The reference’s ac-
curacy and drift specifi cations may not be met, and loading the circuit may
cause accuracy errors within the converter.
4. A passive bandpass fi lter is used at the input of the A/D for all production
testing.
5. Applying a start pulse while a conversion is in progress (EOC = logic "1")
initiates a new and inaccurate conversion cycle. Data for the interrupted
and subsequent conversions will be invalid.
+25°C 0 TO +70°C –55 TO +125°C
DIGITAL OUTPUTS MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS
Logic Levels
Logic "1" +2.4 — — +2.4 — — +2.4 — — Volts
Logic "0" — — +0.4 — — +0.4 — — +0.4 Volts
Logic Loading "1" — — –4 — — –4 — — –4 mA
Logic Loading "0" — — +4 — — +4 — — +4 mA
Delay, Falling Edge of EOC to Output Data Valid — — 35 — — 35 — — 35 ns
Output Coding Straight Binary
POWER REQUIREMENTS, ±15V
Power Supply Range
+15V Supply +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 +14.5 +15.0 +15.5 Volts
–15V Supply –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 –14.5 –15.0 –15.5 Volts
+5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 Volts
Power Supply Current
+15V Supply — +43 +65 — +43 +65 — +43 +65 mA
–15V Supply — –48 –60 — –48 –60 — –48 –60 mA
+5V Supply — +82 +95 — +82 +95 — +82 +95 mA
Power Dissipation — 1.75 2.00 — 1.75 2.00 — 1.75 2.00 Watts
Power Supply Rejection — — ±0.02 — — ±0.02 — — ±0.02 %FSR/%V
POWER REQUIREMENTS, ±12V
Power Supply Range
Power Supply Range
+12V Supply +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 +11.5 +12.0 +12.5 Volts
–12V Supply –11.5 –12.0 –12.5 –11.5 –12.0 –12.5 –11.5 –12.0 –12.5 Volts
+5V Supply +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 Volts
Power Supply Current
+12V Supply — +43 +61 — +43 +61 — +43 +61 mA
–12V Supply — –48 –60 — –48 –60 — –48 –60 mA
+5V Supply — +82 +95 — +82 +95 — +82 +95 mA
Power Dissipation — 1.45 1.7 — 1.45 1.7 — 1.45 1.7 Watts
Power Supply Rejection — — ±0.02 — — ±0.02 — — ±0.02 %FSR/%V
Table 1. Zero and Gain Adjust
INPUT VOLTAGE
RANGE
ZERO ADJUST
+½ LSB
GAIN ADJUST
+FS –1½ LSB
0 to +10V +1.2207mV +9.99634V
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 3 of 8
CALIBRATION PROCEDURE (Refer to Figures 2 and 3)
Any offset and/or gain calibration procedures should not be implemented
until devices are fully warmed up. To avoid interaction, offset must be ad-
justed before gain. The ranges of adjustment for the circuit of Figure 2 are
guaranteed to compensate for the ADS-CCD1202’s initial accuracy errors
and may not be able to compensate for additional system errors.
All fi xed resistors in Figure 2 should be metal-fi lm types, and multi-turn po-
tentiometers should have TCR’s of 100ppm/°C or less to minimize drift with
temperature. In many applications, the CCD will require an offset-adjust
(black balance) circuit near its output and also a gain stage, presumably
with adjust capabilities, to match the output voltage of the CCD to the input
range of the A/D. If one is performing a "system I/O calibration" (from light
in to digital out), these circuits can be used to compensate for the relatively
small initial offset and gain errors of the A/D. This would eliminate the need
for the circuit shown in Figure 2.
A/D converters are calibrated by positioning their digital outputs exactly
on the transition point between two adjacent digital output codes. This can
be accomplished by connecting LED’s to the digital outputs and adjusting
until certain LED’s "fl icker" equally between on and off. Other approaches
employ digital comparators or microcontrollers to detect when the outputs
change from one code to the next.
For the ADS-CCD1202, offset adjusting is normally accomplished at the
point where all output bits are 0’s and the LSB just changes from a 0 to a 1.
This digital output transition ideally occurs when the applied analog input is
+1/2LSB (+1.2207mV).
Gain adjusting is accomplished when all bits are 1’s and the LSB just
changes from a 1 to a 0. This transition ideally occurs when the analog
input is at +full scale minus 1 1/2 LSB’s (+9.99634V).
Offset Adjust Procedure
1. Apply a train of pulses to the START CONVERT input (pin 16) so the con-
verter is continuously converting. If using LED’s on the outputs, a 200kHz
conversion rate will reduce fl icker.
2. Apply +1.2207mV to the ANALOG INPUT (pin 20).
3. Adjust the offset potentiometer until the output bits are 0000 0000 0000
and the LSB fl ickers between 0 and 1.
Gain Adjust Procedure
1. Apply +9.99634V to the ANALOG INPUT (pin 20).
2. Adjust the gain potentiometer until all output bits are 1’s and the LSB fl ick-
ers between 1 and 0.
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and speci-
fi ed over operating temperature (case) ranges of 0 to +70°C and – 55
to +125°C. All room-temperature (TA = +25°C) production testing is
performed without the use of heat sinks or forced-air cooling. Thermal
impedance fi gures for each device are listed in their respective specifi ca-
tion tables.
These devices do not normally require heat sinks, however, standard
precautionary design and layout procedures should be used to ensure
devices do not overheat. The ground and power planes beneath the pack-
age, as well as all pcb signal runs to and from the device, should be as
heavy as possible to help conduct heat away from the package. Electrically
insulating, thermally conductive "pads" may be installed underneath the
package. Devices should be soldered to boards rather than "socketed," and
of course, minimal air fl ow over the surface can greatly help reduce the
package temperature.
13
ADS-CCD1202
14
20
15
12
11
10
9
8
7
6
5
4
3
2
1
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12 (LSB)
EOC
ANALOG
INPUT
19, 23
22
24
0.1F
4.7F
+5V
0.1F
4.7F
0.1F
4.7F +
+
–12V/–15V
+12V/+15V +
0.1F +
4.7F
21 +10V REF. OUT
0 to +10V
NO CONNECT
17, 18
Figure 3. Typical ADS-CCD1202 Connection Diagram
Table 2. ADS-CCD1202 Output Coding
INPUT VOLTAGE
(0 TO +10V)
UNIPOLAR
SCALE
DIGITAL OUTPUT
MSB LSB
+9.9976 +FS – 1LSB 1111 1111 1111
+7.5000 +3/4 FS 1100 0000 0000
+5.0000 +1/2 FS 1000 0000 0000
+2.5000 +1/4 FS 0100 0000 0000
+0.0024 +1LSB 0000 0000 0001
0 0 0000 0000 0000
To Pin 20 of
ADS-CCD1202
–15V
SIGNAL
INPUT
GAIN
ADJUST
1.98k
50
+15V
2k
200k20k
–15V
+15V
ZERO/
OFFSET
ADJUST
77
7
7
7
Figure 2. ADS-CCD1202 Calibration Circuit
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 4 of 8
TIMING
The ADS-CCD1202 is an edge triggered device. A conversion is initiated by the
rising edge of the start convert pulse and no additional external timing signals
are required. The device does not employ "pipeline" delays to increase its
throughput rate. It does not require multiple start convert pulses to bring valid
digital data to its output pins.
Figure 4. ADS-CCD1202 Timing Diagram
Figure 5. ADS-CCD1202 Evaluation Board Schematic
START
CONVERT
OUTPUT DATA
INTERNAL S/H
N
DATA (N-1) VALID
200ns typ.
Acquisition Time
10ns typ.
DATA N VALID
425ns min.
Note: Scale is approximately 25ns per division.
EOC
30ns typ.
Conversion Time
360ns ±20ns
INVALID
DATA
75ns max.
70ns ±10ns
310ns typ.
35ns max.
Hold
N+1
190ns typ.
32
30
28
26
24
22
20
33
6
8
10
12
14
16
18
31
27
29
23
25
19
21
3
5
7
9
11
13
15
P2
17
1
2
4
34
5%200K
R3
0.1%
1.98K
R4
–
+
U6
2
3
4
6
7
OP-77
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
U3
2
4
6
8
11
13
15
17
19
10
20
18
16
14
12
9
7
5
3
1
74LS240
.1%2K
R5
0.1%
10K
R8
P3
P4
74LS86
U4
9
10 8
74LS86
U4
12
13
11
0.1MF
C7
0.1MF
C5
0.1MF
C3
0.1MF
C17
0.1MF
C16
0.1MF
C1
0.1MF
C15
15pF
C2
0.1MF
C10
0.1MF
C12
0.1MF
C13
2.2MF
C6
+
2.2MF
C4
+
2.2MF
C9
+
2.2MF
C8
+
2.2MF
C11
+
2.2MF
C14
+
+5V
+5V
+5V
+5V
+15V
+15V
+15V
+15V
-15V
-15V
-15V
-15V
+5V
P1
1
2
56
4 3
8 7
10 9
12 11
14 13
16 15
18 17
20 19
22 21
24 23
26
25
20K
R2
50
R1
74LS86
U4
4
5
6
74LS86
U4
1
2
3
7
14
B1
B2
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
EOC
+5V
DGND
ST. CONV
AGND
INPUT
+10VREF
+15V
AGND
-15V
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SG1
–
+
U5
2
3
4
6
7
AD845
0.1%
10K
R7
0.1%
2K
R6
-15V
2.2
MF
C22
+
0.1MF
C23
+15V
2.2MF
C19
+
0.1MF
C20
Y1
1
78
14
XTAL
J3
J5
J4
J2
0.1MF
C21
J1
+5V
0.1MF
C18
SG2
SG3
2.2MF
C24
+
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
2A4
2A3
2A2
2A1
1A4
1A3
1A2
1A1
U2
2
4
6
8
11
13
15
17
19
10
20
18
16
14
12
9
7
5
3
1
74LS240
B13
B11
B12
B10
B9
B6
B5
B4
B3
B14
B1
B2
B8
B7
SEE NOTE 1
ST.CONV.
ENABLE
MSB
LSB
EOC
COG
ADJ
GAIN
ADJ
OFFSET
CONVERT
START
INPUT
ANALOG
1. FOR ADS-BCCD1201 Y1 IS 1.2MHZ
FOR ADS-BCCD1202 Y1 IS 2MHZ
NOTES:
ADS-CCD1201/1202
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 5 of 8
Figure 6. ADS-CCD1202 FFT
(fi n = 975kHz, fs = 2MHz, Vin = –0.5dB, 4,096 points)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
0 100 200 300 400 500 600 700 800 900 1000
Fre
q
uenc
y(
kHz
)
Amplitude Relative to Full Scale (dB)
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 6 of 8
Figure 7. ADS-CCD1202 Grounded Input Histogram
Figure 8. ADS-CCD1202 Histogram and Differential Nonlinearity
4000
3500
3000
2500
2000
1500
1000
500
0
Digital Output Code
Number of Occurences
This histogram represents the typical
peak-to-peak noise (including
quantization noise) associated with
the ADS-CCD1202. 4,096
conversions were processed with the
input to the ADS-CCD1202 tied to
analog ground.
Digital Output Code
+0.16
0
–0.15
04096
Number of Occurences
0 4096
Digital Output Code
DNL (LSB's)
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
www.murata-ps.com email: data.acquisition@murata-ps.com
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 7 of 8
MECHANICAL DIMENSIONS INCHES (mm)
0.80 MAX.
(20.32)
0.015
(0.381)
MAX. radius
for any pin
1.31 MAX.
(33.02)
0.100 TYP.
(2.540)
0.100
(2.540)
0.190 MAX.
(4.826)
0.040
(1.016)
0.020 TYP.
(0.508)
0.020
(0.508)
24 13
121
PIN 1
INDEX
0.130 TYP.
(3.302)
Dimension Tolerances (unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
Lead Material: Kovar alloy
Lead Finish: 50 microinches (minimum) gold plating
over 100 microinches (nominal) nickel plating
0.060 TYP.
(1.524)
0.010 TYP.
(0.254)
24-PIN DDIP
0.200 MAX.
(5.080)
0.235 MAX.
(5.969)
0.600 ±0.010
(15.240)
0.80 MAX.
(20.32)
0.100 TYP.
(2.540)
0.100
(2.540)
0.018 ±0.002
(0.457)
0.100
(2.540)
0.040
(1.016)
1.31 MAX.
(33.27)
112
13
24
1.100
(27.940)
0.190 MAX.
(4.826)
0.010
(0.254)
+0.002
–0.001
SEATING
PLANE
0.025
(0.635)
Dimension Tolerances
(unless otherwise indicated):
2 place decimal (.XX) ±0.010 (±0.254)
3 place decimal (.XXX) ±0.005 (±0.127)
Lead Material: Kovar alloy
Lead Finish: 50 microinches (minimum)
gold plating over 100 microinches
(nominal) nickel plating
24-PIN SURFACE MOUNT
ORDERING INFORMATION
MODEL NUMBER OPERATING
TEMP. RANGE ANALOG INPUT ACCESSORIES
ADS-CCD1202MC 0 to +70°C Unipolar (0 to +10V) ADS-BCCD1202 Evaluation Board (without ADS-CCD1202)
ADS-CCD1202MM –55 to +125°C Unipolar (0 to +10V) HS-24 Heat Sink for all ADS-CCD1202 models
Receptacles for pc board mounting can be ordered through AMP, Inc., Part # 3-331272-8 (Component Lead Socket), 24 required.
Contact DATEL for availability of surface-mount packaging or high-reliability screening.
ADS-CCD1202
12-Bit, 2MHz, Sampling A/D’s for CCD Imaging Applications
Murata Power Solutions, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply
the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without
notice. © 2009 Murata Power Solutions, Inc.
www.murata-ps.com/locations email: data.acquisition@murata-ps.com
Murata Power Solutions, Inc.
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 U.S.A.
ISO 9001 and 14001 REGISTERED
11 Nov 2009 MDA_ADS-CCD1202.B01 Page 8 of 8