© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 4
1Publication Order Number:
NTLUS3A18PZ/D
NTLUS3A18PZ
Power MOSFET
−20 V, −8.2 A, Single P−Channel,
2.0x2.0x0.55 mm UDFN Package
Features
•UDFN Package with Exposed Drain Pads for Excellent Thermal
Conduction
•Low Profile UDFN 2.0x2.0x0.55 mm for Board Space Saving
•Ultra Low RDS(on)
•ESD Diode−Protected Gate
•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
•Optimized for Power Management Applications for Portable
Products, such as Cell Phones, Media Tablets, PMP, DSC, GPS, and
Others
•Battery Switch
•High Side Load Switch
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter Symbol Value Unit
Drain-to-Source Voltage VDSS −20 V
Gate-to-Source Voltage VGS ±8.0 V
Continuous Drain
Current (Note 1)
Continuous Drain
Current (Note 1)
Steady
State
TA = 25°CID−8.2 A
TA = 85°C−5.9
t ≤ 5 s TA = 25°C−12.2
Power Dissipa-
tion (Note 1)
Steady
State
TA = 25°CPD1.7 W
t ≤ 5 s TA = 25°C 3.8
Continuous Drain
Current (Note 2)
Steady
State
TA = 25°CID−5.1 A
TA = 85°C−3.7
Power Dissipation (Note 2) TA = 25°C PD0.7 W
Pulsed Drain Current tp = 10 msIDM −25 A
Operating Junction and Storage
Temperature
TJ,
TSTG
-55 to
150
°C
ESD (HBM, JESD22−A114) VESD 2000 V
Source Current (Body Diode) (Note 2) IS−1.7 A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface-mounted on FR4 board using the minimum recommended pad size
of 30 mm2, 2 oz. Cu.
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P−Channel MOSFET
−20 V 25 mW @ −2.5 V
18 mW @ −4.5 V
RDS(on) MAX ID MAXV(BR)DSS
MOSFET
UDFN6
CASE 517BG
See detailed ordering and shipping information on page 5 of
this data sheet.
ORDERING INFORMATION
AC= Specific Device Code
M = Date Code
G= Pb−Free Package
AC MG
G
1
50 mW @ −1.8 V
MARKING DIAGRAM
90 mW @ −1.5 V
(Top View)
(Note: Microdot may be in either location)
Pin 1
−8.2 A
D
S
G
PIN CONNECTIONS
D
S
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2
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction-to-Ambient – Steady State (Note 3) RθJA 72
°C/W
Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 33
Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 189
3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces).
4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter Symbol Test Condition Min Typ Max Units
OFF CHARACTERISTICS
Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA−20 V
Drain-to-Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJID = −250 mA, ref to 25°C+10 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V,
VDS = −20 V
TJ = 25°C−1.0 mA
Gate-to-Source Leakage Current IGSS VDS = 0 V, VGS = ±5.0 V ±5mA
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA−0.4 −1.0 V
Negative Threshold Temp. Coefficient VGS(TH)/TJ3.0 mV/°C
Drain-to-Source On Resistance RDS(on) VGS = −4.5 V, ID = −7.0 A 14.6 18 mW
VGS = −2.5 V, ID = −5.0 A 19 25
VGS = −1.8 V, ID = −3.0 A 25 50
VGS = −1.5 V, ID = −1.0 A 40 90
Forward Transconductance gFS VDS = −5 V, ID = −3.0 A 40 S
CHARGES, CAPACITANCES & GATE RESISTANCE
Input Capacitance CISS
VGS = 0 V, f = 1 MHz,
VDS = −15 V
2240 pF
Output Capacitance COSS 240
Reverse Transfer Capacitance CRSS 210
Total Gate Charge QG(TOT)
VGS = −4.5 V, VDS = −15 V;
ID = −4.0 A
28 nC
Threshold Gate Charge QG(TH) 1.0
Gate-to-Source Charge QGS 2.9
Gate-to-Drain Charge QGD 8.8
SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6)
Turn-On Delay Time td(ON)
VGS = −4.5 V, VDD = −15 V,
ID = −4.0 A, RG = 1 W
8.6 ns
Rise Time tr15
Turn-Off Delay Time td(OFF) 150
Fall Time tf88
DRAIN-SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD VGS = 0 V,
IS = −1.0 A
TJ = 25°C 0.63 1.0 V
TJ = 125°C 0.50
Reverse Recovery Time tRR
VGS = 0 V, dIs/dt = 100 A/ms,
IS = −1.0 A
26.1 ns
Charge Time ta10.2
Discharge Time tb15.9
Reverse Recovery Charge QRR 12 nC
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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3
TYPICAL CHARACTERISTICS
Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics
−VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
−VGS, GATE VOLTAGE (V) −ID, DRAIN CURRENT (A)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
−ID, DRAIN CURRENT (A)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), NORMALIZED DRAIN−TO−
SOURCE RESISTANCE (W)
−IDSS, LEAKAGE (nA)
VGS = −1.8 V
−2.0 V
−4.5 to −2.5 V
−1.5 V
VDS ≤ −10 V
TJ = 25°C
TJ = −55°C
TJ = 125°C
ID = −4.0 A
TJ = 25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 25°C
VGS = −1.8 V
VGS = −2.5 V
VGS = −4.5 V
VGS = −4.5 V
ID = −4.0 A
TJ = 85°C
TJ = 125°C
0
2
4
6
8
10
12
14
16
18
20
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0
2
4
6
8
10
12
14
16
18
20
0 0.5 1 1.5 2 2.5
0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.000
0.010
0.020
0.030
0.040
0.050
0.060
135791113151719
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
50 25 0 25 50 75 100 125 150
100
1000
10000
100000
2 4 6 8 10 12 14 16 18 20
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4
TYPICAL CHARACTERISTICS
Figure 7. Capacitance Variation Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
−VDS, DRAIN−TO−SOURCE VOLTAGE (V) QG, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
RG, GATE RESISTANCE (W)−VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power
Dissipation
TJ, JUNCTION TEMPERATURE (°C) SINGLE PULSE TIME (s)
C, CAPACITANCE (pF)
−VGS, GATE−TO−SOURCE VOLTAGE (V)
t, TIME (ns)
−IS, SOURCE CURRENT (A)
−VGS(th) (V)
POWER (W)
VGS = 0 V
TJ = 25°C
f = 1 MHz
Ciss
Coss
Crss
VDS = −15 V
ID = −4.0 A
TJ = 25°C
VDS VGS
QGS QGD
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS = −4.5 V
VDD = −15 V
ID = −4.0 A
td(off)
td(on)
tf
tr
TJ = 25°C
TJ = −55°C
TJ = 125°C
ID = −250 mA
QT
0
400
800
1200
1600
2000
2400
2800
3200
3600
4000
0 2 4 6 8 101214161820 0
2
4
6
8
10
12
14
16
18
0
1
2
3
4
5
0 5 10 15 20 25 30
1.0
10.0
100.0
1000.0
1 10 100 0.1
1.0
10.0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
0.15
0.25
0.35
0.45
0.55
0.65
0.75
0.85
0.95
50 25 0 25 50 75 100 125 150
0
25
50
75
100
125
150
175
200
225
100m 10 10001m
10m
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5
TYPICAL CHARACTERISTICS
0
10
20
30
40
50
60
70
80
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 14. FET Thermal Response
t, TIME (s)
−ID, DRAIN CURRENT (A)
R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
RqJA = 72°C/W
Single Pulse
Duty Cycle = 0.5
0.2
0.1
0.05 0.02 0.01
VGS = −8 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
10 ms
100 ms
1 ms
10 ms
dc
0.01
0.1
1
10
100
0.1 1 10 100
1E+00 1E+01 1E+02 1E+031E−06 1E−05 1E−04 1E−03 1E−02 1E−01
DEVICE ORDERING INFORMATION
Device Package Shipping†
NTLUS3A18PZTAG UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3A18PZTBG UDFN6
(Pb−Free)
3000 / Tape & Reel
NTLUS3A18PZTCG UDFN6
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NTLUS3A18PZ
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6
PACKAGE DIMENSIONS
ÍÍÍ
ÍÍÍ
ÍÍÍ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS
MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS
THE TERMINALS.
5. CENTER TERMINAL LEAD IS OPTIONAL. CENTER TERMINAL
IS CONNECTED TO TERMINAL LEAD # 4.
6. LEADS 1, 2, 5 AND 6 ARE TIED TO THE FLAG.
CSEATING
PLANE
DB
E
0.10 C
A3
A
A1
0.10 C
UDFN6 2x2, 0.65P
CASE 517BG
ISSUE A
DIM
A
MIN MAX
MILLIMETERS
0.45 0.55
A1 0.00 0.05
A3 0.13 REF
b0.25 0.35
b1
0.65 BSC
D
D2
E
E2
0.27 BSC
e
0.15 REF
K
L
PIN ONE
REFERENCE
0.08 C
0.10 C
NOTE 4
A0.10 C
NOTE 3
Le
D2
E2
b
B
3
66X
1
K4
6X
0.05 C
J
J1
A0.10 C
b1
B
0.05 C
L2
NOTE 5
L2
J
J1
0.51 0.61
2.00 BSC
1.00 1.20
2.00 BSC
1.10 1.30
0.65 BSC
0.20 0.30
0.20 0.30
BOTTOM VIEW
MOUNTING FOOTPRINT*
RECOMMENDED
DIMENSIONS: MILLIMETERS
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
ÇÇ
L
ÇÇÇ
ÉÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
OPTIONAL
CONSTRUCTIONS
PLATING
6X
0.43
2.30
1.10
0.66
1.25
0.65
PITCH
6X
0.35
1
PACKAGE
OUTLINE
0.35
0.34
0.60
L1 --- 0.10
TOP VIEW
DETAIL B
SIDE VIEW
DETAIL A
A
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
NTLUS3A18PZ/D
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