HDSP-2504 - Agilent / Hewlett-Packard

Eight Character 5 mm and 7 mm

Smart Alphanumeric Displays

Technical Data

Features

• X Stackable (HDSP-21xx)

• XY Stackable (HDSP-250x)

• 128 Character ASCII

Decoder

• Programmable Functions

• 16 User Definable

Characters

• Multi-Level Dimming and

Blanking

• TTL Compatible CMOS IC

• Wave Solderable

Applications

• Computer Peripherals

• Industrial Instrumentation

• Medical Equipment

• Portable Data Entry Devices

• Cellular Phones

• Telecommunications

Equipment

• Test Equipment

Description

The HDSP-210x/-211x/-250x

series of products is ideal for

applications where displaying

eight or more characters of dot

matrix information in an

aesthetically pleasing manner is

required. These devices are

8-digit, 5 x 7 dot matrix, alpha-

numeric displays and are all

packaged in a standard 15.24 mm

(0.6 inch) 28 pin DIP. The on-

board CMOS IC has the ability to

decode 128 ASCII characters

which are permanently stored in

ROM. In addition, 16 program-

mable symbols may be stored in

on-board ROM, allowing consider-

HDSP-210x Series

HDSP-211x Series

HDSP-250x Series

able flexibility for displaying

additional symbols and icons.

Seven brightness levels provide

versatility in adjusting the display

intensity and power consumption.

The HDSP-210x/-211x/-250x

products are designed for

standard microprocessor interface

techniques. The display and

special features are accessed

through a bidirectional 8-bit data

bus.

Device Selection Guide

AlGaAs High Efficiency

Font Height Red Red Orange Yellow Green

0.2 inches HDSP-2107 HDSP-2112 HDSP-2110 HDSP-2111 HDSP-2113

0.27 inches HDSP-2504 HDSP-2502 HDSP-2500 HDSP-2501 HDSP-2503

Package Dimensions

ESD WARNING: STANDARD CMOS HANDLING PRECAUTIONS SHOULD BE OBSERVED TO AVOID

STATIC DISCHARGE.

Absolute Maximum Ratings

Supply Voltage, V

DD to Ground[1] ........................................ -0.3 to 7.0 V

Operating Voltage, VDD to Ground[2] ..............................................5.5 V

Input Voltage, Any Pin to Ground.............................. -0.3 to VDD +0.3 V

Free Air Operating Temperature Range, TA[3] ................ -45°C to +85°C

Storage Temperature Range, TS.................................. -55°C to +100°C

Relative Humidity (non-condensing) ............................................... 85%

Maximum Solder Temperature

(Below Seating Plane), t < 5 sec.............................................. 260°C

ESD Protection @ 1.5 kΩ, 100 pF ........................ VZ = 4 kV (each pin)

Notes:

1. Maximum Voltage is with no LEDs illuminated.

2. 20 dots ON in all locations at full brightness.

3. Maximum supply voltage is 5.25 V for operation above 70°C.

Package Dimensions

ASCII Character Set HDSP-210X, HDSP-211X, HDSP-250X Series

Recommended Operating Conditions

Parameter Symbol Minimum Nominal Maximum Units

Supply Voltage VDD 4.5 5.0 5.5 V

Electrical Characteristics Over Operating Temperature Range (-45°C to +85°C)

4.5 V < VDD < 5.5 V, unless otherwise specified

TA = 25°C -45°C < TA < + 85°C

VDD = 5.0 V 4.5 V < VDD < 5.5 V

Parameter Symbol Typ. Max. Min. Max. Units Test Conditions

Input Leakage IIH 1.0 µAV

IN = 0 to VDD,

(Input without pullup) IIL -1.0 pins CLK, D0-D7,

A0-A4

Input Current IIPL -11 -18 -30 µAV

IN = 0 to VDD,

(Input with pullup) pins CLS, RST,

WR, RD, CE, FL

IDD Blank IDD (BLK) 0.5 3.0 4.0 mA VIN = VDD

IDD 8 digits IDD(V) 200 255 330 mA “V” on in all 8

12 dots/character[1,2] locations

IDD 8 digits IDD(#) 300 370 430 mA “#” on in all

20 dots/character[1,2,3,4] locations

Input Voltage High V

IH 2.0 VDD V

+0.3

Input Voltage Low V

IL GND 0.8 V

-0.3 V

Output Voltage High VOH 2.4 V VDD = 4.5 V,

IOH = -40 µA

Output Voltage Low VOL 0.4 V VDD = 4.5 V,

D0-D7IOL = 1.6 mA

Output Voltage Low VOL 0.4 V VDD = 4.5 V,

CLK IOL = 40 µA

High Level Output IOH -60 mA VDD = 5.0 V

Current

Low Level Output IOL 50 mA VDD = 5.0 V

Current

Thermal Resistance RθJ-C 15 °C/W

IC Junction-to-Case

Notes:

1. Average IDD measured at full brightness. See Table 2 in Control Word Section for IDD at lower brightness levels. Peak

IDD = 28/15 x IDD (#).

2. Maximum IDD occurs at -55°C.

3. Maximum IDD(#) = 355 mA at VDD = 5.25 V and IC TJ = 150°C.

4. Maximum IDD(#) = 375 mA at VDD = 5.5 V and IC TJ = 150°C.

Optical Characteristics at 25°C

VDD = 5.0 V at Full Brightness

Luminous Intensity Peak Dominant

Character Average (#) Wavelength Wavelength

Part Iv (mcd) λPeak λd

Description Number Min. Typ. (nm) (nm)

AlGaAs HDSP-2107 5.0 15.0 645 637

-2504

HER HDSP-2112 2.5 7.5 635 626

-2502

Orange HDSP-2110 2.5 7.5 600 602

-2500

Yellow HDSP-2111 2.5 7.5 583 585

-2501

High HDSP-2113 2.5 7.5 568 574

Performance -2503

Green

Note: 1. Refers to the initial case temperature of the device immediately prior to measurement.

[1]

AC Timing Characteristics Over Temperature Range (-45°C to +85°C)

4.5 V < VDD < 5.5 V, unless otherwise specified

Reference

Number Symbol Description Min.[1] Units

ACC Display Access Time

Write 210

Read 230 ns

ACS Address Setup Time to Chip Enable 10 ns

CE Chip Enable Active Time[2,3]

Write 140

Read 160 ns

ACH Address Hold Time to Chip Enable 20 ns

CER Chip Enable Recovery Time 60 ns

CES Chip Enable Active Prior to Rising Edge of[2,3]

Write 140

Read 160 ns

CEH Chip Enable Hold Time to Rising Edge of

Read/Write Signal[2,3] 0ns

Write Active Time 100 ns

WSU Data Write Setup Time 50 ns

10 tWH Data Write Hold Time 20 ns

11 tRChip Enable Active Prior to Valid Data 160 ns

12 tRD Read Active Prior to Valid Data 75 ns

13 tDF Read Data Float Delay 10 ns

tRC Reset Active Time[4] 300 ns

Notes:

1. Worst case values occur at an IC junction temperature of 150° C.

2. For designers who do not need to read from the display, the Read line can be tied to V

DD and the Write and Chip Enable lines can be

tied together.

3. Changing the logic levels of the Address lines when CE = “0” may cause erroneous data to be entered into the Character RAM,

regardless of the logic levels of the WR and RD lines.

4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the

reset line.

AC Timing Characteristics Over Temperature Range (-45°C to +85°C)

4.5 V < VDD < 5.5 V, unless otherwise specified

Write Cycle Timing Diagram

Symbol Description 25°C Typ. Min.[1] Units

FOSC Oscillator Frequency 57 28 kHz

FRF[2] Display Refresh Rate 256 128 Hz

FFL[3] Character Flash Rate 2 1 Hz

tST[4] Self Test Cycle Time 4.6 9.2 sec

Notes:

1. Worst case values occur at an IC junction temperature of 150°C.

2. FRF = FOSC/224

3. FFL = FOSC/28,672

4. tST = 262,144/FOSC

INPUT PULSE LEVELS: 0.6 V TO 2.4 V

Read Cycle Timing Diagram

Relative Luminous Intensity vs. Temperature

HER HDSP-2112/2502

HDSP-2113/2503

YELLOW HDSP-2111/2501

Electrical Description

Pin Function Description

RESET (RST, pin 1) Initializes the display.

FLASH (FL, pin 2) FL low indicates an access to the Flash RAM and is unaffected by the

state of address lines A3-A4.

ADDRESS INPUTS Each location in memory has a distinct address. Address inputs (A0-A2)

(A0-A4, pins 3-6, 10) select a specific location in the Character RAM, the Flash RAM or a

particular row in the UDC (User-Defined Character) RAM. A3-A4 are

used to select which section of memory is accessed. Table 1 shows the

logic levels needed to access each section of memory.

Table 1. Logic Levels to Access Memory

Section of Memory FL A4 A3A2 A1 A0

Flash RAM 0 X X Char. Address

UDC Address Register 1 0 0 Don't Care

UDC RAM 1 0 1 Row Address

Control Word Register 1 1 0 Don’t Care

Character RAM 1 1 1 Character Address

CLOCK SELECT Used to select either an internal (CLS = 1) or external (CLS = 0) clock source.

(CLS, pin 11)

CLOCK INPUT/OUTPUT Outputs the master clock (CLS = 1) or inputs a clock (CLS = 0) for slave

(CLK, pin 12) displays.

WRITE (WR, pin 13) Data is written into the display when the WR input is low and the

CE input is low.

CHIP ENABLE (CE, pin 17) Must be at a logic low to read or write data to the display and must go

high between each read and write cycle.

READ (RD, pin 18) Data is read from the display when the RD input is low and the CE

input is low.

DATA Bus (D0-D7, Used to read from or write to the display.

pins 19, 20, 23-28)

GND (SUPPLY) (pin 15) Analog ground for the LED drivers.

GND (LOGIC) (pin 16) Digital ground for internal logic.

VDD (POWER) (pin 14) Positive power supply input.

Figure 1. HDSP-210X/-211X/-212X/-250X Internal Block Diagram.

Character RAM This RAM stores either ASCII character data or a UDC RAM address.

Flash RAM This is a 1 x 8 RAM which stores Flash data.

User-Defined Character RAM This RAM stores the dot pattern for custom characters.

(UDC RAM)

User-Defined Character This register is used to provide the address to the UDC RAM when

Address Register the user is writing or reading a custom character.

(UDC Address Register)

Control Word Register This register allows the user to adjust the display brightness, flash

individual characters, blink, self test, or clear the display.

Display Internal Block

Diagram

Figure 1 shows the internal block

diagram of the HDSP-210X/

-211X/-250X displays. The CMOS

IC consists of an 8 byte Character

RAM, an 8 bit Flash RAM, a 128

character ASCII decoder, a 16

character UDC RAM, a UDC

Address Register, a Control Word

necessary to synchronize the

decoding and driving of eight 5 x

7 dot matrix characters. The

major user-accessible portions of

the display are listed below:

Character Ram

Figure 2 shows the logic levels

needed to access the

HDSP-210X/-211X/-250X

Character RAM. During a normal

access, the CE = “0” and either

RD = “0” or WR = “0.” However,

erroneous data may be written

into the Character RAM if the

address lines are unstable when

CE = “0” regardless of the logic

levels of the RD or WR lines.

Address lines A0-A2 are used to

select the location in the Charac-

ter RAM. Two types of data can

be stored in each Character RAM

location: an ASCII code or a UDC

RAM address. Data bit D7 is used

to differentiate between the ASCII

character and a UDC RAM

address. D7 = 0 enables the ASCII

decoder and D7 = 1 enables the

UDC RAM. D0-D6 are used to

input ASCII data and D0-D3 are

used to input a UDC address.

Figure 2. Logic Levels to Access the Character RAM.

UDC RAM and UDC Address

Figure 3 shows the logic levels

needed to access the UDC RAM

and the UDC Address Register.

The UDC Address Register is

eight bits wide. The lower four

bits (D0-D3) are used to select one

of the 16 UDC locations. The

upper four bits (D4-D7) are not

used. Once the UDC address has

been stored in the UDC Address

accessed.

To completely specify a 5 x 7

character, eight write cycles are

required. One cycle is used to

store the UDC RAM address in the

UDC Address Register and seven

cycles are used to store dot data

in the UDC RAM. Data is entered

by rows and one cycle is needed

to access each row. Figure 4

shows the organization of a UDC

character assuming the symbol to

be stored is an “F.” A0-A2 are used

to select the row to be accessed

and D0-D4 are used to transmit

the row dot data. The upper three

bits (D5-D7) are ignored. D0 (least

significant bit) corresponds to the

right most column of the 5 x 7

matrix and D4 (most significant

bit) corresponds to the left most

column of the 5 x 7 matrix.

Flash RAM

Figure 5 shows the logic levels

needed to access the Flash RAM.

The Flash RAM has one bit

associated with each location of

the Character RAM. The Flash

input is used to select the Flash

RAM while address lines A3-A4 are

ignored. Address lines A0-A2 are

used to select the location in the

Flash RAM to store the attribute.

D0 is used to store or remove the

flash attribute. D0 = “1” stores

the attribute and D0 = “0”

removes the attribute.

When the attribute is enabled

through bit 3 of the Control Word

and a “1” is stored in the Flash

RAM, the corresponding

character will flash at approxi-

mately 2 Hz. The actual rate is

dependent on the clock frequency.

For an external clock the flash

rate can be calculated by dividing

the clock frequency by 28,672.

CCCCC

OOOOO

LLLLL

12345 UDC HEX

D4D3D2D1D0CHARACTER CODE

11111 ROW 1 * * * * * 1F

10000 ROW 2 * 10

10000 ROW 3 * 10

11110 ROW 4 * * * * 1D

10000 ROW 5 * 10

10000 ROW 6 * 10

10000 ROW 7 * 10

IGNORED

0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED.

Figure 4. Data to Load ""F'' into the UDC RAM.

Figure 3. Logic Levels to Access a UDC Character.

Figure 5. Logic Levels to Access the Flash RAM.

Table 2. Current Requirements at

Different Brightness Levels VDD = 5.0 V

% Current at 25°C

Symbol D2D1D0Brightness Typ. Units

IDD (V) 0 0 0 100 200 mA

0 0 1 80 160 mA

0 1 0 53 106 mA

011 40 80 mA

100 27 54 mA

101 20 40 mA

110 13 26 mA

Figure 6. Logic Levels to Access the Control Word

Control Word Register

Figure 6 shows how to access the

Control Word Register. This 8-bit

Brightness control, Flash RAM

control, Blinking, Self Test, and

Clear. Each function is

independent of the others; how-

ever, all bits are updated during

each Control Word write cycle.

Brightness (Bits 0-2)

Bits 0-2 of the Control Word

adjust the brightness of the

display. Bits 0-2 are interpreted

as a three bit binary code with

code (000) corresponding to

maximum brightness and code

(111) corresponding to a blanked

display. In addition to varying the

display brightness, bits 0-2 also

vary the average value of IDD. IDD

can be calculated at any bright-

ness level by multiplying the

percent brightness level by the

value of IDD at the 100% bright-

ness level. These values of IDD are

shown in Table 2.

Flash Function (Bit 3)

Bit 3 determines whether the

flashing character attribute is on

or off. When bit 3 is a“1,” the

output of the Flash RAM is

checked. If the content of a loca-

tion in the Flash RAM is a “1,” the

associated digit will flash at

approximately 2 Hz. For an

external clock, the blink rate can

be calculated by driving the clock

frequency by 28,672. If the flash

enable bit of the Control Word is

a “0,” the content of the Flash

RAM is ignored. To use this

function with multiple display

systems, see the Display Reset

section.

Blink Function (Bit 4)

Bit 4 of the Control Word is used

to synchronize blinking of all

eight digits of the display. When

this bit is a “1” all eight digits of

the display will blink at approxi-

mately 2 Hz. The actual rate is

dependent on the clock frequency.

For an external clock, the blink

rate can be calculated by dividing

the clock frequency by 28,672.

This function will override the

Flash function when it is active.

To use this function with multiple

display systems, see the Display

Reset section.

Self Test Function (Bits 5, 6)

Bit 6 of the Control Word Register

is used to initiate the self test

function. Results of the internal

self test are stored in bit 5 of the

Control Word. Bit 5 is a read only

bit where bit 5 = “1” indicates a

passed self test and bit 5 = “0”

indicates a failed self test.

Setting bit 6 to a logic 1 will start

the self test function. The built-in

self test function of the IC

consists of two internal routines

which exercise major portions of

the IC and illuminate all of the

LEDs. The first routine cycles the

ASCII decoder ROM through all

states and performs a checksum

on the output. If the checksum

agrees with the correct value, bit

5 is set to “1.” The second routine

provides a visual test of the LEDs

using the drive circuitry. This is

accomplished by writing

checkered and inverse checkered

patterns to the display. Each

pattern is displayed for approxi-

mately 2 seconds.

During the self test function the

display must not be accessed. The

time needed to execute the self

test function is calculated by

multiplying the clock period by

262,144. For example, assume a

clock frequency of 58 KHz, then

the time to execute the self test

function frequency is equal to

(262,144/58,000) = 4.5 second

duration.

At the end of the self test func-

tion, the Character RAM is loaded

with blanks, the Control Word

bit 5, the Flash RAM is cleared,

and the UDC Address Register is

set to all ones.

Clear Function (Bit 7)

Bit 7 of the Control Word will

clear the Character RAM and the

Flash RAM. Setting bit 7 to a “1”

will start the clear function. Three

clock cycles (110 ms minimum

using the internal refresh clock)

are required to complete the clear

function. The display must not be

accessed while the display is

being cleared. When the clear

function has been completed, bit

7 will be reset to a “0.” The ASCII

character code for a space (20H)

will be loaded into the Character

RAM to blank the display and the

Flash RAM will be loaded with

“0”s. The UDC RAM, UDC

Address Register, and the re-

mainder of the Control Word are

unaffected.

Display Reset

Figure 7 shows the logic levels

needed to Reset the display. The

display should be Reset on

Power-up. The external Reset

clears the Character RAM, Flash

RAM, Control Word and resets

the internal counters. After the

rising edge of the Reset signal,

three clock cycles (110 µs

minimum using the internal

refresh clock) are required to

complete the reset sequence. The

display must not be accessed

while the display is being reset.

The ASCII Character code for a

space (20H) will be loaded into

the Character RAM to blank the

display. The Flash RAM and

Control Word Register are loaded

with all “0”s. The UDC RAM and

UDC Address Register are

unaffected. All displays which

operate with the same clock

source must be simultaneously

reset to synchronize the Flashing

and Blinking functions.

Mechanical and Electrical

Considerations

The HDSP-210X/-211X/-250X are

28 pin dual-in-line packages with

26 external pins. The devices can

be stacked horizontally and verti-

cally to create arrays of any size.

The HDSP-210X/-211X/-250X are

designed to operate continuously

from -45°C to +85°C with a

maximum of 20 dots on per

character at 5.25 V. Illuminating

all thirty-five dots at full bright-

ness is not recommended.

The HDSP-210X/-211X/-250X are

assembled by die attaching and

wire bonding 280 LED chips and

a CMOS IC to a thermally

conductive printed circuit board.

A polycarbonate lens is placed

over the PC board creating an air

gap over the LED wire bonds. A

protective cap creates an air gap

over the CMOS IC. Backfill epoxy

environmentally seals the display

package. This package

construction makes the display

highly tolerant to temperature

cycling and allows wave

soldering.

The inputs to the IC are protected

against static discharge and input

current latchup. However, for

best results standard CMOS

handling precautions should be

Figure 7. Logic Levels to Reset the

Display.

used. Prior to use, the HDSP-

210X/-211X/-250X should be

stored in antistatic tubes or in

conductive material. During

assembly, a grounded conductive

work area should be used, and

assembly personnel should wear

conductive wrist straps. Lab

coats made of synthetic material

should be avoided since they are

prone to static buildup. Input

current latchup is caused when

the CMOS inputs are subjected to

either a voltage below ground

(VIN < ground) or to a voltage

higher than V

DD (VIN > VDD) and

when a high current is forced into

the input. To prevent input

current latchup and ESD damage,

unused inputs should be con-

nected either to ground or to VDD.

Voltages should not be applied to

the inputs until VDD has been

applied to the display.

Thermal Considerations

The HDSP-210X/-211X/-212X/

250X have been designed to

provide a low thermal resistance

path for the CMOS IC to the 26

package pins. Heat is typically

conducted through the traces of

the printed circuit board to free

air. For most applications no

additional heatsinking is

required.

Measurements were made on a 32

character display string to

determine the thermal resistance

of the display assembly. Several

display boards were constructed

using 0.062 in. thick printed

circuit material, and one ounce

copper 0.020 in. traces. Some of

the device pins were connected to

a heatsink formed by etching a

copper area on the printed circuit

board surrounding the display. A

maximally metallized printed

circuit board was also evaluated.

The junction temperature was

measured for displays soldered

directly to these PC boards,

displays installed in sockets, and

finally displays installed in

sockets with a filter over the

display to restrict airflow. The

results of these thermal

resistance measurements, RθJ-A

are shown in Table 3 and include

the effects of RθJ-C.

Ground Connections

Two ground pins are provided to

keep the internal IC logic ground

clean. The designer can, when

necessary, route the analog

ground for the LED drivers

separately from the logic ground

until an appropriate ground plane

is available. On long interconnec-

tions between the display and the

host system, the designer can

keep voltage drops on the analog

ground from affecting the display

logic levels by isolating the two

grounds.

The logic ground should be

connected to the same ground

potential as the logic interface

circuitry. The analog ground and

the logic ground should be

connected at a common ground

which can withstand the current

introduced by the switching LED

drivers. When separate ground

connections are used, the analog

ground can vary from -0.3 V to

+0.3 V with respect to the logic

ground. Voltage below -0.3 V can

cause all dots to be on. Voltage

above +0.3 V can cause dimming

and dot mismatch.

Soldering and Post Solder

Cleaning Instructions for

the HDSP-210X/-211X/

-250X

The HDSP-210X/-211X/-250X

may be hand soldered or wave

soldered with SN63 solder. When

hand soldering, it is recom-

mended that an electronically

temperature controlled and

securely grounded soldering iron

be used. For best results, the iron

tip temperature should be set at

315°C (600°F). For wave solder-

ing, a rosin-based RMA flux can

be used. The solder wave temper-

ature should be set at 245°C ±

5°C (473°F ± 9°F), and the dwell

in the wave should be set

between 11 /2 to 3 seconds for

optimum soldering. The preheat

temperature should not exceed

105°C (221°F) as measured on

the solder side of the PC board.

Table 3. Thermal Resistance, θJA, Using Various Amounts of

Heatsinking Material

Heatsinking

Metal W/Sockets W/O Sockets W/Sockets

per Device W/O Filter W/O Filter W/Filter

sq. in. (Avg.) (Avg.) (Avg.) Units

0313035°C/W

1312833°C/W

3302633°C/W

Max. Metal 29 25 32 °C/W

4 Board Avg 30 27 33 °C/W

www.semiconductor.agilent.com

Data subject to change.

October 29, 2001

Obsoletes 5988-2259EN

5988-4668EN

Color Range (nm)

Color Bin Min. Max.

Yellow 3 581.5 585.0

4 584.0 587.5

5 586.5 590.0

6 589.0 592.5

7 591.5 595.0

Green 1 576.0 580.0

2 573.0 577.0

3 570.0 574.0

4 567.0 571.5

Intensity Range (mcd)

Bin Min. Max.

I 5.12 9.01

J 7.68 13.52

K 11.52 20.28

L 17.27 30.42

M 25.39 45.63

Note:

Test conditions as specified in Optical Characteristic table.

Color Bin Limits

Note:

Test conditions as specified in Optical Characteristic table.

Intensity Range (mcd)

Bin Min. Max.

G 2.50 4.00

H 3.41 6.01

I 5.12 9.01

J 7.68 13.52

K 11.52 20.28

Note:

Test conditions as specified in Optical Characteristic table.

Intensity Bin Limits for HDSP-2107

Intensity Bin Limits for HDSP-211x

and HDSP-250x

For additional information on

soldering and post solder clean-

ing, see Application Note 1027,

Soldering LED Components.

Contrast Enhancement

The objective of contrast

enhancement is to provide good

readability in a variety of ambient

lighting conditions. For informa-

tion on contrast enhancement see

Application Note 1015, Contrast

Enhancement Techniques for

LED Displays.