M29F400BT70N6E - Numonyx - Product.Network

March 2007 Rev 5 1/40

M29F400BT

M29F400BB

4 Mbit (512Kb x8 or 256Kb x16, Boot Block)

single supply Flash memory

Features

■Single 5 V ± 10% supply voltage for program,

erase and read operations

■Access tim e: 45 ns

■Programming time

– 8 µs per Byte/Word typical

■11 memory blocks

– 1 Boot Block (Top or Bottom Location)

– 2 Param eter and 8 Main Blocks

■Program/erase contr oller

– Embedded Byte/Word Progr am algorithm

– Embedded Multi-Block/Chip Erase

algorithm

– Status Register Polling and Toggle Bits

– Ready/Bu sy Ou tp ut Pin

■Erase Susp end and Resume modes

– Read and Program anot he r Block during

Erase Suspend

■Unlock Bypass Program command

– Faster Production/Batch Programming

■Temporary block unprotection mode

■Low power consumption

– Standby and Automatic Standby

■100,000 progr am/erase cycles per block

■20-year data ret ention

– Defectivity below 1 ppm/year

■Electronic signature

– Manufacturer Code: 0020h

– Top Device Code M29F400BT: 00D5h

– Bottom Device Code M29F400BB: 00D6h

■ECOPACK® packages available

TSOP48 (N)

12 x 20mm

SO44 (M)

www.st.com

Contents M29F400BT, M29F400BB

2/40

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1 Address inputs (A0-A17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Data inputs/outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Data inputs/outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Data input/output or address input (DQ15A-1) . . . . . . . . . . . . . . . . . . . . . 10

2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.8 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.9 Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.10 Byte/Word organization select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.11 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.12 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.6.2 Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 14

4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.5 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

M29F400BT, M29F400BB Contents

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4.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.9 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.10 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.11 Read/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.12 Auto Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.13 Program, Unlock Bypass Program, Chip Erase, Block Erase . . . . . . . . . 20

4.14 Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.15 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.16 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.17 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 27

8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Appendix A Block address tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

List of tables M29F400BT, M29F400BB

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List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 3. Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 5. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 6. Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 8. Program/ Erase times endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 12. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 15. Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package mecha nical data. . . . 35

Table 17. SO44 - 44 lead Plastic Sm all Outline, 500 mils body width, package mechanical data . . . 36

Table 18. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 19. Top boot block addresses, M29F400BT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 20. Bottom boot block addresses, M29F400BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

M29F400BT, M29F400BB List of figures

5/40

List of figures

Figure 1. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 5. Data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6. AC testing input output waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 7. AC testing load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 8. Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 9. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 10. Write AC waveforms, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 12. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 35

Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package outline. . . . . . . . . . . 36

Description M29F400BT, M29F400BB

6/40

1 Description

The M29F400B is a 4 Mbit (512 Kb x8 or 256 Kb x16) non-v olatile m emory that can be read,

erased and r eprogrammed. These operations can be performed using a single 5V supply.

On power-up the memory defaults to its Read mode where it can be read in the same way

as a ROM or EPROM. Th e M29F400B is fully backward compatible with the M29F400.

The memory is divided into blocks that can be erased independen tly so it is possibl e to

preserve valid data while old data is erased. Each block can be protected ind ependently to

prevent accidental Program or Erase commands from modif ying the memory. Program and

Erase commands are written to the Command Interface of the memory. An on-chip

Program/Erase Controller simplifies the process of progr amming or erasing the memory by

taking care of all o f the sp ecial operations that a re requir ed to update t he memory contents.

The end of a program or erase operation can be detected and any error conditions

identified. The command set required to control the memory is consistent with JEDEC

standards.

The blocks in the memory are asym metrically arranged, see Table 19. and Table 20., Block

Addresses. The first or last 64 Kbytes ha ve been divided into four additional blocks. The 16

Kbyte Boot Block can be used for small initialization code to start the microprocessor, the

two 8 Kb yt e Pa ramete r Bloc ks can be u sed for pa ramet er stor age an d the remainin g 32 K is

a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the

memory. They allow simple connection to most microprocessors, often without additional

logic.

The memory is off er ed in TSOP48 (12 x 20 mm) and SO44 packages and it is sup plied with

all the bits erased (set to ’1’).

In order to meet environmental requirements, ST offers the M29F400B in ECOPACK®

packages.

ECOPACK packages are Lead-free. The category of seco nd Level Interconnect is marked

on the package and on the inner box label, in compliance with JEDEC Standard JESD97.

The maximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

M29F400BT, M29F400BB D escription

7/40

Figure 1. Logic diagram

Table 1. Signal names

A0-A17 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

EChip Enable

GOutput Enable

WWrite Enable

RP Reset/Block Temporary Unprotect

RB Ready/Busy Output

BYTE Byte/Word Organization Select

VCC Supply voltage

VSS Ground

NC Not Connected Internally

AI02904

A0-A17

DQ0-DQ14

VCC

M29F400BT

M29F400BB

VSS

DQ15A–1

BYTE

Description M29F400BT, M29F400BB

8/40

Figure 2. TSOP connections

DQ3

DQ9

DQ2

A6 DQ0

DQ6

A9 DQ13

A17

A10 DQ14

DQ12

DQ10

DQ15A–1

VCC

DQ4

DQ5

DQ7

AI02905

M29F400BT

M29F400BB

24 25

DQ8

DQ1

DQ11

A12

A13

A16

A11

BYTE

A15

A14 VSS

VSS

M29F400BT, M29F400BB D escription

9/40

Figure 3. SO connections

DQ0

DQ8

VSS

A13

VSS

A14

A15

DQ7

A12

A16

BYTE

DQ15A–1

DQ5DQ2

DQ3 VCC

DQ11 DQ4

DQ14

WRB

NC RP

AI02906

M29F400BT

M29F400BB

2322

17DQ1

DQ9

DQ6

DQ13

A11

A10

DQ10 21 DQ12

A17 A8

Signal descriptions M29F400BT, M29F400BB

10/40

2 Signal descriptions

See Figure 1 ., Logic Diagram, and Tab le 1., Signal Names, for a brief ov erview of the sig nals

connected to this device.

2.1 Address inputs (A0-A17)

The Address Inputs select the cells in the me mory array to access during Bus Read

operations. During Bus Write operations they cont rol the commands sent to the Command

Interface of the internal state machine.

2.2 Data inputs/outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operat ion. During Bus Write operations t hey r epresent the command s sent to the Command

Interface of the internal state machine.

2.3 Data inputs/outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operat ion when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used an d are

high impedance. During Bus Write operations the Command Register does not use these

bits. When reading the Status Register these bits should be ignored.

2.4 Data input/output or address input (DQ15A-1)

When BYTE is High, VIH, this pin beha ves as a Dat a Input/Output pin ( as DQ8-DQ14).

When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the

LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout

the text conside r references to the Data Input/Output to include this pin when BYTE is High

and references to the Address Inputs to include this pin when BYTE is Low except when

stated explicitly otherwise.

2.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

M29F400BT, M29F400BB Signal descriptions

11/40

2.7 Write Enable (W)

The Write Enab le , W, controls the Bus Write operation of the memory’s Com mand Inte rface .

2.8 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the

memory or to temporarily unprotect all Blocks that have been protected.

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at

least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be

ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.

See the Ready/Busy Output section, Table 15. and Figure 11., Reset/Temporary Unprotect

AC Characteristics f or more details.

Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program

and Erase operations on all blocks will be possible. The tr ansition from VIH to VID must be

slower than tPHPHH.

2.9 Ready/Busy output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the memory

array can be read. Ready/Busy is high-impedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardw are Reset, Bus Read and Bus Write oper ations cannot begi n until Ready/Busy

becomes high-impedance. See Table 15. and Figure 11., Reset/Temporary Unprotect AC

Characteristics.

During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy will remain Low

during Read/Reset commands o r Hardwa re Resets until the memory is ready to enter Read

mode.

The use of an open-drain output allows the Ready/Busy pins from se veral memories to be

connected to a single pull-up resistor. A Low will then indicate that one, or more, of the

memories is busy.

2.10 Byte/Word organization select (BYTE)

The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus

modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8-

bit mode, when it is High, VIH, the memory is in 16-bit mode.

Signal descriptions M29F400BT, M29F400BB

12/40

2.11 VCC supply volta ge

The VCC Supply Voltage supplies the power f or all operations (Read, Progra m, Erase etc.).

The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout

Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data

during pow er up, power do wn and power surges . If the Program/Erase Controller is

progr amming or erasin g during this time then th e operation abo rts and the memory contents

being altered will be invalid.

A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS

Ground pin to decouple the current surges from the power supply. The PCB track widths

must be sufficient to carry the currents required during program and erase operations, ICC4.

2.12 VSS ground

The VSS Ground is the reference for all voltage measurements.

M29F400BT, M29F400BB Bus operations

13/40

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus

Write, Output Disable, Standby and Automatic Standby. See Table 2. and Tabl e 3., Bus

Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write

Enable are ignored by the memory and do not affect bus oper ations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command

Interface. A valid Bus Read operation involves setting the desired address on the Address

Inputs , applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write

Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 8., Read Mode

AC Waveforms, and Table 12., Read AC Characteristics, for details of whe n the output

becomes valid.

3.2 Bus Write

Bus Write operations write to the Command I nterf ace. A v alid Bus Write operat ion begins b y

setting the desire d address on the Address Inputs. The Address Inputs are latched by the

Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs

last. The Data Inputs/Outputs are latched by t he Command Interface on the rising edge of

Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,

durin g the who le Bu s Write operation. See Figure 9. and Figure 10., Write AC Waveforms,

and Tab le 13 . and Table 14., Write AC Cha r acteristics, for detail s of the timing requireme nts .

3.3 Output Disable

The Data Inputs/Outputs are in the high imp edance state when Output Enable is High, VIH.

3.4 Standby

When Chip Enable is High, VIH, the Data Inputs/Outputs pins are placed in the high-

impedance state and the Supply Current is reduced to the Standby level.

When Chip Enable is at VIH the Supply Current is reduced to the TTL Standby Supply

Current, ICC2. To further reduce the Supply Current to the CMOS Standby Supply Current,

ICC3, Chip Enable should be held within VCC ± 0.2V. For Standby current levels see Table

11., DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase

Supply Current, ICC4, for Program or Erase operations until the operation completes.

Bus operations M29F400BT, M29F400BB

14/40

3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or

more the memory enters A utomatic Standb y where the inte rnal Supply Current is reduced to

the CMOS Standby Supply Current, ICC3. The Data Inputs/Outputs will still output data if a

Bus Read operation is in progress.

3.6 Special bus operations

Additional bus operations can be performed to read the Electronic Signature and also to

apply and remove Block Protection. These bus operations are intended f or use by

programming equipment an d are not usually used in application s. They require VID to be

applied to some pins.

3.6.1 Electronic Signature

The memory has two codes, the manufacturer code and the device code , that can be read

to identify the memory. These codes can be read by applying the signals listed in Table 2.

and Table 3., Bus Operations.

3.6.2 Block Protection and Blocks Unprotection

Each block can be separately protected against accidental Program or Erase. Protected

bl ocks can be unprotected to allow data to be changed.

There are two methods availab le for protecting and unprotecting the blocks, one for use on

programming equipment and the other for in-system use. For further information refer to

Application Note AN1122, Ap plying Protection and Unprotection to M29 Series Flash.

Table 2. Bus operations, BYTE = VIL(1)

1. X = VIL or VIH.

Operation E G W Address Inputs

DQ15A–1, A0-A17

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Bus Read VIL VIL VIH Cell Address Hi-Z Data Output

Bus Write VIL VIH VIL Command Address Hi-Z Data Input

Output Disable X VIH VIH X Hi-Z Hi-Z

Standby VIH X X X Hi-Z Hi-Z

Read Manufa cturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9

= VID, Others VIL or VIH Hi-Z 20h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9

= VID, Others VIL or VIH Hi-Z D5h (M29F400BT)

D6h (M29F400BB)

M29F400BT, M29F400BB Bus operations

15/40

Table 3. Bus operations, BYTE = VIH(1)

1. X = VIL or VIH.

Operation E G W Address Inputs

A0-A17 Data In put s/Outputs

DQ15A–1, DQ14-DQ0

Bus Read VIL VIL VIH Cell Address Data Output

Bus Write VIL VIH VIL Command Address Data Input

Output Disable X VIH VIH XHi-Z

Standby VIH XXX Hi-Z

Read Manufa cturer

Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 =

VID, Others VIL or VIH 0020h

Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 =

VID, Others VIL or VIH

00D5h (M29F 4 00 BT)

00D6h (M29F400BB)

Command interface M29F400BT, M29F400BB

16/40

4 Command interface

All Bus Write operations to the memory are int erpreted by the Command Interface.

Commands consist of one or more sequential Bus Write operations. Fa ilur e to observe a

v alid sequence of Bus Write operations will result in the memory returning to Read mode.

The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16-

bit or 8-bit mode. See either Table 4., or Table 5. , depending on the configuration that is

being used, for a summary of the commands.

4.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode where it behaves lik e a

RO M or EPROM. It also resets the errors in the Status Register. Either one or three Bus

Write operations can be used to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or followin g a

Programming or Erase error then the memory will take upto 10µs to abort. During the abort

period no v alid data can be read f rom the memory. Issuing a Read/Reset command during a

Block Erase operation will leave invalid data in the memory.

4.2 Auto Select command

The A uto Sele ct command is used t o read the Ma nuf act urer Code , the Device Code and the

Block Protection Status. Three consecutive Bus Write operations are required to issue the

Auto Select command. Once the Auto Select command is issued the memory remains in

Auto Select mode until another command is issued.

F rom the A uto Select mode the Manuf acture r Code can be read using a Bus Read ope ration

with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The

Manufactur er Code for STMicroelectronics is 0020h.

The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The

other address bits may be set t o either VIL or VIH. The Device Code f or the M29F400BT is

00D5h and for the M29F400BB is 00D6h.

The Block Protection Status of each block can be read using a Bus Read operation with A0

= VIL, A1 = VIH, and A12-A17 specifying the address of the block. The other address bits

ma y be set to either VIL or VIH. If th e addressed block is protected then 01h is outp ut on

Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

M29F400BT, M29F400BB Command interface

17/40

4.3 Program command

The Prog ram command can be used to prog ram a v alue to one address in the memory arra y

at a time. The command requir es f our Bus Write operat ions, the final write oper ation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data

remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to

issue any command to abort or pause the operation. Typical program times are given in

Table 8.. Bus Read operations during the program operation will output the Status Register

on the Data Inpu ts/Outputs. See the section on t he Status Register for mor e details.

After the progr am operation has completed the memory will return to the Read mode , unless

an error has occurred. When an error occurs the memory will continue to output the Status

Read mode.

Note that the Prog r am command ca nnot cha nge a bit set at ’0’ bac k to ’1’. One of the Er ase

Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.4 Unlock Bypass command

The Unloc k Bypass command is used in conjunction with the Unlock Bypass Program

command to program the memory. When the access time to the device is long (as with

some EPROM programmers) considerable time saving can be made by using these

commands. Thr ee Bus Write oper at ions ar e requir ed to issue t he Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock

Bypass Program command and th e Unlo ck Bypass Reset comm a nd . The mem o ry can be

read as if in Read mode.

4.5 Unlock Bypass Pr ogram command

The Unlock Bypass Program command can be used to program one address in memory at

a time. The command requires tw o Bus Write operations, th e final write operation latches

the address and data in the internal state machine and starts the Program/Erase Controller.

The Program operat ion using the Unlock Bypass Program command behaves identically to

the Program operation using the Program command. A protected bloc k cannot be

programmed; the operation cannot be aborted and the Status Register is read. Errors must

be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode.

See the Program command for details on the behavior.

4.6 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from

Unloc k Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass

Reset command.

Command interface M29F400BT, M29F400BB

18/40

4.7 Chip Erase command

The Chip Erase comman d can be used to erase the entire chip. Six Bus Write operations

are required to issue the Chip Erase Command and start the Prog ram/Erase Controller.

If any blocks are protected th en thes e are igno red an d all the other blocks are erased. If all

of the blocks are protected the Chip Erase operation appears to start but will terminate

within about 100µs , leaving the data unchange d. No error condition is given wh en protected

blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue

any command to abort the operation. Typical chip erase times are given in Table 8.. All Bus

Read operations during the Chip Erase oper ation will output the Status Register on the Data

Inputs/Outputs. See the section on the Status Register f or more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and

return to Read Mode.

The Chip Erase Comm and set s all of th e bits in unpr ot ected blocks of the m emory to ’1’. All

previous data is lost.

4.8 Block Erase command

The Block Erase comma nd can be used to e r ase a list of one or m ore blocks. Six Bus Write

operat ions are required to select the first b loc k in the list. Each additional bl ock in the list can

be selected by repeating the sixth Bus Write operation using the address of the additional

bl ock. The Block Erase o peration starts the Program/Erase Controller about 50µs after the

last Bus Write operation. Once the Program/Erase Controller starts it is not possible to

select any more blocks. Each additional block must therefore be selected within 50µs of the

last b loc k. The 50µs timer rest arts when an additio nal bloc k is select ed. The Status Regist er

can be read after the sixth Bus Write operation. See the Status Register for details on how

to identify if the Program/Erase Controller has started the Block Erase operation.

If an y selected b l oc ks are prote cted then t hese are ignored and all the other selected b locks

are erased. If all of the selected blocks are protected the Block Erase operation appears to

start but will terminate within about 100µs, lea ving the data unchanged. No error condition is

given when protec ted blo cks are ignored.

During the Block Erase oper ation the memory will ignore all commands except the Erase

Suspend and Read/Reset commands. Typical block erase times are given in Table 8.. All

Bus Read operations during the Block Er ase operation will output the Status Register on the

Data Inputs/Outputs. See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,

unless an error has occurred. When an error occurs the memory will continue to output the

Status Register. A Read/Reset command must be issued to reset the error condition and

return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All

previous data in the selected blocks is lost.

M29F400BT, M29F400BB Command interface

19/40

4.9 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase

operation and return the memory to Read mode. The command requires one Bus Write

operation.

The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command

being issued. Once the Program/Erase Controller has stopped the memory will be set to

Read mode and the Erase will be suspended. If the Erase Suspend command is issued

during the period when the memory is waiting for an addit ional block (before the

Program/Erase Controller starts) then the Erase is suspended immediately and will start

immediately when the Erase Resume Command is issued. It will not be possible to select

any further blocks for erasure after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being

erased; both Read and Program operations behave as normal on these blocks. Reading

from blocks that are being erased will output the Status Register. It is also possible to enter

the A uto Select mode: the memory will behave as in the A uto Select mode on all bloc ks until

a Read/Reset command returns the memory to Erase Suspend mode.

4.10 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller from

Erase Suspend. An erase can be suspended and resumed more than once.

Table 4. Commands, 16-bit mode, BYTE = VIH

Command

Length

Bus Write operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1XF0

3555AA2AA55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass

Reset 2X90X00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

Command interface M29F400BT, M29F400BB

20/40

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands;

A11-A17, DQ8-DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or

DQ15 when BYTE is VIH.

4.11 Read/Reset

After a Read/Reset command, read the memory as normal unt il another command is

issued.

4.12 Auto Select

After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

4.13 Program, Unlock Bypass Program, Chip Erase, Block Erase

After these commands rea d the Status Register until the Program/Erase Controller

completes and the memory returns to Read Mode. Add additional Bloc ks during Block

Erase Command with additional Bus Write Operations until Timeout Bit is set.

Table 5. Commands, 8-bit mode, BYTE = V IL(1) (2)

1. X = Don’t Care, PA = Program Address, PD = Program Data, BA = Any address in the Block.

2. All values are in hexadecimal.

Command

Length

Bus Write Operations

1st 2nd 3rd 4th 5th 6th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset 1X F0

3 AAA AA 555 55 X F0

Au to Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass

Program 2 X A0 PA PD

Unlock Bypass

Reset 2X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 X B0

Erase Resume 1 X 30

M29F400BT, M29F400BB Command interface

21/40

4.14 Unlock Bypass

After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset

commands.

4.15 Unlock Bypass Reset

After the Unlock Bypass Reset command read the memory as normal until another

command is issued.

4.16 Erase Suspend

After the Er a s e Suspend comma nd read no n-e r asing me mory bl ocks as normal, issue Auto

Select and Prog ram commands on non-erasing blocks as normal.

4.17 Erase Resume

After the Erase Resume command the suspended Erase operation resumes, read the

Status Register until the Program/Erase Controller completes and the memory returns to

Read Mode.

Status Register M29F400BT, M29F400BB

22/40

5 Status Register

Bus Read oper ations from any a ddress alwa ys read the Stat us Register during Program a nd

Erase operations. It is also read during Erase Suspend when an address within a block

being erased is accessed.

The bits in the Status Register are summarized in Table 6., Stat us Register Bits.

5.1 Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Erase Suspend. The Data

Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being

programmed to DQ7. After successful completion of the Program operation the memory

returns to Read mode and Bus Read operations from the address just programmed output

DQ7, not its complement.

During Erase operations the Data P olling Bit outputs ’0’, the complement of the erased state

of DQ7. After successful completion of the Erase operation the memory returns to Read

Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation

within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the

Program/Erase Controller has suspended th e Erase operation.

Figure 4., Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A

Valid Address is the address being programmed or an address within the block being

erased.

5.2 Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has

successfully completed its operation or if it has responded to an Er ase Suspend. The Toggle

Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations at any address . After successful completion of the

operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a b lock

being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has

suspended the Erase operation.

Figure 5., Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

M29F400BT, M29F400BB Status Register

23/40

5.3 Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The

Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the

correct data to the memory. If the Error Bit is set a Read /Reset command must be issued

before other commands are issued. The Error bit is output on DQ5 when the Status Register

is read.

Note that the Prog ram command cannot change a bit se t at ’0 ’ back to ’1’ and at temp tin g to

do so may or may not set DQ5 at ‘1’. In both cases, a successive Bus Read operation will

show the bit is still ‘0’. One of the Er ase commands must be used to set all the bits in a b lock

or in the whole memory from ’0’ to ’1’.

5.4 Erase Timer Bit (DQ3)

The Erase Timer Bit can be u sed to iden tify the st art of Program/Erase Controller operation

during a Bloc k Erase command. Once the Program/Erase Controller starts erasing the

Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit

is set to ’0’ and additional blo cks to be erased may be written to the Command Interface.

The Erase Timer Bit is output on DQ3 when the Status Regi ster is read.

5.5 Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during

Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is

read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,

etc., with successive Bus Read operations from addresses within the blocks being erased.

Once the oper ation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with

successive Bus Read ope r at ion s f rom addre sses within the blocks being era s ed. Bu s Read

operations to addresses within bloc ks not being erased will output the memory cell data as if

in Read mode.

After an Er ase oper ation that causes t he Error Bit to b e set the Alternative Toggle Bit can be

used to identify which block or blocks have caused the error. The Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses

within blocks that have not erased correctly. The Alternative Toggle Bit does not change if

the addressed block has erased correctly.

Status Register M29F400BT, M29F400BB

24/40

Figure 4. Data polling flowchart

Table 6. Status Register bits(1)

1. Unspecified data bits should be ignored.

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle 0 – – 0

Program During

Erase Suspend Any Address DQ7 Toggle 0 – – 0

Program Error Any Address DQ7 Toggle 1 – – 0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before

timeout Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Block Erase Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erase Suspend Erasing Block 1 No

Toggle 0 – Toggle 1

Non-Erasing Block Data read as nor mal 1

Erase Error Good Block Addr ess 0 Toggle 1 1 No Toggle 0

Faulty Bl ock Addr ess 0 Toggle 1 1 Toggle 0

READ DQ5 & DQ7

at VALID ADDRESS

START

READ DQ7

at VALID ADDRESS

FAIL PASS

AI03598

DQ7

DATA YES

YES

DQ5

= 1

DQ7

DATA YES

M29F400BT, M29F400BB Status Register

25/40

Figure 5. Data toggle flowchart

READ DQ6

START

READ DQ6

TWICE

FAIL PASS

AI01370B

DQ6

TOGGLE NO

YES

DQ5

= 1

YES

DQ6

TOGGLE

READ

DQ5 & DQ6

Maximum rating M29F400BT, M29F400BB

26/40

6 Maximum rating

Stressing the device abov e the rating l isted in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sect ions of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 7. Absolute maximum ratings

Symbol Parameter Value Unit

Ambient Operating Temperature (Temperature Range

Option 1) 0 to 70 °C

Ambient Operating Temperature (Temperature Range

Option 6) –40 to 85 °C

Ambient Operating Temperature (Temperature Range

Option 3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO(1)

1. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Input or Output Voltage –0.6 to 6 V

VCC Supply Voltage –0.6 to 6 V

VID Identification Voltage –0.6 to 13.5 V

M29F400BT, M29F400BB Program and erase times and endurance cycles

27/40

7 Program and erase times and endurance cycles

The Program and Erase times and the number of Program/ Erase cycles per block are

shown in Table 8. Exact erase times may chang e depe nding on th e memory array cond ition.

Table 8. Pr ogram/ Erase times endurance cycles(1)

1. TA = 0 to 70°C, –40 to 85°C or –40 to 125°C

Parameter Min Typ(2)

2. TA = 25°C, VCC = 5V.

Typical after

100k W/E Cycles

(2) Max Unit

Chip Erase (All bits in the memory set to ‘0’) 1.5 1.5 s

Chip Erase 5 5 20 s

Block Erase (64 Kbytes) 0.6 0.6 4 s

Program (Byte or Word) 8 8 150 µs

Chip Program (Byte by Byte) 4.5 4.5 18 s

Chip Program (Word by Word) 2.3 2.3 9 s

Program/Erase Cycles (per Block ) 100,000 cycles

DC and AC parameters M29F400BT, M29F400BB

28/40

8 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics Tables that

follow, are derived from tests performed under the Measurement Conditions summarized in

Table 9: A C m easurem ent cond itio ns . Design ers should ch ec k th at the operating conditions

in their circuit match t he operating conditions when relying on the quoted parameters.

Figure 6. AC testing input output waveform

Table 9. AC measurement conditions

Parameter M29F400B

45 / 55 70 / 90

AC Test Conditions High Speed Standard

Load Capacita nce (C L) 30pF 100pF

Input Rise and Fall Times ≤ 10ns ≤ 10ns

Input Pulse Voltag es 0 to 3V 0.45 to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2.0V

AI01275B

High Speed

1.5V

2.4V

Standard

0.45V

2.0V

0.8V

M29F400BT, M29F400BB DC and AC parameters

29/40

Figure 7. AC testing load circuit

Table 10. Capacitance(1) (2)

1. TA = 25 °C, f = 1 MHz

2. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance V OUT = 0V 12 pF

AI03027

1.3V

OUT

CL = 30pF or 100pF

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

DC and AC parameters M29F400BT, M29F400BB

30/40

Table 11. DC characteristics(1)

1. TA = 0 to 70°C, –40 to 85°C or –40 to 125°C

Symbol Parameter Test Condition Min Typ(2)

2. TA = 25 °C, VCC = 5V.

Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current (Read) E = VIL, G = VIH, f =

6MHz 720mA

ICC2 Supply Current (Standby)

TTL E = VIH 1mA

ICC3 Supply Current (Standby)

CMOS E = VCC ±0.2V,

RP = VCC ±0.2V 30 100 µA

ICC4(3)

3. Sampled only, not 100% tested.

Supply Current

(Program/Erase) Program/Erase

Controller active 20 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2 VCC +0.5 V

VOL Output Low Voltage IOL = 5.8mA 0.45 V

VOH

Output High Voltage TTL IOH = –2.5mA 2.4 V

Output High Voltage

CMOS IOH = –100µAV

CC –0.4 V

VID Identification Voltage 11.5 12.5 V

IID Identification Current A9 = VID 100 µA

VLKO(3) Prog ram/Erase Loc kout

Supply Voltage 3.2 4.2 V

M29F400BT, M29F400BB DC and AC parameters

31/40

Figure 8. Read mode AC waveforms

Table 12. Read AC characteristics(1)

1. TA = 0 to 70°C, –40 to 85°C or –40 to 125°C

Symbol Alt Parameter Test

Condition

M29F400B Unit

45 55 70 / 90

tAVAV tRC Address Valid to Next Address

Valid E = VIL,

G = VIL Min 45 55 70 ns

tAVQV tACC Address Valid to Output Valid E = VIL,

G = VIL Max 45 55 70 ns

tELQX(2)

2. Sampled only, not 100% tested.

tLZ Chip Enable Low to Output

Transition G = VIL Min 0 0 0 ns

tELQV tCE Chip Enable Low to Output Valid G = VIL Max 45 55 70 ns

tGLQX(2) tOLZ Output Enable Low to Output

Transition E = VIL Min 0 0 0 ns

tGLQV tOE Output Enable Low to Output Valid E = VIL Max 25 30 30 ns

tEHQZ(2) tHZ Chip Enable High to Output Hi-Z G = VIL Max 15 18 20 ns

tGHQZ(2) tDF Output Enable High to Output Hi-Z E = VIL Max 15 18 20 ns

tEHQX

tGHQX

tAXQX

tOH

Chip Enable, Output Enable or

Address Transition to Output

Transition Min 0 0 0 ns

tELBL

tELBH

tELFL

tELFH Chip Enable to BYTE Low or High Max 5 5 5 ns

tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 15 15 20 ns

tBHQV tFHQV BYTE High to Output Valid Max 30 30 30 ns

AI02907

tAVAV

tAVQV tAXQX

tELQX tEHQZ

tGLQV

tGLQX tGHQX

VALID

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

tELQV tEHQX

tGHQZ

VALID

tBHQV

tELBL/tELBH tBLQZ

BYTE

DC and AC parameters M29F400BT, M29F400BB

32/40

Figure 9. Write AC waveforms, Write Enable controlled

Table 13. Write AC characteristics, Write Enable controlled(1)

1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C

Symbol Alt Parameter M29F400B Unit

45 55 70 / 90

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 0 ns

tWLWH tWP Write Enable Low to Write Enable High Min 40 40 45 ns

tDVWH tDS Input Valid to Write Enable High Min 25 25 30 ns

tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns

tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns

tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 20 ns

tAVWL tAS Address Valid to Write Enable Low Min 0 0 0 ns

tWLAX tAH Write Enable Low to Address Transition Min 40 40 45 ns

tGHWL Output Enable High to Write Enable Low Min 0 0 0 ns

tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 0 ns

tWHRL(2)

2. Sampled only, not 100% tested.

tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 50 µs

AI01869C

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHEL

tWHEH

tWHWL

tELWL

tAVWL

tWHGL

tWLAX

tWHDX

tAVAV

tDVWH

tWLWHtGHWL

tWHRL

M29F400BT, M29F400BB DC and AC parameters

33/40

Figure 10. Write AC waveforms, Chip Enable controlled

Table 14. Write AC characteristics, Chip Enable contr olled(1)

1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C

Symbol Alt Parameter M29F400B Unit

45 55 70 / 90

tAVAV tWC Address Valid to Next Address Valid Min 45 55 70 ns

tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 0 ns

tELEH tCP Chip Enable Low to Chip Enable High Mi n 40 40 45 ns

tDVEH tDS Input Valid to Chip Enable High Min 25 25 30 ns

tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns

tEHWH tWH Chip Enable High to Write Enable High Min 0 0 0 ns

tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 20 ns

tAVEL tAS Address Valid to Chip Enable Low Min 0 0 0 ns

tELAX tAH Chip Enable Low to Address Transition Min 40 40 45 ns

tGHEL Output Enable High Chip Enable Low Min 0 0 0 ns

tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 0 ns

tEHRL(2)

2. Sampled only, not 100% tested.

tBUSY Program/Erase Valid to RB Low Max 30 30 30 ns

tVCHWL tVCS VCC High to Write Enable Low Min 50 50 50 µs

AI01870C

A0-A17/

A–1

DQ0-DQ7/

DQ8-DQ15

VALID

VCC

tVCHWL

tEHWH

tEHEL

tWLEL

tAVEL

tEHGL

tELAX

tEHDX

tAVAV

tDVEH

tELEHtGHEL

tEHRL

DC and AC parameters M29F400BT, M29F400BB

34/40

Figure 11. Reset/Block Temporary Unprotect AC waveforms

Table 15. Reset/Block Temporary Unprotect AC characteristics(1)

1. TA = 0 to 70 °C, –40 to 85 °C or –40 to 125 °C

Symbol Alt Parameter M29F400B Unit

45 55 70 / 90

tPHWL(2)

tPHEL

tPHGL(2)

2. Sampled only, not 100% tested.

tRH RP High to Write Enable Low, Chip

Enable Low, Output Enable Low Min 50 50 50 ns

tRHWL(2)

tRHEL(2)

tRHGL(2) tRB RB High to Write Enable Low, Chip

Enable Low, Output Enable Low Min 0 0 0 ns

tPLPX tRP RP Pulse Width Min 500 500 500 ns

tPLYH(2) tREADY RP Low to Read Mode Max 10 10 10 µs

tPHPHH(2) tVIDR RP Rise Time to VID Min 500 500 500 ns

AI02931

RP tPLPX

tPHWL, tPHEL, tPHGL

tPLYH

tPHPHH

E, G

tRHWL, tRHEL, tRHGL

M29F400BT, M29F 400BB Package mechanical

35/40

9 Package mechanical

Figure 12. TSOP48 - 48 lead Plas tic Thin Small Outline, 12 x 20mm, p ackage outline

1. Drawing is not to scale.

Table 16. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α3° 0° 5° 3° 0° 5°

TSOP-G

DIE

LA1 α

Package mechanical M29F400BT, M29F400BB

36/40

Figure 13. SO44 - 44 lead Plastic Small Outline, 500 mils body width, package

outline

1. Drawing is not to scale.

Table 17. SO44 - 44 lead Plastic Small Ou tline, 500 mils body width, package

mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A3.000.118

A1 0.10 0.004

A2 2.69 2.56 2.79 0.106 0.101 0.110

b 0.35 0.50 0.014 0.020

c 0.18 0.28 0.007 0.011

D 28.50 28.37 28.63 1.122 1.117 1.127

ddd 0.10 0.004

E 16.03 15.77 16.28 0.631 0.621 0.641

E1 12.60 12.47 12.73 0.496 0.491 0.501

e 1.27 – – 0.050 – –

L 0.79 0.031

L1 1.73 0.068

Θ8° 8°

N44 44

122

SO-F

LA1

ddd

M29F400BT, M29F400BB Part numbering

37/40

10 Part numbering

Note: The last two characters of the ord ering code may be replaced by a letter code for

preprogrammed parts , otherwise devices are shipped from the f actory with the memory

content bits erased to ‘1’.

For a list of available options (Speed, Package, etc...) or for further information on any

aspect of this device, please contact the ST Sales Office nearest to you.

Table 18. Ordering information scheme

Example: M29F400BB 55 N 1 T

Device Type

M29

Operating Voltage

F = VCC = 5V ± 10%

Device Function

400B = 4 Mbit (512Kb x8 or 256Kb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

45 = 45 ns

55 = 55 ns

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

M = SO44

Temperature Range

1 = 0 to 70 °C

3 = –40 to 125 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Block address tables M29F400BT, M29F400BB

38/40

Appendix A Block address tables

Table 19. Top boot block addresses, M29F400BT

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

10 16 7C000h-7FFFFh 3E000h-3FFFFh

9 8 7A000h-7BFFFh 3D000h-3DFFFh

8 8 78000h-79FFFh 3C000h-3CFFFh

7 32 70000h-77FFFh 38000h-3BFFFh

6 64 60000h-6FFFFh 30000h-37FFFh

5 64 50000h-5FFFFh 28000h-2FFFFh

4 64 40000h-4FFFFh 20000h-27FFFh

3 64 30000h-3FFFFh 18000h-1FFFFh

2 64 20000h-2FFFFh 10000h-17FFFh

1 64 10000h-1FFFFh 08000h-0FFFFh

0 64 00000h-0FFFFh 00000h-07FFFh

Table 20. Bottom boot block addresses, M29F400BB

#Size

(Kbytes) Address Range

(x8) Address Range

(x16)

10 64 70000h-7FFFFh 38000h-3FFFFh

9 64 60000h-6FFFFh 30000h-37FFFh

8 64 50000h-5FFFFh 28000h-2FFFFh

7 64 40000h-4FFFFh 20000h-27FFFh

6 64 30000h-3FFFFh 18000h-1FFFFh

5 64 20000h-2FFFFh 10000h-17FFFh

4 64 10000h-1FFFFh 08000h-0FFFFh

3 32 08000h-0FFFFh 04000h-07FFFh

2 8 06000h-07FFFh 03000h-03FFFh

1 8 04000h-05FFFh 02000h-02FFFh

0 16 00000h-03FFFh 00000h-01FFFh

M29F400BT, M29F400BB Revision history

39/40

Revision history

Table 21. Document revision hi story

Date Revision Changes

July 1999 First Issue

09/21/99

Chip Erase Max. specification added (Table 8.)

Block Erase Max. specification added (Table 8.)

Program Max. specification added (Tabl e 8.)

Chip Program Max. specification added (Table 8.)

ICC1 and ICC3 Typ. specification add ed ( Table 11.)

10/04/99 ICC3 Te st Condition change (Table 11.)

07/28/00 1.1

New document template

Document type: from Preliminary Data to Data Sheet

Status Register bit DQ5 clarification

Data Polling Flowchart diagram change (Figure 4.)

Data Toggle Flowchart diagram change (Figure 5.)

19-Sep-2005 2.0

Table 18. Ordering Information Scheme: standard package added

and ECOPACK v ersion added f or both standard package and Tape &

Reel packing.

TSOP48 Mechanical Data updated . SO4 4 525mm width changed to

500mm width.

20-Jul-2006 3 Document converted to new ST template. Small text changes.

Figure 12: TSOP48 - 48 lead Plasti c Thin Smal l Outlin e , 12 x 20mm,

package outline updated.

12-Dec-2006 4 Updated Table 18: Ordering information scheme.

22-Mar-2007 5 SO44 package code changed to ‘M’ inSection : Features .

M29F400BT, M29F400BB

40/40

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