Atmel-42618B-SmartConnect-ATSAMW25-MR210PB_Datasheet_05/2016
ATSAMW25-MR210PB
IEEE 802.11 b/g/n SmartConnect Wi-Fi Module
DATASHEET
Description
The Atmel® | SMART SAMW25 module is based on the industry-leading low-
power 2.4GHz IEEE® 802.11 b/g/n Wi-Fi® ATWINC1500 SoC (System on Chip)
combined with the ARM® Cortex®-M0+ based microcontroller technology from
Atmel.
This turnkey system provides an integrated software solution with application and
security protocols such as TLS and integrated network services (TCP/IP stack)
which are all available through Atmel Studio 6 integrated development
environment (IDE). The Atmel SmartConnect modules offer the ideal solutions for
designers seeking to add Wi-Fi connectivity with minimal previous experience in
802.11, IP Stack, or RF. Atmel SmartConnect Wi-Fi opens the door of the
Internet of Things (IoT) to the vast array of battery-powered devices and
applications requiring the integration of WLAN connectivity without compromising
on cost or power consumption. While we compete with other Wi-Fi modules on
size, RF performance, cost, and other characteristics, the Atmel SmartConnect
product family has a distinctive advantage when it comes to power consumption
and power saving modes. The ATSAMW25 device is a standalone end point,
where a complete small application can be executed on the module by itself.
Features
Key features with SAMW25 Wireless connectivity solution:
Certified Wi-Fi ATWINC1500B-MU-T with SAMD21 MCU
IEEE 802.11 b/g/n 20MHz (1x1) solution
Single spatial stream in 2.4GHz ISM band
Compact footprint: 33.863 x 14.882mm
Radio:
–
Output power - 802.11b /11Mbps: 17dBm ±1dB
– 802.11g /54Mbps: 16dBm ±1dB @ EVM -28dB
– 802.11n /72Mbps: 14dBm ±1dB @ EVM -30dB
Application processor:
–
Atmel SAM D21 ARM Cortex M0+ based microcontroller
–
256KB embedded Flash and 32KB SRAM
–
Full-Speed USB Device and embedded Host
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CryptoAuthentication™ ATECC508 (optional) I/O operating voltage:
2.7 to 3.6V
Power Amplifier and On-board Switching Regulator operating voltage:
2.7 to 4.3V
Power states supported:
–
Provision (AP/Sniffer) IDLE LISTEN
• IDLE
• SUSPEND
Extreme low-power, on-chip low-power sleep oscillator
Serial Host Interface SPI or UART
Software Upgrade Over-the-Air (OTA)
FCC, CE, IC, and TELEC Certified; RoHS compliant
Security protocols; WPA/WPA2 Personal, TLS, and SSL
Network services; DHCP, DNS, TCP/IP (IPv4), UDP, HTTP, and HTTPS
Target Applications
IoT applications
Smart appliances
Multimedia streaming
Safety and security
Home automation
Consumer electronics
Industrial automation
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Table of Contents
1 Block Diagram ............................................................................................................... 4
2 Ordering Information and IC Marking ........................................................................... 4
3 Pinout and Package Information .................................................................................. 5
3.1
Pin Description ........................................................................................................................................ 5
3.2
Package Description ............................................................................................................................... 8
4 Electrical Specifications ................................................................................................ 9
4.1
Absolute Ratings ..................................................................................................................................... 9
4.2
Recommended Operating Conditions ................................................................................................... 10
4.3
DC Electrical Characteristics ................................................................................................................. 10
5 Application and Core Subsystems ............................................................................. 11
5.1
Host Processor ...................................................................................................................................... 11
5.1.1
Host MCU Description .............................................................................................................. 11
5.1.2
Host MCU Key Features ........................................................................................................... 11
5.2
Wi-Fi Core Processor ............................................................................................................................ 11
5.2.1
Memory Subsystem .................................................................................................................. 12
5.2.2
Non-volatile Memory (eFuse).................................................................................................... 12
6 WLAN Subsystem ........................................................................................................ 13
6.1
MAC ................................................................................................................................................. 13
6.1.1
Features ................................................................................................................................... 13
6.1.2
Description ................................................................................................................................ 13
6.2
PHY ................................................................................................................................................. 14
6.2.1
Features ................................................................................................................................... 14
6.2.2
Description ................................................................................................................................ 14
6.3
Radio ................................................................................................................................................. 14
6.3.1
Receiver Performance .............................................................................................................. 14
6.3.2
Transmitter Performance .......................................................................................................... 16
7 Recommended Reflow Profile .................................................................................... 17
8 Module Schematic ....................................................................................................... 18
9 Bill of Materials (BOM)................................................................................................. 20
10 Application Schematic ................................................................................................ 21
11 Design Guidelines ....................................................................................................... 22
12 Reference Documentation and Support ..................................................................... 23
12.1
Reference Documents ........................................................................................................................... 23
12.2
Related Documents ............................................................................................................................... 23
13 Revision History .......................................................................................................... 24
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1 Block Diagram
Figure 1-1. ATSAMW25 Block Diagram
2 Ordering Information and IC Marking
Table 2-1. Ordering Details
Atmel ordering code
Package
ATSAMW25-MR210PB
ATWINC1500 + SAM D21 module. Tray Packing.
ATSAMW25-MR510PA
ATWINC1500 + SAM D21 + ATECC508 module. Tray Packing.
ATSAMW25-XPRO
Xplained board evaluation kit
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3 Pinout and Package Information
3.1
Pin Description
Figure 3-1. Pin Assignment
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Table 3-1. Pin Description
Pin #
Pin description
I/O type
Programmable
pull-up/-down
resistor
1
GND
N/A
2
UART_TxD
ATWINC1500 output
Yes – pull-up
3
UART_RxD
ATWINC1500 input
Yes – pull-up
4
Wi-Fi Chip_En
ATWINC1500 input
No
5
Wi-Fi GPIO_1/RTC
ATWINC1500 I/O
Yes – pull-up
6
Wi-Fi GPIO_3
-
Yes – pull-up
7
VBAT
Power
8
PA16
See SAM D21G datasheet
Yes
9
PA17
See SAM D21G datasheet
Yes
10
GND
Power
11
PA18
See SAM D21G datasheet
Yes
12
PA19
See SAM D21G datasheet
Yes
13
PA20
See SAM D21G datasheet
Yes
14
PA21
See SAM D21G datasheet
Yes
15
PA22
See SAM D21G datasheet
Yes
16
PA23
See SAM D21G datasheet
Yes
17
GND
Power
18
PA24/USB_DM
See SAM D21G datasheet
Yes
19
PA25/USB_DP
See SAM D21G datasheet
Yes
20
GND
Power
21
VCC
Power
22
PB22
See SAM D21G datasheet
Yes
23
PB23
See SAM D21G datasheet
Yes
24
RESET_N
Input see SAM D21G
datasheet
Yes
25
PA30/SWCLK
See SAM D21G datasheet
Yes
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Pin #
Pin description
I/O type
Programmable
pull-up/-down
resistor
26
PA31/SWDIO
See SAM D21G datasheet
Yes
27
PB02
See SAM D21G datasheet
Yes
28
PB03
See SAM D21G datasheet
Yes
29
PA00/GPIO/XIN32
See SAM D21G datasheet
Yes
30
PA01/GPIO/XOUT32
See SAM D21G datasheet
Yes
31
PA02
I/O
Yes
32
GND
Power
Yes
33
PA03
See SAM D21G datasheet
Yes
34
PA04
See SAM D21G datasheet
Yes
35
PA05
See SAM D21G datasheet
Yes
36
PA06
See SAM D21G datasheet
Yes
37
PA07
See SAM D21G datasheet
Yes
38
PA08
See SAM D21G datasheet
Yes
39
PA09
See SAM D21G datasheet
Yes
40
PA10
See SAM D21G datasheet
Yes
41
PA11
See SAM D21G datasheet
Yes
42
GND
Power
43
PB10
See SAM D21G datasheet
Yes
44
PB11
See SAM D21G datasheet
Yes
45
Wi-Fi GPIO_4
ATWINC1500 I/O
Yes – pull-up
46
Wi-Fi GPIO_5
ATWINC1500 I/O
Yes – pull-up
47
Wi-Fi GPIO_6
ATWINC1500 I/O
Yes – pull-up
48
Wi-Fi I2C_SCL
ATWINC1500 I/O
Yes – pull-up
49
Wi-Fi I2C_SDA
ATWINC1500 I/O
Yes – pull-up
50
Wi-Fi Reset_n
ATWINC1500 Input
No
51
GND
Power
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3.2
Package Description
The ATSAMW25-MR210PB package information.
Figure 3-2. SAMW25 MR210PB Package
BOTTOM VIEW
P1
P51
GND
GND GND
GND
GND
GND
GND
GND
SIDE VIEW
TOP VIEW
SHIELD
SOLDER PADS FOOTPRINT - TOP VIEW
P1
SHIELD
NOTE: GND PADS MUST
BE SOLDERED TO
SYSTEM GND.
NOTE: GND PADS MUST BE
SOLDERED TO GND.
ATSAMW25-MR210
Untoleranced
Dimensions
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4 Electrical Specifications
4.1
Absolute Ratings
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are
valid across operating temperature and voltage unless otherwise specified.
Table 4-1. Absolute Maximum Ratings
Parameters
Minimum
Maximum
Unit
VBAT power supply voltage
0
5.0
V
VCC power supply voltage
0
3.63
Pin voltage with respect to GND and VCC
GND-0.3
VCC+0.3
Storage temperature range
-40
+125
°C
Table 4-2. General Operating Ratings
Parameters
Minimum
Typical
Maximum
Unit
VBATT
3.0
3.6
4.3
°C
VCC
2.7
3.30
3.6
Operating temperature range
-40
25
85
Table 4-3. Physical Characteristics
Parameters
Value
Comments
Size
33.863 x 14.882mm
-
Connector pins pitch
See module footprint
-
Table 4-4. I/O Pins Characteristics
Characteristic
Minimum
Typical
Maximum
Unit
Input Low Voltage VIL
-0.30
0.65
V
Input High Voltage VIH
VCC-0.60
VCC+0.30
Output Low Voltage VOL
0.45
Output High Voltage VOH
VCC-0.50
Output Loading
20
pF
Digital Input Load
6
Pull-up Resistor
76K
90K
104K
Ω
I/O pin characteristics for pins 5, 45, 46, and 47 (for all other I/O, see the SAM D21G datasheet).
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4.2
Recommended Operating Conditions
Table 4-5. Recommended Operating Conditions
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
I/O supply voltage
VCC
2.7
3.3
3.6
V
Battery supply voltage
VBATT
3.0
3.6
4.3
Operating temperature
-40
85
ºC
Notes: 1. I/O supply voltage is applied to the following pins: VDDIO_A and VDDIO.
2. Battery supply voltage is applied to following pins: VDD_BATT_PPA, VDD_BATT_PA, and VBATT_BUCK.
4.3
DC Electrical Characteristics
Table 4-6 provides the DC characteristics for the ATSAMW25 digital pads.
Table 4-6. DC Electrical Characteristics
Characteristic
Minimum
Maximum
Unit
Input Low Voltage VIL
-0.30
0.65
V
Input High Voltage VIH
VCC-0.60
VCC+0.30
Output Low Voltage VOL
0.45
Output High Voltage VOH
VCC-0.50
Output Loading
20
pF
Digital Input Load
6
Pad Drive Strength (regular pads1)
8
13.5
mA
Pad Drive Strength (high-drive pads1)
16
27
Note: 1. The following are high-drive pads: I2C_SCL, I2C_SDA; all other pads are regular.
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5 Application and Core Subsystems
5.1
Host Processor
The Atmel | SMART SAM D ARM Cortex-M0+ based microcontroller (MCU) series builds on decades of
innovation and experience in embedded Flash microcontroller technology. It not only sets a new benchmark for
flexibility and ease-of-use but also combines the performance and energy efficiency of an ARM Cortex-M0+
based MCU with an optimized architecture and peripheral set. The Atmel | SMART SAM D gives you a truly
differentiated general-purpose microcontroller that is ideal for many low-power, cost-sensitive industrial, and
consumer applications.
5.1.1
Host MCU Description
A rich set of peripherals, flexibility, and ease-of-use combined with low power consumption make the Atmel
SAM D21 ideal for a wide range of home automation, consumer, metering, and industrial applications.
ARM Cortex-M0+ based MCU running up to 48MHz
256KB embedded Flash and 32KB SRAM
DMA and Event system
Six flexible serial communication modules (SERCOM)
Full-speed USB device and embedded Host
12-bit ADC (SAM D21G: 14 channels); 10-bit DAC
Hardware touch support
5.1.2
Host MCU Key Features
Low power consumption, down to 70µA/MHz
Enhanced Analog Performance
–
ADC with offset and gain correction
–
Averaging, oversampling, and decimation
–
Flexible DAC
–
New low-power internal oscillators
–
±2% accuracy over operating range
Digital Innovations
–
Programmable Event System
–
Enhanced TC for Control Applications
–
Programmable SERCOM module
–
I2C / SPI / USART / LIN2 / IrDA
–
Full Speed USB Device and Host
–
No external components needed
–
6-12 channel DMA with CRC module
–
PTC Hardware touch module
–
I2S module with PDM support
5.2
Wi-Fi Core Processor
ATWINC1500B has a Cortus APS3 32-bit processor. This processor performs many of the MAC functions,
including but not limited to association, authentication, power management, security key management, and
MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various modes of
operation, such as STA and AP modes.
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5.2.1
Memory Subsystem
The APS3 core uses a 128KB instruction/boot ROM along with a 128KB instruction RAM and a 64KB data
RAM. ATWINC1500B also has 8Mb of flash memory, which can be used for system software. In addition, the
device uses a 128KB shared RAM, accessible by the processor and MAC, which allows the APS3 core to
perform various data management tasks on the TX and RX data packets.
5.2.2
Non-volatile Memory (eFuse)
ATWINC1500B has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset.
This non-volatile one-time-programmable (OTP) memory can be used to store customer-specific parameters,
such as MAC address; various calibration information, such as TX power, crystal frequency offset, etc.; and
other software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks. Each bank
has the same bit map, which is shown in Figure 5-1. The purpose of the first 80 bits in each bank is fixed, and
the remaining 48 bits are general-purpose software dependent bits, or reserved for future use. Since each
bank can be programmed independently, this allows for several updates of the device parameters following the
initial programming, e.g. updating MAC address. Refer to ATWINC1500B Programming Guide for the eFuse
programming instructions.
Figure 5-1. eFuse Bit Map
Used
Invalid
Reserved
MAC ADDR
Used
Used
TX Gain
Correcti
on
Used
Freq.
Offset
F MAC Addr G FO
Version
1141
1115
7
16
8
48
8
Flags
3
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
128 Bits
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6 WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). The
following two subsections describe the MAC and PHY in detail.
6.1
MAC
6.1.1
Features
The ATWINC1500B IEEE802.11 MAC supports the following functions:
IEEE 802.11b/g/n
IEEE 802.11e WMM® QoS EDCA/PCF multiple access categories traffic scheduling
Advanced IEEE 802.11n features:
–
Transmission and reception of aggregated MPDUs (A-MPDU)
–
Transmission and reception of aggregated MSDUs (A-MSDU)
–
Immediate Block Acknowledgement
–
Reduced Interframe Spacing (RIFS)
Support for IEEE802.11i and WFA security with key management
–
WEP 64/128
–
WPA-TKIP
–
128-bit WPA2 CCMP (AES)
Support for WAPI security
Advanced power management
–
Standard 802.11 Power Save Mode
–
Wi-Fi Alliance WMM-PS (U-APSD)
RTS-CTS and CTS-self support
Supports either STA or AP mode in the infrastructure basic service set mode
Supports independent basic service set (IBSS)
6.1.2
Description
The ATWINC1500B MAC is designed to operate at low power while providing high data throughput. The IEEE
802.11
MAC functions are implemented with a combination of dedicated data path engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a
programmable processor provides optimal power efficiency and real-time response while providing the
flexibility to accommodate evolving standards and future feature enhancements. Dedicated data path engines
are used to implement data path functions with heavy computational. For example, an FCS engine checks the
CRC of the transmitting and receiving packets, and a cipher engine performs all the required encryption and
decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI security requirements. Control
functions, which have real-time requirements, are implemented using hardwired control logic modules. These
logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX
control, inter-frame spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module, aggregation/de-
aggregation module, block ACK controller (implements the protocol requirements for burst block
communication), and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher
engine, and the DMA interface to the TX/RX FIFOs).ø
The MAC functions implemented solely in software on the microprocessor have the following characteristics:
Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing.
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Functions with low computational load or without critical real-time requirements. Examples are
authentication and association.
Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling.
6.2
PHY
6.2.1
Features
The ATWINC1500B IEEE802.11 PHY supports the following functions:
Single antenna 1x1 stream in 20MHz channels
Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, and 11Mbps
Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, and 54Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0,
14.4, 19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, and 72.2Mbps
IEEE 802.11n mixed mode operation
Per packet TX power control
Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and
frame detection
6.2.2
Description
The ATWINC1500B WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication environment
with impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC
(Viterbi decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier
sensing, and clear channel assessment, as well as the automatic gain control.
6.3
Radio
6.3.1
Receiver Performance
Radio performance under typical conditions: VBAT = 3.3V; VDDIO = 3.3V; Temp.: 25°C @ RF pins
Table 6-1. Receiver Performance
Parameter
Description
Minimum
Typical
Maximum
Unit
Frequency
2,412
2,484
MHz
Sensitivity
802.11b
1Mbps DSS
-98
dBm
2Mbps DSS
-94
dBm
5.5Mbps DSS
-92
dBm
11Mbps DSS
-88
dBm
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Parameter
Description
Minimum
Typical
Maximum
Unit
Sensitivity
802.11g
6Mbps OFDM
-90
dBm
9Mbps OFDM
-89
dBm
12Mbps OFDM
-88
dBm
18Mbps OFDM
-85
dBm
24Mbps OFDM
-83
dBm
36Mbps OFDM
-80
dBm
48Mbps OFDM
-76
dBm
54Mbps OFDM
-74
dBm
Sensitivity
802.11n
(BW=20MHz)
MCS 0
-89
dBm
MCS 1
-87
dBm
MCS 2
-85
dBm
MCS 3
-82
dBm
MCS 4
-77
dBm
MCS 5
-74
dBm
MCS 6
-72
dBm
MCS 7
-70.5
dBm
Maximum Receive
Signal Level
1-11Mbps DSS
0
dBm
6-54Mbps OFDM
0
dBm
MCS 0 – 7
0
dBm
Adjacent Channel
Rejection
1Mbps DSS (30MHz offset)
50
dB
11Mbps DSS (25MHz offset)
43
dB
6Mbps OFDM (25MHz offset)
40
dB
54Mbps OFDM (25MHz offset)
25
dB
MCS 0 – 20MHz BW (25MHz offset)
40
dB
MCS 7 – 20MHz BW (25MHz offset)
20
dB
Cellular Blocker
Immunity
776-794MHz CDMA
-14
dBm
824-849MHz GSM
-10
dBm
880-915MHz GSM
-10
dBm
1710-1785MHz GSM
-15
dBm
1850-1910MHz GSM
-15
dBm
1850-1910MHz WCDMA
-24
dBm
1920-1980MHz WCDMA
-24
dBm
Measured at RF pin assuming 50Ω differential; RF performance guaranteed for temperature range -30 to 85ºC. 1dB
derating in performance at -40ºC.
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6.3.2
Transmitter Performance
Radio performance under typical conditions: VBAT = 3.3V; VDDIO = 3.3V; Temp.: 25°C @ RF pins
Table 6-2. Transmitter Performance
Parameter
Description
Minimum
Typical
Maximum
Unit
Frequency
2,412
2,484
MHz
Output Power1,
ON_Transmit_High_Power Mode
802.11b 1Mbps
18.5
dBm
802.11b 11Mbps
19.5
dBm
802.11g 6Mbps
18.5
dBm
802.11g 54Mbps
16.5
dBm
802.11n MCS 0
17.0
dBm
802.11n MCS 7
14.5
dBm
Output Power1,
ON_Transmit_Low_Power Mode
802.11b 1Mbps
17.0
dBm
802.11b 11Mbps
17.5
dBm
802.11g 6-18Mbps
16.0
dBm
802.11g >18Mbps
N/A
dBm
802.11n MCS 0-3
14.5
dBm
802.11n >MCS 3
N/A
dBm
TX Power Accuracy
±1.52
dB
Carrier Suppression
30.0
dBc
Out of Band Transmit Power
76-108
-125
dBm/Hz
776-794
-125
dBm/Hz
869-960
-125
dBm/Hz
925-960
-125
dBm/Hz
1570-1580
-125
dBm/Hz
1805-1880
-125
dBm/Hz
1930-1990
-125
dBm/Hz
2110-2170
-125
dBm/Hz
Harmonic Output Power
2nd
-41
dBm/MHz
3rd
-41
dBm/MHz
Notes: 1. Measured at 802.11 spec compliant EVM/Spectral Mask.
2. Measured after RF matching network. See reference design.
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7 Recommended Reflow Profile
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8 Module Schematic
The ATSAMW25-MR210PB/MR510PB Module schematic is shown in Figure 8-1.
Figure 8-1. ATSAMW25-MR210PB/MR510 Module Schematic
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ATSAMW25-MR210PB IEEE 802.11 b/g/n SmartConnect Wi-Fi Module [DATASHEET]
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9 Bill of Materials (BOM)
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10 Application Schematic
Figure 10-1. Connections for the ATSAMW25
The basic power supply connections for the ATSAMW25 module are shown in Figure 10-1. The test points
shown (TP1 – TP6) should be added in case Atmel is required to debug the design.
The Wi-Fi chip can use its own internal oscillator for a Real Time Clock (RTC) or it can use an external
32.768KHz clock provided on the RTC pin. Using an external clock derived from a crystal oscillator can be
used as a more accurate sleep timer for the Wi-Fi chip than its own internal oscillator. This in turn can reduce
sleep current. If power consumption during sleep is a priority then a 32.768KHz crystal can be added to the
SAM D21 module as shown in the reference design. The design shown above displays a connection from pin
15 (PA22) to pin 5 (GPIO_1).
GPIO_1 is the input pin for the Wi-Fi’s Real Time Clock. PA22 can be configured to output a 32.768KHz RTC
clock – derived from the 32.768KHz crystal - to be used as the source for the Wi-Fi’s RTC. If cost is a priority
versus power consumption, then the 32.768KHz crystal can be left off of the design and the PA22 – GPIO_1
connection can be deleted.
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11 Design Guidelines
It is critical to follow the recommendations listed below to achieve the best RF performance:
When the module is placed on the motherboard, a provision for the antenna must be made. There
should be nothing under the portion of the module which contains the antenna. This means the antenna
should not be placed directly on top of the motherboard PCB. This can be accomplished by, for example,
placing the module at the edge of the board such that the module edge with the antenna extends beyond
the main board edge by 6.5mm. Alternatively, a cutout in the motherboard can be provided under the
antenna. The cutout should be at least 22 x 6.5mm. Ground vias spaced 2.5mm apart should be placed
all around the perimeter of the cutout. No large components should be placed near the antenna.
Keep away from antenna, as far as possible, large metal objects to avoid electromagnetic field blocking
Do not enclose the antenna within a metal shield
Keep any components which may radiate noise or signals within the 2.4 – 2.5GHz frequency band far
away from the antenna, or better yet, shield those components. Any noise radiated from the main board
in this frequency band will degrade the sensitivity of the module.
The main board should have a solid ground plane. Each ground pin of the module (including each of the
center ground pads) should have a via placed either in the pad or right next to the pad going down to the
ground plane.
Place a 10µF decoupling capacitor from VBAT to ground right next to pin 7. Place another 10µF
capacitor from VCC to ground right next to pin 21.
Contact Atmel for assistance if any other placement is required
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12 Reference Documentation and Support
12.1
Reference Documents
Atmel offers a set of collateral documentation to ease integration and device ramp.
The following list of documents available on Atmel web or integrated into development tools.
Table 12-1. Reference Documents
Title
Content
Datasheet
This document
Design Files
User Guide, Schematic, PCB layout, Gerber, BOM, and System notes on:
RF/Radio Full Test Report, radiation pattern, design guidelines, temperature perfor-
mance, ESD.
Package
How to use package:
Out of the Box starting guide, HW limitations and notes, SW Quick start guidelines.
Platform Getting started
Guide
Best practices and recommendations to design a board with the product, including:
Antenna Design for Wi-Fi (layout recommendations, types of antennas, impedance
matching, using a power amplifier etc.), SPI/UART protocol between Wi-Fi SoC and the
Host MCU.
HW Design Guide
Integration guide with clear description of:
High level Arch, overview on how to write a networking application, list all API, parame-
ters and structures.
Features of the device, SPI/handshake protocol between device and host MCU, with
flow/sequence/state diagram, timing.
SW Design Guide
Explain in details the flow chart and how to use each API to implement all generic use
cases (e.g. start AP, start STA, provisioning, UDP, TCP, http, TLS, p2p, errors manage-
ment, connection/transfer recovery mechanism/state diagram) - usage and sample appli-
cation note.
For a complete listing of development-support tools and documentation, visit http://www.atmel.com/ or contact
the nearest Atmel field representative.
12.2
Related Documents
[1] ATSAM D21 Datasheet:
Web page: http://www.atmel.com/products/microcontrollers/arm/sam-d.aspx?tab=documents.
Document: Atmel SAM D21 Datasheet (.pdf file).
Then select the required device (ATSAMD21E18A) and get the latest datasheet (.pdf file).
[2] ATWINC1500B Datasheet.
[3] ATSAM W25 Network Controller Programming Guide.
[4] ATSAM W25 Starter Kit User Guide.
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13 Revision History
Doc Rev.
Date
Comments
42618B
05/2016
Updated Figure 3-2 with new POD drawing which has PCB footprint and to solder GND
pads.
42618A
11/2015
Initial document release.
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