1/16
XC61G Series
Low Voltage Detectors (VDF= 0.8V～1.5V)
Standard Voltage Detectors (VDF 1.6V～6.0V)
■GENERAL DESCRIPTION
The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-channel open drain output
configurations are available.
■
A
PPLICATIONS
●Microprocessor reset circuitry
●Memory battery back-up circuits
●Power-on reset circuits
●Power failure detection
●System battery life and charge voltage monitors
■TYPICAL PERFORMANCE CHARACTERISTICS
■FEATURES
Highly Accurate : ±2%
Low Power Consumption
: 0.7 μA [ VIN=1.5V ] (TYP.)
Detect Voltage Range : 0.8V ~ 1.5V in 0.1V
increments (Low Voltage)
: 1.6V～6.0V in 0.1V
increments (Standard Voltage)
Operatin g Voltage Range
: 0.7V ~ 6.0V (Low Voltage)
:
0.7V
～
10.0V (Standard Voltage)
Detect Voltage Temperature characteristics
: ±100ppm/℃ (TYP.)
Output Configuration : N-channel open drain or CMOS
CMOS
Package : USP-3
Environmentally Friendly: EU RoHS Compliant, Pb Free
■TYPICAL APPLICATION CIRCUITS
ETR0203_003
2/16
XC61G Series
PIN NUMBER
USP-3 PIN NAME FUNCTION
3 VIN Supply Voltage
1 VSS Ground
2 VOUT Output
DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION
C CMOS output
① Output Configuration
N N-ch open drain output
e.g. 0.8V → ②0, ③8
② ③ Detect Voltage 08 ~ 60
e.g. 1.5V → ②1, ③5
④ Output Delay 0 No delay
⑤ Detect Accuracy 2 Within ± 2%
HR USP-3
⑥⑦-⑧ Packages
Taping Type (*2) HR-G USP-3
■PIN CONFIGURATION
■PIN ASSIGNMENT
■PRODUCT CLASSIFICATION
●Ordering Information
XC61G ①②③④⑤⑥⑦-⑧(*1)
■BLOCK DIAGRAMS
(1) CMOS Output (2) N-ch Open Drain Output
(*1) The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
(*2) The device orientation is fixed in its embossed tape pocket. For reverse orientation, please contact your local Torex sales office o
r
representative. (Standard orientation: ⑥R-⑧, Reverse orientation: ⑥L-⑧)
(BOTTOM VIEW)
VIN VIN
VOUT VSS
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XC61G
Series
PARAMETER SYMBOL RATINGS UNITS
*1 9.0
Input Voltage *2 VIN 12.0 V
*1 50
Output Current *2 IOUT 50 mA
CMOS VSS -0.3 ~ VIN +0.3
N-ch Open Drain Output *1 VSS -0.3 ~ 9.0
Output Voltage
N-ch Open Drain Output *2
VOUT
VSS -0.3 ~ 12.0
V
Power Dissipation
USP-3 Pd 120 mW
Operating Temperature Range Topr -40～+85 ℃
Storage Temperature Range Tstg -40～+125 ℃
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX.
UNITS
CIRCUITS
Detect Voltage VDF VDF
x 0.98 VDF VDF
x 1.02 V 1
Hysteresis Range VHYS VDF
x 0.02
VDF
x 0.05
VDF
x 0.08 V 1
VIN = 1.5V - 0.7 2.3
VIN = 2.0V - 0.8 2.7
VIN = 3.0V - 0.9 3.0
VIN = 4.0V - 1.0 3.2
Supply Current ISS
V
IN = 5.0V - 1.1 3.6
μA 2
VDF(T) = 0.9V to 1.5V 0.7 - 6.0
Operating Voltage VIN VDF(T) = 1.6V to 6.0V 0.7 - 10.0 V 1
VIN =0.7V 0.10 0.80 -
N-ch, VDS = 0.5V VIN =1.0V 0.85 2.70 - 3
Output Current
(Low Voltage)
CMOS, P-ch, V
DS
=2.1V
VIN =6.0V - -7.5 -1.5 4
VIN =1.0V 1.0 2.2 -
VIN =2.0V 3.0 7.7 -
VIN =3.0V 5. 0 10.1 -
VIN =4.0V 6.0 11.5 -
N-ch, VDS = 0.5V
VIN =5.0V 7.0 13.0 -
3
Output Current
(Standard Voltage)
IOUT
CMOS,
P-ch, VDS=2.1V VIN =8.0V - -10.0 -2.0
mA
4
Temperature
Characteristics
ΔVDF
Δ
Topr
･
V
DF
-40℃ ≦ Topr ≦ 85℃ - ±100 - ppm/
℃ -
Delay Time
(VDR → VOUT inversion) tDLY - - 0.2 ms 5
■
A
BSOLUTE MAXIMUM RATINGS
Ta = 25℃
■ELECTRICAL CHARACTERISTICS
VDF (T) = 0.9 to 1.5V ± 2%
NOTE:
VDF (T): Setting detect voltage
Release Voltage: VDR = VDF + VHYS
Ta=25 ℃
4/16
XC61G Series
■OPERATIONAL EXPLANATION
●CMOS output
① When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN.
(A condition of high impedance exists with N-ch open drain output configurations.)
② When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage
(VSS) level.
③ When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become
unstable. In this condition, VIN will equal the pulled-up output (should output be pulled-up.)
④ When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the
minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS)
level will be maintained.
⑤ When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥ The difference between VDR and VDF represents the hysteresis range.
●Timing Chart
5/16
XC61G
Series
■NOTES ON USE
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent
damage to the device.
2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur
as a result of voltage drops at RIN if load current (IOUT) exists. (refer to the Oscillation Description (1) below)
3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of through current at the time of voltage release even if load
current (IOUT) does not exist. (refer to the Oscillation Description (2) below )
4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's
supply current flowing through the VIN pin.
5. In order to stabilize the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than
severalμs / V.
6. Please use N-ch open drains configuration, when a resistor RIN is connected between the VIN pin and power source.
In such cases, please ensure that RIN is less than 10kΩ and that C is more than 0.1μF.
●Oscillation Description
(1) Output current oscillation with the CMOS output configuration
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load
current (IOUT) will flow at RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the
input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the
voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will
commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the
voltage level at the VIN pin will rise and release operations will begin over again.
Oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current
Since the XC61G series are CMOS IC S, through current will flow when the IC's internal circuit switching operates (during
release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through
current's resistor (RIN) during release voltage operations. (refer to Figure 3 )
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
6/16
XC61G Series
■TEST CIRCUITS
7/16
XC61G
Series
■TYPICAL PERFORMANCE CHARACTERISTICS
●Low Voltage
8/16
XC61G Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
●Low Voltage (Continued)
9/16
XC61G
Series
●Standard Voltage
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
10/16
XC61G Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
●Standard Voltage (Continued)
11/16
XC61G
Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(
Continued
)
●Standard Voltage (Continued)
12/16
XC61G Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(
Continued
)
●Standard Voltage (Continued)
13/16
XC61G
Series
■PACKAGING INFORMATION
●USP-3
14/16
XC61G Series
■PACKAGING INFORMATION (Continued)
●USP-3
Reference metal mask design
Reference Pattern Layout Dimension
15/16
XC61G
Series
MARK CONFIGURATION VOLTAGE (V)
A CMOS 0.x
B CMOS 1.x
C CMOS 2.x
D CMOS 3.x
E CMOS 4.x
F CMOS 5.x
G CMOS 6.x
N-channel Open Drain Output (XC61GN series)
MARK CONFIGURATION VOLTAGE (V)
K N-ch 0.x
L N-ch 1.x
M N-ch 2.x
N N-ch 3.x
P N-ch 5.x
R N-ch 6.x
S N-ch 7.x
MARK VOLTAGE (V) MARK VOLTAGE (V)
0 x.0 5 x.5
1 x.1 6 x.6
2 x.2 7 x.7
3 x.3 8 x.8
4 x.4 9 x.9
MARK
3
■MARKING RULE
●USP-3 ① represents integer of output voltage and detect voltage
CMOS Output (XC61GC series)
② represents decimal number of detect voltage
③ based on internal standards
④ represents production lot number
0 to 9, A to Z repeated (G, I, J, O, Q, W excluded)
USP-3
（TOP VIEW）
16/16
XC61G Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
