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Si4706-C30

HIGH-PERFORMANCE FM RDS/RBDS RECEIVER

Note: The Si4706-C30 requires a patch for production operation. See section

“11. Additional Reference Resources”

Features

Applications

Description

The high-performance Si4706-C30 FM RDS receiver provides the most advanced

and flexible audio and RDS data processing available for portable devices today.

The 100% CMOS IC integrates the complete FM and data receiver function from

antenna to analog or digital audio and data out in a single 3 x 3 mm 20-pin QFN.

Functional Block Diagram

Worldwide FM band support

(76–108 MHz)

Advanced patented RDS/RBDS

decoding engine

Outstanding RDS sensitivity

Leading RDS synchronization

metrics

Highly reliable RDS decoder

RDS reception with FM mono

broadcast

Received signal quality indicators

On-chip tuned resonance for

embedded antenna support

FM multi-path detection and

mitigation

FM Hi-cut control

Advanced FM stereo-mono blend

Automatic gain control (AGC)

Integrated FM LNA

Image-rejection mixer

Frequency synthesizer with

integrated VCO

Low-IF direct conversion with no

external ceramic filters

2.7 to 5.5 V supply voltage

Programmable reference clock

Stereo audio out

I2S Digital audio out

20-pin 3 x 3 mm QFN package

Pb-free/RoHS compliant

Cellular handsets

Portable media devices

In-car navigation systems

Dedicated data receiver

Personal navigation devices (PND)

GPS-enabled handsets and portable

devices

ADC

Si4706

DSP

DAC

DAC ROUT

LOUT

AFC

DIGITAL INTERFACE

GPO

PGA

RCLK

REG

VDD

2.7–5.5 V

XTAL

OSC

32.768 kHz

0/90

DOUT

DCLK

DFS

VIO

SCLK

SDIO

CONTROL

INTERFACE

SEN

RSSI

RST

RDS

RFGND

LNA

FMI

AGC

Half-wavelength

antenna

LPI

Embedded

antenna

(TYP)

This product, its features, and/or its

architecture is covered by one or

more of the following patents, as well

as other patents, pending and

issued, both foreign and domestic:

7,127,217; 7,272,373; 7,272,375;

7,321,324; 7,355,476; 7,426,376;

7,471,940; 7,339,503; 7,339,504.

Ordering Information:

See page 29.

Pin Assignments

GND

PAD

17181920

6789

GPO2/INT

VIO

DOUT

LOUT

ROUT

GNDRST

LPI

RCLK

SDIO

VDD

FMI

RFGND

GPO3/DCLK

GPO1

DFS

SCLK

SEN

Si4706-GM

(Top View)

Si4706-C30

2 Rev. 1.0

Si4706-C30

Rev. 1.0 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.2. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.3. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.4. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4.5. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.6. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.7. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.8. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.9. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.10. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.11. Digital Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.12. Embedded Antenna Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.13. RDS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

4.14. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.15. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

4.16. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.17. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.18. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

6. Pin Descriptions: Si4706-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

8.1. Si4706 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

9. Package Outline: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

10. PCB Land Pattern: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Si4706-C30

4 Rev. 1.0

1. Electrical Specifications

Table 1. Recommended Operating Conditions1

Parameter Symbol Test Condition Min Typ Max Unit

Supply Voltage VDD 2.7 — 5.5 V

Interface Supply Voltage2VIO 1.62 — 3.6 V

Power Supply Powerup Rise Time VDDRISE 10 — — µs

Interface Power Supply Powerup

Rise Time

VIORISE 10 — — µs

Ambient Temperature TA–20 25 85 C

Notes:

1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.

Typical values apply at VDD = 3.3 V and 25 C unless otherwise stated. Parameters are tested in production unless

otherwise stated.

2. Operation with VIO < 2.0 V requires a patch. See section “11. Additional Reference Resources”.

Table 2. Absolute Maximum Ratings1,2

Parameter Symbol Value Unit

Supply Voltage VDD –0.5 to 5.8 V

Interface Supply Voltage VIO –0.5 to 3.9 V

Input Current3IIN 10 mA

Input Voltage3VIN –0.3 to (VIO + 0.3) V

Operating Temperature TOP –40 to 95 C

Storage Temperature TSTG –55 to 150 C

RF Input Level40.4 VpK

Notes:

1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation

should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond

recommended operating conditions for extended periods may affect device reliability.

2. The Si4706 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < 2 kV HBM.

Handling and assembly of these devices should only be done at ESD-protected workstations.

3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, and GPO3.

4. At RF input pins FMI and LPI.

Si4706-C30

Rev. 1.0 5

Table 3. DC Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

FM Receiver to Line Output

VDD Supply Current IFM Analog Output Mode — 21.4 24 mA

Supplies and Interface

Interface Supply Current IIO —400600µA

VDD Powerdown Current IDDPD —1020 µA

VIO Powerdown Current IIOPD SCLK, RCLK inactive — 1 10 µA

High Level Input Voltage1VIH 0.7 x VIO —V

IO +0.3 V

Low Level Input Voltage1VIL –0.3 — 0.3 x VIO V

High Level Input Current1IIH VIN =V

IO =3.6V –10 — 10 µA

Low Level Input Current1IIL VIN =0V,

VIO =3.6V

–10 — 10 µA

High Level Output Voltage2VOH IOUT =500µA 0.8xV

IO ——V

Low Level Output Voltage2VOL IOUT = –500 µA — — 0.2 x VIO V

Notes:

1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3.

2. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3.

Si4706-C30

6 Rev. 1.0

Figure 1. Reset Timing Parameters for Busmode Select Method

Table 4. Reset Timing Characteristics1,2,3

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Min Typ Max Unit

RST Pulse Width and GPO1, GPO2/INT Setup to RSTtSRST 100 — — µs

GPO1, GPO2/INT Hold from RSTtHRST 30 — — ns

Important Notes:

1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until

after the first start condition.

3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns

before the rising edge of RST.

4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is high

impedance, then minimum tSRST is 100 µs to provide time for on-chip 1 M devices (active while RST is low) to pull

GPO1 high and GPO2 low.

70%

30%

GPO1 70%

30%

GPO2 70%

30%

tSRST

RST

tHRST

Si4706-C30

Rev. 1.0 7

Table 5. 2-Wire Control Interface Characteristics1,2,3

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fSCL 0 — 400 kHz

SCLK Low Time tLOW 1.3 — — µs

SCLK High Time tHIGH 0.6 — — µs

SCLK Input to SDIO  Setup

(START)

tSU:STA 0.6 — — µs

SCLK Input to SDIO  Hold

(START)

tHD:STA 0.6 — — µs

SDIO Input to SCLK  Setup tSU:DAT 100 — — ns

SDIO Input to SCLK  Hold 4, 5 tHD:DAT 0 — 900 ns

SCLK Input to SDIO  Setup

(STOP)

tSU:STO 0.6 — — µs

STOP to START Time tBUF 1.3 — — µs

SDIO Output Fall Time tf:OUT — 250 ns

SDIO Input, SCLK Rise/Fall Time tf:IN

tr:IN

— 300 ns

SCLK, SDIO Capacitive Loading Cb——50pF

Input Filter Pulse Suppression tSP — — 50 ns

Notes:

1. When VIO = 0 V, SCLK and SDIO are low impedance.

2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is

high) does not occur within 300 ns before the rising edge of RST.

3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high

until after the first start condition.

4. The Si4706 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the minimum tHD:DAT

specification.

5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be

violated as long as all other timing parameters are met.

20 0.1 Cb

1pF

-----------

20 0.1 Cb

1pF

-----------

Si4706-C30

8 Rev. 1.0

Figure 2. 2-Wire Control Interface Read and Write Timing Parameters

Figure 3. 2-Wire Control Interface Read and Write Timing Diagram

SCLK 70%

30%

SDIO 70%

30%

START STARTSTOP

tf:IN

tr:IN

tLOW tHIGH

tHD:STA

tSU:STA tSU:STO

tSP tBUF

tSU:DAT

tr:IN tHD:DAT tf:IN,

tf:OUT

SCLK

SDIO

START STOPADDRESS + R/W ACK DATA ACK DATA ACK

A6-A0,

R/W D7-D0 D7-D0

Si4706-C30

Rev. 1.0 9

Figure 4. 3-Wire Control Interface Write Timing Parameters

Figure 5. 3-Wire Control Interface Read Timing Parameters

Table 6. 3-Wire Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0—2.5MHz

SCLK High Time tHIGH 25 — — ns

SCLK Low Time tLOW 25 — — ns

SDIO Input, SEN to SCLK Setup tS20 — — ns

SDIO Input to SCLK Hold tHSDIO 10 — — ns

SEN Input to SCLK Hold tHSEN 10 — — ns

SCLK to SDIO Output Valid tCDV Read 2 — 25 ns

SCLK to SDIO Output High Z tCDZ Read 2 — 25 ns

SCLK, SEN, SDIO, Rise/Fall Time tR, tF— — 10 ns

SCLK 70%

30%

SEN 70%

30%

SDIO A7 A0

70%

30%

tHSDIO tHSEN

A6-A5,

R/W,

A4-A1

Address In Data In

D15 D14-D1 D0

tHIGH tLOW

tRtF

½ Cycle Bus

Turnaround

SCLK 70%

30%

SEN 70%

30%

SDIO

70%

30%

tHSDIO tCDV tCDZ

Address In Data Out

A7 A0

A6-A5,

R/W,

A4-A1

D15 D14-D1 D0

tStHSEN

Si4706-C30

10 Rev. 1.0

Figure 6. SPI Control Interface Write Timing Parameters

Figure 7. SPI Control Interface Read Timing Parameters

Table 7. SPI Control Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

SCLK Frequency fCLK 0—2.5MHz

SCLK High Time tHIGH 25 — — ns

SCLK Low Time tLOW 25 — — ns

SDIO Input, SEN to SCLKSetup tS15 — — ns

SDIO Input to SCLKHold tHSDIO 10 — — ns

SEN Input to SCLKHold tHSEN 5——ns

SCLKto SDIO Output Valid tCDV Read 2 — 25 ns

SCLKto SDIO Output High Z tCDZ Read 2 — 25 ns

SCLK, SEN, SDIO, Rise/Fall time tR

— — 10 ns

Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the

rising edge of RST.

SCLK 70%

30%

SEN 70%

30%

SDIO C7 C0

70%

30%

C6–C1

Control Byte In 8 Data Bytes In

D7 D6–D1 D0

tHSDIO

tHIGH tLOW tHSEN

Bus

Turnaround

SCLK 70%

30%

SEN 70%

30%

SDIO 70%

30%

tHSDIO

Control Byte In

C7 C0C6–C1

tStHSEN

tCDZ

tCDV

16 Data Bytes Out

(SDIO or GPO1)

D7 D6–D1 D0

Si4706-C30

Rev. 1.0 11

Figure 8. Digital Audio Interface Timing Parameters, I2S Mode

Table 8. Digital Audio Interface Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

DCLK Cycle Time tDCT 26 — 1000 ns

DCLK Pulse Width High tDCH 10 — — ns

DCLK Pulse Width Low tDCL 10 — — ns

DFS Set-up Time to DCLK Rising Edge tSU:DFS 5—— ns

DFS Hold Time from DCLK Rising Edge tHD:DFS 5—— ns

DOUT Propagation Delay from DCLK Falling

Edge

tPD:DOUT 0—12ns

DCLK

DFS

tDCT

tPD:OUT

tSU:DFS

tHD:DFS

DOUT

tDCH tDCL

Si4706-C30

12 Rev. 1.0

Table 9. FM Receiver Characteristics1,2

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Input Frequency fRF 76 — 108 MHz

RDS Sensitivity3,4 f=2kHz,

RDS BLER < 5%

— 8 — µV EMF

RDS Synchronization Persistence3,4 f=2kHz

RDSSYNC = 1 10 sec

— 3.8/60 — µV

EMF/RDS

BLER%

RDS Synchronization Stability3,4 f=2kHz

RDSSYNC = 1 10 sec

— 5.9/10 — µV EMF/

RDS

BLER%

RDS Synchronization Time3,4,5 f=2kHz — 40 — ms

RDS PI Lock Time3,4,5,5 f=2kHz — 60 — ms

LNA Input Resistance3345 k

LNA Input Capacitance3456 pF

Input IP33400 and 800 kHz

blockers, AGC disabled

100 105 — dBµV EMF

Image Rejection3—50— dB

AM Suppression3m=0.3 40 50 — dB

Audio Sensitivity4,6,7 (S+N)/N = 26 dB — 2.2 3.5 µV EMF

Audio Sensitivity with 50 

Network3,6,7

(S+N)/N = 26 dB — 1.1 — µV EMF

Adjacent Channel Selectivity ±200 kHz 35 50 — dB

Alternate Channel Selectivity ±400 kHz 60 70 — dB

Blocking Sensitivity3,8,9,10 f = ±400 kHz — 32 — dBµV

f = ±4 MHz — 38 — dBµV

Spurious Response Rejection3In-band 35 — — dB

Audio Output Voltage672 80 90 mVRMS

Notes:

1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test

Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz.

2. To ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”,

“AN344: Si4706/07/4x Programming Guide”, and “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines”.

Silicon Laboratories will evaluate schematics and layouts for qualified customers.

3. Guaranteed by characterization.

4. Half-wavelength FM antenna matching network.

5. VEMF =1 mV.

6. f = 22.5 kHz.

7. BAF = 300 Hz to 15 kHz, A-weighted.

8. FMOD =1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.

9. Blocker Amplitude = 100 dBµV

10. Sensitivity measured at (S+N)/N = 26 dB.

11. f = 75 kHz.

12. At temperature 25 °C.

Si4706-C30

Rev. 1.0 13

Audio Output L/R Imbalance Mono –1 — 1 dB

Audio Frequency Response Low3–3 dB — — 30 Hz

Audio Frequency Response High3–3 dB 15 — — kHz

Audio Stereo Separation5,6 35 40 — dB

Audio Mono S/N5,6,7 55 63 — dB

Audio Stereo S/N5,6,7 —58— dB

Audio THD5,11 —0.10.5 %

De-emphasis Time Constant3FM_DEEMPHASIS = 2 70 75 80 µs

FM_DEEMPHASIS = 1 45 50 54 µs

Audio Output Load Resistance3RL

Single-ended, at

LOUT/ROUT pins 10 — — k

Audio Output Load Capacitance3CL

Single-ended, at

LOUT/ROUT pins ——50 pF

Seek/Tune Time3RCLK tolerance

=100ppm

— — 60 ms/channel

Powerup Time3From powerdown — — 110 ms

RSSI Offset12 Input levels of 8 and

60 dBµV at RF Input

–3 — 3 dB

Table 9. FM Receiver Characteristics1,2 (Continued)

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA= –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Notes:

1. Additional testing information is available in application note, “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test

Procedure.” Volume = maximum for all tests. Tested at RF = 98.1 MHz.

2. To ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”,

“AN344: Si4706/07/4x Programming Guide”, and “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines”.

Silicon Laboratories will evaluate schematics and layouts for qualified customers.

3. Guaranteed by characterization.

4. Half-wavelength FM antenna matching network.

5. VEMF =1 mV.

6. f = 22.5 kHz.

7. BAF = 300 Hz to 15 kHz, A-weighted.

8. FMOD =1kHz, 75µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.

9. Blocker Amplitude = 100 dBµV

10. Sensitivity measured at (S+N)/N = 26 dB.

11. f = 75 kHz.

12. At temperature 25 °C.

Si4706-C30

14 Rev. 1.0

Table 10. Reference Clock and Crystal Characteristics

(VDD = 2.7 to 5.5 V, VIO = 1.62 to 3.6 V, TA = –20 to 85 °C)

Parameter Symbol Test Condition Min Typ Max Unit

Reference Clock

RCLK Supported Frequencies1,2 31.130 32.768 40,000 kHz

RCLK Frequency Tolerance1,3 –100 — 100 ppm

REFCLK_PRESCALE1,2 1 — 4095

REFCLK131.130 32.768 34.406 kHz

Crystal Oscillator

Crystal Oscillator Frequency1— 32.768 — kHz

Crystal Frequency Tolerance1,3 –100 — 100 ppm

Board Capacitance1——3.5pF

Notes:

1. Guaranteed by characterization.

2. The Si4706 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies

between 31.130 kHz and 40 MHz that are not supported. See “AN332: Universal Programming Guide,” Table 6 for

more details.

3. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.

Si4706-C30

Rev. 1.0 15

2. Typical Application Schematic

Notes:

1. Place C1 close to VDD pin.

2. Pins 1 and 20 are no connects, leave floating.

3. To ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic,

Layout and Design Guidelines”. Silicon Laboratories will evaluate schematics and layouts for qualified customers.

4. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna.

5. Place Si4706 as close as possible to antenna jack and keep the FMI and LPI traces as short as possible.

Optional: Digital Audio Output

Si4706

SEN

SCLK

SDIO

RST

RCLK

LOUT

ROUT

VBATTERY

2.7 to 5.5 V

GPO1

GPO2/INT

GPO3/DCLK

VIO

1.62 to 3.6 V

FMI

C2 C3

X1 RCLK

GPO3

Optional: for crystal oscillator option

DOUT

LOUT

ROUT

GND

VDD

GPO1

GPO2/INT

GPO3/DCLK

DFS

FMI

RFGND

LPI

RST

SEN

SCLK

SDIO

RCLK

VIO

DFS

R3 DOUT

LPI

Si4706-C30

16 Rev. 1.0

3. Bill of Materials

Component(s) Value/Description Supplier

C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata

U1 Si4706 FM Radio Receiver Silicon Laboratories

Optional Components

C2, C3 Crystal load capacitors, 22 pF, ±5%, COG

(Optional: for crystal oscillator option)

Venkel

X1 32.768 kHz crystal (Optional: for crystal oscillator option) Epson

R1 Resistor, 2 k(Optional: for digital audio) Venkel

R2 Resistor, 2 k(Optional: for digital audio) Venkel

R3 Resistor, 600 (Optional: for digital audio) Venkel

Si4706-C30

Rev. 1.0 17

4. Functional Description

4.1. Overview

Figure 9. Functional Block Diagram

The Si4706-C30 offers advanced audio processing plus

advanced RDS processing in a very small, 100%

CMOS receiver integrated circuit. The device provides

both analog and digital audio out, and a highly flexible

RDS pre-processor and 100 block RDS buffer. It is an

ideal product for handsets and portable devices seeking

to optimize both sound and data receiver performance.

For sound, the advanced audio processing is

unprecedented in portable devices. For RDS data

applications such as song-tagging, meta-data, traffic

message channel, or other open data applications, the

advanced and patented R(B)DS decoding engine offers

outstanding data synchronization and integrity. The

RDS engine includes demodulation, symbol decoding,

advanced error correction, detailed visibility to block-

error rates (BLER), advanced decoder reliability, and

synchronization status. The Si4706 provides complete,

decoded and error-corrected RDS groups (100 blocks),

up to 25 groups at a time. The Si4706 offers several

modes of operation for various applications which

require more or less visibility to the RDS status and

group data.

*Note: The term “RDS” will be used to mean “RDS/RBDS”

throughout the document.

The Si4706 receiver draws on Silicon Laboratories’

broadcast audio know-how and patent portfolio, using a

digital low intermediate frequency (low-IF) receiver

architecture proven by hundreds of millions of Silicon

Laboratories’ broadcast audio receivers shipped

worldwide.

Silicon Labs has shipped 1/2 billion broadcast audio

receivers worldwide using this architecture. The low-IF

architecture allows the Si4706 to deliver superior

performance while integrating the great majority of

external components required by competing solutions.

The Si4706 digital integration reduces the required

external components of traditional offerings, resulting in

a solution requiring only an external bypass capacitor

and occupying board space of approximately 15 mm2.

The Si4706 is the first FM radio receiver IC to support

embedded antenna technology, allowing the FM

antenna to be integrated into the enclosure or PCB of a

portable device. For portable navigation devices, the

Si4706 embedded antenna feature permits integration

of the FM antenna into the enclosure of the device and

eliminates the need for external antenna cables. Refer

to “AN383: Si47XX Antenna, Schematic, Layout, And

Design Guidelines” for antenna design guidelines.

ADC

Si4706

DSP

DAC

DAC ROUT

LOUT

AFC

DIGITAL INTERFACE

GPO

PGA

RCLK

REG

VDD

2.7–5.5 V

XTAL

OSC

32.768 kHz

0/90

DOUT

DCLK

DFS

VIO

SCLK

SDIO

CONTROL

INTERFACE

SEN

RSSI

RST

RDS

RFGND

LNA

FMI

AGC

Half-wavelength

antenna

LPI

Integrated

antenna

(TYP)

Si4706-C30

18 Rev. 1.0

The Si4706 is feature-rich, providing highly automated

performance with default settings and extensive

programmability and flexibility for customized system

performance.

The Si4706 performs much of the FM demodulation

digitally to achieve high fidelity, optimal performance

versus power consumption, and flexibility of design. The

on-board DSP provides unmatched pilot rejection,

selectivity, and optimum sound quality. The integrated

micro-controller offers both the manufacturer and the

end-user unmatched programmability and flexibility in

the listening experience.

4.2. FM Receiver

The Si4706 FM receiver is based on the proven

Si4700/01/02/03 FM radio receiver.

The part leverages

Silicon Laboratories' proven and patented FM broadcast

radio receiver digital architecture, delivering excellent RF

performance and interference rejection. The proven

digital techniques provide good sensitivity in weak signal

environments while providing superb selectivity and

inter-modulation immunity in strong signal environments.

The part supports the worldwide FM broadcast band (76

to 108 MHz) with channel spacings of 50–200 kHz. The

Low-IF architecture utilizes a single converter stage and

digitizes the signal using a high-resolution analog-to-

digital converter. The audio output can be directed

either to an external headphone amplifier via analog

in/out or to other system ICs through digital audio

interface (I2S).

4.3. Stereo Audio Processing

The output of the FM demodulator is a stereo

multiplexed (MPX) signal. The MPX standard was

developed in 1961, and is used worldwide. Today's

MPX signal format consists of left + right (L+R) audio,

left – right (L–R) audio, a 19 kHz pilot tone, and

RDS/RBDS data as shown in Figure 10 below.

Figure 10. MPX Signal Spectrum

4.3.1. Stereo Decoder

The Si4706's integrated stereo decoder automatically

decodes the MPX signal using DSP techniques. The 0

to 15 kHz (L+R) signal is the mono output of the FM

tuner. Stereo is generated from the (L+R), (L–R), and a

19 kHz pilot tone. The pilot tone is used as a reference

to recover the (L–R) signal. Output left and right

channels are obtained by adding and subtracting the

(L+R) and (L–R) signals respectively.

4.3.2. Stereo-Mono Blending

Adaptive noise suppression is employed to gradually

combine the stereo left and right audio channels to a

mono (L+R) audio signal as the signal quality degrades

to maintain optimum sound fidelity under varying

reception conditions. Three metrics, received signal

strength indicator (RSSI), signal-to-noise ratio (SNR),

and multi-path interference, are monitored

simultaneously in forcing a blend from stereo to mono.

The metric which reflects the minimum signal quality

takes precedence and the signal is blended

appropriately.

All three metrics have programmable stereo/mono

thresholds and attack/release rates detailed in AN344

Revision 0.3: Si4706/07/4x Programming Guide (NDA)

and greater. If a metric falls below its mono threshold,

the signal is blended from stereo to full mono. If all

metrics are above their respective stereo thresholds,

then no action is taken to blend the signal. If a metric

falls between its mono and stereo thresholds, then the

signal is blended to the level proportional to the metric’s

value between its mono and stereo thresholds, with an

associated attack and release rate. Stereo/mono status

can be monitored with the FM_RSQ_STATUS

command.

4.4. Received Signal Qualifiers

A tuned signal's quality can vary with the environmental

conditions, time of day, and position of the antenna

among many other factors. To adequately manage the

audio output and avoid unpleasant audible effects to the

end-user, the Si4706-C30 monitors and provides

indicators of the signal quality, allowing the host

processor to perform additional processing if required

by the customer. The Si4706-C30 monitors and reports

a set of standard industry signal quality metrics

including RSSI, SNR, and multi-path interference on FM

signals. As with other Si4706-C30 features, how these

variables are used to improve audio performance can

be left to the Silicon Labs default on-chip algorithms

(recommended), or they can be customized to modify

the performance of the part.

0575338231915

Frequency (kHz)

Modulation Level

Stereo Audio

Left - Right

RDS/

RBDS

Mono Audio

Left + Right Stereo

Pilot

Si4706-C30

Rev. 1.0 19

4.5. De-emphasis

Pre-emphasis and de-emphasis is a technique used by

FM broadcasters to improve the signal-to-noise ratio of

FM receivers by reducing the effects of high-frequency

interference and noise. When the FM signal is

transmitted, a pre-emphasis filter is applied to

accentuate the high audio frequencies. The Si4706

incorporates a de-emphasis filter which attenuates high

frequencies to restore a flat frequency response. Two

time constants are used in various regions. The de-

emphasis time constant is programmable to 50 or 75 µs

and is set by the FM_DEEMPHASIS property.

4.6. Stereo DAC

High-fidelity stereo digital-to-analog converters (DACs)

drive analog audio signals onto the LOUT and ROUT

pins. The audio output may be muted. Volume is

adjusted digitally with the RX_VOLUME property.

4.7. Soft Mute

The soft mute feature is available to attenuate the audio

outputs and minimize audible noise in very weak signal

conditions. The soft mute feature is triggered by the

SNR metric. The SNR threshold for activating soft mute

is programmable, as are soft mute attenuation levels

and attack and decay rates.

4.8. FM Hi-Cut Control

Hi-cut control is employed on audio outputs with

degradation of the signal due to low SNR and/or multi-

path interference. Two metrics, SNR and multi-path

interference, are monitored concurrently in forcing hi-cut

of the audio outputs. Programmable minimum and

maximum thresholds are available for both metrics. The

transition frequency for hi-cut is also programmable with

up to seven hi-cut filter settings. A single set of attack

and release rates for hi-cut are programmable for both

metrics from a range of 2 ms to 64 s. The level of hi-cut

applied can be monitored with the FM_RSQ_STATUS

command. Hi-cut can be disabled by setting the hi-cut

filter setting to the default audio bandwidth of 15 kHz.

4.9. Tuning

The frequency synthesizer uses Silicon Laboratories’

proven technology, including a completely integrated

VCO. The frequency synthesizer generates the

quadrature local oscillator signal used to downconvert

the RF input to a low intermediate frequency. The VCO

frequency is locked to the reference clock and adjusted

with an automatic frequency control (AFC) servo loop

during reception. The tuning frequency can be directly

programmed using the FM_TUNE_FREQ. The Si4706

supports channel spacing of 50, 100, or 200 kHz in FM

mode.

4.10. Seek

The Si4706 seek functionality is performed completely

on-chip and will search up or down the selected

frequency band for a valid channel. A valid channel is

qualified according to a series of programmable signal

indicators and thresholds. The seek function can be

made to stop at the band edge and provide an interrupt,

or wrap the band and continue seeking until arriving at

the original departure frequency. The device sets

interrupts with found valid stations or, if the seek results

in zero found valid stations, the device indicates failure

and again sets an interrupt.(Refer to “AN332: Si47xx

Programming Guide” and “AN344: Si4706/07/4x

Programming Guide”).

The Si4706-C30 uses RSSI, SNR, and AFC to qualify

stations. Most of these variables have programmable

thresholds to tailor the seek function to the subjective

tastes of customers.

RSSI is employed first to screen all possible candidate

stations. SNR and AFC are subsequently used in

screening the RSSI qualified stations. The more

thresholds the system engages, the higher the

confidence that any found stations will indeed be valid

broadcast stations; however, the more challenging

levels the thresholds are set to, the longer the overall

seek time as more stations and more qualifiers will be

assessed. The Si4706-C30 defaults set RSSI to a mid-

level threshold and add an SNR threshold set to a level

delivering acceptable audio performance. This trade-off

will eliminate very low RSSI stations whilst keeping the

seek time to acceptable levels. Generally, the time to

auto-scan and store valid channels for an entire FM

band with all thresholds engaged is very short

depending on the band content.

Seek is initiated using the FM_SEEK_START or

AM_SEEK_START commands. The RSSI and SNR

threshold settings are adjustable using properties.

4.11. Digital Audio Interface

The digital audio interface operates in slave mode and

supports a variety of MSB-first audio data formats

including I2S and left-justified modes. The interface has

three pins: digital data input (DIN), digital frame

synchronization input (DFS), and a digital bit

synchronization input clock (DCLK). The Si4706

supports a number of industry-standard sampling rates

including 32, 40, 44.1, and 48 kHz. The digital audio

interface enables low-power operation by eliminating

the need for redundant DACs and ADCs on the audio

baseband processor.

Si4706-C30

20 Rev. 1.0

4.11.1. Audio Data Formats

The digital audio interface operates in slave mode and

supports three different audio data formats:

I2S

Left-Justified

DSP Mode

In I2S mode, by default the MSB is captured on the

second rising edge of DCLK following each DFS

transition. The remaining bits of the word are sent in

order, down to the LSB. The left channel is transferred

first when the DFS is low, and the right channel is

transferred when the DFS is high.

In Left-Justified mode, by default the MSB is captured

on the first rising edge of DCLK following each DFS

transition. The remaining bits of the word are sent in

order, down to the LSB. The left channel is transferred

first when the DFS is high, and the right channel is

transferred when the DFS is low.

In DSP mode, the DFS becomes a pulse with a width of

1DCLK period. The left channel is transferred first,

followed right away by the right channel. There are two

options in transferring the digital audio data in DSP

mode: the MSB of the left channel can be transferred on

the first rising edge of DCLK following the DFS pulse or

on the second rising edge.

In all audio formats, depending on the word size, DCLK

frequency, and sample rates, there may be unused

DCLK cycles after the LSB of each word before the next

DFS transition and MSB of the next word. In addition, if

preferred, the user can configure the MSB to be

captured on the falling edge of DCLK via properties.

The number of audio bits can be configured for 8, 16,

20, or 24 bits.

4.11.2. Audio Sample Rates

The device supports a number of industry-standard

sampling rates including 32, 40, 44.1, and 48 kHz. The

digital audio interface enables low-power operation by

eliminating the need for redundant DACs on the audio

baseband processor.

Si4706-C30

Rev. 1.0 21

Figure 11. I2S Digital Audio Format

Figure 12. Left-Justified Digital Audio Format

Figure 13. DSP Digital Audio Format

LEFT CHANNEL RIGHT CHANNEL

1 DCLK 1 DCLK

132nn-1

n-2 132n

n-1n-2

LSBMSB

DCLK

DOUT

DFS

INVERTED

DCLK

(OFALL = 1)

(OFALL = 0)

I2S

(OMODE = 0000)

LEFT CHANNEL RIGHT CHANNEL

132nn-1n-2 132nn-1

n-2

LSBMSB

DCLK

DOUT

DFS

INVERTED

DCLK

(OFALL = 1)

(OFALL = 0)

Left-Justified

(OMODE = 0110)

132nn-1n-2 nn-1n-2

LSBMSB

DCLK

DOUT

(MSB at 1st rising edge)

DFS

132

LEFT CHANNEL RIGHT CHANNEL

1 DCLK

(OFALL = 0)

(OMODE = 1100)

132nn-1n-2 nn-1n-2

LSBMSB

132

LEFT CHANNEL RIGHT CHANNEL

DOUT

(MSB at 2nd rising edge)

(OMODE = 1000)

Si4706-C30

22 Rev. 1.0

4.12. Embedded Antenna Support

The Si4706 is the first FM receiver to support the fast

growing trend to integrate the FM receiver antenna into

the device enclosure. The chip is designed with this

function in mind from the outset, with multiple

international patents pending, thus it is superior to many

other options in price, board space, and performance.

Testing indicates that using Silicon Laboratories'

patented techniques, FM performance using an

embedded antenna can be very similar in many key

metrics to performance using standard half-wavelength

FM antennas. Refer to “AN383: Si47XX Antenna,

Schematic, Layout, And Design Guidelines” for

additional details on the implementation of support for

an embedded antenna.

Figure 14 shows a conceptual block diagram of the

Si4706 architecture used to support the embedded

antenna. The half-wavelength FM receive antenna is

therefore optional. Host software can detect the

presence of an external antenna and switch between

the embedded antenna if desired.

Figure 14. Conceptual Block Diagram of the

Si4706 Embedded Antenna Support

4.13. RDS Decoder

The Si4706 implements an advanced, patented, high-

performance RDS processor for demodulation, symbol

decoding, block synchronization, error detection, and

error correction. The RDS decoder provides several

significant benefits over traditional implementations,

including very fast and robust RDS synchronization in

noisy signal levels with very high block error rates

(BLER), industry-leading sensitivity, and improved data

reliability in all signal environments.

Figure 15 illustrates the benefit of robust

synchronization. The Si4706's strong synchronization

performance at noisy signal levels minimizes or even

eliminates re-synchronization time required as the

signal carrier-to-noise ratio (CNR) fluctuates. The

Si4706 decoder is continuously synchronized to the

RDS block/group despite loss of data due to data block

errors. This translates to lower loss of data compared to

competing solutions.

Figure 16 illustrates the Si4706 RDS decoder

performance. With the aid of robust synchronization, the

decoder additionally provides for operation at lower

sensitivity levels for a given BLER compared to

competing solutions, and delivers reception in

environments where signal power is very low or

compromised. The decoder failure probability drops

significantly compared to competing solutions.

The Si4706 also provides unmatched flexibility in

programming the interaction between the host

processor and the device. The Si4706 can be

configured to provide varying levels of visibility from

very high visibility to each RDS block with

corresponding BLER, to a lower level of granularity

providing complete RDS groups with BLER by block.

Additionally, the Si4706 can provide interrupts on

changes to RDS block A and/or B. The Si4706 device

provides a configurable interrupt when RDS is

synchronized and RDS group data has been received.

The device provides configurable interrupts for up to

100 blocks with detailed BLER (25 groups), providing

flexibility in interrupt configuration to the host controller.

The Si4706 reports RDS decoder synchronization

status and detailed bit errors for each RDS block with

the FM_RDS_STATUS command. The range of

reportable bit errors that are detected and corrected are

0, 1-2, 3-5, and "not correctable." More than five bit

errors indicates that the corresponding block

information word is not correctable.

Si4706

RFGND

LNA

FMI

AGC

Half-wavelength

antenna

LPI

Integrated

antenna

Si4706-C30

Rev. 1.0 23

Figure 15. Illustrative Si4706 Advanced RDS Synchronization

Figure 16. Si4706 Preliminary Decoder Performance

time

CNR

Level at which typical RDS decoder returns

block error and declares sync loss.

Re-synchronization time in

typical RDS decoder using

hard decision techniques.

Si4706 RDS advanced decoder

with persistent synchronization

delivers data during “dead time.”

Level at which Si4706 advanced

RDS decoder declares sync loss.

Decoder Failure Probability

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

0123456

Eb/N0

Probability

RDS Standard Limits

Si4706 RDS Decoder

Si4706-C30

24 Rev. 1.0

4.14. Reference Clock

The Si4706 reference clock is programmable,

supporting RCLK frequencies in Table 10. Refer to

Table 3, “DC Characteristics” on page 5 for switching

voltage levels and Table 10, “Reference Clock and

Crystal Characteristics” on page 14 for frequency

tolerance information.

An onboard crystal oscillator is available to generate the

32.768 kHz reference when an external crystal and load

capacitors are provided. Refer to "2. Typical Application

Schematic" on page 15. This mode is enabled using the

POWER_UP command. Refer to Refer to “AN332:

Si47xx Programming Guide” and “AN344: Si4706/07/4x

Programming Guide.”

The Si4706 performance may be affected by data

activity on the SDIO bus when using the integrated

internal oscillator. SDIO activity results from polling the

tuner for status or communicating with other devices

that share the SDIO bus. If there is SDIO bus activity

while the Si4706 is performing the seek/tune function,

the crystal oscillator may experience jitter, which may

result in mistunes, false stops, and/or lower SNR.

For best seek/tune results, Silicon Laboratories

recommends that all SDIO data traffic be suspended

during Si4706 seek and tune operations. This is

achieved by keeping the bus quiet for all other devices

on the bus, and delaying tuner polling until the tune or

seek operation is complete. The seek/tune complete

(STC) interrupt should be used instead of polling to

determine when a seek/tune operation is complete.

4.15. Control Interface

A serial port slave interface is provided, which allows an

external controller to send commands to the Si4706 and

receive responses from the device. The serial port can

operate in three bus modes: 2-wire mode, 3-wire mode,

or SPI mode. The Si4706 selects the bus mode by

sampling the state of the GPO1 and GPO2 pins on the

rising edge of RST. The GPO1 pin includes an internal

pull-up resistor, which is connected while RST is low,

and the GPO2 pin includes an internal pull-down

resistor, which is connected while RST is low.

Therefore, it is only necessary for the user to actively

drive pins which differ from these states. See Table 11.

After the rising edge of RST, the pins GPO1 and GPO2

are used as general purpose output (O) pins as

described in Section “4.16. GPO Outputs”. In any bus

mode, commands may only be sent after VIO and VDD

supplies are applied.

In any bus mode, before sending a command or reading

a response, the user must first read the status byte to

ensure that the device is ready (CTS bit is high).

Table 11. Bus Mode Select on Rising Edge of

RST

Bus Mode GPO1 GPO2

2-Wire 1 0

SPI 1 1 (must drive)

3-Wire 0 (must drive) 0

Si4706-C30

Rev. 1.0 25

4.15.1. 2-Wire Control Interface Mode

When selecting 2-wire mode, the user must ensure that

SCLK is high during the rising edge of RST, and stays

high until after the first start condition. Also, a start

condition must not occur within 300 ns before the rising

edge of RST.

The 2-wire bus mode uses only the SCLK and SDIO

pins for signaling. A transaction begins with the START

condition, which occurs when SDIO falls while SCLK is

high. Next, the user drives an 8-bit control word serially

on SDIO, which is captured by the device on rising

edges of SCLK. The control word consists of a 7-bit

device address, followed by a read/write bit (read = 1,

write = 0). The Si4706 acknowledges the control word

by driving SDIO low on the next falling edge of SCLK.

Although the Si4706 will respond to only a single device

address, this address can be changed with the SEN pin

(note that the SEN pin is not used for signaling in 2-wire

mode). When SEN = 0, the 7-bit device address is

0010001b. When SEN = 1, the address is 1100011b.

For write operations, the user then sends an 8-bit data

byte on SDIO, which is captured by the device on rising

edges of SCLK. The Si4706 acknowledges each data

byte by driving SDIO low for one cycle, on the next

falling edge of SCLK. The user may write up to 8 data

bytes in a single 2-wire transaction. The first byte is a

command, and the next seven bytes are arguments.

For read operations, after the Si4706 has

acknowledged the control byte, it will drive an 8-bit data

byte on SDIO, changing the state of SDIO on the falling

edge of SCLK. The user acknowledges each data byte

by driving SDIO low for one cycle, on the next falling

edge of SCLK. If a data byte is not acknowledged, the

transaction will end. The user may read up to 16 data

bytes in a single 2-wire transaction. These bytes contain

the response data from the Si4706.

A 2-wire transaction ends with the STOP condition,

which occurs when SDIO rises while SCLK is high. For

details on timing specifications and diagrams, refer to

Table 5, “2-Wire Control Interface Characteristics” on

page 7; Figure 2, “2-Wire Control Interface Read and

Write Timing Parameters,” on page 8, and Figure 3, “2-

Wire Control Interface Read and Write Timing Diagram,”

on page 8.

4.15.2. 3-Wire Control Interface Mode

When selecting 3-wire mode, the user must ensure that

a rising edge of SCLK does not occur within 300 ns

before the rising edge of RST

The 3-wire bus mode uses the SCLK, SDIO, and SEN_

pins. A transaction begins when the user drives SEN

low. Next, the user drives a 9-bit control word on SDIO,

which is captured by the device on rising edges of

SCLK. The control word consists of a 3-bit device

address (A7:A5 = 101b), a read/write bit (read = 1, write

= 0), and a 5-bit register address (A4:A0).

For write operations, the control word is followed by a

16-bit data word, which is captured by the device on

rising edges of SCLK.

For read operations, the control word is followed by a

delay of one-half SCLK cycle for bus turn-around. Next,

the Si4706 will drive the 16-bit read data word serially

on SDIO, changing the state of SDIO on each rising

edge of SCLK.

A transaction ends when the user sets SEN high, then

pulses SCLK high and low one final time. SCLK may

either stop or continue to toggle while SEN is high.

In 3-wire mode, commands are sent by first writing each

argument to register(s) 0xA1–0xA3, then writing the

command word to register 0xA0. A response is

retrieved by reading registers 0xA8–0xAF.

For details on timing specifications and diagrams, refer

to Table 6, “3-Wire Control Interface Characteristics” on

page 9; Figure 4, “3-Wire Control Interface Write Timing

Parameters,” on page 9, and Figure 5, “3-Wire Control

Interface Read Timing Parameters,” on page 9.

Si4706-C30

26 Rev. 1.0

4.15.3. SPI Control Interface Mode

When selecting SPI mode, the user must ensure that a

rising edge of SCLK does not occur within 300 ns

before the rising edge of RST.

SPI bus mode uses the SCLK, SDIO, and SEN pins for

read/write operations. The system controller can

choose to receive read data from the device on either

SDIO or GPO1. A transaction begins when the system

controller drives SEN = 0. The system controller then

pulses SCLK eight times, while driving an 8-bit control

byte serially on SDIO. The device captures the data on

rising edges of SCLK. The control byte must have one

of five values:

0x48 = write a command (controller drives 8

additional bytes on SDIO).

0x80 = read a response (device drives one

additional byte on SDIO).

0xC0 = read a response (device drives 16 additional

bytes on SDIO).

0xA0 = read a response (device drives one

additional byte on GPO1).

0xE0 = read a response (device drives 16 additional

bytes on GPO1).

For write operations, the system controller must drive

exactly eight data bytes (a command and seven

arguments) on SDIO after the control byte. The data is

captured by the device on the rising edge of SCLK.

For read operations, the controller must read exactly 1

byte (STATUS) after the control byte or exactly 16 data

bytes (STATUS and RESP1–RESP15) after the control

byte. The device changes the state of SDIO (or GPO1, if

specified) on the falling edge of SCLK. Data must be

captured by the system controller on the rising edge of

SCLK.

Keep SEN low until all bytes have transferred. A

transaction may be aborted at any time by setting SEN

high and toggling SCLK high and then low. Commands

will be ignored by the device if the transaction is

aborted.

For details on timing specifications and diagrams, refer

to Figure 6 and Figure 7 on page 10.

4.16. GPO Outputs

The Si4706 provides three general-purpose output pins.

The GPO pins can be configured to output a constant

low, constant high, or high-Z. The GPO pins are

multiplexed with the bus mode pins or DCLK,

depending on the application schematic of the device.

GPO2/INT can be configured to provide interrupts for

seek and tune complete, receive signal quality, and

RDS.

4.17. Reset, Powerup, and Powerdown

Setting the RST pin low will disable analog and digital

circuitry, reset the registers to their default settings, and

disable the bus. Setting the RST pin high will bring the

device out of reset. A powerdown mode is available to

reduce power consumption when the part is idle. Putting

the device in powerdown mode will disable analog and

digital circuitry while keeping the bus active.

4.18. Programming with Commands

To ease development time and offer maximum

customization, the Si4706 provides a simple yet

powerful software interface to program the receiver. The

device is programmed using commands, arguments,

properties, and responses. To perform an action, the

user writes a command byte and associated arguments,

causing the chip to execute the given command.

Commands control an action such as powerup the

device, shut down the device, or tune to a station.

Arguments are specific to a given command and are

used to modify the command. A complete list of

commands is available in “AN332: Si47xx Programming

Guide” and “AN344: Si4706/07/4x Programming

Guide.”

Properties are a special command argument used to

modify the default chip operation and are generally

configured immediately after powerup. Examples of

properties are de-emphasis level, RSSI seek threshold,

and soft mute attenuation threshold. Responses provide

the user information and are echoed after a command

and associated arguments are issued. All commands

provide a one-byte status update indicating interrupt

and clear-to-send status information. For a detailed

description of the commands and properties for the

Si4706, see “AN332: Si47xx Programming Guide” and

“AN344: Si4706/07/4x Programming Guide.”

Si4706-C30

Rev. 1.0 27

5. Commands and Properties

Refer to “AN332: Si47xx Programming Guide” and “AN344: Si4706/07/4x Programming Guide.”

Si4706-C30

28 Rev. 1.0

6. Pin Descriptions: Si4706-GM

Pin Number(s) Name Description

1, 20 NC No connect. Leave floating.

2 FMI FM RF input.

3 RFGND RF ground. Connect to ground plane on PCB.

4 LPI Loop antenna RF input.

5RST

Device reset input (active low).

6 SEN Serial enable input (active low).

7 SCLK Serial clock input.

8 SDIO Serial data input/output.

9 RCLK External reference or crystal oscillator input.

10 VIO I/O supply voltage.

11 VDD Supply voltage. May be connected directly to battery.

13 ROUT Right audio analog line output.

14 LOUT Left audio analog line output.

15 DOUT Digital audio output data.

16 DFS Digital frame synchronization.

17 GPO3/DCLK General purpose output/digital bit synchronous clock or crystal oscillator

input.

18 GPO2/INT General purpose output/interrupt.

19 GPO1 General purpose output.

12, GND PAD GND Ground. Connect to ground plane on PCB.

GND

PAD

17181920

67 8 9

GPO2/INT

VIO

DOUT

LOUT

ROUT

GNDRST

LPI

RCLK

SDIO

VDD

FMI

RFGND

GPO3/DCLK

GPO1

DFS

SCLK

SEN

Si4706-C30

Rev. 1.0 29

7. Ordering Guide

Part Number* Description Package

Type

Operating

Temperature

Si4706-C30-GM FM RDS Broadcast Radio Receiver QFN

Pb-free

–20 to 85 °C

*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.

Si4706-C30

30 Rev. 1.0

8. Package Markings

8.1. Si4706 Top Mark

Figure 17. Si4706 Top Mark

8.2. Top Mark Explanation

Mark Method: YAG Laser

Line 1 Marking: Part Number 06 = Si4706

Firmware Revision 30 = Firmware Revision 30

Line 2 Marking: R = Die Revision C = Revision C Die

TTT = Internal Code Internal tracking code.

Line 3 Marking: Circle = 0.5 mm Diameter

(Bottom-Left Justified)

Pin 1 Identifier.

Y = Year

WW = Workweek

Assigned by the Assembly House. Corresponds to the last

significant digit of the year and workweek of the mold date.

0630

CTTT

YWW

Si4706-C30

Rev. 1.0 31

9. Package Outline: Si4706 QFN

Figure 18 illustrates the package details for the Si4706. Table 12 lists the values for the dimensions shown in the

illustration.

Figure 18. 20-pin Quad Flat No-Lead (QFN)

Table 12. Package Dimensions

Symbol Millimeters Symbol Millimeters

Min Nom Max Min Nom Max

A 0.50 0.55 0.60 f 2.53 BSC

A1 0.00 0.02 0.05 L 0.35 0.40 0.45

b 0.180.250.30 L1 0.00 — 0.10

c 0.27 0.32 0.37 aaa — — 0.05

D 3.00 BSC bbb — — 0.05

D2 1.60 1.70 1.80 ccc — — 0.08

e 0.50 BSC ddd — — 0.10

E 3.00 BSC eee — — 0.10

E2 1.60 1.70 1.80

Notes:

1. All dimensions are shown in millimeters unless otherwise noted.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

Si4706-C30

32 Rev. 1.0

10. PCB Land Pattern: Si4706 QFN

Figure 19 illustrates the PCB land pattern details for the Si4706-GM. Table 13 lists the values for the dimensions

shown in the illustration.

Figure 19. PCB Land Pattern

Si4706-C30

Rev. 1.0 33

Table 13. PCB Land Pattern Dimensions

Symbol Millimeters Symbol Millimeters

Min Max Min Max

D 2.71 REF GE 2.10 —

D2 1.60 1.80 W — 0.34

e 0.50 BSC X — 0.28

E 2.71 REF Y 0.61 REF

E2 1.60 1.80 ZE — 3.31

f 2.53 BSC ZD — 3.31

GD 2.10 —

Notes: General

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and tolerancing is per the ANSI Y14.5M-1994 specification.

3. This land pattern design is based on IPC-SM-782 guidelines.

4. All dimensions shown are at maximum material condition (MMC). Least material

condition (LMC) is calculated based on a fabrication allowance of 0.05 mm.

Notes: Solder Mask Design

1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the

solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.

Notes: Stencil Design

1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should

be used to assure good solder paste release.

2. The stencil thickness should be 0.125 mm (5 mils).

3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.

4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides

approximately 70% solder paste coverage on the pad, which is optimum to assure

correct component stand-off.

Notes: Card Assembly

1. A No-Clean, Type-3 solder paste is recommended.

2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification

for small body components.

Si4706-C30

34 Rev. 1.0

11. Additional Reference Resources

Customer Support Site: http://www.silabs.com

This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA

is required for complete access. To request access, register at http://www.silabs.com and send user’s first and

last name and company name to FMinfo@silabs.com.

AN332: Si47xx Programming Guide

AN342: Quick Start Guide

AN344: Si4706/07/4x Programming Guide

AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines

AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure

Si47xx EVB User’s Guide

Low VIO patch: See “AN332: Si47xx Programming Guide”, Section 7.2: Powerup from a Component Patch, for

details about downloading the required patch. Contact Silicon Laboratories for more information.

Si4706-C30

Rev. 1.0 35

NOTES:

Si4706-C30

36 Rev. 1.0

CONTACT INFORMATION

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Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

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Email: FMinfo@silabs.com

Internet: www.silabs.com

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