SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER
DATASHEET
Rev. 1.1
24 April 2003
Track ID: JATR-1076-21
RTL8309SB
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller ii Track ID: JATR-1076-21 Rev. 1.1
COPYRIGHT
©2003 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed,
stored in a retrieval system, or translated into any language in any form or by any means without the written permission of
Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited
to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this
document at any time. This document could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC
design with the RTL8309SB Single-Chip 9-port 10/100Mbps Switch Controller.
Though every effort has been made to assure that this document is current and accurate, more information may have become
available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional
information that may help in the development process.
REVISION HISTORY
Revision Release Date Summary
1.0 2003/04/12 First release.
1.1 2003/05/15 Revised pin descriptions.
Revised description for bi-color LED.
New Bi-color LED Reference Schematic figure.
Add 3.3V items to electrical characteristics.
Add thermal operating range temperatures.
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller iii Track ID: JATR-1076-21 Rev. 1.1
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................3
3. BLOCK DIAGRAM.............................................................................................................................................................4
4. PIN ASSIGNMENTS ...........................................................................................................................................................5
5. PIN DESCRIPTION ............................................................................................................................................................7
5.1. MEDIA CONNECTION PINS ..........................................................................................................................................7
5.2. MII PORT MAC INTERFACE PINS ................................................................................................................................7
5.3. MISCELLANEOUS PINS ................................................................................................................................................9
5.4. PORT LED PINS ..........................................................................................................................................................9
5.5. SERIAL EEPROM AND SMI PINS..............................................................................................................................11
5.6. STRAPPING PINS........................................................................................................................................................12
5.7. POWER PINS..............................................................................................................................................................15
6. EEPROM REGISTER DESCRIPTION ..........................................................................................................................16
6.1. GLOBAL CONTROL REGISTERS..................................................................................................................................16
6.1.1. Global Control Register0 ...................................................................................................................................16
6.1.2. Global Control Register1 ...................................................................................................................................16
6.1.3. Global Control Register2 ...................................................................................................................................17
6.1.4. Global Control Register3 ...................................................................................................................................17
6.1.5. Global Control Register4 ...................................................................................................................................18
6.1.6. Global Control Register5 ...................................................................................................................................18
6.1.7. Global Control Register6 ...................................................................................................................................18
6.1.8. Global Control Register7 ...................................................................................................................................19
6.2. PORT 1~4 CONTROL PINS ..........................................................................................................................................19
6.2.1. Port 0 Control 0..................................................................................................................................................19
6.2.2. Port 0 Control 1..................................................................................................................................................20
6.2.3. Port 0 Control 2..................................................................................................................................................20
6.2.4. Port 0 Control 3..................................................................................................................................................20
6.2.5. Port 0 Control 4..................................................................................................................................................21
6.2.6. IP Address...........................................................................................................................................................21
6.2.7. Port 1 Control 0..................................................................................................................................................22
6.2.8. Port 1 Control 1..................................................................................................................................................22
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller iv Track ID: JATR-1076-21 Rev. 1.1
6.2.9. Port 1 Control 2..................................................................................................................................................23
6.2.10. Port 1 Control 3..................................................................................................................................................23
6.2.11. Port 1 Control 4..................................................................................................................................................24
6.2.12. IP Mask ..............................................................................................................................................................24
6.2.13. Port 2 Control 0..................................................................................................................................................25
6.2.14. Port 2 Control 1..................................................................................................................................................25
6.2.15. Port 2 Control 2..................................................................................................................................................26
6.2.16. Port 2 Control 3..................................................................................................................................................26
6.2.17. Port 2 Control 4..................................................................................................................................................27
6.2.18. Switch MAC Address ..........................................................................................................................................27
6.2.19. Port 3 Control 0..................................................................................................................................................28
6.2.20. Port 3 Control 1..................................................................................................................................................28
6.2.21. Port 3 Control 2..................................................................................................................................................29
6.2.22. Port 3 Control 3..................................................................................................................................................29
6.2.23. Port 3 Control 4..................................................................................................................................................29
6.2.24. ISP MAC Address ...............................................................................................................................................30
6.2.25. Port 4 Control 0..................................................................................................................................................30
6.2.26. Port 4 Control 1..................................................................................................................................................31
6.2.27. Port 4 Control 2..................................................................................................................................................31
6.2.28. Port 4 Control 3..................................................................................................................................................32
6.2.29. Port 4 Control 4..................................................................................................................................................32
6.3. MII PORT CONTROL PINS..........................................................................................................................................33
6.3.1. MII Port Control 0..............................................................................................................................................33
6.3.2. MII Port Control 1..............................................................................................................................................33
6.3.3. MII Port Control 2..............................................................................................................................................34
6.3.4. CPU Port and WAN Port....................................................................................................................................34
6.4. PORT 5~7 CONTROL PINS ..........................................................................................................................................35
6.4.1. Port 5 Control 0..................................................................................................................................................35
6.4.2. Port 5 Control 1..................................................................................................................................................35
6.4.3. Port 5 Control 2..................................................................................................................................................36
6.4.4. Port 5 Control 3..................................................................................................................................................36
6.4.5. Port 5 Control 4..................................................................................................................................................36
6.4.6. Port 6 Control 0..................................................................................................................................................37
6.4.7. Port 6 Control 1..................................................................................................................................................37
6.4.8. Port 6 Control 2..................................................................................................................................................38
6.4.9. Port 6 Control 3..................................................................................................................................................38
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller v Track ID: JATR-1076-21 Rev. 1.1
6.4.10. Port 6 Control 4..................................................................................................................................................38
6.4.11. Port 7 Control 0..................................................................................................................................................39
6.4.12. Port 7 Control 1..................................................................................................................................................39
6.4.13. Port 7 Control 2..................................................................................................................................................40
6.4.14. Port 7 Control 3..................................................................................................................................................40
6.4.15. Port 7 Control 4..................................................................................................................................................40
7. PHY REGISTERS DESCRIPTION .................................................................................................................................41
7.1. PHY 0 REGISTERS.....................................................................................................................................................41
7.1.1. PHY 0 Register 0: Control..................................................................................................................................41
7.1.2. PHY 0 Register 1: Status ....................................................................................................................................42
7.1.3. PHY 0 Register 2: PHY Identifier 1....................................................................................................................43
7.1.4. PHY 0 Register 3: PHY Identifier 2....................................................................................................................43
7.1.5. PHY 0 Register 4: Auto-Negotiation Advertisement...........................................................................................43
7.1.6. PHY 0 Register 5: Auto-Negotiation Link Partner Ability..................................................................................44
7.1.7. PHY 0 Register 6: Auto-Negotiation Expansion.................................................................................................44
7.1.8. PHY 0 Register 16: Global Control 0.................................................................................................................45
7.1.9. PHY 0 Register 17: Global Control 1.................................................................................................................47
7.1.10. PHY 0 Register 18: Global Control 2.................................................................................................................48
7.1.11. PHY 0 Register 19: Global Control 3.................................................................................................................48
7.1.12. PHY 0 Register 22: Port 0 Control 0..................................................................................................................49
7.1.13. PHY 0 Register 23: Port 0 Control 1..................................................................................................................50
7.1.14. PHY 0 Register 24: Port 0 Control 2 &VLAN Entry [A]....................................................................................50
7.1.15. PHY 0 Register 25: VLAN Entry [A] ..................................................................................................................51
7.2. PHY 1 REGISTERS.....................................................................................................................................................51
7.2.1. PHY 1 Register 0: Control..................................................................................................................................51
7.2.2. PHY 1 Register 1: Status ....................................................................................................................................51
7.2.3. PHY 1 Register 2: PHY Identifier 1....................................................................................................................51
7.2.4. PHY 1 Register 3: PHY Identifier 2....................................................................................................................51
7.2.5. PHY 1 Register 4: Auto-Negotiation Advertisement...........................................................................................51
7.2.6. PHY 1 Register 5: Auto-Negotiation Link Partner Ability..................................................................................51
7.2.7. PHY 1 Register 6: Auto-Negotiation Expansion.................................................................................................51
7.2.8. PHY 1 Register 16~17: IP Priority Address [A].................................................................................................52
7.2.9. PHY 1 Register 18~19: IP Priority Address [B].................................................................................................52
7.2.10. PHY 1 Register 22: Port 1 Control 0..................................................................................................................52
7.2.11. PHY 1 Register 23: Port 1 Control 1..................................................................................................................52
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller vi Track ID: JATR-1076-21 Rev. 1.1
7.2.12. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]...................................................................................53
7.2.13. PHY 1 Register 25: VLAN Entry [B] ..................................................................................................................53
7.3. PHY 2 REGISTERS.....................................................................................................................................................53
7.3.1. PHY 2 Register 0: Control..................................................................................................................................53
7.3.2. PHY 2 Register 1: Status ....................................................................................................................................53
7.3.3. PHY 2 Register 2: PHY Identifier 1....................................................................................................................53
7.3.4. PHY 2 Register 3: PHY Identifier 2....................................................................................................................54
7.3.5. PHY 2 Register 4: Auto-Negotiation Advertisement...........................................................................................54
7.3.6. PHY 2 Register 5: Auto-Negotiation Link Partner Ability..................................................................................54
7.3.7. PHY 2 Register 6: Auto-Negotiation Expansion.................................................................................................54
7.3.8. PHY 2 Register 16~17: IP Priority Mask [A] ....................................................................................................54
7.3.9. PHY 2 Register 18~19: IP Priority Mask [B] ....................................................................................................54
7.3.10. PHY 2 Register 22: Port 2 Control 0..................................................................................................................55
7.3.11. PHY 2 Register 23: Port 2 Control 1..................................................................................................................55
7.3.12. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]...................................................................................55
7.3.13. PHY 2 Register 25: VLAN Entry [C]..................................................................................................................55
7.4. PHY 3 REGISTERS.....................................................................................................................................................56
7.4.1. PHY 3 Register 0: Control..................................................................................................................................56
7.4.2. PHY 3 Register 1: Status ....................................................................................................................................56
7.4.3. PHY 3 Register 2: PHY Identifier 1....................................................................................................................56
7.4.4. PHY 3 Register 3: PHY Identifier 2....................................................................................................................56
7.4.5. PHY 3 Register 4: Auto-Negotiation Advertisement...........................................................................................56
7.4.6. PHY 3 Register 5: Auto-Negotiation Link Partner Ability..................................................................................56
7.4.7. PHY 3 Register 6: Auto-Negotiation Expansion.................................................................................................56
7.4.8. PHY 3 Register 16~18: Switch MAC Address ....................................................................................................57
7.4.9. PHY 3 Register 22: Port 3 Control 0..................................................................................................................57
7.4.10. PHY 3 Register 23: Port 3 Control 1..................................................................................................................57
7.4.11. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D] ..................................................................................57
7.4.12. PHY 3 Register 25: VLAN Entry [D]..................................................................................................................58
7.5. PHY 4 REGISTERS.....................................................................................................................................................58
7.5.1. PHY 4 Register 0: Control..................................................................................................................................58
7.5.2. PHY 4 Register 1: Status ....................................................................................................................................58
7.5.3. PHY 4 Register 2: PHY Identifier 1....................................................................................................................58
7.5.4. PHY 4 Register 3: PHY Identifier 2....................................................................................................................58
7.5.5. PHY 4 Register 4: Auto-Negotiation Advertisement...........................................................................................58
7.5.6. PHY 4 Register 5: Auto-Negotiation Link Partner Ability..................................................................................58
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller vii Track ID: JATR-1076-21 Rev. 1.1
7.5.7. PHY 4 Register 6: Auto-Negotiation Expansion.................................................................................................58
7.5.8. PHY 4 Register 16~18: ISP MAC Address .........................................................................................................59
7.5.9. PHY 4 Register 22: Port 4 Control 0..................................................................................................................59
7.5.10. PHY 4 Register 23: Port 4 Control 1..................................................................................................................59
7.5.11. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]...................................................................................59
7.5.12. PHY 4 Register 25: VLAN Entry [E] ..................................................................................................................60
7.6. PHY 5 REGISTERS.....................................................................................................................................................60
7.6.1. PHY 5 Register 1: Control..................................................................................................................................60
7.6.2. PHY 5 Register 1: Status ....................................................................................................................................60
7.6.3. PHY 5 Register 2: PHY Identifier 1....................................................................................................................60
7.6.4. PHY 5 Register 3: PHY Identifier 2....................................................................................................................60
7.6.5. PHY 5 Register 4: Auto-Negotiation Advertisement...........................................................................................60
7.6.6. PHY 5 Register 5: Auto-Negotiation Link Partner Ability..................................................................................60
7.6.7. PHY 5 Register 6: Auto-Negotiation Expansion.................................................................................................60
7.6.8. PHY 5 Register 16: MII Port Control 0..............................................................................................................61
7.6.9. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]................................................................................62
7.6.10. PHY 5 Register 18: VLAN Entry [I] ...................................................................................................................62
7.6.11. PHY 5 Register 19: CPU Port & WAN Port.......................................................................................................62
7.6.12. PHY 5 Register 22: Port 5 Control 0..................................................................................................................63
7.6.13. PHY 5 Register 23: Port 5 Control 1..................................................................................................................63
7.6.14. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]...................................................................................63
7.6.15. PHY 5 Register 25: VLAN Entry [F] ..................................................................................................................63
7.7. PHY 6 REGISTERS.....................................................................................................................................................64
7.7.1. PHY 6 Register 0: Control..................................................................................................................................64
7.7.2. PHY 6 Register 1: Status ....................................................................................................................................64
7.7.3. PHY 6 Register 2: PHY Identifier 1....................................................................................................................64
7.7.4. PHY 6 Register 3: PHY Identifier 2....................................................................................................................64
7.7.5. PHY 6 Register 4: Auto-Negotiation Advertisement...........................................................................................64
7.7.6. PHY 6 Register 5: Auto-Negotiation Link Partner Ability..................................................................................64
7.7.7. PHY 6 Register 6: Auto-Negotiation Expansion.................................................................................................64
7.7.8. PHY 6 Register 22: Port 6 Control 0..................................................................................................................64
7.7.9. PHY 6 Register 23: Port 6 Control 1..................................................................................................................65
7.7.10. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G] ..................................................................................65
7.7.11. PHY 6 Register 25: VLAN Entry [G]..................................................................................................................65
7.8. PHY 7 REGISTERS.....................................................................................................................................................66
7.8.1. PHY 7 Register 0: Control..................................................................................................................................66
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller viii Track ID: JATR-1076-21 Rev. 1.1
7.8.2. PHY 7 Register 1: Status ....................................................................................................................................66
7.8.3. PHY 7 Register 2: PHY Identifier 1....................................................................................................................66
7.8.4. PHY 7 Register 3: PHY Identifier 2....................................................................................................................66
7.8.5. PHY 7 Register 4: Auto-Negotiation Advertisement...........................................................................................66
7.8.6. PHY 7 Register 5: Auto-Negotiation Link Partner Ability..................................................................................66
7.8.7. PHY 7 Register 6: Auto-Negotiation Expansion.................................................................................................66
7.8.8. PHY 7 Register 16: indirect Access Control.......................................................................................................67
7.8.9. PHY 7 Register 17~20: Indirect Access Data.....................................................................................................67
7.8.10. PHY 7 Register 22: Port 7 Control 0..................................................................................................................67
7.8.11. PHY 7 Register 23: Port 7 Control 1..................................................................................................................67
7.8.12. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H] ..................................................................................68
7.8.13. PHY 7 Register 25: VLAN Entry [H]..................................................................................................................68
7.9. PHY 8 REGISTERS.....................................................................................................................................................69
7.9.1. PHY 8 Register 0: Control..................................................................................................................................69
7.9.2. PHY 8 Register 1: Status ....................................................................................................................................69
7.9.3. PHY 8 Register 4: Auto-Negotiation Advertisement...........................................................................................70
7.9.4. MII Port NWay Mode .........................................................................................................................................71
7.9.5. MII Port Force Mode .........................................................................................................................................71
8. FUNCTIONAL DESCRIPTION.......................................................................................................................................72
8.1. PHYSICAL LAY ER TRANSCEIVER FUNCTIONAL OVERVIEW .......................................................................................72
8.1.1. Auto Negotiation for UTP ..................................................................................................................................72
8.1.2. 100Base-Tx Transmit Function ..........................................................................................................................72
8.1.3. 100Base-Tx Receive Function ............................................................................................................................72
8.1.4. 10Base-T Transmit Function ..............................................................................................................................73
8.1.5. 10Base-T Receive Function................................................................................................................................73
8.1.6. Link Monitor.......................................................................................................................................................73
8.1.7. Power Saving Mode............................................................................................................................................73
8.1.8. Power-Down Mode.............................................................................................................................................74
8.1.9. Auto Crossover Detection...................................................................................................................................74
8.2. SWITCH CORE FUNCTIONAL OVERVIEW....................................................................................................................74
8.2.1. Address Search, Learning, and Aging ................................................................................................................74
8.2.2. Flow Control ......................................................................................................................................................75
8.2.3. Half Duplex Operation.......................................................................................................................................75
8.2.4. Back Pressure .....................................................................................................................................................76
8.2.5. UTP Port Status Configuration ..........................................................................................................................76
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller ix Track ID: JATR-1076-21 Rev. 1.1
8.2.6. MII Port (The 9th Port) ......................................................................................................................................76
8.3. ADVANCED FUNCTIONALITY OVERVIEW...................................................................................................................80
8.3.1. Port-Based VLAN ...............................................................................................................................................80
8.3.2. 802.1Q Tagged-VID based VLAN.......................................................................................................................81
8.3.3. QoS Operation....................................................................................................................................................83
8.3.4. Insert/Remove VLAN Priority Tag......................................................................................................................84
8.3.5. Port VID (PVID) ................................................................................................................................................85
8.3.6. Port Trunking .....................................................................................................................................................85
8.3.7. ISP MAC Address Translation............................................................................................................................85
8.3.8. Lookup Table Access...........................................................................................................................................87
8.3.9. Serial Management Interface (SMI) ...................................................................................................................87
8.3.10. Broadcast Storm Control ....................................................................................................................................88
8.3.11. Broadcast In/Out Drop.......................................................................................................................................88
8.3.12. EEPROM Configuration Interface .....................................................................................................................89
8.3.13. 24LC02 Device Operation..................................................................................................................................89
8.3.14. Head-of-Line Blocking .......................................................................................................................................91
8.3.15. MII Port Diagnostic Loopback...........................................................................................................................91
8.3.16. Loop Detection ...................................................................................................................................................92
8.3.17. LEDs 93
9. CHARACTERISTICS .......................................................................................................................................................96
9.1. ABSOLUTE MAXIMUM RATI NG S ................................................................................................................................96
9.2. OPERATING RANGE ...................................................................................................................................................96
9.3. DC CHARACTERISTICS..............................................................................................................................................96
9.4. AC CHARACTERISTICS..............................................................................................................................................97
9.5. DIGITAL TIMING CHARACTERISTICS .........................................................................................................................98
9.6. THERMAL CHARACTERISTICS .................................................................................................................................100
10. SYSTEM APPLICATIONS .........................................................................................................................................101
11. DESIGN AND LAYOUT GUIDE................................................................................................................................101
12. MECHANICAL DIMENSIONS .................................................................................................................................105
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller x Track ID: JATR-1076-21 Rev. 1.1
List of Tables
Table 1. Pin Assignments .............................................................................................................................................................6
Table 2. Media Connection Pins...................................................................................................................................................7
Table 3. MII Port MAC Interface Pins .........................................................................................................................................7
Table 4. Miscellaneous Pins .........................................................................................................................................................9
Table 5. Port LED Pins.................................................................................................................................................................9
Table 6. Serial EEPROM and SMI Pins .....................................................................................................................................11
Table 7. Strapping Pins...............................................................................................................................................................12
Table 8. Power Pins....................................................................................................................................................................15
Table 9. Global Control Register0..............................................................................................................................................16
Table 10. Global Control Register1..............................................................................................................................................16
Table 11. Global Control Register2..............................................................................................................................................17
Table 12. Global Control Register3..............................................................................................................................................17
Table 13. Global Control Register4..............................................................................................................................................18
Table 14. Global Control Register5..............................................................................................................................................18
Table 15. Global Control Register6..............................................................................................................................................18
Table 16. Global Control Register7..............................................................................................................................................19
Table 17. Port 0 Control 0 ............................................................................................................................................................19
Table 18. Port 0 Control 1 ............................................................................................................................................................20
Table 19. Port 0 Control 2 ............................................................................................................................................................20
Table 20. Port 0 Control 3 ............................................................................................................................................................20
Table 21. Port 0 Control 4 ............................................................................................................................................................21
Table 22. IP Address.....................................................................................................................................................................21
Table 23. Port 1 Control 0 ............................................................................................................................................................22
Table 24. Port 1 Control 1 ............................................................................................................................................................22
Table 25. Port 1 Control 2 ............................................................................................................................................................23
Table 26. Port 1 Control 3 ............................................................................................................................................................23
Table 27. Port 1 Control 4 ............................................................................................................................................................24
Table 28. IP Mask.........................................................................................................................................................................24
Table 29. Port 2 Control 0 ............................................................................................................................................................25
Table 30. Port 2 Control 1 ............................................................................................................................................................25
Table 31. Port 2 Control 2 ............................................................................................................................................................26
Table 32. Port 2 Control 3 ............................................................................................................................................................26
Table 33. Port 2 Control 4 ............................................................................................................................................................27
Table 34. Switch MAC Address ...................................................................................................................................................27
Table 35. Port 3 Control 0 ............................................................................................................................................................28
Table 36. Port 3 Control 1 ............................................................................................................................................................28
Table 37. Port 3 Control 2 ............................................................................................................................................................29
Table 38. Port 3 Control 3 ............................................................................................................................................................29
Table 39. Port 3 Control 4 ............................................................................................................................................................29
Table 40. ISP MAC Address.........................................................................................................................................................30
Table 41. Port 4 Control 0 ............................................................................................................................................................30
Table 42. Port 4 Control 1 ............................................................................................................................................................31
Table 43. Port 4 Control 2 ............................................................................................................................................................31
Table 44. Port 4 Control 3 ............................................................................................................................................................32
Table 45. Port 4 Control 4 ............................................................................................................................................................32
Table 46. MII Port Control 0 ........................................................................................................................................................33
Table 47. MII Port Control 1 ........................................................................................................................................................33
Table 48. MII Port Control 2 ........................................................................................................................................................34
Table 49. CPU Port and WAN Port ..............................................................................................................................................34
Table 50. Port 5 Control 0 ............................................................................................................................................................35
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller xi Track ID: JATR-1076-21 Rev. 1.1
Table 51. Port 5 Control 1 ............................................................................................................................................................35
Table 52. Port 5 Control 2 ............................................................................................................................................................36
Table 53. Port 5 Control 3 ............................................................................................................................................................36
Table 54. Port 5 Control 4 ............................................................................................................................................................36
Table 55. Port 6 Control 0 ............................................................................................................................................................37
Table 56. Port 6 Control 1 ............................................................................................................................................................37
Table 57. Port 6 Control 2 ............................................................................................................................................................38
Table 58. Port 6 Control 3 ............................................................................................................................................................38
Table 59. Port 6 Control 4 ............................................................................................................................................................38
Table 60. Port 7 Control 0 ............................................................................................................................................................39
Table 61. Port 7 Control 1 ............................................................................................................................................................39
Table 62. Port 7 Control 2 ............................................................................................................................................................40
Table 63. Port 7 Control 3 ............................................................................................................................................................40
Table 64. Port 7 Control 4 ............................................................................................................................................................40
Table 65. PHY 0 Register 0: Control............................................................................................................................................41
Table 66. PHY 0 Register 1: Status ..............................................................................................................................................42
Table 67. PHY 0 Register 2: PHY Identifier 1 .............................................................................................................................43
Table 68. PHY 0 Register 3: PHY Identifier 2 .............................................................................................................................43
Table 69. PHY 0 Register 4: Auto-Negotiation Advertisement....................................................................................................43
Table 70. PHY 0 Register 5: Auto-Negotiation Link Partner Ability ...........................................................................................44
Table 71. PHY 0 Register 6: Auto-Negotiation Expansion ..........................................................................................................44
Table 72. PHY 0 Register 16: Global Control 0...........................................................................................................................45
Table 73. PHY 0 Register 17: Global Control 1...........................................................................................................................47
Table 74. PHY 0 Register 18: Global Control 2...........................................................................................................................48
Table 75. PHY 0 Register 19: Global Control 3...........................................................................................................................48
Table 76. PHY 0 Register 22: Port 0 Control 0 ............................................................................................................................49
Table 77. PHY 0 Register 23: Port 0 Control 1 ............................................................................................................................50
Table 78. PHY 0 Register 24: Port 0 Control 2 &VLAN Entry [A].............................................................................................50
Table 79. PHY 0 Register 25: VLAN Entry [A]...........................................................................................................................51
Table 80. PHY 1 Register 16~17: IP Priority Address [A] ...........................................................................................................52
Table 81. PHY 1 Register 18~19: IP Priority Address [B] ...........................................................................................................52
Table 82. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B] ............................................................................................53
Table 83. PHY 1 Register 25: VLAN Entry [B]...........................................................................................................................53
Table 84. PHY 2 Register 16~17: IP Priority Mask [A] ...............................................................................................................54
Table 85. PHY 2 Register 18~19: IP Priority Mask [B] ...............................................................................................................54
Table 86. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C] ............................................................................................55
Table 87. PHY 2 Register 25: VLAN Entry [C]...........................................................................................................................55
Table 88. PHY 3 Register 16~18: Switch MAC Address.............................................................................................................57
Table 89. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]............................................................................................57
Table 90. PHY 3 Register 25: VLAN Entry [D]...........................................................................................................................58
Table 91. PHY 4 Register 16~18: ISP MAC Address ..................................................................................................................59
Table 92. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E] ............................................................................................59
Table 93. PHY 4 Register 25: VLAN Entry [E] ...........................................................................................................................60
Table 94. PHY 5 Register 16: MII Port Control 0 ........................................................................................................................61
Table 95. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I] .........................................................................................62
Table 96. PHY 5 Register 18: VLAN Entry [I] ............................................................................................................................62
Table 97. PHY 5 Register 19: CPU Port & WAN Port.................................................................................................................62
Table 98. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F].............................................................................................63
Table 99. PHY 5 Register 25: VLAN Entry [F] ...........................................................................................................................63
Table 100. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]..........................................................................................65
Table 101. PHY 6 Register 25: VLAN Entry [G].........................................................................................................................65
Table 102. PHY 7 Register 16: indirect Access Control...............................................................................................................67
Table 103. PHY 7 Register 17~20: Indirect Access Data .............................................................................................................67
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller xii Track ID: JATR-1076-21 Rev. 1.1
Table 104. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]..........................................................................................68
Table 105. PHY 7 Register 25: VLAN Entry [H].........................................................................................................................68
Table 106. PHY 8 Register 0: Control..........................................................................................................................................69
Table 107. PHY 8 Register 1: Status ............................................................................................................................................69
Table 108. PHY 8 Register 4: Auto-Negotiation Advertisement..................................................................................................70
Table 109. MII Port NWay Mode.................................................................................................................................................71
Table 110. MII Port Force Mode..................................................................................................................................................71
Table 111. 802.1Q VLAN Tag Frame Format ..............................................................................................................................84
Table 112. IPv4 Frame Format .....................................................................................................................................................84
Table 113. IPv6 Frame Format .....................................................................................................................................................84
Table 114. SMI Read/Write Cycles ..............................................................................................................................................87
Table 115. Loop Frame Format ....................................................................................................................................................92
Table 116. Speed and Bi-color Link/Act Truth Table...................................................................................................................94
Table 117. Absolute Maximum Ratings .......................................................................................................................................96
Table 118. Operating Range .........................................................................................................................................................96
Table 119. DC Characteristics ......................................................................................................................................................96
Table 120. AC Characteristics ......................................................................................................................................................97
Table 121. Digital Timing Characteristics....................................................................................................................................99
Table 122. Thermal Operating Range.........................................................................................................................................100
Table 123. Thermal Resistance...................................................................................................................................................101
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller xiii Track ID: JATR-1076-21 Rev. 1.1
List of Figures
Figure 1. Block Diagram..............................................................................................................................................................4
Figure 2. Pin Assignments............................................................................................................................................................5
Figure 3. MII Port Application ...................................................................................................................................................77
Figure 4. MII Port Operating Mode Overview...........................................................................................................................79
Figure 5. VLAN Grouping Example ..........................................................................................................................................81
Figure 6. Tagged and Untagged Packet Forwarding When 802.1Q Tag Aware VLAN is Disabled...........................................82
Figure 7. ISP MAC Outbound Process.......................................................................................................................................86
Figure 8. ISP MAC Inbound Process .........................................................................................................................................86
Figure 9. Input Drop vs. Output Drop ........................................................................................................................................88
Figure 10. Start and Stop Definition.............................................................................................................................................89
Figure 11. Output Acknowledge...................................................................................................................................................90
Figure 12. Random Read..............................................................................................................................................................90
Figure 13. Sequential Read ..........................................................................................................................................................90
Figure 14. MII Port Loopback......................................................................................................................................................91
Figure 15. Loop Example.............................................................................................................................................................92
Figure 16. Floating and Pull-down of LED Pins..........................................................................................................................93
Figure 17. Two Pin Bi-color LED for SPD Floating or Pull-high ................................................................................................94
Figure 18. Two Pin Bi-color LED for SPD Pull-down.................................................................................................................94
Figure 19. Bi-color LED Reference Schematic............................................................................................................................95
Figure 20. Reception Data Timing of MII/SNI/SMI Interface .....................................................................................................98
Figure 21. Transmission Data Timing of MII/SNI/SMI Interface ................................................................................................98
Figure 22. Cross-section of 128 PQFP.......................................................................................................................................100
Figure 23. Application for Transformer with Connected Central Tap ........................................................................................103
Figure 24. Bob Smith Termination.............................................................................................................................................104
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller 1 Track ID: JATR-1076-21 Rev. 1.1
1. General Description
The RTL8309SB is a 128-pin, ultra low power, high-performance 8-port Fast Ethernet single-chip switch with one extra MII
port for specific applications. It integrates all the functions of a high speed switch system—including SRAM for packet
buffering, non-blocking switch fabric, address management, one general use MII interface, eight 10/100Base-TX transceivers,
and nine Media Access Controllers—into a single 0.18um CMOS device. It provides compatibility with all industry standard
Ethernet and Fast Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs.
The embedded packet storage SRAM in the RTL8309SB features superior memory management technology to efficiently
utilize the memory space. The RTL8309SB also integrates a 1024 entry look-up table to store MAC address and associated
information in a 10-bit direct mapping scheme. The table provides read/write access from the SMI interface, and each of the
entries can be configured as a static entry. A static entry indicates that this entry is controlled by the external management
processor and automatic aging and learning of the entry will not take place. To prevent MAC address mapping collisions, the
embedded 16-entry CAM affords another memory space for recording the MAC address when the mapped entry in the lookup
table is occupied by others. For each incoming packet, the RTL8309SB searches the entries in the lookup table and the 16-
entry CAM simultaneously, then it obtains the correct destination port information to determine which output port the packet
should be forwarded to. The aging time of the RTL8309SB is around 300 seconds (this may be sped up to 800µs via EEPROM
configuration).
The ninth port of the RTL8309SB implements a MAC module without a PHY transceiver to provide an MII interface for
connection with an external PHY or MAC in specific applications. This MII interface may be set to MII PHY mode, SNI PHY
mode, or MII MAC mode to work with an external MAC module in a routing engine application, PHY module in a HomePNA
application, or other physical layer transceivers. In order to operate correctly, both sides of the connection must be configured
to the same speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This interface
should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO of this interface.
The RTL8309SB is capable of preventing broadcast storms by setting strapping pins upon system reset. When this function is
enabled, it will drop broadcast packets after receiving 64 continuous broadcast packets. This counter will be reset to 0 every
800ms or when the RTL8309SB receives a non-broadcast packet.
The RTL8309SB displays the port status supports via four LED indicators (with optional blinking time setting). These LEDs
blink for diagnostic purposes at system reset time. The RTL8309SB provides various type of LED combinations to fit different
applications. Eight combinations of link, activity, speed, duplex, and collision, are available. Bi-color LED mode is also
supported on the Link/Act LED.
The RTL8309SB supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It
determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet
buffers and transmitting queues. If one of the forwarding ports are blocked, or system resources are unavailable, broadcast
frames will be dropped according to the system configuration. The RTL8309SB support two types of dropping methods. The
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller 2 Track ID: JATR-1076-21 Rev. 1.1
input dropping method will not forward broadcast packets to any output ports and will drop these packets directly. The output
dropping method will forward broadcast packets to the non-blocked ports only.
To improve real-time or multimedia networking applications, the RTL8309SB supports four types of QoS (Quality of Service).
These are based on (1) Port-based priority, (2) 802.1p/Q VLAN priority tag, (3) TOS field in IPv4 header, (4) Specific IP
address. Each output ports supports a weighted ratio of high-priority and low-priority queues to fit bandwidth requirements in
different applications.
The RTL8309SB provides 802.1Q port-based VLAN operation to separate logical connectivity from physical connectivity.
Each port may be set to any topology via EEPROM upon reset or SMI after reset. The RTL8309SB also provides options to
meet special application requirements. The first option is the ARP VLAN function, which is used to select to broadcast ARP
frames to all VLANs or only forward ARP frames to the originating VLAN. The second option is the Leaky VLAN function,
which is used to select to send unicast frames to other VLANs or only forward unicast frames to the originating VLAN. The
VLAN tags can be inserted or removed on a per port basis.
In router applications, the router may want to know which input port this packet came from. The RTL8309SB supports Port
VID (PVID) for each port to insert a PVID in the VLAN tag on egress. In this function, the VID information carried in the
VLAN tag will be changed to PVID. The RTL8309SB also provide an option to admit VLAN tagged packet with a specific
PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID.
Each physical layer channel consists of a 4B5B encoder/decoder, Manchester encoder/decoder, transmit output driver,
scrambler/descrambler, output wave shaping, filters, digital adaptive equalizer, PLL circuit, and DC restoration circuit for
clock/data recovery. This integrated chip benefits from low power consumption, advanced functions with flexible
configuration for a small workgroup switch, multimedia or real-time traffic mixed with other data type traffic, and other
applications.
RTL8309SB
Datasheet
Single-Chip 9-port 10/100Mbps Switch Controller 3 Track ID: JATR-1076-21 Rev. 1.1
2. Features
Integrated eight 10/100 transceivers and nine MAC
units for 10Base-T and 100Base-TX.
Embedded SRAM for packet storage.
On-chip 1024 entry look-up table in direct mapping
mode.
Embedded 16-entry CAM for hash collision mapping.
Provides read/write access to look-up table entries via
SMI interface.
Provides non-blocking wire speed reception and
transmission.
Flow control fully supported:
Half-duplex: back pressure flow control.
Full-duplex: IEEE 802.3x flow control.
Per-port support for 4 LEDs with various
combinations for comprehensive applications.
Optional loop detection function with an LED to
indicate the existence of a loop.
Supports MII loopback.
Flexible system configuration by strapping pins,
EEPROM, or SMI interface.
Optional Forwarding /Filtering reserved control frames
(DID= 0180C2000003~0180C200000F).
Optional Broadcast Input/Output Drop flow control.
Optional maximum packet length 1536/1552 Bytes.
Supports QoS function
QoS based on: (1) Port-based priority (2) 802.1p
VLAN tag (3) DiffServ/TOS field in TCP/IP
header (4) IP address.
Supports two level priority queues on various
weighting ratios
Queue service rate based on weighted round robin
algorithm
Optional auto turn off Flow Control for 1~2 sec to
avoid head of line blocking.
Supports MII interface connection to external MAC or
PHY via 3 modes.
PHY mode MII for router applications.
PHY mode SNI for router applications.
MAC mode MII for HomePNA or other PHY
applications.
Flexible 802.1Q port / tag based VLAN.
Optional 802.1Q tag-VID aware function.
Optional VLAN Ingress Tag Admit Control.
Optional VLAN Ingress Member set filtering.
Optional ARP VLAN for broadcast packet.
Optional Leaky VLAN for unicast packet.
Optional 802.1P/Q tag insertion or removal on per-port
basis (egress).
Supports two Power Reduction methods:
Power saving mode (automatic cable detection).
Power down mode (by PHY register 0.11).
Optional MDI/MDIX auto crossover for plug-and-
play.
Fully compliant with IEEE 802.3/802.3u.
LEDs blink upon reset for LED diagnostics.
25MHz crystal input.
0.18um, CMOS technology.
128-pin PQFP package.
1.8V core voltage.
Independent power options for 2.5V or 3.3V MII
interface.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 4 Track ID: JATR-1076-21 Rev. 1.1
3. Block Diagram
Waveform
Shaping
IBREF
P8MODE[1:0]
10Base-T or
100Base-TX
PHYceiver
10Base-T or
100Base-TX
PHYceiver
10Base-T or
100Base-TX
PHYceiver
10Base-T or
100Base-TX
PHYceiver
10Base-T or
100Base-TX
PHYceiver
Mode
Select
10/100
MAC 0 TX/RX
FIFO
Flow
Control
10/100
MAC 1 TX/RX
FIFO
Flow
Control
10/100
MAC 2 TX/RX
FIFO
Flow
Control
10/100
MAC 3 TX/RX
FIFO
Flow
Control
10/100
MAC 4 TX/RX
FIFO
Flow
Control
10/100
MAC 5 TX/RX
FIFO
Flow
Control
10/100
MAC 6 TX/RX
FIFO
Flow
Control
10Base-T or
100Base-TX
PHYceiver
RX+-[0]
TX+-[0]
10Base-T or
100Base-TX
PHYceiver
RX+-[1]
TX+-[1]
RX+-[2]
TX+-[2]
RX+-[3]
TX+-[3]
RX+-[4]
TX+-[4]
RX+-[5]
TX+-[5]
RX+-[6]
TX+-[6]
Switch Fabric, VLAN, QoS, Trunking
Look-up Table
(1024-entries)
Queue
Management
Buffer
Management
Packet Buffer
10/100
MAC 8 TX/RX
FIFO
Flow
Control
10Base-T or
100Base-TX
PHYceiver
RX+-[7]
TX+-[7]
PHY
Mode
Inter
face
MAC
Mode
10/100
MAC 7 TX/RX
FIFO
Flow
Control
Control
Registers
EEPROM
Interface
RTL8309SB
13
/
MII
Signal
Figure 1. Block Diagram
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 5 Track ID: JATR-1076-21 Rev. 1.1
4. Pin Assignments
103
124
123
122
121
125
128
127
126
113
112
111
110
109
108
107
106
105
104
114
120
119
118
117
116
115
90
89
79
83
80
82
84
81
86
85
87
88
102
101
91
95
92
94
96
93
98
97
99
100
P5_LED[3]/Dis_DS_Pri
P6_LED[0]/QWeight[0]
VSSD
P7_LED[0]/Dis_ARPVLAN
P7_LED[3]/Dis_FC_AutoOff
P7_LED[1]/LED_BLNK_TIME
P6_LED[3]/Dis_LeakyVLAN
P7_LED[2]/Port_LED_LOC
VDDD
P6_LED[2]/Dis_VLAN
VSSD
P6_LED[1]/QWeight[1]
P3_LED[2]/En_Forward
P5_LED[2]/Dis_VLAN_Pri
VSSD
P5_LED[1]/Sel_PortPri[1]
VDDD
P4_LED[3]/Max_Pause_Count
P5_LED[0]/Sel_PortPri[0]
P4_LED[1]/En_Agrs_Back
P4_LED[2]/Max_Pkt_Len
P4_LED[0]/En_48pass1
P3_LED[3]/En_Defer
78
77
67
71
68
70
72
69
74
73
75
76
66
65
VDDD
MRXC/PTXC
MRXD[0]/PTXD[0]
MRXDV/PTXEN
MRXD[2]/PTXD[2]
MRXD[1]/PTXD[1]
MRXD[3]/PTXD[3]
MCOL/PCOL
1
11
9
8
7
6
5
4
3
2
10
12
22
21
20
19
18
17
16
15
14
13
23
33
32
31
30
29
28
27
26
25
24
34
38
37
36
35
VDDD
55
59
56
58
60
57
62
61
63
64
54
53
47
48
50
49
51
52
43
44
46
45
39
40
42
41
MII_LNK_STA#
MTXC/PRXC
VSSD
MTXEN/PRXDV
MTXD[1]/PRXD[1]
MTXD[0]/PRXD[0]
MTXD[2]/PRXD[2]
MTXD[3]/PRXD[3]
RTL8309SB
VSSD
VDDD
VDDIO
VSSIO
MII_DUP_STA
MII_SPD_STA
MII_FCTRL_STA
VDDD
VSSD
VSSD
VDDD
P3_LED[1]/Dis_Trunk
P3_LED[0]/LED_MODE[2]
P2_LED[3]/LED_MODE[1]
P2_LED[2]/LED_MODE[0]
P2_LED[1]/MII_MODE[1]
P2_LED[0]/MII_MODE[0]
En_AutoXover/P1_LED[3]
TXON[2]
TXOP[2]
RXIP[2]
RXIN[2]
VDDA
RXIN[1]
RXIP[1]
VSSA
VDDA
TXOP[4]
VSSA
RXIP[4]
RXIN[4]
VDDA
RXIN[3]
VSSA
TXOP[3]
TXON[3]
VDDA
VSSA
RXIP[6]
RXIN[6]
RXIN[5]
RXIP[5]
VSSA
TXOP[5]
TXON[5]
TXOP[6]
RXIN[7]
RXIP[7]
TXON[6]
TXON[1]
VSSA
RXIP[3]
TXON[4]
VDDA
TXOP[1]
VSSA
X1
VSSA
TXOP[0]
VDDA
IBREF
VDDPLL
Test Pin
X2
RXIP[0]
RXIN[0]
TXON[0]
SCL_MDC
SDA_MDIO
VSSA
TXOP[7]
VDDA
TXON[7]
Test Pin
En_ANEG/P1_LED[2]
Force_Duplex/P0_LED[3]
Force_Speed/P0_LED[2]
En_FCTRL/P1_LED[1]
En_BKPRS/P1_LED[0]
En_BRD_CTRL/P0_LED[1]
En_RST_BLNK/P0_LED[0]
RESET#
Test pin
EnEEPROM/LoopLED#
VDDA
VDDA
NC
VSSPLL
Figure 2. Pin Assignments
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 6 Track ID: JATR-1076-21 Rev. 1.1
Codes used in the following tables: ‘A’ stands for analog; ‘D’ stands for digital, ‘I’ stands for input; ‘O’ stands for output.
Table 1. Pin Assignments
Name Pin No. Type Name Pin No Type
VDDA,
VSSA,
TXON[1],
TXOP[1],
VSSA,
RXIP[1],
RXIN[1],
VDDA,
RXIN[2],
RXIP[2],
VSSA,
TXOP[2],
TXON[2],
VDDA,
TXON[3],
TXOP[3],
VSSA,
RXIP[3],
RXIN[3],
VDDA,
RXIN[4],
RXIP[4],
VSSA,
TXOP[4],
TXON[4],
VDDA,
TXON[5],
TXOP[5],
VSSA,
RXIP[5],
RXIN[5],
VDDA,
RXIN[6],
RXIP[6],
VSSA,
TXOP[6],
TXON[6],
VDDA,
RXIN[7],
RXIP[7],
VSSA,
TXOP[7],
TXON[7],
VDDA,
NC,
NC
RESET#
MII_FCTRL_STA,
MII_SPD_STA,
MII_DUP_STA,
MII_LNK_STA#,
VDDD,
VSSD,
SCL_MDC,
SDA_MDIO,
MTXC/PRXC,
MTXEN/PRXDV,
MTXD[0]/PRXD[0],
MTXD[1]/PRXD[1],
MTXD[2]/PRXD[2],
MTXD[3]/PRXD[3],
VDDIO,
VSSIO,
MCOL/PCOL
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
64
AVDD
AGND
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
AVDD
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
AVDD
AO
AO
AGND
AI
AI
AVDD
AI
AI
AGND
AO
AO
AVDD
AI
AI
AGND
AO
AO
AVDD
I
I
I
I
I
DVDD
DGND
I/O
I/O
I/O
O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
MRXC / PTXC
MRXDV / PTXDV,
MRXD[0] / PTXD[0],
MRXD[1] / PTXD[1],
MRXD[2] / PTXD[2],
MRXD[3] / PTXD[3],
VDDD,
VSSD,
P7_LED[3] / Dis_FC_AutoOff,
P7_LED[2] / Port_LED_LOC,
P7_LED[1] / LED_BLNK_TIME,
P7_LED[0] / Dis_ARPVLAN,
P6_LED[3] / Dis_LeakyVLAN,
P6_LED[2] / Dis_VLAN,
VDDD,
VSSD,
P6_LED[1] / QWeight[1],
P6_LED[0] / QWeight[0],
P5_LED[3] / Dis_DS_Pri,
P5_LED[2] / Dis_VLAN_Pri,
P5_LED[1] / Sel_PortPri[1],
P5_LED[0] / Sel_PortPri[0],
VDDD,
VSSD,
P4_LED[3] / Max_Pause_Count,
P4_LED[2] / Max_Pkt_Len,
P4_LED[1] / En_Agrs_Back,
P4_LED[0] / En_48pass1,
P3_LED[3] / En_Defer,
P3_LED[2] / En_Forward,
VDDD,
VSSD
P3_LED[1] / Dis_Trunk,
P3_LED[0] / LED_MODE[2],
P2_LED[3] / LED_MODE[1],
P2_LED[2] / LED_MODE[0],
P2_LED[1] / MII_MODE[1],
P2_LED[0] / MII_MODE[0],
P1_LED[3] / En_AutoXover,
P1_LED[2] / En_ANEG,
P1_LED[1] / En_FCTRL
P1_LED[0] / En_BKPRS,
VDDD,
VSSD
P0_LED[3] / Force_Duplex,
P0_LED[2] / Force_Speed,
P0_LED[1] / En_BRD_CTRL,
P0_LED[0] / En_RST_BLNK,
LoopLED#,/EnEEPROM
VDDD,
VSSD,
NC,
VSSPLL,
X1,
X2,
VDDPLL,
NC,
IBREF,
VDDA,
TXON[0],
TXOP[0],
VSSA,
RXIP[0],
RXIN[0],
65,
66,
67,
68,
69,
70,
71,
72,
73,
74,
75,
76,
77,
78,
79
80,
81,
82,
83,
84,
85,
86,
87,
88,
89,
90,
91,
92,
93,
94,
95,
96,
97,
98,
99,
100,
101,
102,
103,
104,
105,
106,
107,
108,
109,
110,
111,
112,
113,
114,
115,
116,
117,
118,
119,
120,
121,
122,
123,
124,
125,
126,
127,
128
I/O
I
I
I
I
I
DVDD
DGND
I/O
I/O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
I/O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
I/O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DVDD
DGND
I/O
I/O
I/O
I/O
I/O
DVDD
DGND
AGND
I
O
AVDD
AO
AVDD
AO
AO
AGND
AI
AI
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 7 Track ID: JATR-1076-21 Rev. 1.1
5. Pin Description
“Type” codes used in the following tables: ‘A’ stands for analog; ‘D’ stands for digital, ‘I’ stands for input; ‘O’ stands for
output, ‘Ipu’ stands for input with internal pull-up.
Upon reset: defined as a short time after the end of a hardware reset. After reset: defined as the time after the specified “Upon
Reset” time.
5.1. Media Connection Pins
Table 2. Media Connection Pins
Pin Name Pin No. Type Description Default
RXIP[7:0]
RXIN[7:0]
6, 7,
9, 10,
18, 19,
21, 22,
30, 31,
33, 34,
39, 40,
127, 128
AI Differential Receive Data Input shared by 100Base-TX, 10Base-T
for connection to transformer.
TXOP[7:0]
TXON[7:0]
3, 4,
12, 13,
15, 16,
24, 25,
27, 28,
36, 37,
42, 43,
124, 125
AO Differential Transmit Data Output shared by 100Base-TX, 10Base-
T for connection to transformer.
5.2. MII Port MAC Interface Pins
The external device can be either 2.5V or 3.3V compatible depending on the power supplied to VDDIO. The input and
input/output pins listed below do not implement an internal pull-high resistor. An external pull-high resistor is required for
these floating input pins to reduce power consumption.
Table 3. MII Port MAC Interface Pins
Pin Name Pin No. Type Description Default
MRXD[3:0]
/PTXD[3:0]
67, 68,
69, 70
I For MII MAC mode, these pins are MRXD[3:0], MII receive data
nibble.
For MII PHY mode, these pins are PTXD[3:0], MII transmit data
nibble.
For SNI PHY mode, PTXD[0] is serial transmit data.
MRXDV/PTXEN 66 I For MII MAC mode, this pin represents MRXDV, MII receive data
valid.
For MII PHY mode, this pin represents PTXEN, MII transmit enable.
For SNI PHY mode, this pin represents PTXEN, transmit enable.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 8 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
MRXC/PTXC 65 I/O For MII MAC mode, this pin represents MRXC, MII receive clock
(acts as input).
For MII/SNI PHY mode, this pin represent PTXC, MII transmit clock
(acts as output).
MCOL/PCOL 64 I/O For MII MAC mode, this pin represents MCOL, MII collision detect
(acts as input).
For MII/SNI PHY mode, this pin represents PCOL, MII collision
detect (acts as output).
MTXD[3:0]
/PRXD[3:0]]
58, 59,
60, 61
O Output after reset =
For MII MAC mode, these pins are MTXD[3:0], MII transmit data of
MAC.
For MII PHY mode, these pins are PRXD[3:0], MII receive data of
MAC.
For SNI PHY mode, PRXD[0] is SNI serial receive data. PRXD[3:1]
are unused.
MTXEN/PRXDV 57 O For MII MAC mode, this pin represents MTXEN, MII transmit enable.
For MII PHY mode, this pin represents PRXDV, MII receive data valid.
For SNI PHY mode, this pin represents PRXDV, SNI receive data valid.
MTXC/PRXC 56 I/O For MII MAC mode, this pin represents MTXC, MII transmit clock
(acts as input).
For MII/SNI PHY mode, this pin represents MRXC, MII/SNI receive
clock (acts as output).
MII_MODE[1:0]
/P2_LED[1:0]
101,
102
Ipu Input upon reset = Select MII port (9th port) operating mode:
11=Tristate MII output
10=MII MAC mode
01=MII PHY mode
00=SNI PHY mode
11
MII_LNK_STA# 51 Ipu Provide MII port (9th port) Link Status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time:
This pin sets the link status of the MII port MAC module in real-time.
1
MII_DUP_STA 50 Ipu Provide MII port (9th port) duplex status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time:
1=MII port operates in full duplex mode.
0=MII port operates in half duplex mode.
1
MII_SPD_STA 49 Ipu Provide MII port (9th port) speed status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time:
1=MII port operates at 100Mbps speed.
0=MII port operates at 10Mbps speed.
For applications as below, this pin should be left floating:
For HomePNA (MII MAC mode), speed is determined by RXC and
TXC from PHY of HomePNA running at 1Mbps.
For SNI PHY mode, speed is fixed at 10MHz clock rate.
1
MII_FCTRL_STA 48 Ipu Provide MII port (9th port) flow control status for MAC module at MII
MAC/MII PHY/SNI PHY operation mode in real time:
1=MII port has flow control ability.
0=MII port does not have flow control ability.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 9 Track ID: JATR-1076-21 Rev. 1.1
5.3. Miscellaneous Pins
Table 4. Miscellaneous Pins
Pin Name Pin No. Type Description Default
X1 118 I 25MHz crystal input. The clock tolerance is +-50ppm.
X2 119 O 25MHz crystal output.
RESET# 47 I Active low reset signal. To complete the reset function, this pin must be
asserted for at least 10ms. After reset, about 30ms is needed for the
RTL8309SB to complete the internal test function and initialization.
Note: This pin is a Schmitt input pin.
IBREF 122 A Control transmit output waveform Vpp.
This pin should be grounded through a 2.0K ohm resistor.
NC 45, 46,
116, 121 Not Connected – Floating in normal operation.
5.4. Port LED Pins
Each port supports four LED pins for status indication. The indicated status of these four LED pins may be changed by setting
different values for strapping pin LED_MODE[2:0].
Note 1: All LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-
color LED mode, whose polarity depends on Bi-color Speed status.
Note 2: Those pins are dual function pins: output for LED or input for strapping.
Table 5. Port LED Pins
Pin Name Pin No. Type Description Default
P0_LED[0]
P1_LED[0]
P2_LED[0]
P3_LED[0]
P4_LED[0]
P5_LED[0]
P6_LED[0]
P7_LED[0]
112, 106,
102, 98,
92, 86,
82, 76
Ipu/O Output after reset = used for the 1st LED:
Mode 7: Speed (On =100 Mbps, Off =10Mbps)
Mode 6: Activity (Flash=Tx or Rx activity)
Mode 5: Speed (On =100 Mbps, Off =10Mbps)
Mode 4: Collision (Flash=Collision)
Mode 3: Reserved for internal use.
Mode 2: RxAct+10/100 (Flash every 120ms=10Mbps Rx activity,
Flash every 43ms = 100Mbps Rx activity)
Mode 1: Duplex+Collision (On=Full, Off=Half with no collision,
Flash = Collision)
Mode 0: Bi-color Speed (Polarity depends on Bi-color Link+Activity
LED status, please refer to LED section for detail information)
1
1
1
1
1
1
1
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 10 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
P0_LED[1]
P1_LED[1]
P2_LED[1]
P3_LED[1]
P4_LED[1]
P5_LED[1]
P6_LED[1]
P7_LED[1]
111, 105,
101, 97,
91, 85,
81, 75
Ipu/O Output after reset = used for the 2nd LED:
Mode 7: Duplex+Collision (On=Full, Off=Half with no collision,
Flash = Collision)
Mode 6: Speed (On =100 Mbps, Off =10Mbps)
Mode 5: Duplex (On=Full, Off=Half)
Mode 4: Duplex (On=Full, Off=Half)
Mode 3: Duplex+Collision (On=Full, Off=Half with no collision,
Flash = Collision)
Mode 2: TxAct+10/100 (Flash every 120ms = 10Mbps Tx activity,
Flash every 43ms = 100Mbps Tx activity)
Mode 1: 10Link+Act (On=Link on 10Mbps, Off=No link on 10Mbps,
Flash=10Mbps Tx or Rx activity)
Mode 0: Duplex+Collision (On=Full, Off=Half with no collision,
Flash = Collision)
1
1
1
1
1
1
1
1
P0_LED[2]
P1_LED[2]
P2_LED[2]
P3_LED[2]
P4_LED[2]
P5_LED[2]
P6_LED[2]
P7_LED[2]
110, 104,
100, 94,
90, 84,
78, 74,
Ipu/O Output after reset = used for the 3rd LED:
Mode 7: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity)
Mode 6: Link (On=Link, Off=No link)
Mode 5: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity)
Mode 4: Link+Act+Speed (On=Link, Off=No link, Flash every
120ms=10Mbps activity, flash every 43ms=100Mbps)
Mode 3: Link+Act+Speed (On=Link, Off=No link, Flash every
120ms=10Mbps activity, flash every 43ms=100Mbps)
Mode 2: Link (On=Link, Off=No link)
Mode 1: 100Link+Act (On=Link on 100Mbps, Off=No link on
100Mbps, Flash=100Mbps Tx or Rx activity)
Mode 0: Bi-color Link+Activity (Polarity depends on Bi-color Speed
LED status). See LEDs, page 93, for detailed information.
1
1
1
1
1
1
1
1
P0_LED[3]
P1_LED[3]
P2_LED[3]
P3_LED[3]
P4_LED[3]
P5_LED[3]
P6_LED[3]
P7_LED[3]
109, 103,
99, 93,
89, 83,
77, 73
Ipu/O Output after reset = used for the 4th LED:
Mode 7: Reserved for internal use.
Mode 6: Reserved for internal use.
Mode 5: Reserved for internal use.
Mode 4: Reserved for internal use.
Mode 3: 10/100 (On =100 Mbps, Off =10Mbps)
Mode 2: Reserved for internal use.
Mode 1: Reserved for internal use.
Mode 0: Reserved for internal use.
1
1
1
1
1
1
1
1
LED_MODE[2]
/P3_LED[0]
LED_MODE[1]
/P2_LED[3]
LED_MODE[0]
/P2_LED[2]
98,
99,
100
I/O Input upon reset = Select LED display mode upon reset
LED_MODE[2:0]=111 -> Mode 7:
Speed, Duplex+Collision, Link+Act, Reserved.
LED_MODE[2:0]=110 -> Mode 6:
Activity, Speed, Link, Reserved.
LED_MODE[2:0]=101 -> Mode 5:
Speed, Duplex, Link+Act, Reserved.
LED_MODE[2:0]=100 -> Mode 4:
Collision, Duplex, Link+Act+Speed, Reserved.
LED_MODE[2:0]=011 -> Mode 3:
Reserved, Duplex+Collision, Link+Act+Speed, 10/100
LED_MODE[2:0]=010 -> Mode 2:
RxAct+10/100, TxAct+10/100, Link, Reserved.
LED_MODE[2:0]=001 -> Mode 1:
Duplex+Collision, 10Link+Act, 100Link+Act, Reserved.
LEDM_ODE[2:0]=000 -> Mode 0:
Bi-color Speed, Duplex+Collision, Bi-color Link+Act, Reserved.
111
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 11 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
Port_LED_LOC
/P7_LED[2]
74 Ipu/O Input upon reset = Per port LED pin location reversed:
1=For designs where LEDs are placed at the opposite side to the
phone jack.
Port 0 LEDs are assigned at pins 109~112.
Port 1 LEDs are assigned at pins 103~106.
Port 2 LEDs are assigned at pins 99~102.
Port 3 LEDs are assigned at pins 93, 94, 97, 98.
Port 4 LEDs are assigned at pins 89~92.
Port 5 LEDs are assigned at pins 83~86.
Port 6 LEDs are assigned at pins 77, 78, 80, 81.
Port 7 LEDs are assigned at pins 73~76.
0=Suitable for designs where LEDs are placed on the same side as the
phone jack.
Port 0 LEDs are assigned at pins 73~76.
Port 1 LEDs are assigned at pins 77, 78, 80, 81.
Port 2 LEDs are assigned at pins 83~86.
Port 3 LEDs are assigned at pins 89~92.
Port 4 LEDs are assigned at pins 93, 94, 97, 98.
Port 5 LEDs are assigned at pins 99~102.
Port 6 LEDs are assigned at pins 103~106.
Port 7 LEDs are assigned at pins 109~112.
LoopLED#
/EnEEPROM
113 Ipu/O Output after reset = LoopLED# used for LED:
If Loop detection is enabled, this pin indicates whether a Network loop
is detected or not. Otherwise, this pin has no function.
Note: The LED statuses are represented as active-low or high
depending on input strapping.
=> If Input=1: Output 0= Network loop is detected. 1=No loop.
=> If Input=0: Output 1= Network loop is detected. 0= No loop.
1
5.5. Serial EEPROM and SMI Pins
Table 6. Serial EEPROM and SMI Pins
Pin Name Pin No. Type Description Default
EnEEPROM
/LoopLED#
113 Ipu/O Input upon reset = Enable loading of serial EEPROM upon
reset:
1=Enable to load Serial EEPROM upon reset.
0=Disable to load Serial EEPROM upon reset.
1
SCL_MDC 54 I/O
EEPROM Serial Clock or MDC:
This pin is three state when pin RESET#=0.
When RTL8309SB detects an EEPROM connected to it, this pin
becomes SCL (output) to load the serial EEPROM upon reset. Then
this pin changes as MDC (input) after reset. In this case, this pin
should be pulled high (VDDIO 2.5V/3.3V) by external register.
When RTL8309SB doesn’t detect an EEPROM connected to it, this
pin is MDC (input). In this case, it needs an external pull-high
resistor, unless it is floated.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 12 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
SDA_MDIO 55 I/O
EEPROM Serial Data Input/Output or MDIO:
This pin is three state when pin RESET#=0.
When RTL8309SB detects an EEPROM connected to it, this pin
becomes SDA (input/output) to load the serial EEPROM upon reset.
Then this pin changes as MDIO (input/output) after reset.
When RTL8309SB doesn’t detect an EEPROM connected to it, this
pin is MDIO (input/output). It should be pulled high by an external
resistor.
5.6. Strapping Pins
Note: All strapping pins are dual function pins: output for LED or input for strapping. The table below covers strapping only.
See Port LED Pins, on page 9 for LED pin settings.
Table 7. Strapping Pins
Pin Name Pin No. Type Description Default
En_ANEG
/P1_LED[2]
104 Ipu Input upon reset = Enable Auto-negotiation function:
1: Enable the auto-negotiation function (NWay mode) and set PHY
register 0.12.
0: Disable the auto-negotiation function (force mode) and deselect
PHY register 0.12.
1
En_FCTRL
/P1_LED[1]
105 Ipu Input upon reset = Enable flow control ability in full duplex mode:
1: In NWay mode, this pin sets PHY register 4.10, but the flow control
function is finally enabled based on the auto negotiation result. In
force mode, this pin will always enable the flow control function.
0: Disable the flow control function.
Output after reset = used for LED
1
En_BKPRS
/P1_LED[0]
106 Ipu Input upon reset = Enable back pressure ability in half duplex
mode:
1: Enable back pressure.
0: Disable back pressure.
Output after reset = used for LED
1
Force_Duplex
/P0_LED[3]
109 Ipu Force duplex mode:
This pin sets PHY Reg.0.8 and influences the contents of PHY Reg.4.
1: Force full duplex if auto-negotiation is disabled.
0: Force half duplex if auto-negotiation is disabled.
Output after reset = used for LED
1
Force_Speed
/P0_LED[2]
110 Ipu Force operating speed:
This pin sets PHY Reg.0.13 and influences the contents of PHY Reg.4.
1=Force 100Mbps speed if auto-negotiation is disabled.
0=Force 10Mbps speed if auto-negotiation is disabled.
Output after reset = used for LED
1
En_BRD_CTRL
/P0_LED[1]
111 Ipu Input upon reset = Disable Broadcast Storm Control:
1: Disable Broadcast Storm Control.
0: Enable Broadcast Storm Control.
Output after reset = used for LED
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 13 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
En_RST_BLNK
/P0_LED[0]
112 Ipu Input upon reset = Enable blinking of LEDs upon reset:
1: Enable power-on LED blinking for diagnosis.
0: Disable power-on LED blinking.
Output after reset = used for LED
1
En_AutoXover
/P1_LED[3]
103 Ipu Input upon reset = Enable Auto crossover detection:
1: Enable auto crossover detection.
0: Disable auto crossover detection. MDI only.
Output after reset = used for LED
1
Dis_FC_AtuoOff
/P7_LED[3]
73 Ipu Disable auto turn off of flow control ability:
1: Disable
0: Enable auto turn off flow control ability on the low priority queue
for 1~2 seconds whenever the port receives a high priority frame. The
flow control ability will be re-enabled if this port does not receive
another high priority frame during this 1~2 sec duration.
Output after reset = used for LED
1
En_Forward
/P3_LED[2]
94 Ipu Input upon reset = Enable forwarding of 802.1D specified reserved
group MAC address frames:
1: Forward reserved control packets with DID=01-80-C2-00-00-03 to
01-80-C2-00-00-0F.
0: Filter reserved control packets with DID=01-80-C2-00-00-03 to 01-
80-C2-00-00-0F.
Output after reset = used for LED
1
En_Defer
/P3_LED[3]
93 Ipu Input upon reset = Enable carrier sense defering function:
1: Enable carrier sense deferring function for half duplex back
pressure.
0: Disable carrier sense deferring function for half duplex back
pressure.
Output after reset = used for LED
1
En_48pass1
/P4_LED[0]
92 Ipu Enable 48 pass 1 mechanism:
1: 48 pass 1, continuously collides 48 input packets then passes 1
packet to retain system resources and avoid repeater partition when
buffer is full.
0: Continuously collides input packets to avoid packet loss when
buffer is full.
Output after reset = used for LED
1
En_Agrs_Back
/P4_LED[1]
91 Ipu Input upon reset = Enable aggressive back-off mechanism:
1: Enable more aggressive back-off mechanism in half duplex mode
for performance enhancement. The back-off limitation will become 3
at this duration (default is 10).
0: Disable aggressive back-off mechanism in half duplex mode.
Output after reset = used for LED
1
Max_Pkt_Len
/P4_LED[2]
90 Ipu Input upon reset = Select maximum frame length:
1: 1536 bytes.
0: 1552 bytes.
Output after reset = used for LED
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 14 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
Max_Pause_Count
/P4_LED[3]
89 Ipu Input upon reset = Select the max Pause frame count during a
congested event:
1: Generates maximum of 128 pause frames, even if congestion still
exists
0: Continuously generates pause frames until congestion is resolved
Output after reset = used for LED
1
Dis_Trunk
/P3_LED[1]
97 Ipu Disable Two Port Trunking function:
1=Disable two port trunking function.
0=Port 0 and port 1 are combined as one trunk.
Output after reset = used for LED
1
Sel_PortPri[1:0]
/P5_LED[1:0]
85, 86 Ipu Input upon reset = Select high priority port for port-based priority
QoS :
11: Disable port-based priority function.
10: Select port 0 as high priority port.
01: Select port 2 as high priority port.
00: Select port 3 as high priority port.
Output after reset = used for LED
1
Dis_VLAN_Pri
/P5_LED[2]
84 Ipu Input upon reset = Disable 802.1p VLAN tag priority based QoS:
1: Disable 802.1p priority classification for ingress packets on each
port.
0: Enable 802.1p priority classification for ingress packets on each
port. A User priority field in the VLAN tag greater or equal to 4 will
be considered a high priority packet.
Output after reset = used for LED
1
Dis_DS_Pri
/P5_LED[3]
83 Ipu Input upon reset = Disable Diffserv priority based QoS:
1: Disable diffserv priority classification for ingress packets on each
port.
0: Enable diffserv priority classification for ingress packets on each
port.
Output after reset = used for LED
1
QWeight[1:0]
/P6_LED[1:0]
81, 82 Ipu Input upon reset = Weighted round robin ratio priority queue:
The frame service ratio between the high priority queue and low
priority queue is:
11=16:1
10=always high priority queue first
01=8:1
00=4:1
Output after reset = used for LED
1
Dis_VLAN
/P6_LED[2]
78 Ipu Input upon reset = Disable VLAN.
1: Disable VLAN.
0: Enable VLAN. The default VLAN membership configuration is
port 7 overlapped with all the other ports, including the MII port, to
form 8 individual VLANs. The default membership configuration may
be modified by setting internal registers via the SMI interface or
EEPROM.
Output after reset = used for LED
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 15 Track ID: JATR-1076-21 Rev. 1.1
Pin Name Pin No. Type Description Default
Dis_LeakyVLAN
/P6_LED[3]
77 Ipu Input upon reset = Disable Leaky VLAN:
1: Disable forwarding of unicast frames to other VLANs.
0: Enable forwarding of unicast frames to other VLANs.
Note: Broadcast and multicast frames adhere to the VLAN
configuration.
Output after reset = used for LED
1
Dis_ARPVLAN
/P7_LED[0]
76 Ipu Input upon reset = Disable ARP broadcast to all VLANs:
1: Disable broadcast of ARP broadcast packets to all VLANs
0: Enable broadcast of ARP broadcast packets to all VLANs.
Output after reset = used for LED
1
LED_BLNK_TIME
/P7_LED[1]
75 Ipu Input upon reset = Select blinking speed of activity and collision
LED:
1: On 43ms then Off 43ms.
0: On 120ms then Off 120ms.
Note: this pin only affects LEDs that are configured in LED mode 1, 5,
and 7.
Output after reset = used for LED
1
5.7. Power Pins
Table 8. Power Pins
Pin Name Pin No. Type Description Default
VDDD 52, 71,
79, 87,
95,107,
114
P 1.8V digital power.
VSSD 53, 72,
80, 88,
96, 108,
115
G Digital ground.
VDDIO 62 P 2.5/3.3V digital VDD for MII interface.
VSSIO 63 G Digital ground for MII interface.
VDDPLL 120 P 1.8V analog power for PLL.
VSSPLL 117 G 1.8V analog power for PLL.
VDDA 1, 8,
14, 20,
26, 32,
38, 44,
123
P 1.8V analog power (Used for transmitters and equalizers).
VSSA 2, 5,
11, 17,
23, 29,
35, 41,
126
G Analog ground.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 16 Track ID: JATR-1076-21 Rev. 1.1
6. EEPROM Register Description
6.1. Global Control Registers
6.1.1. Global Control Register0
Table 9. Global Control Register0
Name Byte.bit Description Default
EEPROM
existence
0.7 1=EEPROM does not exist.
0=EEPROM exists.
0
Accept Error
disable
0.6 1=Filter bad packets in normal operation.
0=Switch all packets including bad ones.
1
IEEE 802.3x
transmit flow
control enable
0.5 1=Invoke transmit flow control based on auto-negotiation result.
0=Switch will not enable transmit flow control.
1
IEEE 802.3x
receive flow
control enable
0.4 1=When the switch receives a pause control frame, it has the ability to stop
the next transmission of a normal frame until the timer has expired based on
the auto negotiation result.
0=Receive flow control not enabled.
1
Broadcast input
or output drop
0.3 1=Broadcast input drop is selected.
0=Broadcast output drop is selected.
1
Aging enable 0.2 1=Enable aging function in the switch.
0=Disable aging function in the switch.
1
Fast aging
enable
0.1 1=An entry learned in the lookup table will be aged out if it is not updated
within an 800µs period.
0=Disable fast aging function. The normal aging time of the RTL8309SB is
around 200~300 seconds.
0
Enable ISP
MAC Address
Translation
0.0 1=Enable ISP MAC Address Translation.
0=Disable ISP MAC Address Translation.
0
6.1.2. Global Control Register1
Table 10. Global Control Register1
Name Byte.bit Description Default
LED Mode 1.7~1.5 111 -> Mode 7: Speed, Duplex+Collision, Link+Act, SQI
110 -> Mode 6: Activity, Speed, Link, SQI
101 -> Mode 5: Speed, Duplex, Link+Act, SQI
100 -> Mode 4: Collision, Duplex, Link+Act+Speed, SQI
011 -> Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100
010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI
001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI
000 -> Mode 0: Duplex+Collision, Bi-color Speed, Bi-color Link+Act,
SQI
111
Reserved 1.4 1
Disable VLAN 1.3 1: Disable VLAN.
0: Enable VLAN.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 17 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
Disable 802.1Q
tag aware
VLAN
1.2 1=Disable the 802.1Q tagged-VID Aware function.
0=Use tagged-VID VLAN mapping for tagged frames but still use Port-
Based VLAN mapping for priority-tagged and untagged frame.
0
Disable VLAN
member set
ingress filtering
1.1 1=The switch will not drop the received frame if the ingress port of this
packet is not included in the matched VLAN member set.
0=The switch will drop the received frame if the ingress port of this packet
is not included in the matched VLAN member set.
1
Disable VLAN
tag admit
control
1.0 1=The switch accepts all frames received.
0=The switch will only accept tagged frames and will drop untagged
frames.
1
6.1.3. Global Control Register2
Table 11. Global Control Register2
Name Byte.bit Description Default
Enable default
high priority
DiffServ code
point
2.7 1=The default DiffServ code point listed below will be considered a high
priority code point if DiffServ priority function is enabled.
EF – “101110”
AF – “001010” “010010” “011010” “100010”
Network Control – “111000” “110000”
0=The default DiffServ code point will be considered as low priority.
1
Reserved 2.6~2.0 1111
111
6.1.4. Global Control Register3
Table 12. Global Control Register3
Name Byte.bit Description Default
802.1p base
priority
3.7~3.5 Used to classify priority for incoming 802.1Q packets when 802.1p priority
classification is enabled. “User priority” compared against this value.
>=: Classify as high priority
<: Classify as low priority
100
Trunking port
assignment
3.4 1=Combine port 0 and 1 as one trunking port, if trunking is enabled by
strapping pin, Dis_Trunk.
0=Combine port 6 and 7 as one trunking port, if trunking is enabled by
strapping pin, Dis_Trunk.
1
Queue weight 3.3~3.2 The frame service ratio between the high priority queue and low priority
queue is:
11=16:1
10=always high priority queue first
01=8:1
00=4:1
11
Disable IP
priority for IP
address [A]
3.1 1=The switch will compare both the source and destination IP addresses of
an incoming packet against the value, IP address [A] AND IP mask [A], to
classify priority for the packet.
0=The switch will not compare the source or destination IP addresses of an
incoming packet against the value, IP address [A] AND IP mask [A].
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 18 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
Disable IP
priority for IP
address [B]
3.0 1=The switch will compare both the source and destination IP addresses of
an incoming packet against the value, IP address [B] AND IP mask [B], to
classify priority for the packet.
0=The switch will not compare the source and destination IP addresses of
an incoming packet against the value, IP address [B] AND IP mask [B].
0
6.1.5. Global Control Register4
Table 13. Global Control Register4
Name Byte.bit Description Default
Enable
Differential
Service Code
Point [B]
4.7 1=If Differential Service Priority is enabled, this bit specifies differential
service code point [B] is high priority.
0=If Differential Service Priority is enabled, this bit specifies differential
service code point [B] is low priority.
0
Reserved 4.6 1
Differential
Service Code
Point [B]
4.5~4.0 Used to specify a high priority differential service code point B. For
example, if these bits are set as “000000”, all incoming packets with a TOS
field equal to “000000” will be considered high priority packets.
000000
6.1.6. Global Control Register5
Table 14. Global Control Register5
Name Byte.bit Description Default
Enable
Differential
Service Code
Point [A]
5.7 1=If Differential Service Priority is enabled, this bit specifies differential
service code point [A] is high priority.
0=If Differential Service Priority is enabled, this bit specifies differential
service code point [A] is low priority.
0
Reserved 5.6 1
Differential
Service Code
Point [A]
5.5~5.0 Used to specify a high priority differential service code point A. For
example, if these bits are set as “111111”, all incoming packets with a TOS
field equal to “000000” will be considered high priority packets.
111111
6.1.7. Global Control Register6
Table 15. Global Control Register6
Name Byte.bit Description Default
Reserved 6.7~6.0 0000
0001
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 19 Track ID: JATR-1076-21 Rev. 1.1
6.1.8. Global Control Register7
Table 16. Global Control Register7
Name Byte.bit Description Default
Enable drop for
48 pass 1
7.7 1=Enable drop packet when SRAM full for 48 pass 1
0=Disable drop packet when SRAM full for 48 pass 1. This will result in
SRAM run out.
1
Bypass CRC 7.6 1=Disable bypass CRC. This will cause CRC recalculation.
0=Enable bypass CRC. This will cause the switch to not recalculate the
CRC. Only used for debug.
1
TX IPG
compensation
7.5 1=90ppm TX IPG compensation.
0=65ppm TX IPG compensation.
1
Disable loop
detection
7.4 1=Disable loop detection function.
0=Enable loop detection function.
1
Reserved 7.3 1
Lookup table
accessible
enable
7.2 1=Lookup table is accessible via indirect access registers.
0=Lookup table is not accessible.
0
Reserved 7.1~7.0 11
6.2. Port 1~4 Control Pins
6.2.1. Port 0 Control 0
Table 17. Port 0 Control 0
Name Byte.bit Description Default
Reserved 8.7~8.6 11
Speed and
Duplex ability
8.5~
8.4
In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 8.3 1
Backpressure
enable
8.2 1=Enable port 0 half duplex backpressure.
0=Disable port 0 half duplex backpressure.
1
VLAN tag
insertion and
removal
8.1~8.0 11=Do not insert or remove VLAN tags to/from packet.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 20 Track ID: JATR-1076-21 Rev. 1.1
6.2.2. Port 0 Control 1
Table 18. Port 0 Control 1
Name Byte.bit Description Default
Reserved 9.7~9.6 11
Local loopback 9.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
9.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
9.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
9.2 1=Disable 802.1p priority classification for ingress packets on port 0.
0=Enable 802.1p priority classification on port 0.
1
Disable
Diffserv
priority
9.1 1=Disable Diffserv priority classification for ingress packets on port 0.
0=Enable Diffserv priority classification on Port 0.
1
Disable port-
based priority
9.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 0 will be
classified as high priority.
1
6.2.3. Port 0 Control 2
Table 19. Port 0 Control 2
Name Byte.bit Description Default
Reserved 10.7~
10.4
1111
Good link
quality
threshold
10.3~
10.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.2.4. Port 0 Control 3
Table 20. Port 0 Control 3
Name Byte.bit Description Default
Reserved 11.7~
11.4
1111
Transmission
enable
11.3 1=Enable packet transmission on port 0.
0=Disable packet transmission on port 0.
1
Reception
enable
11.2 1=Enable packet reception on port 0.
0=Disable packet reception on port 0.
1
Learning enable 11.1 1=Enable switch address learning capability.
0=Disable switch address learning capability.
1
Reserved 11.0 1
VLAN Entry [A]
VLAN ID [A]
membership Bit
[7:0]
12.7~
12.0
This register along with byte 13.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0000
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 21 Track ID: JATR-1076-21 Rev. 1.1
6.2.5. Port 0 Control 4
Table 21. Port 0 Control 4
Name Byte.bit Description Default
Port 0 VLAN
index [3:0]
13.7~
13.4
In a port-based VLAN configuration, this register indexes port 0’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 0 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0000
Reserved 13.3~
13.1
111
VLAN ID [A]
membership Bit
[8]
13.0 This register along with byte 12.7~12.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [A]
VLAN ID [A]
[7:0]
14.7~
14.0
This register along with byte 15.3~15.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN A.
0000
0000
VLAN Entry [A]
Reserved 15.7~
15.4
1111
VLAN ID [A]
[11:8]
15.3~
15.0
This register along with byte 14.7~14.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN A.
0000
6.2.6. IP Address
Table 22. IP Address
Name Byte.bit Description Default
IP Address [A]
IP Address [A]
[16:23]
16.7~
16.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Address [A]
IP Address [A]
[31:24]
17.7~
17.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Address [A]
IP Address [A]
[7:0]
18.7~
18.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Address [A]
IP Address [A]
[15:8]
19.7~
19.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Address [B]
IP Address [B]
[16:23]
20.7~
20.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 22 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
IP Address [B]
IP Address [B]
[31:24]
21.7~
21.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
IP Address [B]
IP Address [B]
[7:0]
22.7~
22.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
IP Address [B]
IP Address [B]
[15:8]
23.7~
23.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
6.2.7. Port 1 Control 0
Table 23. Port 1 Control 0
Name Byte.bit Description Default
Reserved 24.7~
24.6
11
Speed and
Duplex ability
24.5~
24.4
In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 24.3 1
Backpressure
enable
24.2 1=Enable port 1 half duplex backpressure.
0=Disable port 1 half duplex backpressure.
1
VLAN tag
insertion and
removal
24.1~
24.0
11=Do not insert or remove VLAN tags to/from packets.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
6.2.8. Port 1 Control 1
Table 24. Port 1 Control 1
Name Byte.bit Description Default
Reserved 25.7
~25.6
11
Local loopback 25.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
25.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 23 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
Discard Non
PVID packets
25.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
25.2 1=Disable 802.1p priority classification for ingress packets on port 1.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
25.1 1=Disable Diffserv priority classification for ingress packets on port 1.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
25.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 1 will be
classified as high priority.
1
6.2.9. Port 1 Control 2
Table 25. Port 1 Control 2
Name Byte.bit Description Default
Reserved 26.7~
26.4
1111
Good link
quality
threshold
26.3~
26.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.2.10. Port 1 Control 3
Table 26. Port 1 Control 3
Name Byte.bit Description Default
Reserved 27.7~
27.4
1111
Transmission
enable
27.3 1=Enable packet transmission on port 1.
0=Disable packet transmission on port 1.
1
Reception
enable
27.2 1=Enable packet reception on port 1.
0=Disable packet reception on port 1.
1
Learning enable 27.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 27.0 1
VLAN Entry [B]
VLAN ID [B]
membership Bit
[7:0]
28.7~
28.0
This register along with byte 29.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0000
0010
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 24 Track ID: JATR-1076-21 Rev. 1.1
6.2.11. Port 1 Control 4
Table 27. Port 1 Control 4
Name Byte.bit Description Default
Port 1 VLAN
index [3:0]
29.7~
29.4
In a port-based VLAN configuration, this register indexes port 1’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 1 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0001
Reserved 29.3~
29.1
111
VLAN ID [B]
membership Bit
[8]
29.0 This register along with byte 28.7~28.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [B]
VLAN ID [B]
[7:0]
30.7~
30.0
This register along with byte 31.3~31.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN B.
0000
0001
VLAN Entry [B]
Reserved 31.7~
31.4
1111
VLAN ID [B]
[11:8]
31.3~
31.0
This register along with byte 30.7~30.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN B.
0000
6.2.12. IP Mask
Table 28. IP Mask
IP Mask [A]
IP Mask [A]
[16:23]
32.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Mask [A]
IP Mask [A]
[31:24]
33.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Mask [A]
IP Mask [A]
[7:0]
34.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Mask [A]
IP Mask [A]
[15:8]
35.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [A] AND IP mask [A], to classify priority for
the packet, if IP priority for IP address [A] is enabled.
0xff
IP Mask [B]
IP Mask [B]
[16:23]
36.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 25 Track ID: JATR-1076-21 Rev. 1.1
IP Mask [B]
IP Mask [B]
[31:24]
37.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
IP Mask [B]
IP Mask [B]
[7:0]
38.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
IP Mask [B]
IP Mask [B]
[15:8]
39.7~
32.0
The switch will compare the source IP address of an incoming packet
against the value, IP address [B] AND IP mask [B], to classify priority for
the packet, if IP priority for IP address [B] is enabled.
0xff
6.2.13. Port 2 Control 0
Table 29. Port 2 Control 0
Name Byte.bit Description Default
Reserved 40.7
~40.6
11
Speed and
Duplex ability
40.5~
40.4
In the auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 40.3 1
Backpressure
enable
40.2 1=Enable port 2 half duplex backpressure.
0=Disable port 2 half duplex backpressure.
1
VLAN tag
insertion and
removal
40.1~
40.0
11=Do not insert or remove VLAN tags to/from packets.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace VID with PVID for tagged packets and insert PVID to non-
tagged packets.
11
6.2.14. Port 2 Control 1
Table 30. Port 2 Control 1
Name Byte.bit Description Default
Reserved 41.7~
41.6
11
Local loopback 41.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
41.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 26 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
Discard Non
PVID packets
41.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
41.2 1=Disable 802.1p priority classification for ingress packets on port 2.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
41.1 1=Disable Diffserv priority classification for ingress packets on port 2.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
41.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 2 will be
classified as high priority.
1
6.2.15. Port 2 Control 2
Table 31. Port 2 Control 2
Name Byte.bit Description Default
Reserved 42.7~
42.4
1111
Good link
quality
threshold
42.3~
42.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.2.16. Port 2 Control 3
Table 32. Port 2 Control 3
Name Byte.bit Description Default
Reserved 43.7~
43.4
1111
Transmission
enable
43.3 1=Enable packet transmission on port 2.
0=Disable packet transmission on port 2.
1
Reception
enable
43.2 1=Enable packet reception on port 2.
0=Disable packet reception on port 2.
1
Learning enable 43.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 43.0 1
VLAN Entry [C]
VLAN ID [C]
membership Bit
[7:0]
44.7~
44.0
This register along with byte 45.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0000
0100
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 27 Track ID: JATR-1076-21 Rev. 1.1
6.2.17. Port 2 Control 4
Table 33. Port 2 Control 4
Name Byte.bit Description Default
Port 2 VLAN
index [3:0]
45.7~
45.4
In a port-based VLAN configuration, this register indexes port 2’s ‘Port
VLAN Membership’, which can be defined in one of the registers ‘VLAN
ID [A] Membership’ to “VLAN ID [I] Membership”. Port 2 can only
communicate within the membership. This register also indexes to a default
Port VID (PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0010
Reserved 45.3~
45.1
111
VLAN ID [C]
membership Bit
[8]
45.0 This register along with byte 44.7~44.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [C]
VLAN ID [C]
[7:0]
46.7~
46.0
This register along with byte 47.3~47.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN C.
0000
0010
VLAN Entry [C]
Reserved 47.7~
47.4
1111
VLAN ID [C]
[11:8]
47.3~
47.0
This register along with byte 46.7~46.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN C.
0000
6.2.18. Switch MAC Address
The Switch MAC address is used as the source address in MAC pause control frames.
Table 34. Switch MAC Address
Switch MAC Address
Switch MAC
Address [47:40]
48.7~
48.0
Switch MAC Address Byte 5. 0x52
Switch MAC
Address [39:32]
49.7~
49.0
Switch MAC Address Byte 4. 0x54
Switch MAC
Address [31:24]
50.7~
50.0
Switch MAC Address Byte 3. 0x4C
Switch MAC
Address [23:16]
51.7~
51.0
Switch MAC Address Byte 2. 0x83
Switch MAC
Address [15:8]
52.7~
52.0
Switch MAC Address Byte 1. 0x09
Switch MAC
Address [7:0]
53.7~
53.0
Switch MAC Address Byte 0. 0xB0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 28 Track ID: JATR-1076-21 Rev. 1.1
6.2.19. Port 3 Control 0
Table 35. Port 3 Control 0
Name Byte.bit Description Default
Reserved 54.7~
54.6
11
Speed and
Duplex ability
54.5~
54.4
In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 54.3 1
Backpressure
enable
54.2 1=Enable port 3 half duplex backpressure.
0=Disable port 3 half duplex backpressure.
1
VLAN tag
insertion and
removal
54.1~
54.0
11=Do not insert or remove VLAN tags to/from packets.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
6.2.20. Port 3 Control 1
Table 36. Port 3 Control 1
Name Byte.bit Description Default
Reserved 55.7~
55.6
11
Local loopback 55.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
55.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
55.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
55.2 1=Disable 802.1p priority classification for ingress packets on port 3.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
55.1 1=Disable Diffserv priority classification for ingress packets on port 3.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
55.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 3 will be
classified as high priority.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 29 Track ID: JATR-1076-21 Rev. 1.1
6.2.21. Port 3 Control 2
Table 37. Port 3 Control 2
Name Byte.bit Description Default
Reserved 56.7~
56.4
1111
Good link
quality
threshold
56.3~
56.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.2.22. Port 3 Control 3
Table 38. Port 3 Control 3
Name Byte.bit Description Default
Reserved 57.7~
57.4
1111
Transmission
enable
57.3 1=Enable packet transmission on port 3.
0=Disable packet transmission on port 3.
1
Reception
enable
57.2 1=Enable packet reception on port 3.
0=Disable packet reception on port 3.
1
Learning enable 57.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 57.0 1
VLAN Entry [D]
VLAN ID [D]
membership Bit
[7:0]
58.7~
58.0
This register along with byte 59.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0000
1000
6.2.23. Port 3 Control 4
Table 39. Port 3 Control 4
Name Byte.bit Description Default
Port 3 VLAN
index [3:0]
59.7~
59.4
In a port-based VLAN configuration, this register indexes port 3’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 3 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0011
Reserved 59.3~
59.1
111
VLAN ID [D]
membership Bit
[8]
59.0 This register along with byte 58.7~58.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [D]
VLAN ID [D]
[7:0]
60.7~
60.0
This register along with byte 61.3~61.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN D.
0000
0011
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 30 Track ID: JATR-1076-21 Rev. 1.1
VLAN Entry [D]
Reserved 61.7~
61.4
1111
VLAN ID [D]
[11:8]
61.3~
61.0
This register along with byte 60.7~60.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN D.
0000
6.2.24. ISP MAC Address
The ISP MAC address is used as the source address in MAC address translation.
Table 40. ISP MAC Address
Name Byte.bit Description Default
ISP MAC Address [47:40] 62.7~62.0 ISP MAC address byte 5. 0xff
ISP MAC Address [39:32] 63.7~63.0 ISP MAC address byte 4. 0xff
ISP MAC Address [31:24] 64.7~64.0 ISP MAC address byte 3. 0xff
ISP MAC Address [23:16] 65.7~65.0 ISP MAC address byte 2. 0xff
ISP MAC Address [15:8] 66.7~66.0 ISP MAC address byte 1. 0xff
ISP MAC Address [7:0] 67.7~67.0 ISP MAC address byte 0. 0xff
6.2.25. Port 4 Control 0
Table 41. Port 4 Control 0
Name Byte.bit Description Default
Reserved 68.7~
68.6
11
Speed and
Duplex ability
68.5~
68.4
In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 68.3 1
Backpressure
enable
68.2 1=Enable port 4 half duplex backpressure.
0=Disable port 4 half duplex backpressure.
1
VLAN tag
insertion and
removal
68.1~
68.0
11=Do not insert or remove VLAN tags to/from packet.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 31 Track ID: JATR-1076-21 Rev. 1.1
6.2.26. Port 4 Control 1
Table 42. Port 4 Control 1
Name Byte.bit Description Default
Reserved 69.7~
68,6
11
Local loopback 69.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
69.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
69.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
69.2 1=Disable 802.1p priority classification for ingress packets on port 4.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
69.1 1=Disable Diffserv priority classification for ingress packets on port 4.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
69.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets on port 4 will be classified
as high priority.
1
6.2.27. Port 4 Control 2
Table 43. Port 4 Control 2
Name Byte.bit Description Default
Reserved 70.7~
70.4
1111
Good link
quality
threshold
70.3~
70.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 32 Track ID: JATR-1076-21 Rev. 1.1
6.2.28. Port 4 Control 3
Table 44. Port 4 Control 3
Name Byte.bit Description Default
Reserved 71.7~
71.4
1111
Transmission
enable
71.3 1=Enable packet transmission on port 4.
0=Disable packet transmission on port 4.
1
Reception
enable
71.2 1=Enable packet reception on port 4.
0=Disable packet reception on port 4.
1
Learning enable 71.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 71.0 1
VLAN Entry [E]
VLAN ID [E]
membership Bit
[7:0]
72.7~
72.0
This register along with byte 73.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0001
0000
6.2.29. Port 4 Control 4
Table 45. Port 4 Control 4
Name Byte.bit Description Default
Port 4 VLAN
index [3:0]
73.7~
73.4
In a port-based VLAN configuration, this register indexes port 4’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 4 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0100
Reserved 73.3~
73.1
111
VLAN ID [E]
membership Bit
[8]
73.0 This register along with byte 72.7~72.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [E]
VLAN ID [E]
[7:0]
74.7~
74.0
This register along with byte 75.3~75.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN E.
0000
0100
VLAN Entry [E]
Reserved 75.7~
75.4
1111
VLAN ID [E]
[11:8]
75.3~
75.0
This register along with byte 74.7~74.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN E.
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 33 Track ID: JATR-1076-21 Rev. 1.1
6.3. MII Port Control Pins
6.3.1. MII Port Control 0
Table 46. MII Port Control 0
Name Byte.bit Description Default
Reserved 76.7~
76.2
1111
11
VLAN tag
insertion and
removal
76.1~
76.0
11=Do not insert or remove VLAN tags to/from packets.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00=Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
6.3.2. MII Port Control 1
Table 47. MII Port Control 1
Name Byte.bit Description Default
Transmission
enable
77.7 1=Enable packet transmission on MII interface.
0=Disable packet transmission on MII interface.
1
Reception
enable
77.6 1=Enable packet reception on MII interface.
0=Disable packet reception on MII interface.
1
Learning enable 77.5 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Enable MII
loopback
77.4 1=Enable local loop back function. The switch will only forward local and
broadcast packets from the input of MII RX to the output of MII TX but
drop unicast packets from the input of MII RX. The other ports still can
forward packets to MII port.
0=Disable local loop back function.
0
Disable 802.1p
priority
77.3 1=Disable 802.1p priority classification for ingress packets on MII port.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
77.2 1=Disable Diffserv priority classification for ingress packets on MII port.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
77.1 1=Disable port priority function.
0=Enable port priority function. Ingress packets from the MII port will be
classified as high priority.
1
Reserved 77.0 0
VLAN Entry [I]
VLAN ID [I]
membership Bit
[7:0]
78.7~
78.0
This register along with byte 79.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1111
1111
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 34 Track ID: JATR-1076-21 Rev. 1.1
6.3.3. MII Port Control 2
Table 48. MII Port Control 2
Name Byte.bit Description Default
Null VID
replacement
79.7 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
79.6 1=If the received packets are tagged, the switch will discard packets whose
VID does not match ingress port default VID, which is indexed by port 8’s
“Port based VLAN index”.
0=No packets will be dropped.
0
Reserved 79.5 1
Port 8 VLAN
index [3:0]
79.4~
79.1
In a port-based VLAN configuration, this register indexes port 8’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 8 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0000
VLAN ID [I]
membership Bit
[8]
79.0 This register along with byte 78.7~78.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [I]
VLAN ID [I]
[7:0]
80.7~
80.0
This register along with byte 81.3~81.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN I.
0000
1000
VLAN Entry [I]
Reserved 81.7~
81.4
1111
VLAN ID [I]
[11:8]
81.3~
81.0
This register along with byte 80.7~80.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN I.
0000
6.3.4. CPU Port and WAN Port
Table 49. CPU Port and WAN Port
Name Byte.bit Description Default
WA N Po r t 8 2. 7 ~
82.4
Specifies the WAN port on the RTL8309SB
1111~1000=MII port is WAN port
0111=Port 7 is WAN Port 0110=Port 6 is WAN port
0101=Port 5 is WAN Port 0100=Port 4 is WAN port
0011=Port 3 is WAN Port 0010=Port 2 is WAN port
0001=Port 1 is WAN Port 0000=Port 0 is WAN port
0111
CPU Port 82.3~
82.0
Specifies the CPU port on the RTL8309SB
1111~1000=MII port is CPU port
0111=Port 7 is CPU Port 0110=Port 6 is CPU port
0101=Port 5 is CPU Port 0100=Port 4 is CPU port
0011=Port 3 is CPU Port 0010=Port 2 is CPU port
0001=Port 1 is CPU Port 0000=Port 0 is CPU port
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 35 Track ID: JATR-1076-21 Rev. 1.1
6.4. Port 5~7 Control Pins
6.4.1. Port 5 Control 0
Table 50. Port 5 Control 0
Name Byte.bit Description Default
Reserved 83.7~
83.6
11
Speed and
Duplex ability
83.5~
83.4
In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 83.3 1
Backpressure
enable
83.2 1=Enable port 5 half duplex backpressure.
0=Disable port 5 half duplex backpressure.
1
VLAN tag
insertion and
removal
83.1~
83.0
11=Do not insert or remove VLAN tags to/from packet.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00= Replace the VID with a PVID for tagged packets and insert a PVID to
non-tagged packets.
11
6.4.2. Port 5 Control 1
Table 51. Port 5 Control 1
Name Byte.bit Description Default
Reserved 84.7~
84.6
11
Local loopback 84.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
84.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
84.3 1=If the received packets are tagged, the switch will discard packets whose
VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
84.2 1=Disable 802.1p priority classification for ingress packets on port 5.
0=Enable 802.1p priority classification.
1
Disable
Diffserv
priority
84.1 1=Disable Diffserv priority classification for ingress packets on port 5.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
84.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 5 will be
classified as high priority.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 36 Track ID: JATR-1076-21 Rev. 1.1
6.4.3. Port 5 Control 2
Table 52. Port 5 Control 2
Name Byte.bit Description Default
Reserved 85.7~
85.4
1111
Good link
quality
threshold
85.3~
85.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.4.4. Port 5 Control 3
Table 53. Port 5 Control 3
Name Byte.bit Description Default
Reserved 86.7~
86.4
1111
Transmission
enable
86.3 1=Enable packet transmission on port 5.
0=Disable packet transmission on port 5.
1
Reception
enable
86.2 1=Enable packet reception on port 5.
0=Disable packet reception on port 5.
1
Learning enable 86.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 86.0 1
VLAN Entry [F]
VLAN ID [F]
membership Bit
[7:0]
87.7~
87.0
This register along with byte 88.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
0010
0000
6.4.5. Port 5 Control 4
Table 54. Port 5 Control 4
Name Byte.bit Description Default
Port 5 VLAN
index [3:0]
88.7~88.4 In a port-based VLAN configuration, this register indexes port 5’s
‘Port VLAN Membership’, which could be defined in one of the
registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 5 can only communicate within the membership.
This register also indexes to a default Port VID (PVID) for each port.
The PVID is used in tag insertion and filtering if the tagged VID is
not the same as the PVID.
0101
Reserved 88.3~88.1 111
VLAN ID [F]
membership Bit [8]
88.0 This register along with byte 87.7~87.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g. 1 0000 0001 means
port 8 and 0 are in this VLAN.
1
VLAN Entry [F]
VLAN ID [F] [7:0] 89.7~89.0 This register along with byte 90.3~90.0 defines the IEEE 802.1Q 12-
bit VLAN identifier of VLAN F.
0000
0101
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 37 Track ID: JATR-1076-21 Rev. 1.1
Name Byte.bit Description Default
VLAN Entry [F]
Reserved 90.7~90.4 1111
VLAN ID [F]
[11:8]
90.3~90.0 This register along with byte 89.7~89.0 defines the IEEE 802.1Q 12-
bit VLAN identifier of VLAN F.
0000
6.4.6. Port 6 Control 0
Table 55. Port 6 Control 0
Name Byte.bit Description Default
Reserved 91.7~91.6 11
Speed and Duplex
ability
91.5~91.4 In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 91.3 1
Backpressure
enable
91.2 1=Enable port 6 half duplex backpressure.
0=Disable port 6 half duplex backpressure.
1
VLAN tag
insertion and
removal
91.1~91.0 11=Do not insert or remove VLAN tags to/from packet.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00= Replace the VID with a PVID for tagged packets and insert a
PVID to non-tagged packets.
11
6.4.7. Port 6 Control 1
Table 56. Port 6 Control 1
Name Byte.bit Description Default
Reserved 92.7~92.6 11
Local loopback 92.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
92.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non
PVID packets
92.3 1=If the received packets are tagged, the switch will discard packets
whose VID does not match the ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
92.2 1=Disable 802.1p priority classification for ingress packets on port 6.
0=Enable 802.1p priority classification.
1
Disable Diffserv
priority
92.1 1=Disable Diffserv priority classification for ingress packets on port 6.
0=Enable Diffserv priority classification.
1
Disable port-
based priority
92.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 6 will be
classified as high priority.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 38 Track ID: JATR-1076-21 Rev. 1.1
6.4.8. Port 6 Control 2
Table 57. Port 6 Control 2
Name Byte.bit Description Default
Reserved 93.7~93.4 1111
Good link quality
threshold
93.3~93.0 The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.4.9. Port 6 Control 3
Table 58. Port 6 Control 3
Name Byte.bit Description Default
Reserved 94.7~94.4 1111
Transmission
enable
94.3 1=Enable packet transmission on port 6.
0=Disable packet transmission on port 6.
1
Reception enable 94.2 1=Enable packet reception on port 6.
0=Disable packet reception on port 6.
1
Learning enable 94.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 94.0 0
VLAN Entry [G]
VLAN ID [G]
membership Bit
[7:0]
95.7~95.0 This register along with byte 96.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look
up fails, packets associated with this VLAN will be forwarded to
ports specified in this field. E.g. 1 0000 0001 means port 8 and 0 are
in this VLAN.
0100
0000
6.4.10. Port 6 Control 4
Table 59. Port 6 Control 4
Name Byte.bit Description Default
Port 6 VLAN
index [3:0]
96.7~96.4 In a port-based VLAN configuration, this register indexes port 6’s
‘Port VLAN Membership’, which could be defined in one of the
registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 6 can only communicate within the membership.
This register also indexes to a default Port VID (PVID) for each port.
The PVID is used in tag insertion and filtering if the tagged VID is
not the same as the PVID.
0110
Reserved 96.3~96.1 111
VLAN ID [G]
membership Bit [8]
96.0 This register along with byte 95.7~95.0 forms a 9-bit field that
specifies which ports are members of the VLAN. If a destination
address look up fails, packets associated with this VLAN will be
forwarded to ports specified in this field. E.g. 1 0000 0001 means
port 8 and 0 are in this VLAN.
1
VLAN Entry [G]
VLAN ID [G]
[7:0]
97.7~97.0 This register along with byte 98.3~98.0 defines the IEEE 802.1Q 12-
bit VLAN identifier of VLAN G.
0000
0110
VLAN Entry [G]
Reserved 98.7~98.4 1111
VLAN ID [G]
[11:8]
98.3~98.0 This register along with byte 97.7~97.0 defines the IEEE 802.1Q 12-
bit VLAN identifier of VLAN C.
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 39 Track ID: JATR-1076-21 Rev. 1.1
6.4.11. Port 7 Control 0
Table 60. Port 7 Control 0
Name Byte.bit Description Default
Reserved 99.7~99.6 11
Speed and Duplex
ability
99.5~99.4 In auto negotiation mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=1, 4.6=1, 4.5=1
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=1, 4.5=1
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=1
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
In Force mode:
11=MII Reg0.13=1, 0.8=1, 4.8=1, 4.7=0, 4.6=0, 4.5=0
10=MII Reg0.13=1, 0.8=0, 4.8=0, 4.7=1, 4.6=0, 4.5=0
01=MII Reg0.13=0, 0.8=1, 4.8=0, 4.7=0, 4.6=1, 4.5=0
00=MII Reg0.13=0, 0.8=0, 4.8=0, 4.7=0, 4.6=0, 4.5=1
11
Reserved 99.3 1
Backpressure
enable
99.2 1=Enable port 7 half duplex backpressure.
0=Disable port 7 half duplex backpressure.
1
VLAN tag
insertion and
removal
99.1~99.0 11=Do not insert or remove VLAN tags to/from packet.
10=Insert PVID to non-tagged packets.
01=Remove tag from tagged packets.
00= Replace the VID with a PVID for tagged packets and insert a
PVID to non-tagged packets.
11
6.4.12. Port 7 Control 1
Table 61. Port 7 Control 1
Name Byte.bit Description Default
Reserved 100.7~100.6 11
Local loopback 100.5 1=Perform “local loopback”, i.e. loop back MAC’s RX back to TX.
0=Normal operation.
0
Null VID
replacement
100.4 1=The switch will replace a NULL VID with a port VID (12 bits).
0=No replacement for a NULL VID.
0
Discard Non PVID
packets
100.3 1=If the received packets are tagged, the switch will discard packets
whose VID does not match ingress port’s PVID.
0=No packets will be dropped.
0
Disable 802.1p
priority
100.2 1=Disable 802.1p priority classification for ingress packets on
port 7.
0=Enable 802.1p priority classification.
1
Disable Diffserv
priority
100.1 1=Disable Diffserv priority classification for ingress packets on
port 7.
0=Enable Diffserv priority classification.
1
Disable port-based
priority
100.0 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 7 will be
classified as high priority.
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 40 Track ID: JATR-1076-21 Rev. 1.1
6.4.13. Port 7 Control 2
Table 62. Port 7 Control 2
Name Byte.bit Description Default
Reserved 101.7~
101.4
1111
Good link
quality
threshold
101.3~
101.0
The link quality threshold value of port 0. Link quality higher than this
value will be considered as a link that is operating reliably with a good
signal-to-noise ratio.
1000
6.4.14. Port 7 Control 3
Table 63. Port 7 Control 3
Name Byte.bit Description Default
Reserved 102.7~
102.4
1111
Transmission
enable
102.3 1=Enable packet transmission on port 7.
0=Disable packet transmission on port 7.
1
Reception
enable
102.2 1=Enable packet reception on port 7.
0=Disable packet reception on port 7.
1
Learning enable 102.1 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
Reserved 102.0 1
VLAN Entry [H]
VLAN ID [H]
membership Bit
[7:0]
103.7~
103.0
This register along with byte 104.0 forms a 9-bit field that specifies which
ports are members of the VLAN. If a destination address look up fails,
packets associated with this VLAN will be forwarded to ports specified in
this field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1000
0000
6.4.15. Port 7 Control 4
Table 64. Port 7 Control 4
Name Byte.bit Description Default
Port 7 VLAN
index [3:0]
104.7~
104.4
In a port-based VLAN configuration, this register indexes port 7’s ‘Port
VLAN Membership’, which could be defined in one of the registers
‘VLAN ID [A] Membership’ to “VLAN ID [I] Membership”. Port 7 can
only communicate within the membership. This register also indexes to a
default Port VID (PVID) for each port. The PVID is used in tag insertion
and filtering if the tagged VID is not the same as the PVID.
0111
Reserved 104.3~
104.1
111
VLAN ID [H]
membership Bit
[8]
104.0 This register along with byte 103.7~103.0 forms a 9-bit field that specifies
which ports are members of the VLAN. If a destination address look up
fails, packets associated with this VLAN will be forwarded to ports
specified in this field. E.g. 1 0000 0001 means port 8 and 0 are in this
VLAN.
1
VLAN Entry [H]
VLAN ID [H]
[7:0]
105.7~
105.0
This register along with byte 106.3~106.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN H.
0000
0111
VLAN Entry [H]
Reserved 106.7~
106.4
1111
VLAN ID [H]
[11:8]
106.3~
106.0
This register along with byte 105.7~105.0 defines the IEEE 802.1Q 12-bit
VLAN identifier of VLAN H.
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 41 Track ID: JATR-1076-21 Rev. 1.1
7. PHY Registers Description
“Type” codes used in the following tables: ‘RO’ stands for Read Only; ‘RW’ stands for Read/Write, ‘LL’ stands for Latch
Low until clear; ‘LH’ stands for Latch High until clear, ‘SC’ stands for Self Clearing.
7.1. PHY 0 Registers
7.1.1. PHY 0 Register 0: Control
Table 65. PHY 0 Register 0: Control
Reg.bit Name Mode Description Default
0.15 Reset RW/SC 1=PHY reset. This bit is self-clearing. 0
0.14 Loopback
(digital loopback)
RW 1=Enable loopback. This will loopback TXD to RXD and
ignore all activity on the cable media.
0=Normal operation.
0
0.13 Speed Select RW 1=100Mbps
0=10Mbps
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit is strap option
‘Force_Speed’ and can be configured through SMI.
(Read/Write)
1
0.12 Auto Negotiation
Enable
RW 1=Enable auto-negotiation process.
0=Disable auto-negotiation process.
This bit can be set through SMI (Read/Write).
Pin
En_ANEG
strap option
0.11 Power Down RW 1=Power down. All functions will be disabled except SMI
function.
0=Normal operation.
0
0.10 Isolate RW 1=Electrically isolates the PHY from RMII/SMII.
PHY is still able to respond to MDC/MDIO.
0=Normal operation.
0
0.9 Restart Auto
Negotiation
RW/SC 1=Restart Auto-Negotiation process.
0=Normal operation.
0
0.8 Duplex Mode RW 1=Full duplex operation.
0=Half duplex operation.
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit is strap option
‘Force_Duplex’ and can be configured through SMI.
(Read/Write).
1
0.[7:0] Reserved 0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 42 Track ID: JATR-1076-21 Rev. 1.1
7.1.2. PHY 0 Register 1: Status
Table 66. PHY 0 Register 1: Status
Reg.bit Name Mode Description Default
1.15 100Base_T4 RO 0=No 100Base-T4 capability. 0
1.14 100Base_TX_FD RO 1=100Base-TX full duplex capable.
0=Not 100Base-TX full duplex capable.
1
1.13 100Base_TX_HD RO 1=100Base-TX half duplex capable.
0=Not 100Base-TX half duplex capable.
1
1.12 10Base_T_FD RO 1=10Base-TX full duplex capable.
0=Not 10Base-TX full duplex capable.
1
1.11 10Base_T_HD RO 1=10Base-TX half duplex capable.
0=Not 10Base-TX half duplex capable.
1
1.[10:
7]
Reserved RO 0
1.6 MF Preamble
Suppression
RO The RTL8309SB will accept management frames with
preamble suppressed.
(The RTL8309SB accepts management frames without
preamble. 32 minimum preamble bits are required for the
first SMI read/write transaction after reset. One idle bit is
required between any two management transactions as
defined in the IEEE 802.3u specifications).
1
1.5 Auto-negotiate
Complete
RO 1=Auto-negotiation process completed. MII Reg.4, 5 are
valid if this bit is set.
0=Auto-negotiation process not completed.
0
1.4 Remote Fault RO/LH 1=Remote fault condition detected.
0=No remote fault.
0
1.3 Auto-Negotiation
Ability
RO 1=NWay auto-negotiation capable (permanently =1) 1
1.2 Link Status RO/LL 1=Link is established. If the link fails, this bit will be 0 until
after reading this bit again.
0=Link has failed.
0
1.1 Jabber Detect RO/LH 1=Jabber detect enabled.
0=Jabber detect disabled.
The jabber function is disabled in 100Base-TX operation.
Jabber occurs when a predefined excessively long packet is
detected for 10Base-T. When the duration of TXEN exceeds
the jabber timer (21ms), the transmission and loopback
function are disabled and the COL LED starts blinking.
After TXEN goes low for more than 500 ms, the transmitter
will be re-enabled and the COL LED will stop blinking.
Jabber detect is supported only in 10Base-T operation.
0
1.0 Extended Capability RO 1=Extended register capable. (permanently =1) 1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 43 Track ID: JATR-1076-21 Rev. 1.1
7.1.3. PHY 0 Register 2: PHY Identifier 1
Table 67. PHY 0 Register 2: PHY Identifier 1
Reg.bit Name Mode Description Default
2.[15:
0]
OUI RO Composed of the 3rd to 18th bits of the Organizationally
Unique Identifier (OUI), respectively.
0x001C
7.1.4. PHY 0 Register 3: PHY Identifier 2
Table 68. PHY 0 Register 3: PHY Identifier 2
Reg.bit Name Mode Description Default
3.[15:10] OUI RO Assigned to the 19th through 24th bits of the OUI. 110010
3.[9:4] Model Number RO Manufacturer's model number 08. 001000
3.[3:0] Revision
Number
RO Manufacturer's revision number 01. 0001
7.1.5. PHY 0 Register 4: Auto-Negotiation Advertisement
Note: Any time when the link ability of the RTL8309SB is reconfigured, the auto-negotiation process should be executed again
to allow the configuration to take effect.
Table 69. PHY 0 Register 4: Auto-Negotiation Advertisement
Reg.bit Name Mode Description Default
4.15 Next Page RO 0=Next Page disabled (Permanently =0). 0
4.14 Acknowledge RO Permanently =0. 0
4.13 Remote Fault RW 1=Advertises that the RTL8309SB has detected a remote
fault.
0=No remote fault detected.
0
4.[12:11] Reserved RO 0
4.10 Pause RW 1=Advertises that the RTL8309SB possesses 802.3x flow
control capability.
0=No flow control capability.
Pin
En_FCTRL
strap option
4.9 100Base-T4 RO Technology not supported. (Permanently =0) 0
4.8 100Base-TX-FD RW 1=100Base-TX full duplex capable.
0=Not 100Base-TX full duplex capable.
1
4.7 100Base-TX RW 1=100Base-TX half duplex capable.
0=Not 100Base-TX half duplex capable.
1
4.6 10Base-T-FD RW 1=10Base-TX full duplex capable.
0=Not 10Base-TX full duplex capable.
1
4.5 10Base-T RW 1=10Base-TX half duplex capable.
0=Not 10Base-TX half duplex capable.
1
4.[4:0] Selector Field RO [00001]=IEEE 802.3 00001
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 44 Track ID: JATR-1076-21 Rev. 1.1
7.1.6. PHY 0 Register 5: Auto-Negotiation Link Partner Ability
Table 70. PHY 0 Register 5: Auto-Negotiation Link Partner Ability
Reg.bit Name Mode Description Default
5.15 Next Page RO 1=Link partner desires Next Page transfer.
0=Link partner does not desire Next Page transfer.
0
5.14 Acknowledge RO 1=Link Partner acknowledges reception of Fast Link Pulse
(FLP) words.
0=Not acknowledged by Link Partner.
0
5.13 Remote Fault RO 1=Remote Fault indicated by Link Partner.
0=No remote fault indicated by Link Partner.
0
5.[12:11] Reserved RO 0
5.10 Pause RO 1=Flow control supported by Link Partner.
0= Flow control not supported by Link Partner.
0
5.9 100Base-T4 RO 1=100Base-T4 supported by Link Partner.
0=100Base-T4 not supported by Link Partner.
0
5.8 100Base-TX-FD RO 1=100Base-TX full duplex supported by Link Partner.
0=100Base-TX full duplex not supported by Link Partner.
Note: If auto negotiation is disabled and this bit is set,
Reg0.13 and Reg0.8 will be set to 1 after link is established.
0
5.7 100Base-TX RO 1=100Base-TX half duplex supported by Link Partner.
0=100Base-TX half duplex not supported by Link Partner.
Note: If auto negotiation is disabled and this bit is set,
Reg0.13 will be set to 1 and Reg0.8 will be set to 0 after link
is established.
0
5.6 10Base-T-FD RO 1=10Base-TX full duplex supported by Link Partner.
0=10Base-TX full duplex not supported by Link Partner.
Note: If auto negotiation is disabled and this bit is set,
Reg0.13 will be set to 0 and Reg0.8 will be set to 1 after link
is established.
0
5.5 10Base-T RO 1=10Base-TX half duplex supported by Link Partner.
0=10Base-TX half duplex not supported by Link Partner.
Note: If auto negotiation is disabled and this bit is set,
Reg0.13 and Reg0.8 will be set to 0 after link is established.
0
5.[4:0] Selector Field RO [00001]=IEEE802.3 00001
7.1.7. PHY 0 Register 6: Auto-Negotiation Expansion
Table 71. PHY 0 Register 6: Auto-Negotiation Expansion
Reg.bit Name Mode Description Default
6.[15:5] Reserved RO 0
6.4 Parallel Detection
Fault
RO 1=A fault has been detected via the Parallel Detection
function.
0=A fault has not been detected via the Parallel Detection
function.
0
6.3 Link Partner Next
Page Able
RO 0= Link Partner is not Next Page able (permanently=0). 0
6.2 Local Next Page
Able
RO 1= The RTL8309SB is Next Page able.
0= The RTL8309SB is not Next Page able.
0
6.1 Page Received RO 1= A New Page has been received.
0= A New Page has not been received.
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 45 Track ID: JATR-1076-21 Rev. 1.1
Reg.bit Name Mode Description Default
6.0 Link Partner Auto-
Negotiation Able
RO If NWay is enabled, this bit means:
1= Link Partner is Auto-Negotiation able.
0= Link Partner is not Auto-Negotiation able.
0 (NWay)
or
1 (Force)
7.1.8. PHY 0 Register 16: Global Control 0
Table 72. PHY 0 Register 16: Global Control 0
Reg.bit Name Mode Description Default
16.[15:13] LED Mode R/W 111 -> Mode 7: Speed, Duplex+Collision, Link+Act, SQI
110 -> Mode 6: Activity, Speed, Link, SQI
101 -> Mode 5: Speed, Duplex, Link+Act, SQI
100 -> Mode 4: Collision, Duplex, Link+Act+Speed, SQI
011 -> Mode 3: SQI, Duplex+Collision,
Link+Act+Speed,10/100
010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI
001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act,
SQI
000 -> Mode 0: Duplex+Collision, Bi-color Speed, Bi-color
Link+Act, SQI
111
16.12 Software Reset R/W
S/C
1: Soft reset. This bit is self-clearing.
If this bit is set to 1, the RTL8309SB will reset all registers in
it except PHY registers and will not load configurations from
EEPROM or strapping pins. Software reset is designed to
provide a convenient way for users to change the configuration
via SMI. After changing register values in the RTL8309SB
(except PHY registers) via SMI, the external device must
execute a soft reset in order to update the configuration by
setting this bit to 1.
0
16.11 Disable VLAN R/W 1=Disable VLAN.
0=Enable VLAN. The default VLAN membership
configuration by internal register is port 7 overlapped with all
the other ports, including the MII port, to form 8 individual
VLANs. This default membership configuration may be
modified by setting internal registers via the SMI interface or
EEPROM.
1
16.10 Disable 802.1Q
tag aware VLAN
R/W 1=Disable 802.1Q tagged-VID Aware function. The
RTL8309SB will not check the tagged VID on received frames
to perform tagged-VID VLAN mapping. Under this
configuration, the RTL8309SB only uses the per port VLAN
index register to perform Port-Based VLAN mapping.
0=Enable the Member Set Filtering function of VLAN Ingress
Rule. The RTL8309SB checks the tagged VID on received
frames with the VIDA[11:0]~VIDH[11:0] to index to a
member set, then performs VLAN mapping. The RTL8309SB
uses tagged-VID VLAN mapping for tagged frames but still
uses Port-Based VLAN mapping for priority-tagged and
untagged frames.
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 46 Track ID: JATR-1076-21 Rev. 1.1
Reg.bit Name Mode Description Default
16.9 Disable VLAN
member set
ingress filtering
R/W 1=The switch will not drop the received frame if the ingress
port of this packet is not included in the matched VLAN
member set. It will still forward the packet to the VLAN
members specified in the matched member set. This setting
both works on port-based and tag-based VLAN configurations.
0=The switch will drop the received frame if the ingress port
of this packet is not included in the matched VLAN member
set.
1
16.8 Disable VLAN
tag admit control
R/W 1=The switch accepts all frames it receives whether tagged or
untagged.
0=The switch will only accept tagged frames and will drop
untagged frames.
1
16.7 EEPROM
existence
RO 1=EEPROM does not exist. (pin EnEEPROM=0 or pin
EnEEPROM=1 but EEPROM does not exist)
0=EEPROM exists (pin EnEEPROM=1 and EEPROM exists)
0
16.6 Accept Error
disable
R/W 1=Filter bad packets in normal operation.
0=Switch all packets including bad ones. This bit is intended
for debugging purposes only.
1
16.5 IEEE 802.3x
transmit flow
control enable
R/W 1=Determines when to invoke flow control based on auto-
negotiation results.
0=Will not enable transmit flow control no matter what the
auto-negotiation result is.
1
16.4 IEEE 802.3x
receive flow
control enable
R/W 1=When the RTL8309SB receives a pause control frame, it
has the ability to stop the next transmission of a normal frame
until the timer is expired based on the auto negotiation result.
0=Will not receive flow control no matter what the auto-
negotiation result is.
1
16.3 Broadcast input or
output drop
R/W 1=Broadcast input drop is selected.
0=Broadcast output drop is selected.
1
16.2 Aging enable R/W 1=Enable aging function.
0=Disable aging function. The addresses learned in the lookup
table will not be aged out. If the table is full, the last entry in
the table will be deleted to make room for the new entry.
1
16.1 Fast aging enable R/W 1=Enable fast aging function. The entry learned in the lookup
table will be aged out if it is not updated within an 800µs
period.
0=Disable fast aging function.
0
16.0 Enable ISP MAC
Address
Translation
R/W 1=Enable ISP MAC Address Translation function.
0=Disable ISP MAC Address Translation function
0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 47 Track ID: JATR-1076-21 Rev. 1.1
7.1.9. PHY 0 Register 17: Global Control 1
Table 73. PHY 0 Register 17: Global Control 1
Reg.bit Name Mode Description Default
17.[15:13] 802.1p base
priority
R/W Classifies priority for incoming 802.1Q packets, if 802.1p
priority classification is enabled. “User priority” compared
against this value.
>=: Classify as high priority
<: Classify as low priority
100
17.12 Trunking port
assignment
R/W 1=Combine port 0 and 1 as one trunking port, if trunking is
enabled by strapping pin ‘Dis_Trunk’.
0=Combine port 6 and 7 as one trunking port, if trunking is
enabled by strapping pin ‘Dis_Trunk’.
1
17.[11:10] Queue weight R/W The frame service ratio between the high priority queue and
low priority queue is:
11=16:1
10=always high priority queue first
01=8:1
00=4:1
11
17.9 Disable IP priority
for IP address [A]
R/W 1=Compare both the source and destination IP address of
incoming packets against the value, IP address [A] AND IP
mask [A], to classify packet priority.
0=Do not compare the source or destination IP address of
incoming packets against the value ‘IP address [A] AND IP
mask [A]’.
0
17.8 Disable IP priority
for IP address [B]
R/W 1= Compare both the source and destination IP address of
incoming packet against the value, IP address [B] AND IP
mask [B], to classify packet priority.
0=Do not compare the source or destination IP address of
incoming packets against the value ‘IP address [B] AND IP
mask [B]’
0
17.7 Enable default
high priority
DiffServ code
point
R/W 1=The default DiffServ code point listed below will be
considered as high priority code point if the DiffServ priority
function is enabled.
EF – “101110”
AF – “001010” “010010” “011010” “100010”
Network Control – “111000” “110000”
0=The default DiffServ code point will be considered as low
priority.
1
17.[6:0] Reserved 1111111
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 48 Track ID: JATR-1076-21 Rev. 1.1
7.1.10. PHY 0 Register 18: Global Control 2
Table 74. PHY 0 Register 18: Global Control 2
Reg.bit Name Mode Description Default
18.15 Enable
differential
service code point
[A]
R/W 1=If differential service priority is enabled, this bit specifies
differential service code point [A] is high priority.
0=If differential service priority is enabled, this bit specifies
difference service code point [A] is low priority.
0
18.14 Reserved 1
18.[13:8] Differential
service code point
[A]
R/W Used to specify the high priority differential service code point
A. For example, if these bits are set to “111111”, incoming
packets with a TOS field equal to “111111” will be considered
as high priority packets.
111111
18.7 Enable
differential
service code point
[B]
R/W 1=If differential service priority is enabled, this bit specifies
difference service code point [B] is high priority.
0=If differential service priority is enabled, this bit specifies
difference service code point [B] is low priority.
0
18.6 Reserved 1
18.[5:0] Differential
service code point
[B]
R/W Used to specify a high priority differential service code point
B. For example, if these bits are set to “000000”, incoming
packets with a TOS field equal to “000000” will be considered
as high priority packets.
000000
7.1.11. PHY 0 Register 19: Global Control 3
Table 75. PHY 0 Register 19: Global Control 3
Reg.bit Name Mode Description Default
19.15 Enable drop for
48 pass 1
R/W 1=Enable drop packet after SRAM full for 48 pass 1
0=Disable drop packet after SRAM full for 48 pass 1. This
will result in SRAM run out.
1
19.14 Reserved 1
19.13 TX IPG
compensation
R/W 1=90ppm TX IPG (InterPacketGap) compensation.
0=65ppm TX IPG (InterPacketGap) compensation.
1
19.12 Disable loop
detection
R/W 1=Disable loop detection function.
0=Enable loop detection function.
1
19.11 Reserved 1
19.10 Lookup table
accessible enable
R/W 1=Lookup table is accessible via indirect access registers.
0=Lookup table is not accessible.
0
19.[9:0] Reserved 1111 1111
1
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 49 Track ID: JATR-1076-21 Rev. 1.1
7.1.12. PHY 0 Register 22: Port 0 Control 0
Table 76. PHY 0 Register 22: Port 0 Control 0
Reg.bit Name Mode Description Default
22.[15:14] Reserved R/W 11
22.13 Local loopback R/W 1=Perform “local loopback”, i.e. loop MAC’s RX back to TX.
0=Normal operation.
0
22.12 Null VID
replacement
R/W 1=The switch will replace a NULL VID with a port VID (12
bits).
0=No replacement for a NULL VID.
0
22.11 Discard Non
PVID packets
R/W 1=If the received packets are tagged, the switch will discard
packets whose VID does not match ingress port default VID,
which is indexed by port 0’s “Port based VLAN index”.
0=No packets will be dropped.
0
22.10 Disable 802.1p
priority
R/W 1=Disable 802.1p priority classification for ingress packets on
port 0.
0=Enable 802.1p priority classification.
Pin
Dis_VLAN_Pri
strap option
Default = 1
22.9 Disable Diffserv
priority
R/W 1=Disable Diffserv priority classification for ingress packets
on port 0.
0=Enable Diffserv priority classification.
Pin
Dis_DS_Pri
strap option
Default = 1
22.8 Disable port-
based priority
R/W 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 0
will be classified as high priority.
Pin
Sel_Port_Pri
strap option
Default = 1
22.[7:2] Reserved R/W 1111111
22[1:0] VLAN tag
insertion and
removal
R/W 11=Do not insert or remove VLAN tags to/from packets sent
out from this port.
10=The switch will add VLAN tags to packets, if they are not
tagged when these packets are send out from this port. The
switch will not add tags to packets already tagged. The
inserted tag is the ingress port’s “Default tag”, which is
indexed by port 0’s “Port based VLAN index”.
01=The switch will remove VLAN tags from packets, if they
are tagged when these packets are send out from port 0. The
switch will not modify packets received without tags.
00=The switch will remove VLAN tags from packets then add
new tags to them. The inserted tag is the ingress port’s
“Default tag”, which is indexed by port 0’s “Port based VLAN
index”. This is a replacement processing for tagged packets
and an insertion for untagged packets.
11
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 50 Track ID: JATR-1076-21 Rev. 1.1
7.1.13. PHY 0 Register 23: Port 0 Control 1
Table 77. PHY 0 Register 23: Port 0 Control 1
Reg.bit Name Mode Description Default
23.[15:12] Reserved 1111
23.11 Transmission
enable
R/W 1=Enable packet transmission on port 0.
0=Disable packet transmission on port 0.
1
23.10 Reception enable R/W 1=Enable packet reception on port 0.
0=Disable packet reception on port 0.
1
23.9 Learning enable R/W 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
23.8 Loop status RO 1=A loop has been detected on port 0.
0=No loop exists on port 0.
0
23[7:4] Link quality RO 4-bit field indicating the link quality of the receive twisted-pair
or fiber link.
0000: Highest link quality.
:
:
1111: Lowest link quality.
23[3:0] Good link quality
threshold
R/W The link quality threshold value of port 0. Link quality higher
than this value will be considered as a link that is operating
reliably with a good signal-to-noise ratio.
1000
7.1.14. PHY 0 Register 24: Port 0 Control 2 &VLAN Entry [A]
Table 78. PHY 0 Register 24: Port 0 Control 2 &VLAN Entry [A]
Reg.bit Name Mode Description Default
24[15:12] Port 0 VLAN
index [3:0]
In a port-based VLAN configuration, this register indexes port
0’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 0 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0000
24.[11~9] Reserved 111
24.[8:0] VLAN ID [A]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
A. If a destination address look up fails, the packet associated
with this VLAN will be broadcast to ports specified in this
field. Bit 0 stands for port 0, bit 1 stands for port 8.
E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0000
0001
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 51 Track ID: JATR-1076-21 Rev. 1.1
7.1.15. PHY 0 Register 25: VLAN Entry [A]
Table 79. PHY 0 Register 25: VLAN Entry [A]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25[11:0] VLAN ID [A] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN A. 0000
0000
0000
7.2. PHY 1 Registers
7.2.1. PHY 1 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.2.2. PHY 1 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.2.3. PHY 1 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.2.4. PHY 1 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.2.5. PHY 1 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.2.6. PHY 1 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.2.7. PHY 1 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 52 Track ID: JATR-1076-21 Rev. 1.1
7.2.8. PHY 1 Register 16~17: IP Priority Address [A]
Table 80. PHY 1 Register 16~17: IP Priority Address [A]
Reg.bit Name Mode Description Default
16 IP Address [A]
[31:16]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet, if IP
priority for IP address [A] is enabled.
0xFFFF
17 IP Address [A]
[15:0]
R/W The switch will both compare the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet, if IP
priority for IP address [A] is enabled.
0xFFFF
7.2.9. PHY 1 Register 18~19: IP Priority Address [B]
Table 81. PHY 1 Register 18~19: IP Priority Address [B]
Reg.bit Name Mode Description Default
18 IP Address [B]
[31:16]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
0xFFFF
19 IP Address [B]
[15:0]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
0xFFFF
7.2.10. PHY 1 Register 22: Port 1 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 1. Default value for 22.8 is 1.
7.2.11. PHY 1 Register 23: Port 1 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 53 Track ID: JATR-1076-21 Rev. 1.1
7.2.12. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Table 82. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]
Reg.bit Name Mode Description Default
24[15~12] Port 1 VLAN
index [3:0]
R/W In a port-based VLAN configuration, this register indexes port
1’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 1 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0001
24.[11:9] Reserved 111
24.[8:0] VLAN ID [B]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
B. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0000
0010
7.2.13. PHY 1 Register 25: VLAN Entry [B]
Table 83. PHY 1 Register 25: VLAN Entry [B]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25[11:0] VLAN ID [B] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN B. 0000
0000
0001
7.3. PHY 2 Registers
7.3.1. PHY 2 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.3.2. PHY 2 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.3.3. PHY 2 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 54 Track ID: JATR-1076-21 Rev. 1.1
7.3.4. PHY 2 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.3.5. PHY 2 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.3.6. PHY 2 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.3.7. PHY 2 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
7.3.8. PHY 2 Register 16~17: IP Priority Mask [A]
Table 84. PHY 2 Register 16~17: IP Priority Mask [A]
Reg.bit Name Mode Description Default
16 IP Mask [A]
[31:16]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet, if IP
priority for IP address [A] is enabled.
0xFFFF
17 IP Mask [A]
[15:0]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[A] AND IP mask [A], to classify priority for the packet, if IP
priority for IP address [A] is enabled.
0xFFFF
7.3.9. PHY 2 Register 18~19: IP Priority Mask [B]
Table 85. PHY 2 Register 18~19: IP Priority Mask [B]
Reg.bit Name Mode Description Default
18 IP Mask [B]
[31:16]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
0xFFFF
19 IP Mask [B]
[15:0]
R/W The switch will compare both the source and destination IP
addresses of an incoming packet against the value, IP address
[B] AND IP mask [B], to classify priority for the packet, if IP
priority for IP address [B] is enabled.
0xFFFF
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 55 Track ID: JATR-1076-21 Rev. 1.1
7.3.10. PHY 2 Register 22: Port 2 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is pin Sel_PortPri strap option for port 2. Default value for 22.8 is 1.
7.3.11. PHY 2 Register 23: Port 2 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
7.3.12. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Table 86. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]
Reg.bit Name Mode Description Default
24[15:12] Port 2 VLAN
Index [3:0]
R/W In a port-based VLAN configuration, this register indexes port
2’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 2 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0010
24[11~9] Reserved This bytes are reserved for not used 111
24.[8:0] VLAN ID [C]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
C. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0000
0100
7.3.13. PHY 2 Register 25: VLAN Entry [C]
Table 87. PHY 2 Register 25: VLAN Entry [C]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25[11:0] VLAN ID [C] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN C. 0000
0000
0010
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 56 Track ID: JATR-1076-21 Rev. 1.1
7.4. PHY 3 Registers
7.4.1. PHY 3 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.4.2. PHY 3 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.4.3. PHY 3 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.4.4. PHY 3 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.4.5. PHY 3 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.4.6. PHY 3 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.4.7. PHY 3 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 57 Track ID: JATR-1076-21 Rev. 1.1
7.4.8. PHY 3 Register 16~18: Switch MAC Address
Switch MAC address is used as the source address in MAC pause control frames.
Table 88. PHY 3 Register 16~18: Switch MAC Address
Reg.bit Name Mode Description Default
16 Switch MAC
Address [47:32]
R/W 16.[15:8] = Switch MAC Address Byte 4
16.[7:0] = Switch MAC Address Byte 5
0x5452
17 Switch MAC
Address [31:16]
R/W 17.[15:8] = Switch MAC Address Byte 2
17.[7:0] = Switch MAC Address Byte 3
0x834C
18 Switch MAC
Address [15:0]
R/W 18.[15:8] = Switch MAC Address Byte 0
18.[7:0] = Switch MAC Address Byte 1
0xB009
7.4.9. PHY 3 Register 22: Port 3 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is pin Sel_PortPri strap option for port 3. Default value for 22.8 is 1.
7.4.10. PHY 3 Register 23: Port 3 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
7.4.11. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]
Table 89. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]
Reg.bit Name Mode Description Default
24[15:12] Port 3 VLAN
index [3:0]
R/W In a port-based VLAN configuration, this register indexes
port 3’s ‘Port VLAN Membership’, which could be defined in
one of the registers ‘VLAN ID [A] Membership’ to “VLAN ID
[I] Membership”. Port 3 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0011
24[11~9] Reserved 111
24.[8:0] VLAN ID [D]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
D. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0000
1000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 58 Track ID: JATR-1076-21 Rev. 1.1
7.4.12. PHY 3 Register 25: VLAN Entry [D]
Table 90. PHY 3 Register 25: VLAN Entry [D]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25[11:0] VLAN ID [D] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN D 0000
0000
0011
7.5. PHY 4 Registers
7.5.1. PHY 4 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.5.2. PHY 4 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.5.3. PHY 4 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.5.4. PHY 4 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.5.5. PHY 4 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.5.6. PHY 4 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.5.7. PHY 4 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 59 Track ID: JATR-1076-21 Rev. 1.1
7.5.8. PHY 4 Register 16~18: ISP MAC Address
ISP MAC address is used as the source address in MAC address translation functions.
Table 91. PHY 4 Register 16~18: ISP MAC Address
Reg.bit Name Mode Description Default
16 ISP MAC Address
[15:0]
R/W 16.[15:8] = ISP MAC Address Byte 1
16.[7:0] = ISP MAC Address Byte 0
0xFFFF
17 ISP MAC Address
[31:16]
R/W 17.[15:8] = ISP MAC Address Byte 3
17.[7:0] = ISP MAC Address Byte 2
0xFFFF
18 ISP MAC Address
[47:32]
R/W 18.[15:8] = ISP MAC Address Byte 5
18.[7:0] = ISP MAC Address Byte 4
0xFFFF
7.5.9. PHY 4 Register 22: Port 4 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 4. Default value for 22.8 is 1.
7.5.10. PHY 4 Register 23: Port 4 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
7.5.11. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]
Table 92. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]
Reg.bit Name Mode Description Default
24[15:12] Port 4 VLAN
Index
R/W In a port-based VLAN configuration, this register indexes port
4’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 4 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0100
24.[11~9] Reserved 111
24.[8:0] VLAN ID [E]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
E. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0001
0000
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 60 Track ID: JATR-1076-21 Rev. 1.1
7.5.12. PHY 4 Register 25: VLAN Entry [E]
Table 93. PHY 4 Register 25: VLAN Entry [E]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25.[11:0] VLAN ID [E] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN E. 0000
0000
0100
7.6. PHY 5 Registers
7.6.1. PHY 5 Register 1: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.6.2. PHY 5 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.6.3. PHY 5 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.6.4. PHY 5 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.6.5. PHY 5 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.6.6. PHY 5 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.6.7. PHY 5 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 61 Track ID: JATR-1076-21 Rev. 1.1
7.6.8. PHY 5 Register 16: MII Port Control 0
Table 94. PHY 5 Register 16: MII Port Control 0
Reg.bit Name Mode Description Default
16.15 Transmission
enable
R/W 1=Enable packet transmission on MII interface.
0=Disable packet transmission on MII interface.
1
16.14 Reception enable R/W 1=Enable packet reception on MII interface.
0=Disable packet reception on MII interface.
1
16.13 Learning enable R/W 1=Enable switch address learning capability.
0=Disable switch address learning capability
1
16.12 Enable MII
loopback
R/W 1=Enable local loop back function. The switch will only
forward local and broadcast packets from input of MII RX to
output of MII TX but drop unicast packets from input of MII
RX. The other ports still can forward packets to MII port.
0=Disable local loop back function.
0
16.11 Disable 802.1p
priority
R/W 1=Disable 802.1p priority classification for ingress packets on
port 8.
0=Enable 802.1p priority classification.
Pin
Dis_VLAN_Pri
strap option
Default = 1
16.10 Disable Diffserv
priority
R/W 1=Disable Diffserv priority classification for ingress packets
on port 8.
0=Enable Diffserv priority classification.
Pin
Dis_DS_Pri
strap option
Default = 1
16.9 Disable port-
based priority
R/W 1=Disable port priority function.
0=Enable port priority function. Ingress packets from port 8
will be classified as high priority.
Pin
Sel_Port_Pri
strap option
Default = 1
16.8 Reserved 0
16.[7:2] Reserved 111111
16.[1:0] VLAN tag
insertion and
removal
R/W 11=Do not insert or remove VLAN tags to/from packet when
it is send out from this port.
10=The switch will add VLAN tags to packets, if they are not
tagged when these packets are send out from this port. The
switch will not add tags to packets already tagged. The
inserted tag is the ingress port’s “Default tag”, which is
indexed by MII port’s “Port based VLAN index”.
01=The switch will remove VLAN tags from packets, if they
are tagged when these packets are send out from MII port. The
switch will not modify packets received without tags.
00=The switch will remove VLAN tags from packets then add
new tags to them. The inserted tag is the ingress port’s
“Default tag”, which is indexed by MII port’s “Port based
VLAN index”. This is a replacement processing for tagged
packets and an insertion for untagged packets.
11
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 62 Track ID: JATR-1076-21 Rev. 1.1
7.6.9. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]
Table 95. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]
Reg.bit Name Mode Description Default
17.15 Null VID
replacement
R/W 1=The switch will replace a NULL VID with a port VID (12
bits).
0=No replacement for a NULL VID.
0
17.14 Discard Non
PVID packets
R/W 1=If the received packets are tagged, the switch will discard
packets whose VID does not match ingress port default VID,
which is indexed by MII port’s “Port based VLAN index”.
0=No packets will be dropped.
0
17.13 Reserved 1
17.[12~9] Port 8 VLAN
index [3:0]
In port-based VLAN configuration, this register index to port
8’s “Port VLAN Membership”, which could be defined in
register “VLAN ID [A] Membership” to “VLAN ID [I]
Membership”. Port 8 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID
1000
17.[8:0] VLAN ID [I]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN I.
If a destination address look up fails, packets associated with
this VLAN will be forwarded to ports specified in this field.
E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
1111
1111
7.6.10. PHY 5 Register 18: VLAN Entry [I]
Table 96. PHY 5 Register 18: VLAN Entry [I]
Reg.bit Name Mode Description Default
18.[15:12] Reserved 1111
18.[11:0] VLAN ID [I] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN I. 0000
0001
0000
7.6.11. PHY 5 Register 19: CPU Port & WAN Port
Table 97. PHY 5 Register 19: CPU Port & WAN Port
Reg.bit Name Mode Description Default
19.[15:8] Reserved 0xFF
19.[7:4] WAN Port R/W Specify the WAN port on the RTL8309SB
1111~1000=MII port is WAN port
0111=Port 7 is WAN Port 0110=Port 6 is WAN port
0101=Port 5 is WAN Port 0100=Port 4 is WAN port
0011=Port 3 is WAN Port 0010=Port 2 is WAN port
0001=Port 1 is WAN Port 0000=Port 0 is WAN port
0111
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 63 Track ID: JATR-1076-21 Rev. 1.1
Reg.bit Name Mode Description Default
19.[3:0] CPU Port R/W Specify the CPU port on the RTL8309SB
1111~1000=MII port is CPU port
0111=Port 7 is CPU Port 0110=Port 6 is CPU port
0101=Port 5 is CPU Port 0100=Port 4 is CPU port
0011=Port 3 is CPU Port 0010=Port 2 is CPU port
0001=Port 1 is CPU Port 0000=Port 0 is CPU port
0000
7.6.12. PHY 5 Register 22: Port 5 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 5. Default value for 22.8 is 1.
7.6.13. PHY 5 Register 23: Port 5 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
7.6.14. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]
Table 98. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]
Reg.bit Name Mode Description Default
24.[15:12] Port 5 VLAN
Index [3:0]
R/W In a port-based VLAN configuration, this register indexes port
5’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 5 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0101
24.[11~9] Reserved 111
24.[8:0] VLAN ID [F]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN F.
If a destination address look up fails, packets associated with
this VLAN will be forwarded to ports specified in this field.
E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0010
0000
7.6.15. PHY 5 Register 25: VLAN Entry [F]
Table 99. PHY 5 Register 25: VLAN Entry [F]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25.[11:0] VLAN ID [F] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN F. 0000
0000
0101
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 64 Track ID: JATR-1076-21 Rev. 1.1
7.7. PHY 6 Registers
7.7.1. PHY 6 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.7.2. PHY 6 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.7.3. PHY 6 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.7.4. PHY 6 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.7.5. PHY 6 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.7.6. PHY 6 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.7.7. PHY 6 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
7.7.8. PHY 6 Register 22: Port 6 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 6. Default value for 22.8 is 1.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 65 Track ID: JATR-1076-21 Rev. 1.1
7.7.9. PHY 6 Register 23: Port 6 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
7.7.10. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]
Table 100. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]
Reg.bit Name Mode Description Default
24[15:12] Port 6 VLAN
index [3:0]
R/W In a port-based VLAN configuration, this register indexes
port 6’s ‘Port VLAN Membership’, which could be defined in
one of the registers ‘VLAN ID [A] Membership’ to “VLAN
ID [I] Membership”. Port 6 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0110
24.[11~9] Reserved 111
24.[8:0] VLAN ID [G]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
G. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
0100
0000
7.7.11. PHY 6 Register 25: VLAN Entry [G]
Table 101. PHY 6 Register 25: VLAN Entry [G]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25[11:0] VLAN ID [G] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN G. 0000
0000
0110
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 66 Track ID: JATR-1076-21 Rev. 1.1
7.8. PHY 7 Registers
7.8.1. PHY 7 Register 0: Control
This register has the same definition as PHY 0 Register 0: Control, page 41.
7.8.2. PHY 7 Register 1: Status
This register has the same definition as PHY 0 Register 1: Status, page 42.
7.8.3. PHY 7 Register 2: PHY Identifier 1
This register has the same definition as PHY 0 Register 2: PHY Identifier 1, page 43.
7.8.4. PHY 7 Register 3: PHY Identifier 2
This register has the same definition as PHY 0 Register 3: PHY Identifier 2, page 43.
7.8.5. PHY 7 Register 4: Auto-Negotiation Advertisement
This register has the same definition as PHY 0 Register 4: Auto-Negotiation Advertisement, page 43.
7.8.6. PHY 7 Register 5: Auto-Negotiation Link Partner Ability
This register has the same definition as PHY 0 Register 5: Auto-Negotiation Link Partner Ability, page 44.
7.8.7. PHY 7 Register 6: Auto-Negotiation Expansion
This register has the same definition as PHY 0 Register 6: Auto-Negotiation Expansion, page 44.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 67 Track ID: JATR-1076-21 Rev. 1.1
7.8.8. PHY 7 Register 16: indirect Access Control
PHY 7 register 16 is used for reading or writing data to the MAC address table.
Table 102. PHY 7 Register 16: indirect Access Control
Reg.bit Name Mode Description Default
16[15:2] Reserved 1111
1111
1111
11
16.1 Command
execution
R/W 1=Trigger a command to read or write lookup table
0=Indicate this command is done.
0
16.0 Read or write
operation
R/W 1=Read cycle
0=Write cycle
0
7.8.9. PHY 7 Register 17~20: Indirect Access Data
Table 103. PHY 7 Register 17~20: Indirect Access Data
Reg.bit Name Mode Description Default
17 Indirect Data
[63:48]
R/W Bit 63~48 of indirect data. 0x00
18 Indirect Data
[47:32]
R/W Bit 47~32 of indirect data. 0x00
19 Indirect Data
[31:16]
R/W Bit 31~16 of indirect data. 0x00
20 Indirect Data
[15:0]
R/W Bit 15~0 of indirect data. Bit 9~0 of this register also
determines the address in lookup table of this accessed data.
In write cycle: bit 9~0 indirectly map to an entry in lookup
table for writing. The written data should be filled in Indirect
Data [63:0]
In read cycle: bit 9~0 indirectly map to an entry in lookup
table for reading. The read back data will be shown in Indirect
Data [63:0]
0x00
7.8.10. PHY 7 Register 22: Port 7 Control 0
This register has the same definition as PHY 0 Register 22: Port 0 Control 0, page 49.
Note: Reg 22.8 is not pin Sel_PortPri strap option for port 7. Default value for 22.8 is 1.
7.8.11. PHY 7 Register 23: Port 7 Control 1
This register has the same definition as PHY 0 Register 23: Port 0 Control 1, page 50.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 68 Track ID: JATR-1076-21 Rev. 1.1
7.8.12. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Table 104. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H]
Reg.bit Name Mode Description Default
24[15:12] Port 7 VLAN
index [3:0]
R/W In a port-based VLAN configuration, this register indexes port
7’s ‘Port VLAN Membership’, which could be defined in one
of the registers ‘VLAN ID [A] Membership’ to “VLAN ID [I]
Membership”. Port 7 can only communicate within the
membership. This register also indexes to a default Port VID
(PVID) for each port. The PVID is used in tag insertion and
filtering if the tagged VID is not the same as the PVID.
0111
24.[11~9] Reserved 111
24.[8:0] VLAN ID [H]
Membership Bit
[8:0]
R/W This 9-bit field specifies which ports are members of VLAN
H. If a destination address look up fails, packets associated
with this VLAN will be forwarded to ports specified in this
field. E.g. 1 0000 0001 means port 8 and 0 are in this VLAN.
1
1000
0000
7.8.13. PHY 7 Register 25: VLAN Entry [H]
Table 105. PHY 7 Register 25: VLAN Entry [H]
Reg.bit Name Mode Description Default
25.[15:12] Reserved 1111
25.[11:0] VLAN ID [H] R/W Defines the IEEE 802.1Q 12-bit VLAN identifier of VLAN H. 0000
0000
0111
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 69 Track ID: JATR-1076-21 Rev. 1.1
7.9. PHY 8 Registers
7.9.1. PHY 8 Register 0: Control
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
Table 106. PHY 8 Register 0: Control
Reg.bit Name Mode Description Default
0.15 Reset RO 0=No reset allowed (permanently =0). 0
0.14 Loopback
(digital
loopback)
RO 0=Normal operation (permanently =0). 0
0.13 Speed Select RW 1=100Mbps
0=10Mbps
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit can be set through SMI
(Read/Write).
Pin MII_SPD
_STA strap
option
0.12 Auto
Negotiation
Enable
RW 1=Enable auto-negotiation process.
0=disable auto-negotiation process.
This bit can be set through SMI (Read/Write).
1
0.11 Power Down RO 0=Normal operation (permanently =0). 0
0.10 Isolate RO 0=Normal operation (permanently =0). 0
0.9 Restart Auto
Negotiation
RO 0=Normal operation (permanently =0). 0
0.8 Duplex Mode RW 1=Full duplex operation.
0=Half duplex operation.
When NWay is enabled, this bit reflects the result of auto-
negotiation (Read only).
When NWay is disabled, this bit may be set through SMI
(Read/Write).
Pin MII_DUP
_STA strap
option
0.[7:0] Reserved 0
7.9.2. PHY 8 Register 1: Status
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
Table 107. PHY 8 Register 1: Status
Reg.bit Name Mode Description Default
1.15 100Base_T4 RO 0=No 100Base-T4 capability. 0
1.14 100Base_TX_F
D
RO 1=100Base-TX full duplex capable (permanently =1). 1
1.13 100Base_TX_H
D
RO 1=100Base-TX half duplex capable (permanently =1). 1
1.12 10Base_T_FD RO 1=10Base-TX full duplex capable (permanently =1). 1
1.11 10Base_T_HD RO 1=10Base-TX half duplex capable (permanently =1). 1
1.[10:7] Reserved RO 0
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 70 Track ID: JATR-1076-21 Rev. 1.1
Reg.bit Name Mode Description Default
1.6 MF Preamble
Suppression
RO The RTL8309SB will accept management frames with
preamble suppressed (permanently =1).
1
1.5 Auto-negotiate
Complete
RO 1=Auto-negotiation process completed. MII Reg.4, 5 are valid
if this bit is set (permanently =1).
1
1.4 Remote Fault RO 0=No remote fault (permanently =0). 0
1.3 Auto-
Negotiation
Ability
RO 1=NWay auto-negotiation capable (permanently =1). 1
1.2 Link Status RO 1=Link is established. If link had ever failed, this bit will be 0
until after reading this bit again.
0=Link is failed.
Pin MII_LNK
_STA# strap
option
1.1 Jabber Detect RO 0=No Jabber detected (permanently =0). 0
1.0 Extended
Capability
RO 1=Extended register capable (permanently =1). 1
7.9.3. PHY 8 Register 4: Auto-Negotiation Advertisement
Note: This register only works in MII PHY and SNI PHY mode. In MII MAC mode, these registers have no meaning.
Table 108. PHY 8 Register 4: Auto-Negotiation Advertisement
Reg.bit Name Mode Description Default
4.15 Next Page RO 1=Next Page enabled.
0=Next Page disabled (Permanently =0).
0
4.14 Acknowledge RO Permanently =0. 0
4.13 Remote Fault RO 1=Advertises that the RTL8309S has detected a remote fault.
0=No remote fault detected.
0
4.[12:11] Reserved RO 0
4.10 Pause RW 1=Advertises that the RTL8309SB posses 802.3x flow control
capability.
0=No flow control capability.
Pin
MII_FCTRL
_STA strap
option
4.9 100Base-T4 RO Technology not supported. (Permanently =0) 0
4.8 100Base-TX-
FD
RW 1=100Base-TX full duplex capable.
0=Not 100Base-TX full duplex capable.
1
4.7 100Base-TX RW 1=100Base-TX half duplex capable.
0=Not 100Base-TX half duplex capable.
1
4.6 10Base-T-FD RW 1=10Base-TX full duplex capable.
0=Not 10Base-TX full duplex capable.
1
4.5 10Base-T RW 1=10Base-TX half duplex capable.
0=Not 10Base-TX half duplex capable.
1
4.[4:0] Selector Field RO [00001]=IEEE 802.3 00001
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 71 Track ID: JATR-1076-21 Rev. 1.1
7.9.4. MII Port NWay Mode
Table 109. MII Port NWay Mode
Description
Upon Reset Strapping MII_SPD_STA=1 and MII_DUP_STA=1 Æ Reg0.13=1, Reg0.8=1
Strapping MII_SPD_STA=1 and MII_DUP_STA=0 Æ Reg0.13=1, Reg0.8=0
Strapping MII_SPD_STA=0 and MII_DUP_STA=1 Æ Reg0.13=0, Reg0.8=1
Strapping MII_SPD_STA=0 and MII_DUP_STA=0 Æ Reg0.13=0, Reg0.8=0
Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA
Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down Æ Reg1.2=1
MII_LNK_STA# pulled up Æ Reg1.2=0
After Reset If PHY 8 register 4 is configured as Reg4.8=1, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=1, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=1 and Reg0.8=0.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=1, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=1.
If PHY 8 register 4 is configured as Reg4.8=0, Reg4.7=0, Reg4.6=0, Reg4.5=1, the RTL8309SB
will reflect this configuration in PHY 8 register 0 as Reg0.13=0 and Reg0.8=0.
If the CPU polls register 5, the RTL8309SB replies with the contents in register 4.
If the CPU polls register 4, the RTL8309SB replies with the contents in register 4.
7.9.5. MII Port Force Mode
Table 110. MII Port Force Mode
Description
Upon Reset • Strapping MII_SPD_STA=1 and MII_DUP_STA=1 Æ Reg0.13=1, Reg0.8=1
• Strapping MII_SPD_STA=1 and MII_DUP_STA=0 Æ Reg0.13=1, Reg0.8=0
• Strapping MII_SPD_STA=0 and MII_DUP_STA=1 Æ Reg0.13=0, Reg0.8=1
• Strapping MII_SPD_STA=0 and MII_DUP_STA=0 Æ Reg0.13=0, Reg0.8=0
• Defau1t value of Reg4.10 is strapped from pin MII_FCTRL_STA
• Default value of Reg1.2 is strapped from pin MII_LNK_STA#.
MII_LNK_STA# pulled down Æ Reg1.2=1
MII_LNK_STA# pulled up Æ Reg1.2=0
After Reset The CPU only writes register 0.13 and 0.8 to configure a link status, then reads register 1.2 to
determine whether the link partner can link with this status.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 72 Track ID: JATR-1076-21 Rev. 1.1
8. Functional Description
8.1. Physical Layer Transceiver Functional Overview
8.1.1. Auto Negotiation for UTP
The RTL8309SB obtains the states of duplex, speed, and flow control ability for each port in UTP mode through the auto-
negotiation mechanism defined in the IEEE 802.3u specifications. During auto-negotiation, each port advertises its ability to its
link partner and compares its ability with advertisements received from its link partner. By default, the RTL8309SB advertises
full capabilities (100Full, 100Half, 10Full, 10Half) together with flow control ability.
If the link partner to the RTL8309SB is forced to bypass auto negotiation, or auto negotiation is not supported, the link status
of the RTL8309SB is determined by observing the signal at the receiver.
8.1.2. 100Base-Tx Transmit Function
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ/NRZI conversion,
and MLT3 encoding. The 5-bit serial data stream after 4B/5B coding is then scrambled as defined by the TP-PMD Stream
Cipher function to flatten the power spectrum energy such that EMI effects can be reduced significantly.
The scrambled seed is based on PHY addresses and is unique for each port. After scrambling, the bit stream is driven into the
network media in the form of MLT-3 signaling. The MLT-3 multi-level signaling technology moves the power spectrum
energy from high frequency to low frequency, which also benefits EMI emission.
8.1.3. 100Base-Tx Receive Function
The 100Base-TX receive mechanism includes an adaptive equalizer, DC restoration, MLT3 to NRZI conversion, data and
clock recovery, NRZI to NRZ conversion, de-scrambling, 4B/5B decoding, and serial to parallel conversion. The process starts
with the adaptive equalizer and DC restoration circuits to compensate for the distortion in the MLT-3 signal. This variable
equalizer makes an estimate by comparing the received signal strength against some known cable characteristic, then tunes
itself for optimization. This on-going process allows the RTL8309SB to adjust itself to environmental changes such as
temperature variations. The equalized data then goes through a DC restoration circuit to compensate for the effects of base line
wander in order to improve the dynamic range.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 73 Track ID: JATR-1076-21 Rev. 1.1
After restoration, the MLT-3 to NRZI, NRZI to NRZ converters then converts the analog signal to a digital bit-stream, the
clock recovery circuit extracts the 125MHz clock from the edges of the NRI signal exactly. A De-scrambler, 5B/4B decoder
and serial-to-parallel conversion circuits follow. Finally, the converted parallel data is fed into the MAC.
8.1.4. 10Base-T Transmit Function
The output 10Base-T waveform is Manchester-encoded before it is driven into the network media with a typical 2.3V
amplitude. The internal filter shapes the driven signals to reduce EMI emission, eliminating the need for an external filter. The
harmonic contents are at least 27dB below the fundamental when the RTL8309SB drives an all-ones Manchester-encoded
signal.
8.1.5. 10Base-T Receive Function
The Manchester decoder converts the incoming serial stream to NRZ data when the squelch circuit detects the signal level is
above squelch level.
The squelch circuit eliminates signals with an amplitude lower than 400mV or with short pulse width to prevent the decoder
being abnormally triggered by noise at the differential pairs. When the received signal exceeds the squelch level, the internal
PLL locks the input signal and the RTL8309SB will decode a data frame.
8.1.6. Link Monitor
The 10Base-T link pulse detection circuit continually monitors the RXIP/RXIN pins for the presence of valid link pulses.
Auto-polarity is implemented to correct the detected reverse polarity of RXIP/RXIN signal pairs.
8.1.7. Power Saving Mode
In power saving mode, the power for the MAC and parts of the PHY transceiver are turned off to save power. The
RTL8309SB implements power saving mode on a per port basis. A port automatically enters power saving mode 10 seconds
after the cable is disconnected from it. Once a port enters power saving mode, it transmits normal link pulses only on its
TXOP/TXON pins and continues to monitor the RXIP/RXIN pins to detect incoming signals, which might be the 100Base-TX
MLT-3 idle pattern, 10Base-T link pulses, or Auto-Negotiation’s FLP (Fast Link Pulse). After it detects an incoming signal, it
wakes up from power saving mode and operates in normal mode according to the result of the connection.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 74 Track ID: JATR-1076-21 Rev. 1.1
8.1.8. Power-Down Mode
The RTL8309SB implements power-down mode on a per port basis. Setting MII Reg.0.11 forces the corresponding port of the
RTL8309SB to enter power-down mode. This disables all transmit/receive functions, except SMI (Serial Management
Interface: MDC/MDIO, also known as MII Management Interface).
8.1.9. Auto Crossover Detection
During the link setup phase, the RTL8309SB checks whether it receives active signals on every port in order to determine if a
connection can be established. In cases where the receiver data pin pair is connected to the transmitter data pin pair of the peer
device and vice versa, the RTL8309SB will automatically change its configuration to swap receiver data pins with transmitter
data pins. In other words, the RTL8309SB adapts automatically to a peer device’s configuration. If a port is connected to a PC
or NIC with MDI-X interface with a crossover cable, the RTL8309SB will reconfigure the port to ensure proper connection.
This will effectively replace the DIP switch commonly used for reconfiguring a port on a hub or switch.
By pulling-up EN_AUTOXOVER, the RTL8309SB identifies the type of connected cable and sets the port to MDI or MDIX.
When switching to MDI mode, the RTL8309SB uses TXOP/N as transmit pairs; when switching to MDIX mode, the
RTL8309SB uses RXIP/N as transmit pairs. This function is port-based. Pulling-down EN_AUTOXOVER disables this
function and the RTL8309SB operates in MDI mode, in which TXOP/N represents transmit pairs and RXIP/N represents
receive pairs.
IEEE 802.3 compliant forced mode 100M ports with auto crossover have link issues with NWay (Auto-Negotiation) ports. It is
recommended to not use auto crossover for forced 100M.
8.2. Switch Core Functional Overview
8.2.1. Address Search, Learning, and Aging
When a packet is received, the RTL8309SB uses the least 10 bits of the destination MAC address to index the 1024-entry look-
up table, and at the same time compares the destination MAC address with the contents of the 16-entry CAM. If the indexed
entry is valid or the CAM comparison is matched, the received packet will be forwarded to the corresponding destination port.
Otherwise, the RTL8309SB will broadcast the packet. This is the “Address Search”.
The RTL8309SB then extracts the least 10 bits of the source MAC address to index the 1024-entry look-up table. If the entry is
not already in the table it will record the source MAC address and add switching information. If this is an occupied entry, it
will update the entry with new information. This is called “Learning”. If the indexed location has been occupied by a different
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 75 Track ID: JATR-1076-21 Rev. 1.1
MAC address (hash collision), the new source MAC address will be recorded into the 16-entry CAM. The 16-entry CAM
reduces address hash collisions and improves switching performance.
Address aging is used to keep the contents of the address table correct in a dynamic network topology. The look-up engine will
update the time stamp information of an entry whenever the corresponding source MAC address appears. An entry will be
invalid (aged out) if it’s time stamp information is not refreshed by the address learning process during the aging time period.
The aging time of the RTL8309SB is around 300 seconds.
8.2.2. Flow Control
The RTL8309SB supports standard IEEE 802.3x full duplex flow control ability on both transmit and receive sides. If the
RTL8309SB recognizes that the resources of the destination port of this packet are being used up, it will issue a ‘pause on’
frame to the source port of this packet with a maximum time as defined in IEEE 802.3x. Once the resource is available, the
RTL8309SB sends a ‘pause off’ frame with zero pause time to turn on transmissions.
On the receive side, when the RTL8309SB receives a pause control packet on a port, it stops transmitting any packets to this
port, except flow control packets, for a period of time specified in the received pause control frame. If it receives another pause
control packet in this period of time on the same port, the timer will be updated with the new value specified in the latest pause
control packet. The RTL8309SB will re-start transmitting packets on this port after the timer has expired.
8.2.3. Half Duplex Operation
In half duplex mode, the CSMA/CD media access method is the means by which two or more stations share a common
transmission medium. To transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is
transmitting) and then sends the intended message in bit-serial form. If the message collides with that of another station, then
each transmitting station intentionally transmits for an additional predefined period to ensure propagation of the collision
throughout the system. The station remains silent for a random amount of time (backoff) before attempting to transmit again.
When a transmission attempt has terminated due to a collision, it is retried until it is successful. The scheduling of the
retransmissions is determined by a controlled randomization process called “truncated binary exponential backoff”. At the end
of enforcing a collision (jamming), the switch delays before attempting to retransmit the frame. The delay is an integer
multiple of slotTime (512 bit times). The number of slot times to delay before the nth retransmission attempt is chosen as a
uniformly distributed random integer ‘r’ in the range:
0 ≦ r < 2k
where
k =min (n, backoffLimit). The 802.3 defines the backoffLimit as 10.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 76 Track ID: JATR-1076-21 Rev. 1.1
8.2.4. Back Pressure
The RTL8309SB provides two methods of preventing packet congestion when resources are about to be used up. The first is
by colliding incoming packets when the packets are going to a congested port. The second is by sending preambles to defer
other station’s transmissions.
Back pressure: When the switch is overloaded it will assert a jam pattern to collide incoming packets until the congestion
condition of the destination port is resolved. The 48 pass 1 mechanism prevents the port being partitioned by excessive
collisions. The RTL8309SB will forward one packet successfully after 48 forced collisions. This method carries some risk
since the resource may not be available after 48 forced collisions. If the 48 pass 1 function is turned off, the RTL8309SB will
always collide incoming packets with a jam pattern.
By deferring: The RTL8309SB sends preambles to defer other stations’ transmissions. To avoid jabber and excessive
deference as defined in IEEE 803.3, the RTL8309SB will pull down the carrier sense signal for a certain time then raise it up it
quickly. This short silence time is to prevent other stations seizing the medium and sending packet out. If there are packets to
send out during the carrier sense rising up period, the carrier sense flow control will be replaced by those packets. After the
packets are sent, the carrier sense rises up again, repeating the pattern until the system is available.
8.2.5. UTP Port Status Configuration
The RTL8309SB supports flexible status configuration for each PHY by strapping pins, En_ANEG, En_FCTRL,
Force_Duplex, and Force_Speed on a group basis. These pins are used to assign the initial values to PHY register 0 and 4 upon
reset. The configuration parameters set by these four strapping pins globally control the abilities of each port. For advanced
applications requiring configuration on a per port basis, a serial EEPROM should be attached.
If auto negotiation is enabled by strapping pin ‘En_ANEG’, the link status is determined by the result of the auto negotiation
process. The default configuration of the RTL8309SB is all abilities enabled (the content of the PHY registers will be
Reg0.12=1, Reg4.5=1, Reg4.6=1, Reg4.7=1, Reg4.8=1, and Reg4.10=1). If auto negotiation is disabled by EN_ANEG, the
link speed and duplex mode is forced by strapping pins, Force_Duplex and Force_Speed. These two pins have no effect if auto
negotiation is enabled.
8.2.6. MII Port (The 9th Port)
The RTL8309SB is an 8-port Fast Ethernet switch with one extra MII port for specific applications. It integrates embedded
SRAM for packet storage, nine MAC and eight physical layer transceivers for 10Base-T and 100Base-TX, into a single chip.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 77 Track ID: JATR-1076-21 Rev. 1.1
MII Port Operating Mode
The MII port only provides a MAC part to support the MII interface for connection with an external MAC or PHY. Two
strapping pins, MII_MODE[1:0], are used to configure this interface to act as MII PHY mode, SNI PHY mode SNI, or MII
MAC mode to work with external MAC of routing engine, PHY of HomePNA, or other physical layer transceivers.
If the MII port connects with an external MAC, such as the processor of a router application, it will act as a PHY. This is PHY
mode MII, or PHY mode SNI. In PHY mode MII or PHY mode SNI, the MII port uses the MAC part only, and provides an
external MAC interface to connect MACs of external devices. In order to connect both MACs, the MII of the switch MAC
should be reversed into PHY mode.
If the MII Port connects with an external PHY, such as the PHY of a HomePNA application, it will act as a MAC. This is
MAC mode MII. In MAC mode MII, the MII Port uses its MAC to connect to an external PHY and ignores the internal PHY
part.
The following figures illustrate various utilizations of the ninth port by setting strapping pins. They consist of the following
general system applications:
General standalone 8-port switch applications. HomePNA applications.
Router applications. Other PHY applications.
Mode
Select
10/100
MAC 0
10/100
MAC 1
Switch Fabric, VLAN, QoS, Trunking
10/100
MAC 8
10Based-T or
100Based-TX
PHYceiver
Interface
MAC
mode
10/100
MAC 7
13
/
RTL8309SB
10Based-T or
100Based-TX
PHYceiver
10Based-T or
100Based-TX
PHYceiver
MAC
Router
MAC
ADSL or Cable
Modem
(MII Interface PHY)
13
/
RX+-[0]
TX+-[0]
RX+-[1]
TX+-[1]
RX+-[7]
TX+-[7]
8 LAN
Ports
1 WAN
Interface
Mode
Select
10/100
MAC 0
10/100
MAC 1
Switch Fabric, VLAN, QoS, Trunking
10/100
MAC 8
10Based-T or
100Based-TX
PHYceiver
PHY
mode
Interface
MAC
mode
10/100
MAC 7
/
RTL8309SB
10Based-T or
100Based-TX
PHYceiver
10Based-T or
100Based-TX
PHYceiver
HomePNA or
Other PHYs
RX+-[0]
TX+-[0]
RX+-[1]
TX+-[1]
RX+-[7]
TX+-[7]
8 LAN
Ports
1 WAN
Interface
PHY
mode
13
Router Application HomePNA or Other PHY Application
Figure 3. MII Port Application
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 78 Track ID: JATR-1076-21 Rev. 1.1
MII Interface
In order to act as a PHY when the MII port is in PHY mode, some pins of the external MAC interface should be changed. For
example, TXC are input pins for MAC but output pins for PHY. So the pin MTXC/PRXC is input for MAC mode and output
for PHY mode. Refer to Figure 4, on page 79 to check the relationship between the RTL8309SB and the external device. Hint:
Connect the input of the RTL8309SB to the output of the external device. The RTL8309SB has no RXER, TXER, and CRS
pins for MII signaling. Because the RTL8309SB does not support pin CRS, it is necessary to connect the MTXEN/PRXDV
(output) of PHY mode to both CRS and RXDV (input) of the external device.
MII Port Status Pins
Four signaling pins (MII_LNK_STA#, MII_SPD_STA, MII_DUP_STA, MII_FCTRL_STA) are used to provide operating
status to the MAC of MII port in real time after reset. This means the external MAC or PHY should be forced to the same port
status as the MII port. The MII port automatically detects the link status both from the TXC of the external PHY and
MII_LNK_STA#.
RTL8309SB
VDSL/
HomePNA/
Single PHY
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
MAC mode MII
4
25M/2.5MHz
Floating=High
x
Pull-down=Link On
56 MTXC/PRXC
57 MTXEN/PRXDV
70~67 MRXD[3:0]/PTXD[3:0]
65 MRXC/PTXC
64 MCOL/PCOL
66 MRXDV/PTXEN
61~58 MTXD[3:0]/PRXD[3:0]
102 MII_MODE[0]
101 MII_MODE[1]
51 MII_LNK_STA#
49 MII_SPD_STA
50 MII_DUP_STA
48 MII_FCTRL_STA
Floating=High
Note 1
Note 2
Note 3
4
CPU/
Processor/
Routing Engine
RXC
CRS
RXDV
RXD
TXC
TXEN
TXD
COL
SNI PHY mode
1
1
10MHz
Floating=High
Pull-down
Pull-down=Link On
Note 2
Note 3
RTL8309SB
56 MTXC/PRXC
57 MTXEN/PRXDV
58 MTXD[0]/ PRXD[0]
65 MRXC/PTXC
64 MCOL/PCOL
66 MRXDV/PTXEN
67 MRXD[0]/ PTXD[0]
102 MII_MODE[0]
101 MII_MODE[1]
51 MII_LNK_STA#
49 MII_SPD_STA
50 MII_DUP_STA
48 MII_FCTRL_STA
RTL8309SB
RXC
CRS
RXDV
RXD[3:0]
TXC
TXEN
TXD[3:0]
COL
MII PHY mode
4
4
25M/2.5MHz
Floating=High
Note 1
Note 2
x
Note 3
Pull-down=Link On
56 MTXC/PRXC
57 MTXEN/PRXDV
61~58 MTXD[3:0]/PRXD[3:0]
65 MRXC/PTXC
64 MCOL/PCOL
66 MRXDV/PTXEN
70~67 MRXD[3:0]/PTXD[3:0]
102 MII_MODE[0]
101 MII_MODE[1]
51 MII_LNK_STA#
49 MII_SPD_STA
50 MII_DUP_STA
48 MII_FCTRL_STA
CPU/
Processor/
Routing Engine
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 79 Track ID: JATR-1076-21 Rev. 1.1
Note 1: Pulled high or floating sets the speed to 100Mbps, Pulled down sets the speed to 10Mbps.
Note 2: Pulled high or floating enables full duplex. Pulled down sets half duplex.
Note 3: Pulled high or floating enables flow control or backpressure. Pulled down disables flow control or backpressure.
Figure 4. MII Port Operating Mode Overview
MII PHY Mode/SNI PHY Mode
In routing applications, the RTL8309SB cooperates with a routing engine to communicate with the WAN (Wide Area Network)
through MII/SNI.
In MII PHY mode, pulling MII_SPD_STA up results in the MII port operating at 100Mbps with MTXC, and MRXC runs at
25MHz. Pulling MII_SPD_STA down results in the MII port operating at 10Mbps with MTXC, and MRXC runs at 2.5MHz.
In SNI PHY mode, MII_SPD_STA has no effect and should be pulled down. SNI mode operates at 10Mbps only, with MTXC
and MRXC running at 10MHz. In SNI mode, the RTL8309SB does not loop back a RXDV signal as a response to TXEN and
does not support the heartbeat function (asserting COL signal for each complete TXEN signal). This interface is a bit-wide
data interface used with some controllers to function as a network layer protocol in half duplex operation.
MII MAC Mode
In HomePNA or other PHY applications, the RTL8309SB provides an MII interface to the underlying HomePNA or other
physical devices so as to communicate with other types of LAN media. In such applications, MII_MODE[1:0] should be
pulled high or be floated upon reset.
In HomePNA applications, MII_DUP_STA must be pulled down since HomePNA is half-duplex only. The link speed of the
RTL8309SB is determined by RXC and TXC from the PHY of the HomePNA (running at 1Mbps). Thus, the MII_SPD_STA
has no effect and should be pulled down for compatibility with HomePNA’s PHY. The link state of HomePNA is unstable (a
characteristic of the HomePNA 1.0 standard) such that MII_LNK_STA# must be pulled down instead of being wired to the
LINK LED pin of the HomePNA because of the unstable link state of HomePNA, a characteristic of the HomePNA 1.0
standard.
Because the HomePNA PHY physical layer is half duplex and can only detect a collision event during the AID header interval
(the time when transmitting the Ethernet preamble), the back pressure flow control algorithm is not suitable for a HomePNA
network and MII_FCTRL_STA should be pulled down.
For other PHY applications, the strap status set by MII_SPD_STA, MII_DUP_STA, and MII_FCTRL_STA depends on the
particular application.
MII Port PHY Register
The external MAC automatically polls and accesses the internal PHY registers in the RTL8309SB when the MII port is
operated in MII PHY mode with auto negotiation enabled. For the auto negotiation process in the CPU to function properly,
the RTL8309SB provides PHY register 0, 1, and 4, to virtually provide the MII port’s PHY status to the external MAC.
Because the MII port of the RTL8309SB does not really have a PHY in it, it does not process the auto negotiation. The
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 80 Track ID: JATR-1076-21 Rev. 1.1
contents of PHY registers 4 and 5 should be the same for both terminals of the MII bus when operating on the same link status.
Thus, the RTL8309SB does not provide PHY register 5; it only emulates it. If the CPU polls PHY register 5, the RTL8309SB
returns the contents of PHY register 4 since it cannot execute the auto-negotiation process. If the CPU polls PHY register 4, the
RTL8309SB returns the contents of PHY register 4.
8.3. Advanced Functionality Overview
8.3.1. Port-Based VLAN
If the VLAN function is enabled by pulling down the strapping pin Dis_VLAN, the default VLAN membership configuration
by internal register is port 7 overlapped with all the other ports, including the MII port, to form nine individual VLANs. Via an
attached serial EEPROM or via SMI, the default configuration may be modified for the input ports to join of the nine VLAN
groups: VLAN A, B, C, D, E, F, G, H, and I. These nine VLAN groups provide full flexibility for users to configure the input
ports to associate with different VLAN groups. Each input port can join more than one VLAN group.
Port-based VLAN mapping is the simplest implicit mapping rule. Each incoming frame is assigned to a VLAN based on the
input port into which it arrived at the switch. It is not necessary to parse and inspect frames in real-time to determine their
VLAN mapping. All frames received on a given input port will be forwarded to members of that ports VLAN group. The
RTL8309SB supports nine VLAN indexes to individually index received packets to one of the nine VLAN membership
registers. These nine groups of VLAN membership registers, VLAN ID [A] membership bit [8:0] ~ VLAN ID [I] membership
bit [8:0], determine which ports are members of this VLAN. The RTL8309SB forwards frames to members of this VLAN only
(excluding the input port of this frame). VLAN membership registers descript which port are members in a VLAN member set.
A port that is not specified in this port’s member set should generally not be receiving and/or transmitting frames for that
VLAN.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 81 Track ID: JATR-1076-21 Rev. 1.1
Figure 5 illustrates a typical application. VLAN indexes and VLAN member definitions are set to form three different VLAN
groups.
Figure 5. VLAN Grouping Example
In cases where VLAN and trunking are both enabled at the same time, a situation may occur where a packet is forwarding to a
trunk but one of the members of this trunk is not in the same VLAN group associated with the source port. Under this situation,
the VLAN function has higher priority than the trunking operation. The packet will not be forwarded to the port of this trunk.
For non-VLAN tagged frame, the RTL8309SB performs port-based VLAN. It will use Port n VLAN index [3:0] to index to a
VLAN membership. The VLAN ID associated with this indexed VLAN membership is the Port VID (PVID) of this port.
8.3.2. 802.1Q Tagged-VID based VLAN
802.1Q tagged-VID based VLAN mapping uses a 12-bit explicit identifier in the VLAN tag to associate received packets with
a VLAN. Nine groups of VLAN membership registers, VLAN ID [A] membership [8:0] ~ VLAN ID [I] membership [8:0],
consist of ports that are in the same VLAN corresponding to the registers defined in VLAN ID [A] [11:0] ~ VLAN ID [I]
[11:0]. If the VID of a VLAN-tagged frame does not hit the VLAN ID [A] [11:0] ~ VLAN ID [I] [11:0], then the RTL8309SB
performs port-based VLAN mapping to the member set indexed by Port n VLAN index [3:0]. Otherwise, the RTL8309SB
compares the explicit identifier in the VLAN tag with the nine VLAN registers to determine the VLAN association of this
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 82 Track ID: JATR-1076-21 Rev. 1.1
frame, then forwards it to the member set of this VLAN. Two VIDs are reserved for special purposes. One of them is all ones
and is reserved and currently unused. The other is all zeros and indicates a priority tag, which is treated as an untagged frame.
When 802.1Q tag aware VLAN is enabled, the RTL8309SB performs 802.1Q tag based VLAN mapping for tagged frames, but
performs port-based VLAN mapping for untagged frames. If 802.1Q tag aware VLAN is disabled, the RTL8309SB performs
only port-based VLAN mapping both for non-tagged and tagged frames. Figure 6 illustrates the processing flow when 802.1Q
tag aware VLAN is disabled.
Figure 6. Tagged and Untagged Packet Forwarding When 802.1Q Tag Aware VLAN is Disabled
Two VLAN ingress filtering functions are supported by the RTL8309SB in registers. One is the admit VLAN tagged frame
function, which provides the ability to receive VLAN-tagged frames only. Untagged or priority tagged (VID=0) frames will be
dropped. The other is the ingress member set filtering, which will drop frames if the receive port is not in the member set.
There are also two optional egress filtering functions supported by the RTL8309SB through strapping. One is Leaky VALN,
which enables inter-VLANs unicast packet forwarding. That is, if the layer 2 look-up table search has a hit, then the unicast
packet will be forwarded to the egress port, ignoring the egress rule. The other is ARP VLAN , which will broadcast ARP
packets to all other ports, ignoring the egress rule.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 83 Track ID: JATR-1076-21 Rev. 1.1
8.3.3. QoS Operation
The RTL8309SB can recognize the QoS priority information of incoming packets to give a different egress service priority.
The RTL8309SB identifies the packets as high priority based on several types of QoS priority information:
• Port-based priority
• 802.1p/Q VLAN priority tag
• TCP/IP's TOS/DiffServ (DS) priority field
• IP Address
There are two priority queues, a high-priority queue and a low-priority queue. The queue service rate is based on the Weighted
Round Robin algorithm, the packet-based service weight ratio of the high-priority queue and low-priority queue can be set to
4:1, 8:1, 16:1 or “Always high priority first” by hardware pins upon reset, or internal register via SMI after reset.
Port-Based Priority
When port-based priority is applied, packets received from the high-priority port are sent to the high-priority queue of the
destination port. High priority ports can be partially set by hardware pins, and wholly configured in internal registers.
802.1p-Based Priority
When 802.1p VLAN tag priority applies, the RTL8309SB recognizes the 802.1Q VLAN tag frames and extracts the 3-bit User
Priority information from the VLAN tag. The RTL8309SB sets the threshold of User Priority as 3. Therefore, VLAN tagged
frames with User Priority value = 4~7 will be treated as high priority frames, other User Priority values (0~3) as low priority
frames (follows 802.1p standard). The threshold value can be modified in internal registers via an SMI interface or configured
in EEPROM.
DiffServ-Based Priority
When TCP/IP's TOS/DiffServ(DS) based priority is applied, the RTL8309SB recognizes TCP/IP Differentiated Services
Codepoint (DSCP) priority information from the DS-field defined in RFC2474. The DS field byte for the IPv4 is a Type-of-
Service (TOS) octet and for IPv6 is a Traffic-Class octet. The recommended DiffServ Codepoint is defined in RFC2597 to
classify the traffic into different service classes. The RTL8309SB extracts the codepoint value of DS-fields from IPv4 and IPv6
packets, and identifies the priority of the incoming IP packet following the definition below:
High priority: where the DS-field = (EF, Expected Forwarding:) 101110
(AF, Assured Forwarding:) 001010; 010010; 011010; 100010
(Network Control:) 110000 and 111000
Differential service code point [A] specified in internal register;
Differential service code point [B] specified in internal register;
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 84 Track ID: JATR-1076-21 Rev. 1.1
Low priority: where the DS-field = other values.
The VLAN tagged frame and 6-bit DS-field in the IPv4 and IPv6 frame format are shown below:
Table 111. 802.1Q VLAN Tag Frame Format
6 bytes 6 bytes 2 bytes 3 bits
DA SA 81-00 User-Priority
(0~3:Low-pri ; 4~7: High-pri)
----
Table 112. IPv4 Frame Format
6 bytes 6 bytes 4 bytes 2 bytes 4 bits 4 bits 6 bits
DA SA 802.1Q Tag
(optional)
08-00 Version IPv4=
0100
IHL TOS[0:5]= DS-
field
----
Table 113. IPv6 Frame Format
6 bytes 6 bytes 4 bytes 2 bytes 4 bits 6 bits
DA SA 802.1Q Tag
(optional)
08-00 Version Ipv6=
0110
TOS[0:5]= DS-field ----
Note: IPv6 refer to rcf2460
IP-Based Priority
When IP-based based priority is applied, any incoming packets with IP priority equal to IP address [A] AND IP mask [A] or
IP address [B] AND IP mask [B] will be treated as high priority packet. IP priority [A] and IP priority [B] could be enabled or
disabled independently.
Flow Control Auto Turn Off
The RTL8309SB can be configured to turn off 802.3x flow control and back pressure flow control for 1~2 seconds whenever
the port receives VLAN-tag or TOS/DS high priority frames. Flow control is re-enabled when no priority frame is received for
a 1~2 second duration. The purpose of this function is to avoid head-of-line blocking on priority classification.
8.3.4. Insert/Remove VLAN Priority Tag
The RTL8309SB supports four types of insertion/removal of VLAN tags in packet, controlled by internal registers on a per-
port basis. They are classified as follows:
Type 11: Do not change packets (Default).
Type 10: Insert input port’s PVID for non-tagged packet. Do not packets if they are already tagged
Type 01: Remove VLAN tags from tagged packets. Do not change packets if they are not tagged.
Type 00: Remove VLAN tags from tagged packets then insert the input port’s PVID. For non-tagged packets, insert the input
port’s PVID.
In Type 10, if Null VID replacement is enabled, this function has higher priority than type 10. If both type 10 is selected and
Null VID replacement is enabled, the RTL8309SB inserts a PVID to non-tagged packets and replaces a null VID with a PVID
for tagged packets, and does nothing in tagged packets with a non-null VID.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 85 Track ID: JATR-1076-21 Rev. 1.1
If the tag removed frame is less than 64 bytes, it will be padded with an 0x20 pattern before the packet’s CRC field to fit the
64-byte minimum packet length of the IEEE 802.3 spec. The RTL8309SB will recalculate the FCS (Frame Check Sequence) if
the frame has been changed.
8.3.5. Port VID (PVID)
In a router application, the router may want to know which input port this packet came from. The RTL8309SB supports Port
VID (PVID) for each port to insert a PVID in the VLAN tag on an egress packet. The VID information carried in the VLAN
tag will be changed to a PVID. The RTL8309SB also provide an option to admit VLAN tagged packets with a specific PVID
only. When this function is enabled, packets with an incorrect PVID and non-tagged packets will be dropped.
The RTL8309SB uses an internal register, Port n VLAN index [3:0,] to index to a VLAN membership. The VLAN ID
associated with this indexed VLAN membership is the PVID for this port. Users may select VLAN insert/remove type 10 or 00
to insert a PVID on egress packets.
On 802.1Q tag-based VLANs, do not use a port-based VLAN in PVID applications as the VID information carried in the
VLAN tag will be replaced with a PVID.
8.3.6. Port Trunking
The RTL8309SB can combine two UTP ports as one trunking port (with a balancing mechanism). The default configuration is
to combine port 0 and 1 as one trunk, even if they are operating with different duplex or speed settings. If port 0 and/or port 1
are assigned as a high priority port, this trunk will also be considered as a high priority trunk when the trunking function is
enabled. The RTL8309SB also provides a choice to set port 6 and port 7 as a trunk by configuring a bit, trunking port
assignment, in the internal register.
8.3.7. ISP MAC Address Translation
Some Internet Service Providers only provide service to a single pre-registered MAC address. To share the Internet Service
with more than one station, the RTL8309SB translates the MAC address of multiple NICs by to the ISP registered MAC
address.
Figure 7 illustrates an outbound process. When station G trys to send a packet to the WAN, it broadcasts or unicasts this packet
to the CPU port with a NIC MAC address. After the CPU receives this packet, it translates this MAC address to the ISP
registered MAC address and stores this information in its mapping table. It then forwards this packet to the WAN port through
the CPU port. The RTL8309SB will not learn this packet into it’s forwarding table. This is a special learning mechanism,
which states that any frame coming from the CPU port with a source MAC address equal to internal register, ISP MAC [47:0],
will not be learned. This function must be correctly configured in the VLAN configuration, otherwise the RTL8309SB will
drop such packets.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 86 Track ID: JATR-1076-21 Rev. 1.1
RTL8309SB
P1
WAN
ISP
Server
CPU
Port
Router CPU
w/ 1 EMAC
WAN
MAC
ISP
MAC Data
Special learning
WAN
Port
P7
PC F
P6
PC E
P5
PC D
P4
PC C
P3
PC B
P2
PC A
P8
PC G
VLAN 2
VLAN 1
MII I/F
CPU
MAC
PC E
MAC Data
Figure 7. ISP MAC Outbound Process
In the inbound process, when the RTL8309SB receives a packet from the WAN port, it will be directly forwarded to the CPU
port according to the VLAN 1 configuration. The CPU looks up the mapping table to reverse translate the destination MAC
address from the ISP MAC to the MAC address of the station G NIC. Figure 8 illustrates this inbound process.
RTL8309SB
P1
WAN
ISP
Server
CPU
Port
Router CPU
w/ 1 EMAC
WAN
MAC
ISP
MAC
Data
Special forwarding
WAN
Port
P7
PC F
P6
PC E
P5
PC D
P4
PC C
P3
PC B
P2
PC A
P8
PC E
VLAN 2
VLAN 1
MII I/F
CPU
MAC
PC E
MAC
Data
Figure 8. ISP MAC Inbound Process
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 87 Track ID: JATR-1076-21 Rev. 1.1
8.3.8. Lookup Table Access
The RTL8309SB supports registers for the CPU to read/write to an internal 1024-entry lookup table via the SMI interface.
Before reading/writing from/to the internal forwarding table, the content in internal register Indirect Access Control [15:0]
should be filled correctly.
In write access, the user must assign the write data in register Indirect Access Data [63:0] first. Bit 9~0 of this register will
indirectly map to an entry in the lookup table for writing. To execute write access, bit 0 in the Indirect Access Control register
should be set to 0, and bit 1 should be set to 1. The CPU will poll bit 1 in Indirect Access Control to determine whether the
write access is complete on not.
In read access, the user only has to enter the read address of the lookup table in bit 9~0 of the register Indirect Access Data
[63:0]. To execute read access, bit 0 in the Indirect Access Control register should be set to 1, and bit 1 should be set to 1 to
trigger this command. The CPU will poll bit 1 in Indirect Access Control to determine whether read access is complete on not.
8.3.9. Serial Management Interface (SMI)
SMI is also known as the MII Management Interface. It consists of two signals (MDIO and MDC) that allow an external
device in SMI master mode (MDC is output) to control the state of PHY, and in SMI slave mode (MDC is input) to control the
internal register. MDC is an input clock for the RTL8309SB to latch MDIO on its rising edge. The clock can run from 0MHz
to 25MHz. MDIO is a bi-directional signal that is used to write data to, or read data from, the RTL8309SB. Table 114 shows
the read and write cycle format of the RTL8309SB.
Table 114. SMI Read/Write Cycles
Preamble
(32 bits)
Start
(2 bits)
OP Code
(2 bits)
PHYAD
(5 bits)
REGAD
(5 bits)
Turn Around
(2 bits)
Data
(16 bits)
Idle
Read 1……..1 01 10 A4A3A2A1A0 R4R3R2R1R0 Z0 D15…….D0Z*
Write 1……..1 01 01 A4A3A2A1A0 R
4R3R2R1R0 10 D15…….D0Z*
*Z: high-impedance. During idle time, an external 1.5KΩ pull-up resistor determines MDIO state.
The RTL8309B supports Preamble Suppression, which allows the MAC to issue Read/Write Cycles without preamble bits.
However, for the first cycle of MII management after power-on reset, a 32-bit preamble is needed.
To guarantee the first successful SMI transaction after power-on reset, an external device should delay at least 1 second before
issuing the first SMI Read/Write Cycle relative to the rising edge of reset. The output voltage level of the RTL8309SB is
configurable by supplying different voltages to pin VDDIO. VDDIO can be supplied with either a 2.5V or 3.3V power supply.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 88 Track ID: JATR-1076-21 Rev. 1.1
8.3.10. Broadcast Storm Control
After 64 consecutive broadcast packets (DID=FFFF-FFFF-FFFF) are received by a particular port, the following incoming
broadcast packets will be discarded by this port for approximately 800ms. Any non-broadcast packet can reset the time
window and broadcast counter such that the scheme restarts.
Note: Trigger condition: consecutive 64 DID = FFFF-FFFF-FFFF packets. Release condition: receive non-broadcast packet
on or after 800ms.
8.3.11. Broadcast In/Out Drop
If some destination ports are blocking and the buffer is full, broadcast frames are dropped according to the internal
configuration. There are two options:
Broadcast input drop, which will not forward any broadcast packet to any output port and will drop packets at the source port
directly. Although this function effectively reduces the loading on the RTL8309SB, packets broadcast to non-congested ports
will also be dropped.
Broadcast output drop, which only forwards broadcast packets to non-congested ports. But if a dropped packet is re-transmitted
by a higher protocol in the congested port, the non-congested port will receive duplicate packets. Figure 9 illustrates this
concept.
1. Input Drop: Do not forward to any port and drop the frame directly
2. Output Drop: Forward only to non-blocking ports (Broadcast becomes multicast)
Port 0 1 2 3 4 5 6 7
Rx:
Input Drop:
1. Broadcast packet from Port 0
2. Buffer of Port 7 is full, others are not full
Full
Port 0 1 2 3 4 5 6 7
Rx:
Output Drop:
Full
Figure 9. Input Drop vs. Output Drop
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 89 Track ID: JATR-1076-21 Rev. 1.1
8.3.12. EEPROM Configuration Interface
The EEPROM interface is a 2-wire serial EEPROM interface providing 2K bits storage space. The external device connected
to the RTL8309SB should be 2.5V or 3.3V depending on the VDDIO setting.
8.3.13. 24LC02 Device Operation
Clock and Data transitions: The SDA pin is normally pulled high with an external resistor. Data on the SDA pin may change
only during SCL low time periods. Data changes during SCL high periods will indicate a start or stop condition as defined
below.
Start condition: A high-to-low transition of SDA with SCL high is the start condition and must precede any other command.
Stop condition: A low-to-high transition of SDA with SCL high is a stop condition.
Acknowledge: All addresses and data are transmitted serially to and from the EEPROM in 8-bit words. The 24LC02 sends a
zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
Random Read: A random read requires a “dummy” byte write sequence to load in the data word address.
Sequential Read: For the RTL8309SB, the sequential reads are initiated by a random address read. After the 24LC02 receives
a data word, it responds with an acknowledgement. As long as the 24LC02 receives an acknowledgement, it will continue to
increment the data word address and clock out sequential data words in series.
Figure 10. Start and Stop Definition
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 90 Track ID: JATR-1076-21 Rev. 1.1
Figure 11. Output Acknowledge
Figure 12. Random Read
Figure 13. Sequential Read
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 91 Track ID: JATR-1076-21 Rev. 1.1
8.3.14. Head-of-Line Blocking
The RTL8309SB incorporates an advanced mechanism to prevent Head-Of-Line blocking problems when flow control is
disabled. When the flow control function is disabled, the RTL8309SB first checks the destination address of the incoming
packet. If the destined port is congested, the RTL8309SB will discard this packet to avoid blocking the next packet, which is
going to a non-congested port.
8.3.15. MII Port Diagnostic Loopback
The RTL8309SB provides a MAC loopback function on the MII port to detect cable problems or far end existence. When this
function is enabled, the RTL8309SB will forward local and broadcast packets from the input of the MII port to the output of
the MII port, and drop unicast packets from the input of the MII port. The other port still can forward broadcast or unicast
packets to the MII port. This is especially useful for router application mass production tests.
8309SB CPU
MII
Example1: LoopBack in external MAC mode
CPU
UTP
Example2: LoopBack in UTP mode
8139 PCI8309SB
Figure 14. MII Port Loopback
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 92 Track ID: JATR-1076-21 Rev. 1.1
8.3.16. Loop Detection
Loops should be avoided between switch applications. The simplest loop as shown below results in: 1) Unicast frame
duplication; 2) Broadcast frame multiplication; 3) Address table nonconvergence. Frames may be transmitted from Switch1 to
Switch2 via Link1, then returned to Switch1 via Link2.
Switch 1
Switch 2
Link2
Link1
Figure 15. Loop Example
When the loop detection function is enabled, the RTL8309SB periodically sends out a broadcast 64-byte packet every 3~5
minutes and automatically detects whether if there is a network loop (or bridge loop). If a loop is detected the LoopLED# will
be ON (active low or high). The LED goes out when both RTL8309SB ports of the loop are unplugged. The Loop frame length
is 64 bytes and its format is shown below.
Table 115. Loop Frame Format
FFFF FFFF FFFF SID 8899 0300 000…0000 CRC
In order to achieve loop detection, each switch device needs a unique SID (the source MAC address). If the EEPROM is not
used, a unique SID should be assigned via SMI after reset, and the default SID (0x52 54 4c83 09 b0) should not be used.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 93 Track ID: JATR-1076-21 Rev. 1.1
8.3.17. LEDs
The RTL8309SB supports four parallel LEDs for each port, and one special LED (LOOPLED#). Each port has four LED
indicator pins. Each pin may have different indicator meanings set by pins LED_MODE[2:0]. Refer to the pin descriptions for
details (see Port LED Pins, on page 9). Upon reset, the RTL8309SB supports chip diagnostics and LED functions by blinking
all LEDs once for 320ms. This function can be disabled by asserting EN_RST_BLNK to 0. LED_BLNK_TIME determines the
LED blinking period for activity and collision (1 = 43ms and 0 = 120ms).
All LED pins are dual function pins: input operation for configuration upon reset, and output operation for LED after reset. If
the pin input is floating upon reset, the pin output is active low after reset. Otherwise, if the pin input is pulled down upon reset,
the pin output is active high after reset. Below is an example circuit for LEDs. The typical values for pull-down resistors are
10KΩ.
RTL8309SB
1.8V
LED Pin
Floating
RTL8309SB
LED Pin
Pull-down
10K
ohm
Figure 16. Floating and Pull-down of LED Pins
For two pins Bi-color LED mode, Bi-color Link/Act and Speed can be used for one Bi-color LED package, which is a single
LED package with two LEDs connected in parallel with opposite polarity. As all LED pins are dual function pins, strapping
LED pins to high or low will affect their active status. In bi-color LED mode, the Link/Act and Speed LED pins may both be
strapped to high or low but their active status will be opposed.
Note: For bi-color LED, the 1.8V supply voltage may not be sufficient to turn the LED on. The application schematic in Figure
19, on page 95, illustrates how to directly utilize 7.5 ~ 12V from the DC adapter as the power source for bi-color LED.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 94 Track ID: JATR-1076-21 Rev. 1.1
Table 116. Speed and Bi-color Link/Act Truth Table
Speed:Input=Floating, Active Low.
Bi-color Link/Act: the active status of
LED_ADD is the opposite of LED_SPD
and does not interact with input upon
reset.
Speed:Input=Pull-down, Active High.
Bi-color Link/Act: the active status of
LED_ADD is the opposite of LED_SPD
and does not interact with input upon
reset.
Indication Bi-Color State Speed Link/Act Speed Link/Act
No Link Both Off 1 1 0 0
100M Link Green On 0 1 1 0
10M Link Yellow On 1 0 0 1
100M Act Green Flash 0 Flash 1 Flash
10M Act Yellow Flash 1 Flash 0 Flash
Yellow
Green
Speed
LED
Link/Act
LED
Figure 17. Two Pin Bi-color LED for SPD Floating or Pull-high
Yellow
Green
Speed
LED
Link/Act
LED
Figure 18. Two Pin Bi-color LED for SPD Pull-down
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 95 Track ID: JATR-1076-21 Rev. 1.1
BJTBJT
0.5K
Bi-color LED
0.5K
7.5 ~12V
Speed
LED
Link/Act
LED
Strapping Low
BJTBJT
0.5K
Bi-color LED
0.5K
7.5 ~12V
Speed
LED
Link/Act
LED
Strapping High
50
Figure 19. Bi-color LED Reference Schematic
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 96 Track ID: JATR-1076-21 Rev. 1.1
9. Characteristics
9.1. Absolute Maximum Ratings
WA RN IN G: Absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device
reliability may be affected. All voltages are specified reference to GND unless otherwise specified.
Table 117. Absolute Maximum Ratings
Parameter Min Max Units
Storage Temperature -55 +150 °C
Supply Voltage Referenced to GND: VDDD,
VDDA, and 1.8V VDDIO
GND-0.5 +2.16 V
Supply Voltage Referenced to GND: 2.5V VDDIO GND-0.5 +3.00 V
Supply Voltage Referenced to GND: 3.3V VDDIO GND-0.5 +3.96 V
Digital Input Voltage GND-0.5 VDDD V
DC Output Voltage GND-0.5 VDDD V
9.2. Operating Range
Table 118. Operating Range
Parameter Min Max Units
Ambient Operating Temperature (Ta) 0 +70 °C
1.8V VDDD, VDDA, and VDDIO Supply Voltage
Range
1.71 1.89 V
2.5V VDDIO Supply Voltage Range 2.375 2.625 V
3.3V VDDIO Supply Voltage Range 3.15 3.45 V
9.3. DC Characteristics
Table 119. DC Characteristics
Parameter SYM Condition Min Typical Max Units
Power Supply Current
for 1.8V
Icc 10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100%
utilization
Power saving
Power down
117.4
928.2
718.3
721.6
115.9
140.9
130.5
943.1
743.4
743.8
126.8
134.9
143.6
958.0
765.2
769.3
137.7
146.9
mA
Total Power
Consumption for all
ports
PS 10 Base-T, idle
10 Base-T, Peak continuous 100% utilization
100 Base-TX, idle
100 Base-TX, Peak continuous 100%
utilization
Power saving
Power down
198.4
1584.6
1223.6
1230.0
196.1
253.6
234.9
1697.6
1338.1
1338.8
228.2
242.8
271.4
1810.6
1446.2
1454.0
260.3
264.4
mW
TTL Input High Voltage Vih
VDDIO = 1.8V
VDDIO = 3.3V
1.5
2.0
-
-
-
-
V
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 97 Track ID: JATR-1076-21 Rev. 1.1
Parameter SYM Condition Min Typical Max Units
TTL Input Low Voltage Vil VDDIO = 1.8V
VDDIO = 3.3V
-
-
-
-
0.8
0.8
V
TTL Input Current Iin -10 - 10 uA
TTL Input Capacitance Cin - 3 - pF
Output High Voltage Voh VDDIO = 1.8V
VDDIO = 3.3V
1.7
2.6
-
-
-
3.6
V
Output Low voltage Vol VDDIO = 1.8V
VDDIO = 3.3V
0.0
0.0
-
-
0.4
0.4
V
Output Three State
Leakage Current |IOZ| - - 10 uA
Transmitter, 100Base-TX (1:1 Transformer Ratio)
TX+/- Output Current
High IOH - - 40 mA
TX+/- Output Current
Low IOL 0 - - uA
Transmitter, 10Base-T (1:1 Transformer Ratio)
TX+/- Output Current
High IOH - - 100 mA
TX+/- Output Current
Low IOL 0 - - uA
Receiver, 100Base-TX
RX+/- Common-mode
input voltage
- 1.8 - V
RX+/- Differential input
resistance
- 2.4 - kΩ
Receiver, 10Base-T
Differential Input
Resistance
- 2.4 - kΩ
9.4. AC Characteristics
Table 120. AC Characteristics
Parameter SYM Condition Min Typical Max Units
Transmitter, 100Base-TX
Differential Output
Voltage, peak-to-peak
VOD 50Ω from each output to Vcc, Best-fit over 14
bit times
0.997 1.002 1.008 V
Differential Output
Voltage Symmetry
VOS 50Ω from each output to Vcc, |Vp+|/ |Vp-| 100.8 101.3 101.9 %
Differential Output
Overshoot VOO Percent of Vp+ or Vp- 3.20 3.68 4.31 %
Rise/Fall time tr ,tf 10-90% of Vp+ or Vp- 3.61 3.73 3.82 ns
Rise/Fall time imbalance |tr - tf| 10 30 80 ps
Duty Cycle Distortion Deviation from best-fit time-grid, 010101 …
Sequence
20 40 90 ps
Timing jitter Idle pattern 675 825 900 ns
Transmitter, 10Base-T
Differential Output
Voltage, peak-to-peak
VOD 50Ω from each output to Vcc, all pattern 2.30 2.31 2.32 V
TP_IDL Silence
Duration
Period of time from start of TP_IDL to link
pulses or period of time between link pulses
15.72 15.73 15.76 ms
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 98 Track ID: JATR-1076-21 Rev. 1.1
Parameter SYM Condition Min Typical Max Units
TD Short Circuit Fault
Tolerance
Peak output current on TD short circuit for 10
seconds.
245 254 273 mA
TD Differential Output
Impedance (return loss)
Return loss from 5MHz to 10MHz for
reference resistance of 100 Ω.
24.0 24.5 25.0 dB
TD Common-Mode
Output Voltage
Ecm Terminate each end with 50Ω resistive load. 40.2 44.3 45.1 mV
Transmitter Output Jitter 6.4 8.5 11.5 ns
RD Differential Output
Impedance (return loss)
Return loss from 5MHz to 10MHz for
reference resistance of 100 Ω.
24.0 24.5 25.0 dB
Harmonic Content dB below fundamental, 20 cycles of all ones
data
28.0 28.3 28.5 dB
9.5. Digital Timing Characteristics
Th
Ts
MRXC/PTXC,
MDC
MRXD/PTXD[3: 0],
MRXDV/PTXEN,
MCOL,
MDIO
Figure 20. Reception Data Timing of MII/SNI/SMI Interface
Tcyc Tos Toh
MRXC/PTXC,
MDC
MRXD/PTXD[3: 0],
MRXDV/PTXEN,
MCOL,
MDIO
Figure 21. Transmission Data Timing of MII/SNI/SMI Interface
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 99 Track ID: JATR-1076-21 Rev. 1.1
Table 121. Digital Timing Characteristics
Parameter SYM Condition I/O Min Type Max Units
MAC Mode MII Timing
100BaseT
MTXC/MRXC,
MRXC/PTXC
Tcyc MTXC/MRXC, MRXC/PTXC clock cycle
time
I 40±50
ppm
ns
10BaseT MTXC/MRXC,
MRXC/PTXC
Tcyc MTXC/MRXC, MRXC/PTXC clock cycle
time
I 400±50
ppm
ns
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Setup time
Tos Output Setup time from REFCLK rising edge
to MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV
O 22 24 26 ns
MTXD[3:0]/PRXD[3:0],
MTXEN/PRXDV Output
Hold time
Toh Output Hold time from REFCLK rising edge
to MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV
O 14 16 18 ns
MRXD[3:0]/PTXD[3:0],
MRXDV/PTXEN,
MCOL/PCOL Setup time
Ts MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge setup time
I 4 ns
MRXD/PTXD,
MRXDV/PTXEN,
MCOL/PCOL Hold time
Th MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge hold time
I 2 ns
Parameter SYM Condition I/O Min Type Max Units
PHY Mode MII Timing
100BaseT
MTXC/MRXC,
MRXC/PTXC,
Tcyc MTXC/MRXC, MRXC/PTXC, PHY2PTXC,
PHY2PRXC clock cycle time
O 40±50
ppm
ns
10BaseT
MTXC/PRXC,
MRXC/PTXC,
Tcyc MTXC/MRXC, MRXC/PTXC, PHY2PTXC,
PHY2PRXC clock cycle time
O 400±50
ppm
ns
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output
Setup time
Tos Output Setup time from REFCLK rising edge
to MTXD[3:0]/PRXD[3:0], PHY2PRXD[3:0],
MTXEN/PRXDV, PHY2PRXDV
MCOL/PCOL, PHY2PCOL
O 14 16 18 ns
MTXD/PRXD[3:0],
MTXEN/PRXDV,
MCOL/PCOL, Output
Hold time
Toh Output Hold time from REFCLK rising edge
to MTXD[3:0]/PRXD[3:0], MTXEN/PRXDV,
MCOL/PCOL
O 22 24 26 ns
MRXD/PTXD[3:0],
MRXDV/PTXEN, Setup
time
Ts MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge setup time
I 4 ns
MRXD/PTXD[3:0],
MRXDV/PTXEN, Hold
time
Th MTXD[3:0]/PRXD[3:0], MRXDV/PTXEN to
REFCLK rising edge hold time
I 2 ns
PHY Mode SNI Timing
MTXC/MRXC,
MRXC/PTXC
Tcyc MTXC/PRXC, MRXC/PTXC clock cycle time O 100±50
ppm
ns
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output
Setup time
Tos Output Setup time from REFCLK rising edge
to MTXD[0]/PRXD[0], MTXEN/PRXDV,
MCOL/PCOL
O 28 30 32 ns
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Output
Hold time
Toh Output Hold time from REFCLK rising edge
to MTXD[0]/PRXD[0], MTXEN/PRXDV,
MCOL/PCOL
O 68 70 72 ns
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 100 Track ID: JATR-1076-21 Rev. 1.1
Parameter SYM Condition I/O Min Type Max Units
MRXD/PTXD[0],
MRXDV/PTXEN Setup
time
Ts MTXD[0]/PRXD[0], MRXDV/PTXEN to
REFCLK rising edge setup time
I 4 ns
MTXD/PRXD[0],
MTXEN/PRXDV,
MCOL/PCOL Hold time
Th MTXD[0]/PRXD[0], MRXDV/PTXEN to
REFCLK rising edge hold time
I 2 ns
LED Timing
LED On Time tLEDon While LED blinking O 43 - 120 ms
LED Off Time tLEDoff While LED blinking O 43 - 120 ms
9.6. Thermal Characteristics
Heat generated by the chip causes a temperature rise of the package. If the temperature of the chip (Tj, junction temperature) is
beyond the design limits, there will be negative effects on operation and the life of the IC package. Heat dissipation, either
through a heat sink or electrical fan, is necessary to provide a reasonable environment (Ta, ambient temperature) in a closed
case. As power density increases, thermal management becomes more critical. A method to estimate the possible Ta is outlined
below.
Thermal parameters are defined as below according to JEDEC standard JESD 51-2, 51-6:
1. θja (Thermal resistance from junction to ambient), represents resistance to heat flow from the chip to ambient air. This is
an index of heat dissipation capability. A lower θja means better thermal performance.
θja = (Tj - Ta) / Ph
Where Tj is the junction temperature
Ta is the ambient temperature
Ph is the power dissipation
2. θjc (Thermal resistance from junction to case), represents resistance to heat flow from the chip to the package top case. θjc
is important when an external heat sink is attached on the package top.
θjc = (Tj - Tc) / Ph, where Tj is the junction temperature
Figure 22. Cross-section of 128 PQFP
Table 122. Thermal Operating Range
Parameter SYM Condition Min Typical Max Units
Junction operating
temperature
Tj 0 25 125 °C
Ambient operating
temperature
Ta 0 25 58.9 °C
Ta Tc
Tj
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 101 Track ID: JATR-1076-21 Rev. 1.1
Table 123. Thermal Resistance
Parameter SYM Condition Min Typical Max Units
Thermal resistance:
junction to ambient θja 2 layer PCB, 0 ft/s airflow, ambient
temperature 25°C
- 36.7 - °C/W
Thermal resistance:
junction to case θjc 2 layer PCB, 0 ft/s airflow, ambient
temperature 25°C
- 16.7 - °C/W
* PCB conditions (JEDEC JESD51-7). Dimensions: 85 x 11mm. Thickness: 1.6mm
10. System Applications
Broadband gateway/firewall/VPN
Wireless LAN access point + gateway
Home networking expansion
Standalone 10/100 switch
Small workgroup switch
VoIP infrastructure switch
11. Design and Layout Guide
In order to achieve maximum performance using the RTL8309SB, good design attention is required throughout the design and
layout process. The following are some recommendations on how to implement a high performance system.
General Guidelines
• Provide a good power source, minimizing noise from switching power supply circuits (<50mV).
• Keep power and ground noise levels below 50mV.
• Verify the ability of critical components, e.g. clock source and transformer, to meet application requirements.
• Use bulk capacitors (4.7µF-10µF) between the power and ground planes.
• Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes.
• Keep de-coupling capacitors as close as possible to the RTL8309SB.
Differential Signal Layout Guidelines
• Keep differential pairs as close as possible and route both traces as identically as possible.
• Avoid vias and layer changes if possible.
• Keep transmit and receive pairs away from each other. Run orthogonal or separate by a ground plane.
• Keep each different pair on the same plane.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 102 Track ID: JATR-1076-21 Rev. 1.1
Clock Circuit
• The clock should be 25M 100ppm with jitter less than 0.5ns.
• Surround the clock by ground trace to minimize the high-frequency emission, if possible.
Power Planes
• Divide the power plane into 1.8V digital, 1.8V analog.
• Use 0.1uF decoupling capacitors and bulk capacitors between each power plane and ground plane.
• Place two 47uF bulk capacitor on device-side (primary) center tap of transformer.
Ground Plane
• Keep the system ground region as one continuous, unbroken plane that extends from the primary side of the transformer
to the rest of the board.
• Place a moat (gap) between the system ground and chassis ground.
• Ensure the chassis ground area is voided at some point such that no ground loop exists on the chassis ground area.
Transformer Options
The RTL8309SB can use a transformer that supports AutoMDIX with a 1:1 turn ratio on both transmit and receive paths.
There are many venders improving their transformer design to meet the RTL8309SB’s requirement.
Vendo r Quad
Pulse H1164
Magnetic 1 ML164
BothHand 40ST1041AX
MACRONICS HS2275
The central tap on the primary side for the transmit and receive path in the transformer should be connected together inside the
transformer and provide one common pin outside. This common pin should connect to 1.8V directly and connect to ground via
a 0.1uF capacitor as shown below. This schematic will force the signal on the primary side to bias at 1.8V.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 103 Track ID: JATR-1076-21 Rev. 1.1
RTL8309SB
1
4
3
2
5
8
7
6
RXIN
TXOP
TXON
IBREF
RXIP Transformer RJ-45
1:1
1:1
Chassis GND
2ΚΩ, 1%
0.1uF
0.01uF/1KV
50Ω
1%
75Ω
50Ω
1%
50Ω
1%
50Ω
1%
AGND
AGND
0.1uF
AGND
75Ω 75Ω
AGND
0.1uF
1.8V
Figure 23. Application for Transformer with Connected Central Tap
Bob Smith Termination
‘Bob Smith’ termination is often provided for the unused signal pairs of RJ-45 pins 4, 5, and 7, 8 to minimize the common
mode noise induced from RJ-45 pins 1 & 2, and 3 & 6.
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 104 Track ID: JATR-1076-21 Rev. 1.1
1
4
3
2
5
8
7
6
RJ-45
1:1
1:1
Chassis GN D
0.1uF/3KV
75Ω 75Ω 75Ω
Figure 24. Bob Smith Termination
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 105 Track ID: JATR-1076-21 Rev. 1.1
12. Mechanical Dimensions
Symbol Dimensions in inches Dimensions in mm 1. Dimensions D & E do not include interlead flash.
Min Typical Max Min Typical Max 2. Dimension b does not include dambar
rotrusion/intrusion.
A - - 0.134 - - 3.40 3. Controlling dimension: Millimeter
A1 0.004 0.010 0.036 0.10 0.25 0.91 4. General appearance spec. Should be based on final
visual inspection.
A2 0.102 0.112 0.122 2.60 2.85 3.10
b 0.005 0.009 0.013 0.12 0.22 0.32
c 0.002 0.006 0.010 0.05 0.15 0.25
D 0.541 0.551 0.561 13.75 14.00 14.25 TITLE:
E 0.778 0.787 0.797 19.75 20.00 20.25 -CU L/F, FOOTPRINT 3.2 mm
e 0.010 0.020 0.030 0.25 0.5 0.75 LEADFRAME MATERIAL:
HD 0.665 0.677 0.689 16.90 17.20 17.50 APPROVE DOC. NO.
HE 0.902 0.913 0.925 22.90 23.20 23.50 VERSION 1.0
L 0.027 0.035 0.043 0.68 0.88 1.08 PAGE
L1 0.053 0.063 0.073 1.35 1.60 1.85 CHECK DWG NO. Q128 - 1
y - - 0.004 - - 0.10 DATE 12 April 2003
θ 0° - 12° 0° - 12°
REALTEK SEMICONDUCTOR CO., LTD
RTL8309SB
Datasheet
Single-chip 9-port 10/100Mbps Switch Controller 106 Track ID: JATR-1076-21 Rev. 1.1
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
